A phase repeatable frequency source

Abstract

The application discloses a phase-repetitive frequency source, which comprises a reference clock input and detection circuit, a frequency synthesis and distribution circuit, a DDS signal generation circuit, a first mixing circuit, a frequency multiplication link circuit, a second mixing circuit, a signal separation circuit, a third mixing circuit and a control circuit; the frequency source does not adopt a frequency division mode, but realizes frequency synthesis through frequency multiplication and mixing, has a phase-repetitive function, and can output an ultra-wideband phase-repetitive frequency signal covering 2GHz-18GHz with a step of 1MHz; the application realizes frequency synthesis through frequency multiplication and mixing instead of frequency division, so that the phase of the same frequency signal is consistent when jumping from different frequencies to the same frequency each time, the phase-repetitive function is realized, phase calibration work is avoided, an additional calibration channel does not need to be designed, the complexity of a radar system is simplified, calibration time is saved, and rapid tracking of a target signal is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of frequency source technology, specifically, it relates to a phase repeatable frequency source. Background Technology

[0002] With the rapid development of radar technology, especially in the field of phased array radar, phase-locked loop (PLL) frequency synthesis technology, as an important means of frequency regeneration, plays an increasingly important role in the generation of excitation signals and local oscillator signals. In broadband, fine-stepping, low-phase-noise PLL frequency synthesis, the use of a phase-repeatable design is of great significance.

[0003] A key technical challenge in traditional broadband fine-step phase-locked loop (PLL) frequency synthesis technology is maintaining phase consistency for the same output frequency signal during repeated frequency hopping. Phase repeatability refers to the ability of a PLL frequency synthesis circuit to maintain perfect phase consistency each time it transitions from a different frequency signal to the same frequency signal. However, traditional techniques cannot effectively solve this problem, directly necessitating phase calibration in radar systems, especially phased array radar systems operating at the same target frequency. Figure 1 The diagram shows the circuit structure of a traditional agile frequency source. This circuit achieves spread spectrum through frequency division, resulting in a non-repeatable phase output signal. This calibration process not only requires the design of additional calibration channels, increasing the complexity and cost of the radar system, but also consumes extra time to complete the calibration, severely limiting the ability to quickly track target signals.

[0004] Furthermore, traditional agile frequency sources typically employ frequency division to extend the frequency range when achieving wideband output. However, frequency division results in non-repeatable phase of the output frequency signal. This is because the frequency division process alters the signal's phase characteristics, making it impossible to guarantee phase consistency when hopping to the same frequency each time. This deficiency further limits the application of traditional frequency sources in situations requiring high-precision phase consistency. Summary of the Invention

[0005] The purpose of this invention is to provide a phase-repeatable frequency source, which mainly solves the problem of non-repeatable phase in radar systems using phase-locked frequency synthesis in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A phase-repeatable frequency source includes:

[0008] The reference clock input and detection circuit is used to receive an external reference clock signal and detect its presence. It synchronizes the internal crystal oscillator with the external reference clock through a phase-locked loop and outputs a stable 100MHz clock signal.

[0009] A frequency synthesis and distribution circuit, connected to the reference clock input and detection circuit, is used to distribute the power of the 100MHz clock signal.

[0010] The DDS signal generation circuit is connected to the frequency synthesis and distribution circuit and is used to generate a fine-step intermediate frequency signal of 300MHz~500MHz with a step of 1MHz according to the reference clock.

[0011] The first mixing circuit is connected to the DDS signal generation circuit and the frequency synthesis and distribution circuit, and is used to mix the intermediate frequency signal with the 2.5GHz~3.1GHz local oscillator signal selected from the harmonics to generate a 2GHz~3GHz signal with a step of 1MHz.

[0012] A frequency multiplier link circuit, connected to the frequency synthesis and distribution circuit, is used to multiply the 100MHz clock signal to generate a 1GHz signal.

[0013] The second mixing circuit is connected to the first mixing circuit and the frequency doubling link circuit. It is used to select the 10GHz~15GHz local oscillator signal using the harmonics generated by the 1GHz signal, and mix it with the 2GHz~3GHz signal to generate a 7GHz~18GHz signal with a step of 1MHz.

[0014] A signal separation circuit, connected to the second mixing circuit, is used to perform routing selection on the 7GHz~18GHz signal, with one path output directly and the other path sent to the third mixing circuit;

[0015] The third mixing circuit, connected to the signal separation circuit and the second mixing circuit, is used to mix the input signal with the selected 14GHz or 16GHz local oscillator signal to generate a 2GHz~7GHz signal with a step of 1MHz, which is then output after being combined with the direct signal.

[0016] The control circuit is connected to the reference clock input and detection circuit, the DDS signal generation circuit, the first mixing circuit, the second mixing circuit, the signal separation circuit, and the third mixing circuit, respectively, and is used to receive frequency switching commands and control the working state of each circuit.

[0017] The frequency source achieves frequency synthesis through frequency multiplication and mixing, outputting an ultra-wideband phase repeatable frequency signal covering 2GHz~18GHz with a step of 1MHz.

[0018] Furthermore, in this invention, the reference clock input and detection circuit includes a first power divider, a detector, a comparator, an analog switch, a low-pass filter, a phase detector, and a crystal oscillator. The input terminal of the first power divider receives an external reference clock signal, and its output terminal is divided into two paths, with the first path connected to the reference input terminal of the phase detector and the second path connected to the input terminal of the detector. The output terminal of the detector is connected to the input terminal of the comparator. The output terminal of the comparator is connected to the control terminal of the analog switch. The common terminal of the analog switch is connected to the tuning terminal of the crystal oscillator, and its two switching terminals are respectively connected to the output terminal of the low-pass filter and the output terminal of the linear regulator. The low-pass filter is connected between the loop output terminal of the phase detector and the first switching terminal of the analog switch. The first input terminal of the phase detector receives an external reference clock signal, and the second input terminal receives the loopback signal output by the frequency synthesis and distribution circuit. The output terminal of the crystal oscillator outputs a 100MHz clock signal to the frequency synthesis and distribution circuit.

[0019] Furthermore, in this invention, the frequency synthesis and distribution circuit includes a second power divider, a third power divider, and a fourth power divider; the input terminal of the second power divider is connected to the output terminal of the crystal oscillator, and the output terminal is divided into two paths, the first path being connected to the loopback input terminal of the phase detector, and the second path being connected to the input terminal of the third power divider; the output terminal of the third power divider is divided into two paths, the first path providing a reference clock signal for the entire system, and the second path being connected to the input terminal of the fourth power divider; the output terminal of the fourth power divider is divided into two paths, the first path providing a reference clock signal for the DDS signal generation circuit, and the second path being connected to the input terminal of the frequency multiplication link circuit.

[0020] Furthermore, in this invention, the DDS signal generation circuit includes a first harmonic generator, a fifth power divider, a first bandpass filter, a first amplifier, a DDS, and a first switching filter group; the input terminal of the first harmonic generator receives a 100MHz reference clock signal output from the fourth power divider, and the output terminal outputs a 100MHz harmonic signal to the fifth power divider; the output terminal of the fifth power divider is divided into two paths, wherein the first path is connected to the input terminal of the bandpass filter, and the second path is connected to the input terminal of the first mixing circuit; the first bandpass filter selects and outputs a 3.2GHz signal to the first amplifier; the first amplifier amplifies the 3.2GHz signal and inputs it to the clock input terminal of the DDS; the output terminal of the DDS outputs a fine step signal to the input terminal of the first switching filter group; the first switching filter group outputs to the intermediate frequency input terminal of the first mixing circuit.

[0021] Furthermore, in this invention, the first mixing circuit includes a second switching filter group, a second amplifier, a first mixer, and a third switching filter group; the input terminal of the second switching filter group receives a 100MHz harmonic signal output from the fifth power divider, and switches to select and output a signal of 2.5GHz to 3.1GHz in 200MHz steps to the second amplifier; the second amplifier amplifies the power of the 2.5GHz to 3.1GHz signal in 200MHz steps and inputs it to the local oscillator input terminal of the first mixer; the intermediate frequency input terminal of the first mixer receives an intermediate frequency signal of 300MHz to 500MHz in 1MHz steps, and outputs a 2GHz to 3GHz signal in 1MHz steps generated by mixing to the third switching filter group; the third switching filter group outputs to the intermediate frequency input terminal of the second mixing circuit.

[0022] Further, in this invention, the second mixing circuit includes a second mixer, a second harmonic generator, a seventh power divider, a fourth switching filter group, a fifth switching filter group, a sixth switching filter group, and a sixth amplifier; the input terminal of the second harmonic generator receives the amplified signal output by the frequency multiplier link circuit, the input terminal of the seventh power divider receives the output signal of the second harmonic generator, and the output terminal is divided into two paths, wherein the first path is connected to the input terminal of the fourth switching filter group, and the second path is connected to the input terminal of the sixth switching filter group; the output terminal of the fourth switching filter group is connected to the input terminal of the sixth amplifier, the output terminal of the sixth amplifier is connected to the local oscillator input terminal of the second mixer, the output terminal of the second mixer is connected to the input terminal of the fifth switching filter group, the intermediate frequency input terminal of the second mixer is connected to the output terminal of the third switching filter group, the output terminal of the fifth switching filter group is connected to the signal separation circuit, and the sixth switching filter group is connected to the third mixing circuit.

[0023] Further, in this invention, the frequency multiplier link circuit includes a sixth power divider, a third amplifier, a ×2 frequency multiplier, a second bandpass filter, a fourth amplifier, a ×5 frequency multiplier, a third bandpass filter, and a fifth amplifier. The input terminal of the sixth power divider receives a 100MHz signal output from the fourth power divider, and the output terminal is divided into two paths, where the first path provides a reference clock signal for the control circuit, and the second path is connected to the input terminal of the third amplifier. The third amplifier amplifies the power of the 100MHz signal and inputs it to the ×2 frequency multiplier. The ×2 frequency multiplier multiplies the 100MHz signal to a 200MHz signal and outputs it to the second bandpass filter. The second bandpass filter outputs to the fourth amplifier. The fourth amplifier amplifies the power of the 200MHz signal and inputs it to the ×5 frequency multiplier. The ×5 frequency multiplier multiplies the 200MHz signal to generate a 1GHz signal and outputs it to the third bandpass filter. The third bandpass filter outputs to the fifth amplifier. The fifth amplifier amplifies the power of the 1GHz signal and inputs it to the second harmonic generator.

[0024] Furthermore, in this invention, the signal separation circuit includes a switch SPDT1, a switch SPDT2, a digitally controlled attenuator, and an eighth amplifier; the fixed terminal of the switch SPDT1 is connected to the output terminal of the fifth switch filter group, the two switching terminals of the switch SPDT1 are respectively connected to one switching terminal of the switch SPDT2 and the third mixing circuit, the fixed terminal of the switch SPDT2 is connected to the input terminal of the eighth amplifier, the other switching terminal of the switch SPDT2 is connected to the third mixing circuit, and the output terminal of the eighth amplifier outputs a phase repeatable frequency source in the L~Ku frequency band.

[0025] Furthermore, in this invention, the third mixing circuit includes a third mixer and a seventh switching filter group; the local oscillator input terminal of the third mixer receives the output signal of the sixth switching filter group, the RF input terminal of the third mixer is connected to a switching terminal of switch SPDT1, the IF output terminal of the third mixer is connected to the input terminal of the seventh switching filter group, and the output terminal of the seventh switching filter group is connected to a switching terminal of switch SPDT2.

[0026] Furthermore, in this invention, the control circuit employs an FPGA to control the phase detector, each switching filter group, the DDS, and the digitally controlled attenuator; the reference clock input terminal of the FPGA receives a 100MHz reference clock signal output from the sixth power divider; the control output terminal of the FPGA is connected to the frequency control terminal of the phase detector, the switching control terminal of each switching filter group, the frequency control terminal of the DDS, and the attenuation control terminal of the digitally controlled attenuator.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) This invention uses frequency multiplication and mixing to achieve frequency synthesis. No frequency divider is used in the entire frequency synthesis link, which fundamentally avoids the phase uncertainty caused by the frequency division process. When the frequency jumps, the phase of the same frequency signal can remain completely consistent each time it jumps from a different frequency to the same frequency. This solves the problem of non-repeatable phase in traditional phase-locked loop frequency synthesis technology and eliminates the need for additional phase calibration.

[0029] (2) The present invention realizes the phase repeatability function. When the radar system uses this frequency source, there is no need to design an additional phase calibration channel, nor is there a need to spend time and resources in the calibration process. This simplifies the overall architecture design of the radar system, reduces hardware costs and debugging workload, and helps to improve the integration and reliability of the radar system.

[0030] (3) This invention utilizes the coordinated operation of a reference clock input and detection circuit, a frequency synthesis and distribution circuit, a DDS signal generation circuit, a three-stage mixing circuit, and a frequency doubling link circuit to generate a fine-step intermediate frequency signal of 300MHz to 500MHz with a step of 1MHz using DDS. Combined with the frequency expansion of multi-stage mixing and frequency doubling link, it finally outputs an ultra-wideband frequency signal covering 2GHz to 18GHz with a step of 1MHz, thus satisfying multiple requirements of wideband, fine step and phase repeatability.

[0031] (4) The reference clock input and detection circuit of the present invention detects the existence status of the external reference clock in real time through a detector and a comparator. When the external reference clock is input normally, the internal crystal oscillator is synchronized with the external reference clock to output a high-precision clock signal through a phase-locked loop. When the external reference clock is lost, it automatically switches to the internal crystal oscillator autonomous working mode to ensure that the frequency source can still output a stable frequency signal when the reference clock is abnormal, thereby enhancing the reliability of the system in complex electromagnetic environments. Attached Figure Description

[0032] Figure 1 This is a circuit diagram of a traditional agile frequency source.

[0033] Figure 2 This is a circuit diagram of the frequency source of the present invention.

[0034] Figure 3 This is a schematic diagram of the specific structure of the first switching filter bank in this invention.

[0035] Figure 4 This is a schematic diagram of the specific structure of the second switching filter bank in this invention.

[0036] Figure 5 This is a schematic diagram of the specific structure of the third switching filter bank in this invention.

[0037] Figure 6 This is a schematic diagram of the specific structure of the fourth switching filter bank in this invention.

[0038] Figure 7 This is a schematic diagram of the specific structure of the fifth switching filter bank in this invention.

[0039] Figure 8 This is a schematic diagram of the specific structure of the sixth switching filter bank in this invention.

[0040] Figure 9 This is a schematic diagram of the specific structure of the seventh switching filter bank in this invention. Detailed Implementation

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0042] like Figure 2 As shown, the present invention discloses a phase repeatable frequency source, which mainly consists of a reference clock input and detection circuit, a frequency synthesis and distribution circuit, a DDS signal generation circuit, a first mixing circuit, a frequency doubling link circuit, a second mixing circuit, a signal separation circuit, a third mixing circuit, and a control circuit, with each circuit connected in sequence.

[0043] In the reference clock input and detection circuit, the external reference clock signal is input to the first power divider. The first power divider splits the external reference clock signal into two signals. The first signal is directly sent to the reference input terminal of the phase detector as its reference signal, and the second signal is sent to the input terminal of the detector. The detector performs amplitude detection on the external reference clock signal and sends the detected voltage signal to the input terminal of the comparator. The comparator compares the detected voltage with a preset reference voltage. When the detected voltage is higher than the reference voltage, the comparator outputs a high-level signal to the control terminal of the analog switch; when the detected voltage is lower than the reference voltage, the comparator outputs a low-level signal to the control terminal of the analog switch. The analog switch switches according to the level control signal output by the comparator: When a reference clock is input, the common terminal of the analog switch switches to the first switching terminal connected to the output of the low-pass filter. At this time, the loop output signal of the phase detector is filtered by the low-pass filter and sent to the tuning terminal of the crystal oscillator. Under the control of the phase-locked loop, the crystal oscillator outputs a 100MHz signal with the same frequency and phase as the external reference clock, realizing the same-parameter function between the crystal oscillator and the external reference clock. When there is no reference clock input, the common terminal of the analog switch switches to the second switching terminal connected to the output of the linear regulator. At this time, the stable voltage output by the linear regulator is directly applied to the tuning terminal of the crystal oscillator, controlling the crystal oscillator to output a precise 100MHz frequency signal. The other input terminal of the phase detector receives the loopback signal provided by the second power divider. The phase detector compares the phase of the reference clock signal with the loopback signal, generates an error signal, which is filtered by the low-pass filter to form a tuning voltage, and is sent to the tuning terminal of the crystal oscillator through the analog switch, realizing the function of the phase-locked loop.

[0044] In the frequency synthesis and distribution circuit, the 100MHz clock signal output from the crystal oscillator is sent to the second power divider. The second power divider splits the 100MHz signal into two paths: the first path serves as the loopback signal for the phase detector, and the second path is sent to the input of the third power divider. The third power divider splits the 100MHz signal into two paths: the first path serves as the reference clock signal output for the entire system, enabling the system to function in sync with the frequency source; the second path is sent to the input of the fourth power divider. The fourth power divider splits the 100MHz signal into two paths: the first path is sent to the input of the first harmonic generator as its reference clock signal; the second path is sent to the input of the sixth power divider.

[0045] In the DDS signal generation circuit, the first harmonic generator receives a 100MHz reference clock signal and generates abundant harmonic signals. The 100MHz harmonic signal output from its terminal is sent to the fifth power divider. The fifth power divider splits the 100MHz harmonic signal into two paths. The first path is sent to the input of the first bandpass filter, whose passband is set to 3.2GHz. After filtering out other harmonic components, the 3.2GHz signal is selected for output. The 3.2GHz signal is sent to the input of the first amplifier, which amplifies the 3.2GHz signal to the clock drive power required by the DDS before sending it to the clock input of the DDS. Driven by the 3.2GHz clock signal, the DDS outputs fine-step signals ranging from 300MHz to 500MHz in 1MHz increments, according to the frequency control word provided by the FPGA. This fine-step signal is sent to the input of the first switching filter bank, which performs switching filtering on the signal to remove spurious signals generated by the DDS, improving signal quality. The filtered signal is then sent to the intermediate frequency input of the first mixer. The specific structure of the first switching filter bank is as follows: Figure 3 As shown, it includes multiple parallel filtering channels, each consisting of a filter and a switch. Different filtering channels are selected by controlling the on / off state of the switches through the FPGA to adapt to the filtering requirements of different frequencies.

[0046] In the first mixer circuit, the second 100MHz harmonic signal output from the fifth power divider is sent to the input of the second switching filter bank. The second switching filter bank performs switching filtering on the 100MHz harmonic signal, selecting an output signal ranging from 2.5GHz to 3.1GHz in 200MHz steps. The specific structure of the second switching filter bank is as follows... Figure 4 As shown, the system includes multiple bandpass filters with different center frequencies, corresponding to frequencies of 2.5GHz, 2.7GHz, 2.9GHz, and 3.1GHz. The FPGA controls switches to select the appropriate filter channel, achieving local oscillator signal selection in 200MHz steps. The 2.5GHz–3.1GHz signal output from the second switching filter bank is sent to the input of the second amplifier. The second amplifier amplifies the signal power to the required local oscillator drive power for the first mixer before sending it to the local oscillator input. The first mixer mixes the local oscillator signal with the intermediate frequency signal, generating a sum frequency and a difference frequency signal. The difference frequency signal is the required 2GHz–3GHz signal in 1MHz steps. This signal is sent to the input of the third switching filter bank. The third switching filter bank filters out intermodulation spurious signals generated during mixing and outputs the result to the intermediate frequency input of the second mixer. The specific structure of the third switching filter bank is shown below. Figure 5 As shown, it includes multiple filters with different passband bandwidths, used to filter out spurious signals generated by different mixing combinations.

[0047] The frequency correspondence of the first mixing can be illustrated through the following specific examples: When the local oscillator frequency is set to 2500MHz and the intermediate frequency (IF) to 300MHz, the mixing output frequency is 2200MHz; when the local oscillator frequency is 2500MHz and the IF to 500MHz, the output frequency is 2000MHz, thus obtaining an output range of 2200MHz to 2000MHz. When the local oscillator frequency is 2700MHz and the IF frequency range is 300MHz to 500MHz, the output frequency range is 2200MHz to 2400MHz. And so on, by changing the local oscillator frequency and the IF frequency, any desired output frequency within the range of 2GHz to 3GHz can be obtained.

[0048] In the frequency multiplier circuit, the second 100MHz signal output from the fourth power divider is sent to the sixth power divider. The sixth power divider splits the 100MHz signal into two paths: the first path serves as the reference clock signal for the FPGA, enabling the FPGA to function with the entire system and the frequency source of this invention using the same parameters; the second path is sent to the input of the third amplifier. The third amplifier amplifies the power of the 100MHz signal to the driving power required by the ×2 frequency multiplier and then sends it to the input of the ×2 frequency multiplier. The ×2 frequency multiplier multiplies the 100MHz signal by 2 times, outputting a 200MHz signal. The 200MHz signal is sent to the input of the second bandpass filter, which filters out spurious signals generated by the frequency multiplication and then outputs it to the fourth amplifier. The fourth amplifier amplifies the power of the 200MHz signal to the driving power required by the ×5 frequency multiplier and then sends it to the input of the ×5 frequency multiplier. The ×5 frequency multiplier multiplies the 200MHz signal by 5 times, outputting a 1GHz signal. The 1GHz signal is sent to the input of the third bandpass filter. After filtering out spurious signals generated by the harmonics, the third bandpass filter outputs the signal to the fifth amplifier. The fifth amplifier amplifies the 1GHz signal power to the reference clock drive power required by the second harmonic generator and then sends it to the input of the second harmonic generator.

[0049] In the second mixer circuit, the second harmonic generator receives a 1GHz reference clock signal and generates abundant harmonic signals. The 1GHz harmonic signal output from its terminal is sent to the seventh power divider. The seventh power divider splits the 1GHz harmonic signal into two paths: the first path is sent to the input of the fourth switching filter group, and the second path is sent to the input of the sixth switching filter group. The fourth switching filter group performs switching filtering on the 1GHz harmonic signal, selecting an output signal in the 10GHz–15GHz range, in 1GHz increments. The specific structure of the fourth switching filter group is as follows... Figure 6As shown, the system includes multiple bandpass filters with different center frequencies, corresponding to frequencies of 10GHz, 11GHz, 12GHz, 13GHz, 14GHz, and 15GHz. The FPGA controls a switch to select the appropriate filter channel, achieving 1GHz step local oscillator signal selection. The 10GHz–15GHz signal output from the fourth switch filter bank is sent to the input of the sixth amplifier. The sixth amplifier amplifies the signal power to the required local oscillator drive power for the second mixer before sending it to the local oscillator input. The second mixer mixes the 10GHz–15GHz local oscillator signal with a 2GHz–3GHz intermediate frequency signal to generate a 7GHz–18GHz signal with 1MHz steps. This signal is sent to the input of the fifth switch filter bank, which filters out intermodulation spurious signals generated during mixing before outputting it to the SPDT1 switch. The specific structure of the fifth switch filter bank is shown below. Figure 7 As shown, it includes multiple filters with different passband bandwidths, used to filter out spurious signals generated by different mixing combinations.

[0050] The frequency correspondence of the second mixing can be illustrated through the following specific examples: When the local oscillator frequency is 10.0 GHz and the intermediate frequency (IF) is 2.0 GHz, the mixing output frequency is 8.0 GHz; when the local oscillator frequency is 10.0 GHz and the IF is 3.0 GHz, the output frequency is 7.0 GHz, thus obtaining an output range of 7.0 GHz to 8.0 GHz. When the local oscillator frequency is 11.0 GHz and the IF range is 2.0 GHz to 3.0 GHz, the output frequency range is 8.0 GHz to 9.0 GHz. And so on, by changing the local oscillator frequency and the IF frequency, any desired output frequency within the range of 7 GHz to 18 GHz can be obtained.

[0051] In the signal separation circuit and the third mixer circuit, the input of the SPDT1 switch receives a 7GHz–18GHz signal with 1MHz steps from the output of the fifth switching filter bank. The SPDT1 switch switches according to the FPGA control signals, routing the signal to different output channels. When the complete 7GHz–18GHz frequency band needs to be output, the SPDT1 switch selects the second direct output, sending the 7GHz–18GHz signal directly to the SPDT2 switch. When the 8GHz–10GHz or 11GHz–13GHz frequency band needs to be output, the SPDT1 switch selects the first output, sending the 8GHz–10GHz or 11GHz–13GHz signal to the RF input of the third mixer. The input of the sixth switching filter bank receives the 1GHz harmonic signal from the seventh power divider. The sixth switching filter bank performs switching filtering on the 1GHz harmonic signal, selecting to output a 14GHz or 16GHz signal. The specific structure of the sixth switching filter bank is as follows: Figure 8As shown, it includes two bandpass filter channels corresponding to 14GHz and 16GHz respectively, with the appropriate filter channel selected via an FPGA-controlled switch. The 14GHz or 16GHz signal is sent to the input of the seventh amplifier, which amplifies the signal power to the local oscillator drive power required by the third mixer before sending it to the local oscillator input of the third mixer. The third mixer mixes the 14GHz or 16GHz local oscillator signal with an 8GHz–10GHz or 11GHz–13GHz RF signal to generate a 2GHz–7GHz signal with a 1MHz step. This signal is sent to the input of the seventh switching filter bank, which filters out intermodulation spurious signals generated during mixing before outputting it to the SPDT2 switch. The specific structure of the seventh switching filter bank is shown below. Figure 9 As shown, it includes multiple filters with different passband bandwidths, used to filter out spurious signals generated by different mixing combinations.

[0052] In the third mixing stage, when the local oscillator frequency is 14.0 GHz and the radio frequency is 12.0 GHz, the mixing output frequency is 2.0 GHz; when the local oscillator frequency is 14.0 GHz and the radio frequency range is 11.0 GHz to 12.0 GHz, the output frequency range is 2.0 GHz to 3.0 GHz. Similarly, by changing the local oscillator frequency and the radio frequency, any desired output frequency within the range of 2 GHz to 7 GHz can be obtained.

[0053] The SPDT2 switch receives two signals at its input: the first is a 2GHz–7GHz signal with a 1MHz step from the output of the seventh switch filter bank, and the second is a 7GHz–18GHz signal with a 1MHz step from the second output of the SPDT1 switch. The SPDT2 switch switches according to the FPGA control signals, combining the two signals to output a complete ultra-wideband signal covering 2GHz–18GHz with a 1MHz step. The output signal of the SPDT2 switch is sent to the input of a digitally controlled attenuator (DCA). The DCA, based on the attenuation control signals provided by the FPGA, digitally controls the attenuation of the output signal, adjusting the power flatness to ensure consistent signal power across the entire operating frequency band. The output signal of the DCA is then sent to the input of an eighth amplifier, which amplifies the signal power to the required output power for the entire system, ultimately outputting an ultra-wideband phase-repeatable frequency source in the L–Ku frequency band.

[0054] The control circuit uses an FPGA as the core of the entire frequency source control, integrating multiple control modules to control the phase detector, each switching filter bank, the DDS, and the digitally controlled attenuator. The FPGA's reference clock input receives a 100MHz reference clock signal from the sixth power divider, ensuring that the FPGA's operating clock is synchronized with the overall system and the frequency source of this invention. The FPGA, through its internal frequency control word generation module, calculates and generates the required frequency control word for the DDS based on the frequency switching commands issued by the overall system, and writes it to the DDS's control register through the DDS's data interface, achieving rapid switching of the DDS output frequency. The FPGA, through its switching control module, calculates and generates channel selection control signals for the switching filter banks based on the required local oscillator frequency, and outputs them to the control terminals of each switching filter through the GPIO interface, achieving rapid switching of the local oscillator signal channels. The FPGA, through its phase detector control module, writes frequency synthesis parameters to the phase detector, controlling the phase detector's operating mode and output frequency. The FPGA, through its attenuation control module, calculates and generates the attenuation control word for the digitally controlled attenuator based on power flatness requirements, and writes it to the attenuator's control register through the attenuator's data interface, achieving precise control of the output signal power. The FPGA integrates a status monitoring module that monitors the signal status of each key node in real time. When an anomaly is detected, it can automatically perform fault diagnosis and recovery processing.

[0055] The working principle of this invention can be explained through the following complete workflow: The entire system sends a frequency switching command to the FPGA. After receiving the frequency switching command, the FPGA first calculates the required local oscillator frequency, intermediate frequency frequency, and DDS output frequency based on the target output frequency. Then, according to the timing requirements, it sends control signals to the phase detector, DDS, each switching filter bank, and digitally controlled attenuator sequentially. Under the control of the FPGA, the phase detector completes the establishment and stabilization of the phase-locked loop. Under the control of the FPGA, the DDS outputs the required intermediate frequency. Under the control of the FPGA, the switching filter banks select the required local oscillator frequency channel. Under the control of the FPGA, the digitally controlled attenuator adjusts its output power. After the frequency switching is completed, the FPGA continuously monitors the signal status of each key node to ensure the stable operation of the frequency source. Because this invention uses frequency multiplication and mixing to achieve frequency synthesis without using a frequency divider, the phase of the same frequency signal remains consistent each time it switches from different frequencies to the same frequency, achieving phase repeatability.

[0056] The typical application scenarios of this invention in radar systems are as follows: Phased array radar systems need to generate a large number of local oscillator signals and excitation signals. These signals need to have ultra-wideband, fine-step, and agile characteristics, while also meeting the requirement of phase repeatability. The phase repeatable frequency source provided by this invention can output ultra-wideband signals covering 2GHz to 18GHz with 1MHz steps. The frequency switching time meets the agile requirement, and the phase remains consistent each time the frequency jumps to the same frequency. It can be directly used as the local oscillator source and excitation signal source of a phased array radar without the need for additional phase calibration, simplifying the design of the radar system and improving its operating efficiency.

[0057] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A phase-repeatable frequency source, characterized in that, include: The reference clock input and detection circuit is used to receive an external reference clock signal and detect its presence. It synchronizes the internal crystal oscillator with the external reference clock through a phase-locked loop and outputs a stable 100MHz clock signal. A frequency synthesis and distribution circuit, connected to the reference clock input and detection circuit, is used to distribute the power of the 100MHz clock signal. The DDS signal generation circuit is connected to the frequency synthesis and distribution circuit and is used to generate a fine-step intermediate frequency signal of 300MHz~500MHz with a step of 1MHz according to the reference clock. The first mixing circuit is connected to the DDS signal generation circuit and the frequency synthesis and distribution circuit, and is used to mix the intermediate frequency signal with the 2.5GHz~3.1GHz local oscillator signal selected from the harmonics to generate a 2GHz~3GHz signal with a step of 1MHz. A frequency multiplier link circuit, connected to the frequency synthesis and distribution circuit, is used to multiply the 100MHz clock signal to generate a 1GHz signal. The second mixing circuit is connected to the first mixing circuit and the frequency doubling link circuit. It is used to select the 10GHz~15GHz local oscillator signal using the harmonics generated by the 1GHz signal, and mix it with the 2GHz~3GHz signal to generate a 7GHz~18GHz signal with a step of 1MHz. A signal separation circuit, connected to the second mixing circuit, is used to perform routing selection on the 7GHz~18GHz signal, with one path output directly and the other path sent to the third mixing circuit; The third mixing circuit, connected to the signal separation circuit and the second mixing circuit, is used to mix the input signal with the selected 14GHz or 16GHz local oscillator signal to generate a 2GHz~7GHz signal with a step of 1MHz, which is then output after being combined with the direct signal. The control circuit is connected to the reference clock input and detection circuit, the DDS signal generation circuit, the first mixing circuit, the second mixing circuit, the signal separation circuit, and the third mixing circuit, respectively, and is used to receive frequency switching commands and control the working state of each circuit. The frequency source achieves frequency synthesis through frequency multiplication and mixing, outputting an ultra-wideband phase repeatable frequency signal covering 2GHz~18GHz with a step of 1MHz.

2. The phase-repeatable frequency source according to claim 1, characterized in that, The reference clock input and detection circuit includes a first power divider, a detector, a comparator, an analog switch, a low-pass filter, a phase detector, and a crystal oscillator. The input of the first power divider receives an external reference clock signal, and its output is divided into two paths: the first path is connected to the reference input of the phase detector, and the second path is connected to the input of the detector. The output of the detector is connected to the input of the comparator. The output of the comparator is connected to the control terminal of the analog switch. The common terminal of the analog switch is connected to the tuning terminal of the crystal oscillator, and its two switching terminals are respectively connected to the output of the low-pass filter and the output of the linear regulator. The low-pass filter is connected between the loop output of the phase detector and the first switching terminal of the analog switch; the first input of the phase detector receives an external reference clock signal, and the second input receives the loopback signal output by the frequency synthesis and distribution circuit; the output of the crystal oscillator outputs a 100MHz clock signal to the frequency synthesis and distribution circuit.

3. A phase-repeatable frequency source according to claim 2, characterized in that, The frequency synthesis and distribution circuit includes a second power divider, a third power divider, and a fourth power divider. The input of the second power divider is connected to the output of the crystal oscillator, and its output is divided into two paths: the first path is connected to the loopback input of the phase detector, and the second path is connected to the input of the third power divider. The output of the third power divider is divided into two paths: the first path provides a reference clock signal for the entire system, and the second path is connected to the input of the fourth power divider. The output of the fourth power divider is divided into two paths: the first path provides a reference clock signal for the DDS signal generation circuit, and the second path is connected to the input of the frequency multiplication link circuit.

4. A phase-repeatable frequency source according to claim 3, characterized in that, The DDS signal generation circuit includes a first harmonic generator, a fifth power divider, a first bandpass filter, a first amplifier, a DDS, and a first switching filter bank. The input of the first harmonic generator receives a 100MHz reference clock signal output from the fourth power divider, and the output of the first harmonic generator outputs a 100MHz harmonic signal to the fifth power divider. The output of the fifth power divider is divided into two paths, with the first path connected to the input of the bandpass filter and the second path connected to the input of the first mixing circuit. The first bandpass filter selects and outputs a 3.2GHz signal to the first amplifier. The first amplifier amplifies the 3.2GHz signal and inputs it to the clock input of the DDS. The output of the DDS outputs a fine-stepping signal to the input of the first switching filter bank. The output of the first switching filter bank is sent to the intermediate frequency input of the first mixing circuit.

5. A phase-repeatable frequency source according to claim 4, characterized in that, The first mixing circuit includes a second switching filter group, a second amplifier, a first mixer, and a third switching filter group. The input of the second switching filter group receives a 100MHz harmonic signal output from the fifth power divider, and switches to output a 2.5GHz to 3.1GHz signal in 200MHz steps to the second amplifier. The second amplifier amplifies the power of the 2.5GHz to 3.1GHz signal in 200MHz steps and inputs it to the local oscillator input of the first mixer. The intermediate frequency input of the first mixer receives an intermediate frequency signal of 300MHz to 500MHz in 1MHz steps, and outputs a 2GHz to 3GHz signal in 1MHz steps generated by mixing to the third switching filter group. The output of the third switching filter group is sent to the intermediate frequency input of the second mixing circuit.

6. A phase-repeatable frequency source according to claim 5, characterized in that, The second mixing circuit includes a second mixer, a second harmonic generator, a seventh power divider, a fourth switching filter group, a fifth switching filter group, a sixth switching filter group, and a sixth amplifier. The input terminal of the second harmonic generator receives the amplified signal output from the frequency multiplier circuit. The input terminal of the seventh power divider receives the output signal of the second harmonic generator, and its output terminal is divided into two paths: the first path is connected to the input terminal of the fourth switching filter group, and the second path is connected to the input terminal of the sixth switching filter group. The output terminal of the fourth switching filter group is connected to the input terminal of the sixth amplifier, the output terminal of the sixth amplifier is connected to the local oscillator input terminal of the second mixer, the output terminal of the second mixer is connected to the input terminal of the fifth switching filter group, the intermediate frequency input terminal of the second mixer is connected to the output terminal of the third switching filter group, the output terminal of the fifth switching filter group is connected to the signal separation circuit, and the sixth switching filter group is connected to the third mixing circuit.

7. A phase-repeatable frequency source according to claim 6, characterized in that, The frequency multiplier circuit includes a sixth power divider, a third amplifier, a ×2 frequency multiplier, a second bandpass filter, a fourth amplifier, a ×5 frequency multiplier, a third bandpass filter, and a fifth amplifier. The input of the sixth power divider receives a 100MHz signal output from the fourth power divider, and its output is split into two paths: the first path provides a reference clock signal for the control circuit, and the second path is connected to the input of the third amplifier. The third amplifier amplifies the power of the 100MHz signal and inputs it to the ×2 frequency multiplier. The ×2 frequency multiplier multiplies the 100MHz signal to a 200MHz signal and outputs it to the second bandpass filter. The second bandpass filter outputs to the fourth amplifier. The fourth amplifier amplifies the power of the 200MHz signal and inputs it to the ×5 frequency multiplier. The ×5 frequency multiplier multiplies the 200MHz signal to generate a 1GHz signal and outputs it to the third bandpass filter. The third bandpass filter outputs to the fifth amplifier. The fifth amplifier amplifies the power of the 1GHz signal and inputs it to the second harmonic generator.

8. A phase-repeatable frequency source according to claim 7, characterized in that, The signal separation circuit includes switch SPDT1, switch SPDT2, digitally controlled attenuator, and eighth amplifier; the fixed terminal of switch SPDT1 is connected to the output terminal of the fifth switching filter group, the two switching terminals of switch SPDT1 are respectively connected to one switching terminal of switch SPDT2 and the third mixing circuit, the fixed terminal of switch SPDT2 is connected to the input terminal of the eighth amplifier, the other switching terminal of switch SPDT2 is connected to the third mixing circuit, and the output terminal of the eighth amplifier outputs a phase repeatable frequency source in the L~Ku frequency band.

9. A phase-repeatable frequency source according to claim 8, characterized in that, The third mixing circuit includes a third mixer and a seventh switching filter group; the local oscillator input of the third mixer receives the output signal of the sixth switching filter group, the RF input of the third mixer is connected to a switching terminal of switch SPDT1, the IF output of the third mixer is connected to the input of the seventh switching filter group, and the output of the seventh switching filter group is connected to a switching terminal of switch SPDT2.

10. A phase-repeatable frequency source according to claim 9, characterized in that, The control circuit uses an FPGA to control the phase detector, each switching filter group, DDS, and digitally controlled attenuator. The reference clock input of the FPGA receives the 100MHz reference clock signal output by the sixth power divider. The control output of the FPGA is connected to the frequency control terminal of the phase detector, the switching control terminal of each switching filter group, the frequency control terminal of the DDS, and the attenuation control terminal of the digitally controlled attenuator.

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