Low mismatch low spur charge pump circuit and phase-locked loop structure applied to middle-high speed phase-locked loop

Abstract

The application discloses a low-mismatch low-spur charge pump circuit and a phase-locked loop structure applied to a medium-high speed phase-locked loop, takes a source switch charge pump as a main framework, adopts a gain enhancement structure bias branch, and forms an adaptive feedback network with a charge and discharge branch; meanwhile, a dummy transistor is added at a node of a switch path to inhibit transient current spur caused by charge injection and clock feedthrough, reduce control voltage ripple and reference spur. The dummy transistor compensation branch can compensate charge injection and clock feedthrough in the main switch flip process, reduce output node current peak and control voltage spur. The application does not depend on a complex full-differential current steering structure or a large-scale auxiliary calibration circuit, and is suitable for application in a medium-high speed clock generation phase-locked loop with constraints on power consumption, area and implementation complexity.

Description

Technical Field

[0001] This invention belongs to the field of phase-locked loop application circuits, specifically relating to a low-mismatch, low-glitch charge pump circuit and phase-locked loop structure applied to medium- and high-speed phase-locked loops. Background Technology

[0002] Phase-locked loops (PLLs) are widely used in on-chip clock generation, frequency synthesis, and sampling clock generation circuits in various interface chips. In practical applications, the target output frequency of a PLL does not necessarily reach several GHz. Many medium-to-high-speed clock generation and frequency synthesis scenarios typically operate at frequencies ranging from several hundred MHz to around 1 GHz, such as on-chip sampling clocks, interface word clocks, parallel processing clocks, and medium-frequency control clocks. Charge pump PLLs are a commonly used PLL structure. Figure 1 The frame structure of the charge pump phase-locked loop is shown.

[0003] The charge pump is a key analog module in a charge pump phase-locked loop (PLL), typically located between the phase detector and the loop filter. Its function is to convert the phase error signal output from the phase detector into a charging / discharging current, which forms a control voltage on the loop filter to regulate the output frequency of the voltage-controlled oscillator (VCO). The charge pump's charging / discharging current matching, output swing, and switching transient characteristics affect the control voltage ripple, reference spurious signals, and output clock jitter; therefore, the charge pump's performance has a significant impact on the overall performance of the PLL.

[0004] Traditional charge pump structures mainly include gate-switching, drain-switching, and source-switching types, such as... Figure 2 As shown. The gate switch structure is simple to implement, but has a relatively long settling time; the drain switch structure is faster, but the switching node is directly coupled to the output node, which can easily introduce charge injection and clock feedthrough; the source switch structure offers a good trade-off between implementation complexity, power consumption, and output node disturbance.

[0005] To improve charge pump performance, existing technologies typically employ methods such as increasing the output impedance of the current mirror or introducing an auxiliary amplifier. While these methods can improve current matching or switching transient characteristics to some extent, a charge pump structure that is relatively simple, consumes less power, and can simultaneously achieve low mismatch and low glitches is still needed in medium- and high-speed frequency synthesis phase-locked loops.

[0006] First, some charge pump solutions designed for higher operating frequencies often employ current steering structures. These structures typically improve high-speed operation by keeping the current source continuously on and switching the current between different branches. However, in mid-frequency applications such as clock generation and frequency synthesis at hundreds of MHz, there may be some technical redundancy, which can increase unnecessary static power consumption, layout area, and circuit design complexity.

[0007] Secondly, traditional charge pumps exhibit significant quiescent current mismatch. One of the key performance characteristics of a charge pump is the matching of charging and discharging currents. When the output node voltage changes, the drain-source voltage of the main mirror branch transistor also changes. Under the combined influence of channel length modulation effect and limited branch output impedance, the charging and discharging currents are prone to deviate from the set values, thereby reducing the consistency of currents between the upper and lower branches.

[0008] Furthermore, traditional charge pumps are prone to generating glitches during switching transients. During the switching process, the charge in the parasitic capacitance of the switching transistor couples to the output node, causing non-ideal effects such as charge injection, clock feedthrough, and charge sharing, resulting in output node current spikes and control voltage ripple. These transient disturbances introduce additional phase noise and reference spurious signals into the phase-locked loop system, affecting the output clock quality.

[0009] Therefore, existing solutions struggle to simultaneously achieve low mismatch, low glitches, and low implementation complexity. Some structures are primarily optimized for static current mismatch but are insufficient in suppressing switching transient glitches; others, while improving dynamic errors, often require complex auxiliary circuitry or continuously conducting branches, which is detrimental to achieving low power consumption and small area designs in PLLs with hundreds of MHz clock generation and frequency synthesis. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a low-mismatch, low-glitch charge pump circuit and phase-locked loop structure for medium- and high-speed phase-locked loops, which solves the problem that the existing phase-locked loop charge pump circuits are difficult to simultaneously achieve low mismatch, low glitch and low implementation complexity.

[0011] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0012] The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops uses a source-switched charge pump as the main framework and adopts a bias branch with a gain enhancement structure to form an adaptive feedback network with the charge and discharge branch. At the same time, dummy transistors are added at the nodes of the switching path to suppress transient current glitches caused by charge injection and clock feedthrough, thereby reducing control voltage ripple and reference spurious emissions.

[0013] The adaptive feedback network includes a first feedback network and a second feedback network, which are connected via a CMOS inverter. The first feedback network includes a discharge switch, a discharge current source, and a first auxiliary amplifier unit. The second feedback network includes a charging switch, a charging current source, and a second auxiliary amplifier unit. The input of the first auxiliary amplifier unit is connected to the gate of the discharge current source, and the output is connected to the source of the discharge current source, for adjusting and stabilizing the drain-source voltage of the discharge current source. The input of the second auxiliary amplifier unit is connected to the gate of the charging current source, and the output is connected to the source of the charging current source, for adjusting and stabilizing the drain-source voltage of the charging current source.

[0014] The dummy transistor is selected from the same type of transistor as the switching transistor. Its source and drain are connected together and connected to the drain of the charge pump switching transistor. The gate is connected to the reverse switching signal to generate a compensation charge in the opposite direction when the switching signal flips, thereby offsetting part of the disturbance coupled to the output node by the parasitic capacitance of the main switch.

[0015] The size of the dummy tube is set according to the parasitic capacitance of the discharge switch and the charge switch, as well as the size of the output glitch.

[0016] The bias branch of the gain enhancement structure includes a bias current mirror composed of a PMOS-side current mirror, an NMOS-side bias conversion branch, and a current source. The PMOS-side current mirror is used to generate a PMOS-side bias voltage and replicate an external reference current. The NMOS-side bias conversion branch is used to convert a stable current into an NMOS-side bias voltage. The PMOS-side bias voltage and the NMOS-side bias voltage provide stable bias current to the adaptive feedback network and each branch.

[0017] The gain enhancement structure employs one of the following to implement the auxiliary amplification unit: a push-pull inverting amplifier based on a CMOS inverter, a single transistor amplifier, a simple common-source amplifier, a differential amplifier, or a local gain enhancement circuit.

[0018] A phase-locked loop (PLL) structure includes a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider with negative feedback connected between the VCO and the frequency and phase detector; the charge pump adopts the low-mismatch, low-glitch charge pump circuit described above for medium- and high-speed PLLs.

[0019] A phase-locked loop (PLL) structure for an analog-to-digital converter (ADC) includes an ADC core module. The eight parallel outputs of the ADC core module are connected to an LVDS driver after passing through a parallel-to-serial converter. The PLL uses the ADC output clock as a reference input and generates a serial transmission clock by frequency multiplication to provide it to the parallel-to-serial converter circuit. The charge pump of the PLL adopts the low-mismatch, low-glitch charge pump circuit described above for medium- and high-speed PLLs.

[0020] The digital signals are output in parallel from 8 channels and synchronized with a 125MHz word clock.

[0021] The phase-locked loop generates a 1GHz serial transmission clock by frequency multiplication.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. The circuit utilizes a source-switching structure to reduce continuously conducting branches, resulting in a simpler structure and reduced unnecessary static power consumption, layout area, and design complexity. Because it does not employ a complex fully differential current-switching structure or large-scale calibration circuitry, this invention helps maintain a good output voltage swing and is suitable for low-voltage applications.

[0024] 2. This invention improves the charging and discharging current matching through a gain-enhanced adaptive voltage regulation feedback structure. The gain-enhanced structure itself has high output resistance, enabling high current replication accuracy. Simultaneously, in conjunction with a negative feedback structure, it stabilizes the voltage at key nodes of the master mirror transistor, further improving the equivalent output impedance of the charging and discharging branches and enhancing the charge pump current replication accuracy.

[0025] 3. Reduce switching transient glitches. The dummy transistor compensation branch can compensate for charge injection and clock feedthrough during the main switch switching process, reducing output node current spikes and control voltage glitches.

[0026] 4. Easy to implement in engineering and highly adaptable to various processes. This invention does not rely on complex fully differential current steering structures or large-scale auxiliary calibration circuits, making it suitable for application in medium-to-high-speed clock generation phase-locked loops where power consumption, area, and implementation complexity are constrained. Attached Figure Description

[0027] Figure 1 This is a charge pump phase-locked loop structure in the existing technology.

[0028] Figure 2 It is a traditional structure for charge pumps.

[0029] Figure 3 It is a current-directing charge pump.

[0030] Figure 4 This is a circuit diagram of the low-mismatch, low-glitch charge pump of the present invention.

[0031] Figure 5 The diagram shows the gain enhancement structure of this invention. a is a schematic diagram of the principle, and b is a specific application diagram.

[0032] Figure 6 This is a schematic diagram of the current matching result after adopting the gain-enhanced adaptive voltage regulation feedback structure of the present invention.

[0033] Figure 7 This is a comparison chart showing the signal glitch improvement effects of the present invention and existing technologies.

[0034] Figure 8 This is a schematic diagram of the frequency synthesis phase-locked loop structure applied to the data output interface of an analog-to-digital converter according to the present invention. Detailed Implementation

[0035] The structure and working process of the present invention will be further described below with reference to the accompanying drawings.

[0036] The purpose of this invention is to provide a low-mismatch, low-glitch charge pump circuit for medium-to-high-speed phase-locked loops (PLLs), primarily suitable for medium-to-high-speed frequency synthesis PLLs ranging from several hundred MHz to approximately 1 GHz. It can also be used in other clock generation PLLs that require low mismatch, low glitches, and low power consumption. The objectives of this invention include:

[0037] 1. Design a charge pump suitable for medium-frequency phase-locked loop applications, achieving a good trade-off between design complexity and performance.

[0038] 2. Achieve high current matching of the charge pump to avoid current mismatch during charge pump operation due to limited output impedance of the main mirror branch and channel length modulation effect when the output node voltage changes.

[0039] 3. Reduce output node glitches and control voltage ripple caused by charge injection, clock feedthrough and charge sharing during charge pump switching on and off, thereby reducing phase noise.

[0040] The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops uses a source-switched charge pump as the main framework and adopts a bias branch with a gain enhancement structure to form an adaptive feedback network with the charge and discharge branch. At the same time, dummy transistors are added at the nodes of the switching path to suppress transient current glitches caused by charge injection and clock feedthrough, thereby reducing control voltage ripple and reference spurious emissions.

[0041] Specific embodiments, such as Figures 3 to 8 As shown:

[0042] This embodiment provides a low-mismatch, low-glitch charge pump circuit for use in medium-to-high-speed phase-locked loops, the structure of which is as follows: Figure 4 As shown, the circuit uses a source-switched charge pump as the main framework. Gain-enhanced adaptive voltage regulator current mirrors are introduced in the bias and mirror branches to improve the equivalent output impedance of the branches and reduce the charge and discharge current offset caused by changes in the output node voltage. At the same time, dummy transistors are added to the switching path to suppress transient current glitches caused by charge injection and clock feedthrough, thereby reducing control voltage ripple and reference spurious emissions.

[0043] The left bias branch consists of devices such as MP7, MP6, MN6, and MP5 forming a gain-enhancing current mirror; the middle devices such as MP4, MN3, MP3, and MN4 together with the rightmost branch form an adaptive feedback network; MP2 and MN2 on the right are current source transistors for charging current and discharging current, respectively, which directly determine the current matching performance of the charge pump; MP1 and MN1 are source switches, which are controlled by UPB and DOWN signals to turn on and off the charging and discharging branches, respectively.

[0044] Specifically, the adaptive feedback network includes a first feedback network composed of MN1, MN2, MN3, and MP4, and a second feedback network composed of MP1, MP2, MP3, and MN4. MN1 is a discharge switch, MN2 is a discharge current source, MN3 and MP4 are first auxiliary amplification units, MP1 is a charging switch, MP2 is a charging current source, and MP3 and MN4 are second auxiliary amplification units. The two auxiliary amplification units are connected in the form of CMOS inverters. The input terminal of the first auxiliary amplification unit is connected to the gate of MN2, and the output terminal is connected to the source of MN2, used to regulate and stabilize the drain-source voltage of MN2. The input terminal of the second auxiliary amplification unit is connected to the gate of MP2, and the output terminal is connected to the source of MP2, used to regulate and stabilize the drain-source voltage of MP2. When the output node voltage changes, the first and second feedback networks stabilize the drain-source voltages of MN2 and MP2 through negative feedback, thereby improving the equivalent output impedance of the charging and discharging branch and reducing current mismatch.

[0045] Taking the current sink as an example, the negative feedback process of the adaptive feedback network is as follows: when As the current through MN1 increases, according to the MOSFET saturation current formula, the drain voltage of MN1 increases, which in turn increases the gate voltages of MN3 and MP4. Since the currents in MN3 and MP4 are mirror copies of those in MP6 and MP7, these currents remain stable. To compensate for the gate voltage change, the drain voltages of MN3 and MP4 will decrease, which in turn decreases the gate voltage of MN2. This will lead to a decrease in the current through MN1. This decreases, thus creating negative feedback. When When the current decreases, the opposite is also true. The same principle applies to the current source.

[0046] The bias current mirror, composed of MP7, MP6, MN6, MN5, MP5, and a current source, receives an external reference current. MP5, MP6, and MP7 form a PMOS-side current mirror, with MP7 connected to the power supply terminal as a diode. The gates of MP6 and MP5 are connected to the gate of MP7 to generate a PMOS-side bias voltage and replicate the external reference current. MN6 and MN5 form an NMOS-side bias conversion branch, with MN6 connected to MP6 as a diode to convert the stable current replicated by MP6 into an NMOS-side bias voltage. The PMOS-side bias voltage and NMOS-side bias voltage provide stable bias current to the adaptive feedback network and each branch.

[0047] The working principles of each circuit structure are as follows:

[0048] (1) The bias branch adopts a gain enhancement structure to receive the externally input reference current. The current mirror relationship is used to provide bias conditions for subsequent branches. The principle of the gain enhancement structure is to form local negative feedback through the auxiliary amplification unit, stabilize the voltage of the critical node of the current source tube, and improve the equivalent output impedance of the branch, thereby reducing the influence of channel length modulation effect on the output current and improving the charge pump current matching. The design uses a push-pull inverting amplifier based on CMOS inverter to implement the auxiliary amplification unit. Compared with traditional auxiliary amplifiers, the push-pull inverting amplifier has higher small-signal gain, can enhance local feedback capability, and retain a larger output swing under lower voltage conditions.

[0049] (2) The gain enhancement structure and the charge pump charging / discharging branch form an adaptive feedback network, which stabilizes the charge pump output current and improves current matching through negative feedback. When the output node When the voltage changes, the drain-source voltage of MP2 or MN2 changes accordingly. The gain-enhanced adaptive feedback network adjusts the gate bias of MP2 or MN2 through the auxiliary amplification unit, keeping the operating point of the main mirror transistor relatively stable, thereby reducing the charge-discharge current offset caused by changes in the output node voltage.

[0050] (3) A dummy transistor is placed at the switching node to generate a compensating charge in the opposite direction when the switching signal flips, thereby offsetting part of the disturbance coupled to the output node by the parasitic capacitance of the main switch. The dummy transistor can reduce charge injection and clock feedthrough caused by parasitic capacitance and suppress dynamic glitches in the output current when the switching signal arrives. The size of the dummy transistor can be set according to the parasitic capacitance of the main switch and the size of the output glitches, preferably a certain proportion of the size of the main switch.

[0051] This circuit combines current mismatch suppression and dynamic glitch suppression: the former is mainly achieved by increasing the output impedance through a gain-enhancing current mirror and an adaptive feedback network, while the latter is optimized through source switching and dummy transistors.

[0052] As an alternative implementation, the auxiliary amplification unit is not limited to a CMOS inverter-type push-pull auxiliary amplifier, but can also be implemented using a single-transistor amplifier, a simple common-source amplifier, a differential amplifier, or other local gain enhancement circuits; and the dummy transistor compensation branch is not limited to... Figure 4 The connection configuration shown can also be equivalently configured based on the position of the main switch and the parasitic capacitance coupling path.

[0053] Overall, this design balances low mismatch and low glitches. By working in conjunction with a gain-enhanced adaptive voltage regulation feedback branch and a dummy transistor compensation branch, this invention can simultaneously improve current mismatch and dynamic switching glitches, making it suitable for medium-to-high frequency synthetic phase-locked loops ranging from hundreds of MHz to approximately 1 GHz.

[0054] To further illustrate the application of this circuit, the present invention also discloses a phase-locked loop structure (basic structural framework as follows) Figure 1 The circuit includes a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator connected in sequence, and a frequency divider with negative feedback connected between the voltage-controlled oscillator and the frequency and phase detector; the charge pump adopts the low-mismatch, low-glitch charge pump circuit used in medium- and high-speed phase-locked loops.

[0055] A phase-locked loop (PLL) structure for an analog-to-digital converter (ADC) includes an ADC core module. The eight parallel outputs of the ADC core module are connected to an LVDS driver after passing through a parallel-to-serial converter. The PLL uses the ADC output clock as a reference input and generates a serial transmission clock by frequency multiplication to provide it to the parallel-to-serial converter circuit. The charge pump of the PLL adopts the low-mismatch, low-glitch charge pump circuit described above for medium- and high-speed PLLs.

[0056] Specifically, such as Figure 8 As shown, the low-mismatch, low-glitch charge pump circuit is applied in the frequency synthesis phase-locked loop (PLL) of the analog-to-digital converter (ADC) data output interface. The ADC output provides eight parallel digital signals, synchronized with a 125MHz word clock. The PLL uses this 125MHz clock as a reference input, multiplies it to generate a 1GHz serial transmit clock, and provides this clock to the subsequent 8:1 parallel-to-serial conversion circuit. Under the control of the 1GHz serial clock, the parallel-to-serial conversion circuit converts the original eight parallel data signals into one LVDS differential serial signal output.

[0057] In this embodiment, the charge pump in the phase-locked loop adopts the source-switching type low-mismatch, low-glitch structure described in this invention. A gain-enhanced adaptive voltage regulation feedback branch is used to reduce the static current mismatch between the charging and discharging branches, and a dummy transistor compensation branch is used to reduce switching transient glitches, thereby reducing the control voltage ripple of the loop filter and improving the stability of the serial transmission clock. This structure is suitable for ADC parallel data serialization output, interface word clock multiplication, and other medium-to-high-speed clock generation scenarios ranging from hundreds of MHz to approximately 1 GHz.

[0058] It should be understood that this solution is not limited to the specific embodiments described above. Devices and structures not described in detail herein should be understood as being implemented in a manner common to the art. Any person skilled in the art can make many possible variations and modifications to this solution, or modify it into equivalent embodiments, without departing from the scope of this solution, using the methods and techniques disclosed above. This does not affect the substantive content of this solution. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this solution, without departing from its scope, still fall within the protection scope of this solution.

Claims

1. A low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops, characterized in that: The system uses a source-switched charge pump as the main framework and a bias branch with a gain enhancement structure to form an adaptive feedback network with the charge and discharge branch. At the same time, dummy transistors are added at the nodes of the switching path to suppress transient current spikes caused by charge injection and clock feedthrough, thereby reducing control voltage ripple and reference spurious emissions.

2. The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops according to claim 1, characterized in that: The adaptive feedback network includes a first feedback network and a second feedback network, which are connected via a CMOS inverter. The first feedback network includes a discharge switch, a discharge current source, and a first auxiliary amplifier unit. The second feedback network includes a charging switch, a charging current source, and a second auxiliary amplifier unit. The input of the first auxiliary amplifier unit is connected to the gate of the discharge current source, and the output is connected to the source of the discharge current source, for adjusting and stabilizing the drain-source voltage of the discharge current source. The input of the second auxiliary amplifier unit is connected to the gate of the charging current source, and the output is connected to the source of the charging current source, for adjusting and stabilizing the drain-source voltage of the charging current source.

3. The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops according to claim 2, characterized in that: The dummy transistor is selected from the same type of transistor as the switching transistor. Its source and drain are connected together and connected to the drain of the charge pump switching transistor. The gate is connected to the reverse switching signal to generate a compensation charge in the opposite direction when the switching signal flips, thereby offsetting part of the disturbance coupled to the output node by the parasitic capacitance of the main switch.

4. The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops according to claim 3, characterized in that: The size of the dummy tube is set according to the parasitic capacitance of the discharge switch and the charge switch, as well as the size of the output glitch.

5. The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops according to claim 1, characterized in that: The bias branch of the gain enhancement structure includes a bias current mirror composed of a PMOS-side current mirror, an NMOS-side bias conversion branch, and a current source. The PMOS-side current mirror is used to generate a PMOS-side bias voltage and replicate an external reference current. The NMOS-side bias conversion branch is used to convert a stable current into an NMOS-side bias voltage. The PMOS-side bias voltage and the NMOS-side bias voltage provide stable bias current to the adaptive feedback network and each branch.

6. The low-mismatch, low-glitch charge pump circuit applied to medium- and high-speed phase-locked loops according to claim 5, characterized in that: The gain enhancement structure employs one of the following to implement the auxiliary amplification unit: a push-pull inverting amplifier based on a CMOS inverter, a single transistor amplifier, a simple common-source amplifier, a differential amplifier, or a local gain enhancement circuit.

7. A phase-locked loop structure, comprising a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator (VCO), and a frequency divider with negative feedback connected between the VCO and the frequency and phase detector; characterized in that: The charge pump employs the low-mismatch, low-glitch charge pump circuit described in any one of claims 1 to 6, applicable to medium- and high-speed phase-locked loops.

8. A phase-locked loop structure applied to an analog-to-digital converter, characterized in that: It includes an ADC core module, whose 8 parallel outputs are connected to an LVDS driver after passing through a parallel-to-serial converter. The phase-locked loop uses the ADC output clock as a reference input and generates a serial transmission clock through frequency multiplication to provide it to the parallel-to-serial converter circuit. The charge pump of the phase-locked loop adopts the low-mismatch, low-glitch charge pump circuit of any one of claims 1 to 6 for medium- and high-speed phase-locked loops.

9. The phase-locked loop structure applied to an analog-to-digital converter according to claim 8, characterized in that: The digital signals are output in parallel from 8 channels and synchronized with a 125MHz word clock.

10. The phase-locked loop structure applied to an analog-to-digital converter according to claim 8, characterized in that: The phase-locked loop generates a 1GHz serial transmission clock by frequency multiplication.

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