High gain low noise sampling phase detector based on time amplifier

Abstract

The application discloses a high-gain low-noise sampling phase discriminator based on a time amplifier, belongs to the technical field of analog integrated circuits, and is applied to a phase-locked loop; the sampling phase discriminator comprises a time amplifier, which is used for receiving a reference clock signal Ref and a feedback clock signal Div output by a frequency divider and amplifying a phase difference signal between the two; and a sampling phase discriminator module, which is connected to the time amplifier and is used for performing a sample-and-hold operation on the amplified phase difference signal and converting the amplified phase difference signal into a voltage signal. By applying a resistance-improved time amplifier (RD-TA) to an existing sampling phase discriminator, the sampling gain is greatly improved, and the noise performance is improved by halving the number of time amplifiers.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a high-gain, low-noise sampling phase detector based on a time amplifier. Background Technology

[0002] Phase-locked loop (PLL) circuits, as key components in analog integrated circuits, are widely used in radar, high-speed serial transceivers, communication systems, and other fields. The performance requirements for their output clock signals are increasingly stringent, especially regarding phase noise and jitter. In recent years, with advancements in process technology, performance improvements in traditional charge pump PLLs (CPPLLs) have reached a bottleneck. The main noise sources include phase noise from the voltage-controlled oscillator (VCO), noise from the reference input signal, and noise from the charge pump (CP). These modules are constrained by materials and process limitations, limiting their optimization potential and making it difficult to significantly improve clock purity.

[0003] To overcome the aforementioned limitations, a sampling phase-locked loop (SPLL) based on a sampling phase detector (SPD) was developed. The SPLL directly samples the reference signal using the output signal of a frequency divider. Through a sample-and-hold process, the phase difference is converted into a voltage difference, thus bypassing the charge pump circuit and eliminating the noise source introduced by the charge pump, significantly improving the clock jitter performance of the PLL. The sampling phase detector, as the core module of the SPLL, is responsible for detecting the phase difference between the reference clock and the feedback clock and outputting a pulse signal proportional to the phase difference. However, the performance of the SPD structure directly affects the overall noise suppression capability of the SPLL.

[0004] Existing SPDs can be categorized into two types based on whether they include a ramp generator and an input reference buffer: SPDs that directly sample the reference signal and SPDs with ramp generators. SPDs that directly sample the reference signal have advantages such as simple structure, low power consumption, and small area, but they suffer from problems such as low sampling gain (Kspd), poor linearity, and non-tunable gain, resulting in insufficient suppression of in-band phase noise. SPDs with ramp generators improve gain and linearity by sacrificing the phase detection range when adjusting the ramp slope, but the gain improvement is limited, and the gain drops significantly at low supply voltages. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-gain, low-noise sampling phase detector based on a time amplifier. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high-gain, low-noise sampling phase detector based on a time amplifier, applicable to a phase-locked loop; The sampling phase detector includes: The time amplifier is used to receive the reference clock signal Ref and the feedback clock signal Div output by the frequency divider, and amplify the phase difference signal between the two. The sampling phase detector module is connected to the time amplifier and is used to perform a sample-and-hold operation on the amplified phase difference signal to convert the amplified phase difference signal into a voltage signal.

[0006] In one embodiment of the present invention, the sampling phase detector module includes D flip-flops: DFF1, DFF2, DFF3, DFF4; inverters: INV1, INV2, INV3, INV4; a two-stage inverter BUF2; a high-level boost inverter HB-INV; an AND gate; and a transistor: M. 10 M 11 M 12 M 13 The components include capacitor C3, resistor R3, logic control unit, and inverter delay chain; among which, The clock input CK of D flip-flop DFF1 is connected to the reference clock signal Ref, the input D is connected to the high level VDD, and the output Q is connected to the reference clock input CR of the time amplifier, one input of the AND gate, and the input of the secondary inverter BUF2. The clock input CK of D flip-flop DFF2 is connected to the feedback clock signal Div, the input D is connected to the high level VDD, and the output Q is connected to the feedback clock input DR of the time amplifier. The other input of the AND gate is connected to the output OT of the time amplifier and the reset signal Rst of D flip-flop DFF4. The output of the AND gate, after generating a reset signal via inverter INV4, is connected to the reset signal Rst of D flip-flop DFF1 and the input of the secondary inverter BUF2. The reset signal terminal Rst of flip-flop DFF2; the input terminal of high-level boost inverter HB-INV is connected to the output terminal of the AND gate, and the output terminal is connected to the reset signal input terminal RE of the time amplifier; the output terminal of the second-stage inverter BUF2 is connected to the reset signal terminal Rst of D flip-flop DFF3 and the input terminal of inverter INV2; the output terminal of inverter INV2 is connected to the clock input terminals CK of D flip-flop DFF3 and D flip-flop DFF4; the input terminals D of D flip-flop DFF3 and D flip-flop DFF4 are connected to a high level VDD; the output terminal Q of D flip-flop DFF3 is connected to the input terminal of inverter INV1; the output terminal of inverter INV1 is connected to M... 10 The gate, M 10 The source is connected to a high-level voltage VDD, and the drain is connected to M via resistor R3. 11 The drain and M 12The drain of the D flip-flop DFF4 is connected to the input of the logic control unit, and the output of the logic control unit is connected to the input of the inverter INV3 and M. 11 The gate of the inverter, and the output of the inverter INV3 is connected to M. 12 The gate of the inverter and the input of the inverter delay chain, M 10 The drain is connected to M via resistor R3 11 The drain and M 12 The source pole, M 11 The source connection M 13 The drain and M 12 The drain, M 12 The drain of M is grounded via C3. 13 The gate is connected to the output terminal of the inverter delay chain, and the source is grounded.

[0007] In one embodiment of the present invention, transistor M 11 and M 13 For NMOS transistors, transistor M 10 and M 12 It is a PMOS transistor.

[0008] In one embodiment of the present invention, the logic control unit includes a D flip-flop DFF5, an inverter INV5, and a fixed pulse width generation logic unit; wherein, The input of inverter INV5 is connected to the output Q of D flip-flop DFF4. The output of inverter INV5 is connected to the clock input CK of D flip-flop DFF5 and the input of the fixed pulse width generation logic unit. The input D of D flip-flop DFF5 is connected to a high level VDD, the reset signal Rst is connected to the output of the fixed pulse width generation logic unit, and the output Q is connected to the input of inverter INV3 and the transistor M. 11 The gate.

[0009] In one embodiment of the present invention, the time amplifier includes D flip-flops DFF6: M1, M2, M3, M4, M5, M6, M7, M8, M9; capacitors: C1, C2; a low-voltage bootstrap circuit; resistors: R1, R2; and a two-stage inverter BUF1; wherein, The reset signal terminal of the D flip-flop DFF6 is connected to the reference clock input CR, the clock input terminal is connected to the clock input DR, and the input terminal of the secondary inverter BUF1. The input terminal is connected to a high level VDD, and the output terminal is connected to the gate of M3. The output terminal of the secondary inverter BUF1 is connected to the gate of M2. The drain of M2 is connected to the drain of M1 via resistor R1. The gate of M1 is connected to the reset signal terminal RE, and the source is connected to a high level VDD. The sources of M2 and M3 are both grounded. The drain of M3 is connected to the gate of M1 via resistor R2. Drain; one end of capacitor C1 is grounded, and the other end of capacitor C1 is connected to the drain of M1 and the gates of M4 and M5. The drain of M4 is connected to the drain of M5, the gate of M6 and the gate of M7. The drain of M6 is connected to the drain of M7, the gate of M8 and the gate of M9. The sources of M4, M6 and M8 are all connected to a high level VDD. The sources of M5, M7 and M9 are all grounded. The drains of M8 and M9 are both connected to the output terminal OT of the time amplifier.

[0010] In one embodiment of the present invention, the low-voltage bootstrap circuit includes a D flip-flop DFF7, an inverter INV6, and a capacitor C2; wherein, The input terminal of inverter INV6 is connected to the drain of transistor M1, and the output terminal is connected to the reset signal terminal Rst of D flip-flop DFF7. The input terminal D of D flip-flop DFF7 is connected to the high level VDD, the clock terminal CK is connected to the gate of transistor M1, and the output terminal Q is connected to the other end of capacitor C1 via capacitor C2.

[0011] In one embodiment of the present invention, transistors M1, M4, M6 and M8 are PMOS transistors, and transistors M2, M3, M5, M7 and M9 are NMOS transistors.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: The high-gain, low-noise sampling phase detector provided by this invention significantly improves the sampling gain by applying a resistor-modified time amplifier (RD-TA) to an existing sampling phase detector. Simultaneously, it improves noise performance by halving the number of time amplifiers. Furthermore, it proposes gain linearity enhancement techniques (changing the loop locking point to an inherently programmable phase difference instead of zero phase difference to avoid the gain nonlinearity problem of the TA caused by zero phase difference) and linear range extension techniques (increasing the initial discharge potential of the time amplifier through a low-voltage bootstrap circuit, enabling it to discharge for a longer time under the same current, thus extending the linear gain range of the time amplifier). These further enhance its robustness, providing higher sampling gain for the sampling phase-locked loop even at low supply voltages to generate even lower noise frequencies.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating the variation of SPD sampling gain with power supply voltage in existing technologies; Figure 2 This is a circuit diagram of a high-gain, low-noise sampling phase detector based on a time amplifier provided in an embodiment of the present invention; Figure 3 This is a circuit diagram of the time amplifier provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the sampling gain of a high-gain, low-noise sampling phase detector based on a time amplifier provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the calculation of the noise transfer function of a sampling phase-locked loop; Figure 6 This is another circuit diagram of a high-gain, low-noise sampling phase detector based on a time amplifier provided in this embodiment of the invention; Figure 7 This is a waveform diagram of the key node of the high-gain, low-noise sampling phase detector based on a time amplifier provided in an embodiment of the present invention. Figure 8a The waveforms showing the changes in locked phase difference caused by different programmable delays (Δt1, Δt2) in the gain linearity enhancement technology of a high-gain, low-noise sampling phase detector based on a time amplifier provided in this embodiment of the invention are as follows: Figure 8b This is a schematic diagram of the phase difference at the locking point during traditional TAPFD loop locking; Figure 8c This is a schematic diagram of the phase difference at the locking point during loop locking of a high-gain, low-noise sampling phase detector based on a time amplifier, provided in an embodiment of the present invention. Figure 9a This is a circuit diagram of a high-gain, low-noise sampling phase detector based on a time amplifier provided in an embodiment of the present invention, which extends the linear gain range of the RD-TA by using a low-voltage bootstrap circuit. Figure 9b This is a comparison diagram of the working waveforms of the high-gain low-noise sampling phase detector based on the time amplifier with and without the low-voltage bootstrap circuit provided in the embodiments of the present invention; Figure 9c The RD-TA linear K-type sampling phase detector based on a time amplifier with or without an LV-boost circuit, as provided in the embodiments of the invention, is a high-gain, low-noise sampling phase detector. TA Comparison chart of gain simulation results. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Currently, SPDs with ramp generators are generally used to improve sampling gain. By adjusting the ramp slope, the phase detection range is sacrificed to obtain better linearity and the tunability of Kspd. However, this method can only improve the gain to a limited extent, and the gain drops significantly at lower supply voltages, failing to achieve high sampling gain. Figure 1 This is a schematic diagram illustrating the variation of SPD sampling gain with power supply voltage in existing technology. For example... Figure 1 As shown, as the power supply voltage drops from 0.9V to 0.65V, the sampling gain of the sampling phase detector decreases by nearly 50%, and the PLL output noise increases by nearly 9dB.

[0017] In view of this, the present invention provides a high-gain, low-noise sampling phase detector based on a time amplifier.

[0018] Figure 2 This is a circuit diagram of a high-gain, low-noise sampling phase detector based on a time amplifier, provided in an embodiment of the present invention. Figure 2 As shown, this embodiment of the invention provides a high-gain, low-noise sampling phase detector based on a time amplifier, which is applied to a phase-locked loop; The aforementioned sampling phase detector includes: The time amplifier is used to receive the reference clock signal Ref and the feedback clock signal Div output by the frequency divider, and amplify the phase difference signal between the two. The sampling phase detector module, connected to the time amplifier, is used to perform a sample-and-hold operation on the amplified phase difference signal, converting the amplified phase difference signal into a voltage signal.

[0019] Optionally, please continue to see Figure 2 The sampling phase detector module includes D flip-flops: DFF1, DFF2, DFF3, DFF4; inverters: INV1, INV2, INV3, INV4; a two-stage inverter BUF2; a high-level boost inverter HB-INV; an AND gate; and a transistor: M. 10 M 11 M 12 M 13 The components include capacitor C3, resistor R3, logic control unit, and inverter delay chain; among which, The clock input CK of D flip-flop DFF1 is connected to the reference clock signal Ref, the input D is connected to the high level VDD, and the output Q is connected to the reference clock input CR of the time amplifier, one input of the AND gate, and the input of the second-stage inverter BUF2. The clock input CK of D flip-flop DFF2 is connected to the feedback clock signal Div, the input D is connected to the high level VDD, and the output Q is connected to the feedback clock input DR of the time amplifier. The other input of the AND gate is connected to the output OT of the time amplifier and the reset signal Rst of D flip-flop DFF4. The output of the AND gate, after generating a reset signal via inverter INV4, is connected to the reset signal Rst of D flip-flop DFF1 and DR. The reset signal terminal Rst of flip-flop DFF2 is connected; the input of the high-level boost inverter HB-INV is connected to the output of the AND gate, and its output is connected to the reset signal input RE of the time amplifier; the output of the second-stage inverter BUF2 is connected to the reset signal terminal Rst of D flip-flop DFF3 and the input of inverter INV2; the output of inverter INV2 is connected to the clock input CK of D flip-flop DFF3 and the clock input CK of D flip-flop DFF4; the inputs D of D flip-flop DFF3 and D of D flip-flop DFF4 are connected to the high-level VDD; the output Q of D flip-flop DFF3 is connected to the input of inverter INV1; the output of inverter INV1 is connected to M... 10 The gate, M 10 The source is connected to a high-level voltage VDD, and the drain is connected to M via resistor R3. 11 The drain and M 12 The drain of the circuit; the output of the D flip-flop DFF4 is connected to the input of the logic control unit, and the output of the logic control unit is connected to the input of the inverter INV3 and M. 11 The gate of the inverter, the output of the inverter INV3 is connected to M. 12 The gate and the output of the inverter delay chain, M 10 The drain is connected to M via resistor R3 11 The drain and M 12 The source pole, M 11 The source connection M 13 The drain and M 12 The drain, M 12 The drain of M is grounded via C3. 13 The gate is connected to the output of the inverter delay chain, and the source is grounded.

[0020] It should be noted that transistor M 11 For NMOS transistors, transistor M 10 and M 12 It is a PMOS transistor.

[0021] Furthermore, the logic control unit (Logic-A) includes a D flip-flop DFF5, an inverter INV5, and a fixed pulse width generation logic unit; wherein, The input of inverter INV5 is connected to the output Q of D flip-flop DFF4. The output of inverter INV5 is connected to the clock input CK of D flip-flop DFF5 and the input of the fixed pulse width generation logic unit. The input D of D flip-flop DFF5 is connected to a high level VDD, the reset signal Rst is connected to the output of the fixed pulse width generation logic unit, and the output Q is connected to the input of inverter INV3 and transistor M. 11 The gate.

[0022] Figure 3 This is a circuit diagram of a time amplifier provided in an embodiment of the present invention. Figure 3 As shown, the time amplifier includes D flip-flops DFF6: M1, M2, M3, M4, M5, M6, M7, M8, M9; capacitors: C1, C2; a low-voltage bootstrap circuit (LV Boost); resistors: R1, R2; and a two-stage inverter BUF1; wherein, The reset signal terminal of the D flip-flop DFF6 is connected to the reference clock input CR, the clock input is connected to the clock input DR, and the input of the second-stage inverter BUF1. The input is connected to a high level VDD, and the output is connected to the gate of M3. The output of the second-stage inverter BUF1 is connected to the gate of M2. The drain of M2 is connected to the drain of M1 via resistor R1. The gate of M1 is connected to the reset signal terminal RE, and the source is connected to a high level VDD. The sources of M2 and M3 are both grounded, and the drain of M3 is connected to a high level VDD via resistor R1. Resistor R2 is connected to the drain of M1; one end of capacitor C1 is grounded, and the other end of capacitor C1 is connected to the drain of M1 and the gates of M4 and M5. The drain of M4 is connected to the drain of M5, the gate of M6 and the gate of M7. The drain of M6 is connected to the drain of M7, the gate of M8 and the gate of M9. The sources of M4, M6 and M8 are all connected to the high level VDD. The sources of M5, M7 and M9 are all grounded. The drains of M8 and M9 are both connected to the output terminal OT of the time amplifier.

[0023] Specifically, the low-voltage bootstrap circuit includes a D flip-flop DFF7, an inverter INV6, and a capacitor C2; among which, The input terminal of inverter INV6 is connected to the drain of transistor M1, and the output terminal is connected to the reset signal terminal Rst of D flip-flop DFF7. The input terminal D of D flip-flop DFF7 is connected to the high level VDD, the clock terminal CK is connected to the gate of transistor M1, and the output terminal Q is connected to the other end of capacitor C1 via capacitor C2.

[0024] Optionally, transistors M1, M4, M6 and M8 are PMOS transistors, and transistors M2, M3, M5, M7 and M9 are NMOS transistors.

[0025] In this embodiment, because the application range of the sampling phase detector module needs to be extended to low power supply voltage, a rechargeable SPD is used. Simultaneously, the reset switch M13 is used to set the output potential V before the SPD begins charging in each reference cycle. SPD Reset to ground (GND) to ensure each sampling cycle starts from a defined initial state. To maximize the actual gain of the sampling process, the sampling phase detector module employs dual-switch control, with the large transmission gate (TG) switch control signal arriving first to minimize startup time and achieve the fastest sampling operation. Furthermore, since the transmission gate closes first and only turns on again after the upper PMOS transistor M10 is turned off, and is reset by the M13 control signal after sampling, this avoids the situation where only M10 is switched off. 10 The residual charge in the drain caused by the switch design interferes with the sampling voltage. Since this design uses a master-slave sampling filter, the VCO control voltage will not change abruptly, and the output V will be stably controlled in each reference cycle. SPD The loop locks up when the voltage reaches the preset value Vcm.

[0026] Existing sampling phase detectors use the feedback clock signal output from a frequency divider to sample a reference clock signal. Through a sample-and-hold process, the phase difference between the feedback clock signal and the reference clock signal is directly converted into a corresponding voltage difference. The sampling gain is expressed as:

[0027] In the formula, Indicates the frequency of the reference clock signal. and Both represent sampling gain, with units of V / rad and V / s, respectively.

[0028] Figure 4 This is a schematic diagram of the sampling gain of a high-gain, low-noise sampling phase detector based on a time amplifier provided in an embodiment of the present invention. Figure 4 As shown, in this embodiment, the high-gain, low-noise sampling phase detector based on a time amplifier is equivalent to multiplying the gain formula of the existing sampling phase detector by a gain factor of the time amplifier (TA). ,Right now:

[0029] The time amplifier can control the magnitude of the output node discharge current by using the phase difference between the two input signals, the reference clock signal Ref and the feedback clock signal Div. Specifically, when only one clock edge of the input signal arrives, the time amplifier initiates a large current discharge; when both clock edges of the input signals arrive, the time amplifier initiates a small current discharge. When the voltage of the output node drops to a preset threshold voltage, the output signal flips, thus completing the amplification of the input phase difference.

[0030] During the discharge process, the ratio of the large current to the small current directly determines the gain of the time amplifier. For example, if the ratio of the large current to the small current is 10:1, then a 10ps phase difference at input will be amplified to 100ps. This effective amplification of small phase differences significantly improves the frequency locking accuracy of the phase-locked loop, thereby achieving more precise phase synchronization.

[0031] It is worth noting that since the phase-locked loop aligns the feedback clock signal Div with the reference clock signal Ref, two time amplifiers are typically required to output a signal with a specific phase relationship. The single-time amplifier designed in this invention can effectively overcome the mismatch problem inherent in the dual-time amplifier structure while maintaining high gain performance, further optimizing frequency stability.

[0032] The optimized time amplifier can provide [performance] within the normal operating range. The high gain amplification factor enables the aforementioned high-gain, low-noise sampling phase detector based on a time amplifier to achieve a sampling gain improvement of several to tens of times compared to existing sampling phase detectors. Existing sampling phase detectors, due to the inherent parasitic parameters of the MOS transistor, struggle to achieve such high gain levels under standard operating conditions.

[0033] This significant gain boost results in a major improvement in noise performance. Figure 5 This is a schematic diagram illustrating the calculation of the noise transfer function of a sampling phase-locked loop, as shown below. Figure 5 As shown, in the noise transfer function of the sampling phase-locked loop, This represents the transfer function of a low-pass filter. n_ref、 n_vco、 n_div represents the phase noise of the reference clock signal, the voltage-controlled oscillator, and the frequency divider, respectively. , These represent the voltage noise of the sampling phase detector and the low-pass filter, respectively. In the noise transfer function excluding the reference clock signal and the frequency divider, the gain factor of the sampling phase detector is... All of these are located only in the denominator, which means that increasing the gain of the sampling phase detector can greatly suppress the in-band noise of the sampling phase detector itself, the low-pass filter, and the VCO.

[0034] In this embodiment, the high-gain characteristics of the time amplifier effectively suppress the noise contribution of the second-stage sampling phase detector module, making the noise of the TA pulse generator the main source of noise in the system. To further optimize the noise performance of the TA, this embodiment adopts an improved low-noise resistive discharge TA structure (RD-TAPFD) based on the existing current source TA structure. However, even with the above optimization measures, the noise contribution of the TA is still quite significant. Therefore, this embodiment further optimizes the number of TAs in the TAPFD from the traditional dual TA structure to a single TA design. This not only reduces the TA noise by 3dB, but also achieves amplification and phase detection functions with a single TA, effectively avoiding the phase noise performance degradation problem caused by device mismatch in the dual TA structure.

[0035] Furthermore, theoretical analysis shows that the sampling gain of this structure can be flexibly adjusted by the gain of either the time amplifier or the sampling phase detector, ensuring a stable low-jitter clock signal output over a wide bandwidth and providing a reliable guarantee for the stable operation of high-performance phase-locked loops in various application scenarios.

[0036] Figure 6 This is another circuit diagram of a high-gain, low-noise sampling phase detector based on a time amplifier provided in this embodiment of the invention. It should be noted that the D flip-flops (DFF1-DFF5) used in the sampling phase detector module are all true single-phase clock flip-flops (TSPC) to ensure stable timing characteristics even under low-voltage conditions. The low-noise resistor discharge type time amplifier (RD-TA) structure used in this embodiment utilizes the phase difference between the feedback clock signal Div and the reference clock signal Ref output by the frequency divider to activate resistors R1 and R2 of the time amplifier, generating a large current: when the rising edge of the feedback clock signal Div arrives but the rising edge of the reference clock signal Ref has not arrived, the output of S1 / S2 is high level 1, both switches are on, and the charge stored in C1 discharges with a large current IB1. When the rising edge of the reference clock signal Ref arrives, only the large resistor R2 discharges with a small current IB2 for the remaining time of the current cycle. Therefore, the ratio of large current to small current is The load capacitor C1 is discharged using two current operating modes of the time amplifier, generating two slopes with different gradients. Vx is the discharge potential signal inside the time amplifier. When Vx drops to the preset inverter switching threshold voltage Vth, the output signal Ts of the time amplifier flips to 1, thereby amplifying the phase difference. The phase change of the feedback clock signal Div will be amplified at the output. The input phase shift Δt will result in a change in the sampled voltage. For a traditional SPD, this shift is several times greater. For a time-amplifier type sampling phase detector consisting of a TA pulse generator and a sampling phase detector module, when the input phase shift is Δt, it will cause a change in the charging pulse. This results in a change in the sampled voltage of As can be seen, the sampling gain of the high-gain, low-noise sampling phase detector based on the time amplifier is significantly improved. At a supply voltage of 0.65V, the sampling gain of TASPD can easily reach 100GV / s.

[0037] Figure 7 These are the operating waveforms of each node in the high-gain, low-noise sampling phase detector based on a time amplifier provided in this embodiment of the invention. For example... Figures 6-7 As shown, S UP B represents the inverted signal of the DFF5 output signal Q5. DN This indicates the output signal of DFF4. DFF1-DFF5 are all triggered by a rising edge clock, with output Q=1 and V. x S represents the potential signal indicating the internal discharge of the time amplifier. DN B DN The signal generated after the signal is processed by the logic control unit. The function of the logic control unit is to convert B... DN The falling edge of the signal and S DN The rising edge of the signal is aligned, and it is S. DN The signal is set to a value greater than B. DN A wider fixed-width pulse for the signal. When S UP Signal and S DN When all signal levels are 0, TASPD turns on and begins to supply V. SPD Charge.

[0038] When the rising edge of the feedback clock signal Div arrives first, V X Discharge with a large current until the rising edge of the reference clock signal Ref arrives. After a delay Δt in the delay chain, the rising edge of the reference clock signal Ref reaches the reset signal Rst of DFF5, resetting the output signal Q5 of DFF5 to 0. However, due to S... UP It is the inverted signal of Q5, therefore S UPThe output flips to 1. When Vx drops to the preset inverter flipping threshold voltage Vth, the output signal Ts of the time amplifier flips to 1, where the pulse bandwidth of Ts is simplified to a delay after an AND gate. After this delay, the outputs of DFF1 and DFF2 are reset to 0, and the 0 signal output of DFF1 is delayed again by Δt+t1 before controlling the output signals of DFF4 and DFF5 to flip to 1.

[0039] It should be noted that, Figure 7 The blue dashed line represents the signal change trend in the next working cycle. When the input phase difference of the feedback clock signal Div changes by Δφ between two consecutive cycles, the final result is reflected in the pulse width difference of the output switch control signal. This change in pulse width causes the output voltage difference to become the output voltage difference of a traditional sampling phase detector. times.

[0040] As mentioned above, this charging operation introduces a fixed phase difference into the phase-locked loop, such as Figures 8a-8c As shown, this fixed phase difference allows TASPD to perform a fixed-duration charging operation in each cycle and stabilize the sampled voltage in the locked state at Vcm. Figure 8b As shown, this characteristic allows the sampling phase detector to avoid the nonlinear effects caused by the gain of a conventional TAPFD being locked near zero phase difference. Meanwhile, as... Figure 8c As shown, this embodiment uses a single time amplifier, which can reduce the gain amplification range by 50%. Because the reference input signal Ref arrives before the feedback clock signal Div due to the single time amplifier, the high-gain, low-noise sampling phase detector based on the time amplifier will lose its gain amplification effect. The gain is the same as the existing SPD, 1. To this end, a programmable delay Δt of 200ps to 600ps was added to reduce the detection range required by the TASPD (adjusting the fixed phase difference during locking to ensure locking at...). (Magnified and linear position).

[0041] like Figures 8a-8c As shown, the initial charging time of TASPD can be changed by adjusting Δt. When the delay time is adjusted from Δt1 to Δt2, the charging pulse will become shorter, resulting in V SPD Unable to be charged to the predetermined level V cm Therefore, the loop will automatically adjust to increase the phase difference Δφ to increase the charging time so that V SPD Reaching the predetermined level V cm More importantly, the introduction of programmable Δt prevents TA-SPLL from locking in error. This ensures that the sampling point is within the linear gain amplification range of the time amplifier (too small a Δt results in gain nonlinearity, while too large a Δt exceeds the gain amplification range of the time amplifier). However, the introduction of a programmable delay Δt will lead to abnormal gain in extreme negative phase difference cases, such as: S UP Signal and S DN The signals have overlapping zero potentials, requiring the circuit to charge. However, due to the time offset introduced by Δt, the two signals do not overlap, preventing charging and resulting in an incorrect gain polarity. Alternatively, charging may not be necessary, but Δt causes S to... UP Signal and S DN Signal period overlap leads to erroneous charging operations. The secondary reset operation performed by DFF4 and DFF5 ensures that the introduced Δt does not affect the sampling phase detector across the entire operating phase difference range. The monotonic gain within the sensor ensures that the sampling phase detector can operate normally under any phase difference, thereby maintaining a stable locking effect.

[0042] Furthermore, this embodiment employs a low-voltage bootstrap circuit based on the law of charge conservation to further extend the linear range while reducing the requirement for Δt. For example... Figures 9a-9c As shown, the effective linear gain range of the time amplifier drops significantly when operating at low supply voltages; therefore, an LV-Boost circuit is introduced to improve this. Figure 9c As shown, by introducing a low-voltage bootstrap circuit, the linear variation range of the charging pulse is increased from 22ps to 35ps. It should be noted that during the boost phase, the voltage VX may exceed the supply voltage. Since the source and drain terminals of the MOSFET can be interchanged, to prevent the gate-drain voltage difference (VX) of M1 from exceeding the supply voltage, [further measures are needed]. GD If the voltage exceeds the threshold voltage, it will trigger an incorrect turn-on. A high-level boost inverter (HB-INV) must be introduced into the gate of M1 to synchronously increase the gate voltage.

[0043] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows: The high-gain, low-noise sampling phase detector provided by this invention significantly improves the sampling gain by applying a resistor-modified time amplifier (RD-TA) to an existing sampling phase detector. Simultaneously, it improves noise performance by halving the number of time amplifiers. Furthermore, it proposes gain linearity enhancement techniques (changing the loop locking point to an inherently programmable phase difference instead of zero phase difference to avoid the gain nonlinearity problem of the TA caused by zero phase difference) and linear range extension techniques (increasing the initial discharge potential of the time amplifier through a low-voltage bootstrap circuit, enabling it to discharge for a longer time under the same current, thus extending the linear gain range of the time amplifier). These further enhance its robustness, providing higher sampling gain for the sampling phase-locked loop even at low supply voltages to generate even lower noise frequencies.

[0044] In the description of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-gain, low-noise sampling phase detector based on a time amplifier, characterized in that, Applied to phase-locked loops; The sampling phase detector includes: The time amplifier is used to receive the reference clock signal Ref and the feedback clock signal Div output by the frequency divider, and amplify the phase difference signal between the two. The sampling phase detector module is connected to the time amplifier and is used to perform a sample-and-hold operation on the amplified phase difference signal to convert the amplified phase difference signal into a voltage signal.

2. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 1, characterized in that, The sampling phase detector module includes D flip-flops: DFF1, DFF2, DFF3, DFF4; inverters: INV1, INV2, INV3, INV4; a two-stage inverter BUF2; a high-level boost inverter HB-INV; an AND gate; and a transistor: M. 10 M 11 M 12 M 13 The components include capacitor C3, resistor R3, logic control unit, and inverter delay chain; among which, The clock input CK of D flip-flop DFF1 is connected to the reference clock signal Ref, the input D is connected to the high level VDD, and the output Q is connected to the reference clock input CR of the time amplifier, one input of the AND gate, and the input of the secondary inverter BUF2. The clock input CK of D flip-flop DFF2 is connected to the feedback clock signal Div, the input D is connected to the high level VDD, and the output Q is connected to the feedback clock input DR of the time amplifier. The other input of the AND gate is connected to the output OT of the time amplifier and the reset signal Rst of D flip-flop DFF4. The output of the AND gate, after generating a reset signal via inverter INV4, is connected to the reset signal Rst of D flip-flop DFF1 and the input of the secondary inverter BUF2. The reset signal terminal Rst of flip-flop DFF2; the input terminal of high-level boost inverter HB-INV is connected to the output terminal of the AND gate, and the output terminal is connected to the reset signal input terminal RE of the time amplifier; the output terminal of the second-stage inverter BUF2 is connected to the reset signal terminal Rst of D flip-flop DFF3 and the input terminal of inverter INV2; the output terminal of inverter INV2 is connected to the clock input terminals CK of D flip-flop DFF3 and D flip-flop DFF4; the input terminals D of D flip-flop DFF3 and D flip-flop DFF4 are connected to a high level VDD; the output terminal Q of D flip-flop DFF3 is connected to the input terminal of inverter INV1; the output terminal of inverter INV1 is connected to M... 10 The gate, M 10 The source is connected to a high-level voltage VDD, and the drain is connected to M via resistor R3. 11 The drain and M 12 The drain of the D flip-flop DFF4 is connected to the input of the logic control unit, and the output of the logic control unit is connected to the input of the inverter INV3 and M. 11 The gate of the inverter, and the output of the inverter INV3 is connected to M. 12 The gate of the inverter and the input of the inverter delay chain, M 10 The drain is connected to M via resistor R3 11 The drain and M 12 The source, M 11 The source connection M 13 The drain and M 12 The drain, M 12 The drain of M is grounded via C3. 13 The gate is connected to the output terminal of the inverter delay chain, and the source is grounded.

3. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 2, characterized in that, Transistor M 11 For NMOS transistors, transistor M 10 and M 12 It is a PMOS transistor.

4. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 3, characterized in that, The logic control unit includes a D flip-flop DFF5, an inverter INV5, and a fixed pulse width generation logic unit; wherein... The input of inverter INV5 is connected to the output Q of D flip-flop DFF4. The output of inverter INV5 is connected to the clock input CK of D flip-flop DFF5 and the input of the fixed pulse width generation logic unit. The input D of D flip-flop DFF5 is connected to a high level VDD, the reset signal Rst is connected to the output of the fixed pulse width generation logic unit, and the output Q is connected to the input of inverter INV3 and the transistor M. 11 The gate.

5. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 4, characterized in that, The time amplifier includes D flip-flops DFF6: M1, M2, M3, M4, M5, M6, M7, M8, M9; capacitors: C1, C2; a low-voltage bootstrap circuit; resistors: R1, R2; and a two-stage inverter BUF1; wherein, The reset signal terminal of the D flip-flop DFF6 is connected to the reference clock input CR, the clock input terminal is connected to the clock input DR, and the input terminal of the secondary inverter BUF1. The input terminal is connected to a high level VDD, and the output terminal is connected to the gate of M3. The output terminal of the secondary inverter BUF1 is connected to the gate of M2. The drain of M2 is connected to the drain of M1 via resistor R1. The gate of M1 is connected to the reset signal terminal RE, and the source is connected to a high level VDD. The sources of M2 and M3 are both grounded. The drain of M3 is connected to the gate of M1 via resistor R2. Drain; one end of capacitor C1 is grounded, and the other end of capacitor C1 is connected to the drain of M1 and the gates of M4 and M5. The drain of M4 is connected to the drain of M5, the gate of M6 and the gate of M7. The drain of M6 is connected to the drain of M7, the gate of M8 and the gate of M9. The sources of M4, M6 and M8 are all connected to a high level VDD. The sources of M5, M7 and M9 are all grounded. The drains of M8 and M9 are both connected to the output terminal OT of the time amplifier.

6. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 5, characterized in that, The low-voltage bootstrap circuit includes a D flip-flop DFF7, an inverter INV6, and a capacitor C2; wherein... The input terminal of inverter INV6 is connected to the drain of transistor M1, and the output terminal is connected to the reset signal terminal Rst of D flip-flop DFF7. The input terminal D of D flip-flop DFF7 is connected to the high level VDD, the clock terminal CK is connected to the gate of transistor M1, and the output terminal Q is connected to the other end of capacitor C1 via capacitor C2.

7. The high-gain, low-noise sampling phase detector based on a time amplifier according to claim 6, characterized in that, Transistors M1, M4, M6, and M8 are PMOS transistors, while transistors M2, M3, M5, M7, and M9 are NMOS transistors.

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