High-frequency clock generation method applied to anti-radiation phase-locked loop

Abstract

This invention discloses a high-frequency clock generation method for radiation-hardened phase-locked loops (PLLs). The method involves using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals respectively. Four corresponding low-frequency voters then vote on the high and low levels of the three in-phase signals to suppress single-event upsets (SEE) interference, outputting synchronized four-phase quadrature low-frequency clock signals. These signals are then input to a multimode phase synthesizer (MMS). The MMS synthesizer selectively performs frequency doubling or quadrupling of the input signals based on the mode control signal configuration, directly generating the desired high-frequency clock. This invention effectively improves radiation hardness through a redundant voting mechanism, avoiding the additional power consumption, SEE sensitivity, and phase noise degradation problems associated with traditional long frequency divider chains. It achieves high-performance, configurable, and highly reliable high-frequency clock generation in radiation environments.

Description

Technical Field

[0001] This invention belongs to the field of radiation hardening technology for radio frequency integrated circuits, and relates to a high-frequency clock generation method for radiation-hardened phase-locked loops. Background Technology

[0002] Phase-locked loops (PLLs), as the core clock management module of modern electronic systems, directly determine the timing integrity and signal quality of functions such as communication, computing, and storage. In high-radiation applications such as aerospace, aviation, nuclear facilities, and high-energy physics, electronic devices are highly susceptible to radiation interference such as single-event effects, leading to internal state disorder of the PLL and causing frequency drift, phase abrupt changes, or even complete loss of lock in the output clock, posing a serious threat to the reliability of the entire system. Therefore, developing PLL technology with high radiation tolerance, especially the key high-frequency clock generation unit, has become paramount in the design of highly reliable electronic systems.

[0003] Traditional high-frequency clock generation methods typically use high-frequency oscillators directly. While these methods can achieve high frequencies, their noise performance is poor and they are difficult to harden using methods such as triple-modular redundancy. Furthermore, these methods place extremely stringent timing requirements on the frequency divider circuits. Longer divider chains not only introduce additional power consumption but also increase the risk of single-event faults (SIFs) along the signal path. If a fault occurs at a critical node, it will directly lead to abnormal clock output and reduce system reliability. In addition, after multiple frequency divisions and multiplications, the phase noise deteriorates, especially near the carrier frequency, severely impacting the timing accuracy of the high-frequency clock.

[0004] Therefore, existing technologies struggle to simultaneously achieve pure high-frequency clock generation, wide-range tuning, low-power operation, and high reliability in radiated environments. Designing a novel clock generation architecture capable of directly generating high-quality high-frequency or frequency-multiplied signals in radiated environments, circumventing the drawbacks of long frequency divider chains, and effectively integrating or surpassing the advantages of existing VCO designs, thereby fundamentally improving the performance and reliability of radiation-resistant phase-locked loops, has become a core technical challenge urgently needing breakthroughs in this field. Summary of the Invention

[0005] The purpose of this invention is to provide a high-frequency clock generation method for radiation-resistant phase-locked loops, which solves the problem that existing technologies cannot simultaneously achieve pure generation, wide-range tuning, low-power operation, and high-reliability operation of high-frequency clocks in radiation environments.

[0006] The technical solution adopted in this invention is a high-frequency clock generation method applied to radiation-resistant phase-locked loops. This method involves using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals respectively. Four corresponding low-frequency voters then vote on the high and low levels of the three in-phase signals, outputting a synchronized four-phase quadrature low-frequency clock signal based on the voting results. This four-phase quadrature low-frequency clock signal is then input to a multi-mode phase synthesizer. The multi-mode phase synthesizer selectively performs high-frequency synthesis on the input signal according to the configuration of the mode control signal, directly generating the required high-frequency clock. The low-frequency value of the low-frequency voters is ≤2GHz.

[0007] The low-frequency voter is used to vote on the high and low levels of the three in-phase signals. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

[0008] The three 4-phase output clocks are designated as the first, second, and third 4-phase output clocks. The four low-frequency voting units are designated as the first, second, third, and fourth low-frequency voting units. The first low-frequency voting unit receives the high and low levels of the 0° signals output from the first, second, and third 4-phase output clocks as inputs. By voting on the high and low levels of these three 0° signals, it outputs the 0° clock. The second low-frequency voting unit receives the high and low levels of the 90° signals output from the first, second, and third 4-phase output clocks as inputs. The first input signal is a low level, and the output is a 90° clock. The second input signal is a 90° clock. The third low-frequency voter input is the high and low levels of the 180° signals output by the first, second, and third 4-phase output clocks, and the output is a 180° clock. The fourth low-frequency voter input is the high and low levels of the 270° signals output by the first, second, and third 4-phase output clocks, and the output is a 270° clock. The first input signal of the multimode phase synthesizer is a 0° clock, the second input signal is a 90° clock, the third input signal is a 180° clock, and the fourth input signal is a 270° clock. The output is a high-frequency clock.

[0009] The low-frequency voting circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth PMOS, a fifth PMOS, a sixth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, and a sixth NMOS. The source of the first PMOS is connected to the power supply, the drain is connected to the source of the second PMOS, and the gate is connected to the first input terminal of the low-frequency voting circuit. The drain of the second PMOS is connected to the output terminal of the low-frequency voting circuit, and the gate is connected to the third input terminal. The source of the third PMOS is connected to the power supply, the drain is connected to the source of the fourth PMOS, and the gate is connected to the third input terminal of the low-frequency voting circuit. The drain of the fourth PMOS is connected to the output terminal of the low-frequency voting circuit, and the gate is connected to the second input terminal. The source of the fifth PMOS is connected to the power supply. The drain of the first NMOS is connected to the source of the sixth PMOS, and its gate is connected to the second input terminal of the low-frequency voter. The drain of the sixth PMOS is connected to the output terminal of the low-frequency voter, and its gate is connected to the first input terminal. The source of the first NMOS is grounded, and its drain is connected to the source of the second NMOS, and its gate is connected to the third input terminal of the low-frequency voter. The drain of the second NMOS is connected to the output terminal, and its gate is connected to the first input terminal. The source of the third NMOS is grounded, and its drain is connected to the source of the fourth NMOS, and its gate is connected to the second input terminal of the low-frequency voter. The drain of the fourth NMOS is connected to the output terminal, and its gate is connected to the third input terminal. The source of the fifth NMOS is connected to ground, and its drain is connected to the source of the sixth NMOS, and its gate is connected to the first input terminal of the low-frequency voter. The drain of the sixth NMOS is connected to the output terminal, and its gate is connected to the second input terminal.

[0010] The multimode phase synthesizer selectively multiplies or quadruples the input signal according to the configuration of the mode control signal to generate the required high-frequency clock.

[0011] The multimode phase synthesizer includes a first PMOS, a second PMOS, a third PMOS, a fourth PMOS, a fifth PMOS, a sixth PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, and a first capacitor. The gate of the first PMOS is grounded, its source is connected to the power supply, and its drain is connected to the sources of the third and fourth PMOS. The gate of the second PMOS is connected to the inverted mode control signal, its source is connected to the power supply, and its drain is connected to the sources of the fifth and sixth PMOS. The gate of the third PMOS is connected to the 0° clock signal, and its drain is connected to the output terminal. The gate of the fourth PMOS is connected to the 180° clock signal, and its drain is connected to the output terminal. The fifth PMOS... The gate of the S-type PMOS is connected to the 0° clock, and its drain is connected to the output terminal. The gate of the sixth PMOS is connected to the 270° clock, and its drain is connected to the output terminal. The gate of the first NMOS is connected to the power supply, its source is grounded, and its drain is connected to the source of the third and fourth NMOS. The gate of the second NMOS is connected to the mode control signal, its source is grounded, and its drain is connected to the source of the fifth and sixth NMOS. The gate of the third NMOS is connected to the 0° clock, and its drain is connected to the output terminal. The gate of the fourth NMOS is connected to the 180° clock, and its drain is connected to the output terminal. The gate of the fifth NMOS is connected to the 90° clock, and its drain is connected to the output terminal. The gate of the sixth NMOS is connected to the 270° clock, and its drain is connected to the output terminal. One end of the first capacitor is connected to the output terminal, and the other end is grounded.

[0012] When the mode control signal is 0, both the second NMOS and the second PMOS are turned off. At this time, the left half of the multimode phase synthesizer is working. Since the fundamental signals of the 0° clock and the 180° clock are out of phase, the odd harmonics of the output current are canceled out, and the remaining even harmonic components achieve frequency doubling.

[0013] When the mode control signal = 1, both the second NMOS and the second PMOS are turned on. At this time, the multimode phase synthesizer is affected by the 4-phase clock signal. Each phase signal generates a current pulse in its positive half-cycle. The 4-phase clock generates 4 mutually staggered current pulses, which are superimposed at the output to generate a 4-fold frequency multiplication.

[0014] The beneficial effects of this invention are as follows: It effectively resists interference such as single-event upsets through a low-frequency voting mechanism, generating a pure orthogonal signal. This signal directly drives the multimode phase synthesizer. Without using long frequency division or frequency multiplication chains, it significantly reduces power consumption and avoids increasing jitter. The multimode phase synthesizer can perform frequency multiplication by 2 or 4 according to the mode selection to flexibly generate the required high-frequency clock. While ensuring anti-radiation performance, it achieves efficient and configurable high-frequency clock generation. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the high-frequency clock generation method of the present invention applied to radiation-resistant phase-locked loops; Figure 2 This is a structural diagram of the low-frequency voting device in the high-frequency clock generation method of the radiation-resistant phase-locked loop of the present invention; Figure 3 This is a structural diagram of the multimode phase synthesizer in the high-frequency clock generation method of the radiation-resistant phase-locked loop of the present invention; Figure 4 This is a diagram of the output signal of the multimode phase synthesizer when the mode control signal Mode is 0 in the high-frequency clock generation method of the radiation-resistant phase-locked loop of the present invention; Figure 5 This is a diagram of the output signal of the multimode phase synthesizer when the mode control signal Mode is 1 in the high-frequency clock generation method of the radiation-resistant phase-locked loop of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0017] Example 1 See Figure 1 A high-frequency clock generation method for radiation-hardened phase-locked loops (PLLs) includes using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals respectively. Four corresponding low-frequency voters then vote on the high and low levels of the three in-phase signals, outputting synchronized four-phase quadrature low-frequency clock signals based on the voting results. This suppresses single-event upsets (SEE) and produces clean four-phase quadrature low-frequency clock signals, where the low-frequency values ​​of the low-frequency voters and the four-phase quadrature low-frequency clock signals are both ≤2GHz. These four-phase quadrature low-frequency clock signals are then input to a multimode phase synthesizer (MMS). The MMS synthesizer selectively performs frequency doubling or quadrupling of the input signals based on the mode control signal configuration to directly generate the desired high-frequency clock. This invention effectively improves radiation hardness through a redundant voting mechanism, avoiding the additional power consumption, SEE sensitivity, and phase noise degradation problems associated with traditional long frequency divider chains. It achieves high-performance, configurable, and highly reliable high-frequency clock generation in radiation environments.

[0018] Example 2 A high-frequency clock generation method for radiation-resistant phase-locked loops includes using three 4-phase output clocks to generate 0°, 90°, 180° and 270° phase signals respectively. The three 4-phase output clocks are designated as the first 4-phase output clock, the second 4-phase output clock, and the third 4-phase output clock. The high and low levels of the three in-phase signals are voted on by four corresponding low-frequency voters. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

[0019] The four low-frequency voting units are designated as the first, second, third, and fourth low-frequency voting units, with a low-frequency value ≤ 2GHz. The first low-frequency voting unit receives the high and low levels of the 0° signal output from the first, second, and third four-phase clock outputs as inputs. By performing low-frequency voting on the high and low levels of the three 0° signals, it outputs the 0° clock CK0P. The second low-frequency voting unit receives the high and low levels of the 90° signal output from the first, second, and third four-phase clock outputs as inputs, and outputs the 90° clock CK90P. The third low-frequency voting unit receives the high and low levels of the 180° signal output from the first, second, and third four-phase clock outputs as inputs, and outputs the 180° clock CK180P. The fourth low-frequency voting unit receives the high and low levels of the 270° signal output from the first, second, and third four-phase clock outputs as inputs, and outputs the 270° clock CK270P.

[0020] These four-phase quadrature low-frequency clock signals are then input into a multimode phase synthesizer. The multimode phase synthesizer selectively multiplies or quadruples the input signals according to the configuration of the mode control signal to directly generate the required high-frequency clock.

[0021] Example 3 A high-frequency clock generation method for radiation-resistant phase-locked loops includes using three 4-phase output clocks to generate 0°, 90°, 180° and 270° phase signals respectively. The three 4-phase output clocks are designated as the first 4-phase output clock, the second 4-phase output clock, and the third 4-phase output clock. The high and low levels of the three in-phase signals are voted on by four corresponding low-frequency voters. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output. The four low-frequency voting devices are designated as the first low-frequency voting device, the second low-frequency voting device, the third low-frequency voting device, and the fourth low-frequency voting device. The first low-frequency voting device receives the high and low levels of the 0° signal output from the first, second, and third four-phase output clocks as inputs. By performing low-frequency voting on the high and low levels of the three 0° signals, it outputs the 0° clock CK0P. The second low-frequency voting device receives the high and low levels of the 90° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 90° clock CK90P. The third low-frequency voting device receives the high and low levels of the 180° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 180° clock CK180P. The fourth low-frequency voting device receives the high and low levels of the 270° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 270° clock CK270P.

[0022] See Figure 2The low-frequency voting unit has a low-frequency value ≤ 2GHz. It includes a first PMOS P1′, a second PMOS P2′, a third PMOS P3′, a fourth PMOS P4′, a fifth PMOS P5′, a sixth PMOS P6′, a first NMOS N1′, a second NMOS N2′, a third NMOS N3′, a fourth NMOS N4′, a fifth NMOS N5′, and a sixth NMOS N6′. The source of the first PMOS P1′ is connected to the power supply, its drain is connected to the source of the second PMOS P2′, and its gate is connected to the first input terminal A of the low-frequency voting unit. The drain of the second PMOS P2′ is connected to the output terminal of the low-frequency voting unit, and its gate is connected to the third input terminal C. The source of the third PMOS P3′ is connected to the power supply, its drain is connected to the source of the fourth PMOS P4′, and its gate is connected to the third input terminal C of the low-frequency voting unit. The drain of the fourth PMOS P4′ is connected to the output terminal of the low-frequency voting unit, and its gate is connected to the second input terminal B. The source of the fifth PMOS P5′ is connected to the power supply, and its drain is connected to the sixth PMOS P6′. The source and gate of P6′ are connected to the second input terminal B of the low-frequency voter. The drain of the sixth PMOS P6′ is connected to the output terminal of the low-frequency voter, and its gate is connected to the first input terminal A. The source of the first NMOS N1′ is grounded, and its drain is connected to the source of the second NMOS N2′. Its gate is connected to the third input terminal C of the low-frequency voter. The drain of the second NMOS N2′ is connected to the output terminal, and its gate is connected to the first input terminal A. The source of the third NMOS N3′ is grounded, and its drain is connected to the source of the fourth NMOS N4′. Its gate is connected to the second input terminal B of the low-frequency voter. The drain of the fourth NMOS N4′ is connected to the output terminal, and its gate is connected to the third input terminal C. The source of the fifth NMOS N5′ is connected to ground, and its drain is connected to the source of the sixth NMOS N6′. Its gate is connected to the first input terminal A of the low-frequency voter. The drain of the sixth NMOS N6′ is connected to the output terminal, and its gate is connected to the second input terminal B. The inputs of the first, second, and third input terminals are the high and low levels of the three in-phase signals output by the three 4-phase output clocks, respectively.

[0023] The low-frequency voting mechanism effectively resists interference such as single-event upsets, generating pure orthogonal signals. These four-phase orthogonal low-frequency clock signals are then input into a multimode phase synthesizer. The multimode phase synthesizer selectively performs frequency doubling or quadrupling of the input signals according to the configuration of the mode control signal, directly generating the required high-frequency clock.

[0024] Example 4 A high-frequency clock generation method for radiation-resistant phase-locked loops includes using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals respectively. The three 4-phase output clocks are designated as a first 4-phase output clock, a second 4-phase output clock, and a third 4-phase output clock. Four corresponding low-frequency voters are used to vote on the high and low levels of the three in-phase signals. The low-frequency values ​​of these four low-frequency voters are ≤2GHz. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

[0025] The low-frequency voting circuit includes a first PMOS P1′, a second PMOS P2′, a third PMOS P3′, a fourth PMOS P4′, a fifth PMOS P5′, a sixth PMOS P6′, a first NMOS N1′, a second NMOS N2′, a third NMOS N3′, a fourth NMOS N4′, a fifth NMOS N5′, and a sixth NMOS N6′. The source of the first PMOS P1′ is connected to the power supply, its drain is connected to the source of the second PMOS P2′, and its gate is connected to the first input terminal A of the low-frequency voting circuit. The drain of the second PMOS P2′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the third input terminal C. The source of the third PMOS P3′ is connected to the power supply, its drain is connected to the source of the fourth PMOS P4′, and its gate is connected to the third input terminal C of the low-frequency voting circuit. The drain of the fourth PMOS P4′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the second input terminal B. The source of the fifth PMOS P5′ is connected to the power supply, its drain is connected to the source of the sixth PMOS P6′, and its gate is connected to the second input terminal B of the low-frequency voting circuit. The drain of P6′ is connected to the output of the low-frequency voter, and its gate is connected to the first input terminal A. The source of the first NMOS N1′ is grounded, its drain is connected to the source of the second NMOS N2′, and its gate is connected to the third input terminal C of the low-frequency voter. The drain of the second NMOS N2′ is connected to the output terminal, and its gate is connected to the first input terminal A. The source of the third NMOS N3′ is grounded, its drain is connected to the source of the fourth NMOS N4′, and its gate is connected to the second input terminal B of the low-frequency voter. The drain of the fourth NMOS N4′ is connected to the output terminal, and its gate is connected to the third input terminal C. The source of the fifth NMOS N5′ is connected to ground, its drain is connected to the source of the sixth NMOS N6′, and its gate is connected to the first input terminal A of the low-frequency voter. The drain of the sixth NMOS N6′ is connected to the output terminal, and its gate is connected to the second input terminal B. The inputs of the first, second, and third input terminals are the high and low levels of the three in-phase signals output by the three 4-phase output clocks, respectively.

[0026] The four low-frequency voting devices are designated as the first low-frequency voting device, the second low-frequency voting device, the third low-frequency voting device, and the fourth low-frequency voting device. The first low-frequency voting device receives the high and low levels of the 0° signal output from the first, second, and third four-phase output clocks as inputs. By performing low-frequency voting on the high and low levels of the three 0° signals, it outputs the 0° clock CK0P. The second low-frequency voting device receives the high and low levels of the 90° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 90° clock CK90P. The third low-frequency voting device receives the high and low levels of the 180° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 180° clock CK180P. The fourth low-frequency voting device receives the high and low levels of the 270° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 270° clock CK270P.

[0027] The four-phase quadrature low-frequency clock signals output from the four low-frequency voters are then input into a multimode phase synthesizer. The first input signal of the multimode phase synthesizer is the 0° clock CK0P, the second input signal is the 90° clock CK90P, the third input signal is the 180° clock CK180P, and the fourth input signal is the 270° clock CK270P. The specific structure of this multimode phase synthesizer is as follows: See Figure 3 The multimode phase synthesizer includes a first PMOS P1, a second PMOS P2, a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a first NMOS N1, a second NMOS N2, a third NMOS N3, a fourth NMOS N4, a fifth NMOS N5, a sixth NMOS N6, and a first capacitor C1. The gate of the first PMOS P1 is grounded to GND, its source is connected to the power supply, and its drain is connected to the sources of the third PMOS P3 and the fourth PMOS P4. The gate of the second PMOS P2 is connected to the inverse mode control signal. The source is connected to the power supply, and the drain is connected to the source of the fifth PMOS P5 and the sixth PMOS P6. The gate of the third PMOS P3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth PMOS P4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The gate of the fifth PMOS P5 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the sixth PMOS P6 is connected to the 270° clock CK270P, and the drain is connected to the output terminal. The gate of the first NMOS N1 is connected to the power supply, the source is grounded (GND), and the drain is connected to the source of the third NMOS N3 and the fourth NMOS N4. The gate of the second NMOS N2 is connected to the mode control signal Mode, the source is grounded (GND), and the drain is connected to the source of the fifth NMOS N5 and the sixth NMOS N6. The gate of the third NMOS N3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth NMOS N4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The fifth NMOS... N5's gate is connected to the 90° clock CK90P, and its drain is connected to the output terminal. The sixth NMOS N6's gate is connected to the 270° clock CK270P, and its drain is connected to the output terminal. One end of the first capacitor C1 is connected to the output terminal, and the other end is grounded to GND.

[0028] PMOS, or P-channel MOSFET, and NMOS, or N-channel MOSFET, are two basic types of MOSFETs. They have similar structures, both consisting of three main parts: gate, source, and drain. NMOS uses N-type semiconductors and is formed on a P-type substrate. Its channel is conducted by electrons (carriers). PMOS uses P-type semiconductors and is formed on an N-type substrate. Its channel is conducted by holes (positive carriers).

[0029] The multimode phase synthesizer selectively multiplies or quadruples the input signal according to the configuration of the mode control signal to directly generate the required high-frequency clock.

[0030] This invention effectively improves radiation resistance through a redundant voting mechanism, avoiding the problems of additional power consumption, single-event sensitivity and phase noise degradation caused by traditional long frequency divider chains, and realizes high-performance, configurable and highly reliable high-frequency clock generation in radiation environments.

[0031] Example 5 A high-frequency clock generation method for radiation-resistant phase-locked loops includes using three 4-phase output clocks to generate 0°, 90°, 180° and 270° phase signals respectively. The three 4-phase output clocks are designated as the first 4-phase output clock, the second 4-phase output clock, and the third 4-phase output clock. The high and low levels of the three in-phase signals are voted on by four corresponding low-frequency voters. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output. The low-frequency voting circuit has a low-frequency value ≤2GHz. It includes a first PMOS P1′, a second PMOS P2′, a third PMOS P3′, a fourth PMOS P4′, a fifth PMOS P5′, a sixth PMOS P6′, a first NMOS N1′, a second NMOS N2′, a third NMOS N3′, a fourth NMOS N4′, a fifth NMOS N5′, and a sixth NMOS N6′. The source of the first PMOS P1′ is connected to the power supply, its drain is connected to the source of the second PMOS P2′, and its gate is connected to the first input terminal A of the low-frequency voting circuit. The drain of the second PMOS P2′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the third input terminal C. The source of the third PMOS P3′ is connected to the power supply, its drain is connected to the source of the fourth PMOS P4′, and its gate is connected to the third input terminal C of the low-frequency voting circuit. The drain of the fourth PMOS P4′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the second input terminal B. The source of the fifth PMOS P5′ is connected to the power supply, and its drain is connected to the sixth PMOS P6′. The source and gate of P6′ are connected to the second input terminal B of the low-frequency voter; the drain of the sixth PMOS P6′ is connected to the output terminal of the low-frequency voter, and its gate is connected to the first input terminal A; the source of the first NMOS N1′ is grounded, and its drain is connected to the source of the second NMOS N2′, and its gate is connected to the third input terminal C of the low-frequency voter; the drain of the second NMOS N2′ is connected to the output terminal, and its gate is connected to the first input terminal A; the source of the third NMOS N3′ is grounded, and its drain is connected to the source of the fourth NMOS N4′, and its gate is connected to the second input terminal B of the low-frequency voter; the drain of the fourth NMOS N4′ is connected to the output terminal, and its gate is connected to the third input terminal C; the source of the fifth NMOS N5′ is connected to ground, and its drain is connected to the source of the sixth NMOS N6′, and its gate is connected to the first input terminal A of the low-frequency voter; the drain of the sixth NMOS N6′ is connected to the output terminal, and its gate is connected to the second input terminal B.

[0032] The four low-frequency voting devices are designated as the first low-frequency voting device, the second low-frequency voting device, the third low-frequency voting device, and the fourth low-frequency voting device. The first low-frequency voting device receives the high and low levels of the 0° signal output from the first, second, and third four-phase output clocks as inputs. By performing low-frequency voting on the high and low levels of the three 0° signals, it outputs the 0° clock CK0P. The second low-frequency voting device receives the high and low levels of the 90° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 90° clock CK90P. The third low-frequency voting device receives the high and low levels of the 180° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 180° clock CK180P. The fourth low-frequency voting device receives the high and low levels of the 270° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 270° clock CK270P.

[0033] The four-phase quadrature low-frequency clock signals output from the four low-frequency voters are then input into the multimode phase synthesizer. The first input signal of the multimode phase synthesizer is the 0° clock CK0P, the second input signal is the 90° clock CK90P, the third input signal is the 180° clock CK180P, and the fourth input signal is the 270° clock CK270P.

[0034] The multimode phase synthesizer includes a first PMOS P1, a second PMOS P2, a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a first NMOS N1, a second NMOS N2, a third NMOS N3, a fourth NMOS N4, a fifth NMOS N5, a sixth NMOS N6, and a first capacitor C1. The gate of the first PMOS P1 is grounded to GND, its source is connected to the power supply, and its drain is connected to the sources of the third PMOS P3 and the fourth PMOS P4. The gate of the second PMOS P2 is connected to the inverse mode control signal. The source is connected to the power supply, and the drain is connected to the source of the fifth PMOS P5 and the sixth PMOS P6. The gate of the third PMOS P3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth PMOS P4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The gate of the fifth PMOS P5 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the sixth PMOS P6 is connected to the 270° clock CK270P, and the drain is connected to the output terminal. The gate of the first NMOS N1 is connected to the power supply, the source is grounded (GND), and the drain is connected to the source of the third NMOS N3 and the fourth NMOS N4. The gate of the second NMOS N2 is connected to the mode control signal Mode, the source is grounded (GND), and the drain is connected to the source of the fifth NMOS N5 and the sixth NMOS N6. The gate of the third NMOS N3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth NMOS N4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The fifth NMOS... N5's gate is connected to the 90° clock CK90P, and its drain is connected to the output terminal. The sixth NMOS N6's gate is connected to the 270° clock CK270P, and its drain is connected to the output terminal. One end of the first capacitor C1 is connected to the output terminal, and the other end is grounded to GND.

[0035] See Figure 4 With the mode control signal Mode=0, both the second NMOS N2 and the second PMOS P2 are turned off. At this time, the left half of the multimode phase synthesizer is working. Since the fundamental signals of the 0° clock CK0P and the 180° clock CK180P are out of phase, the odd harmonics of the output current are canceled out. The remaining even harmonic components achieve frequency doubling synthesis and directly generate the required high-frequency clock. This high-frequency clock generation method is suitable for clock generation circuits with high tolerance to radiation environment in aerospace, nuclear industry electronic equipment and high-reliability electronic systems.

[0036] Example 6 A high-frequency clock generation method for radiation-hardened phase-locked loops (PLLs) includes using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals, respectively. The three 4-phase output clocks are designated as the first, second, and third 4-phase output clocks. Four corresponding low-frequency voters vote on the high and low levels of the three in-phase signals. A high-level synchronization signal is output when at least two of the three in-phase signals are high; otherwise, a low-level synchronization signal is output. This low-frequency voting mechanism effectively resists interference such as single-event upsets, generating a pure orthogonal signal that can directly drive a phase synthesizer.

[0037] The low-frequency voting circuit has a low-frequency value ≤2GHz. It includes a first PMOS P1′, a second PMOS P2′, a third PMOS P3′, a fourth PMOS P4′, a fifth PMOS P5′, a sixth PMOS P6′, a first NMOS N1′, a second NMOS N2′, a third NMOS N3′, a fourth NMOS N4′, a fifth NMOS N5′, and a sixth NMOS N6′. The source of the first PMOS P1′ is connected to the power supply, its drain is connected to the source of the second PMOS P2′, and its gate is connected to the first input terminal A of the low-frequency voting circuit. The drain of the second PMOS P2′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the third input terminal C. The source of the third PMOS P3′ is connected to the power supply, its drain is connected to the source of the fourth PMOS P4′, and its gate is connected to the third input terminal C of the low-frequency voting circuit. The drain of the fourth PMOS P4′ is connected to the output terminal of the low-frequency voting circuit, and its gate is connected to the second input terminal B. The source of the fifth PMOS P5′ is connected to the power supply, and its drain is connected to the sixth PMOS P6′. The source and gate of P6′ are connected to the second input terminal B of the low-frequency voter. The drain of the sixth PMOS P6′ is connected to the output terminal of the low-frequency voter, and its gate is connected to the first input terminal A. The source of the first NMOS N1′ is grounded, and its drain is connected to the source of the second NMOS N2′. Its gate is connected to the third input terminal C of the low-frequency voter. The drain of the second NMOS N2′ is connected to the output terminal, and its gate is connected to the first input terminal A. The source of the third NMOS N3′ is grounded, and its drain is connected to the source of the fourth NMOS N4′. Its gate is connected to the second input terminal B of the low-frequency voter. The drain of the fourth NMOS N4′ is connected to the output terminal, and its gate is connected to the third input terminal C. The source of the fifth NMOS N5′ is connected to ground, and its drain is connected to the source of the sixth NMOS N6′. Its gate is connected to the first input terminal A of the low-frequency voter. The drain of the sixth NMOS N6′ is connected to the output terminal, and its gate is connected to the second input terminal B. The inputs of the first, second, and third input terminals are the high and low levels of the three in-phase signals output by the three 4-phase output clocks, respectively. The four low-frequency voting devices are designated as the first low-frequency voting device, the second low-frequency voting device, the third low-frequency voting device, and the fourth low-frequency voting device. The first low-frequency voting device receives the high and low levels of the 0° signal output from the first, second, and third four-phase output clocks as inputs. By performing low-frequency voting on the high and low levels of the three 0° signals, it outputs the 0° clock CK0P. The second low-frequency voting device receives the high and low levels of the 90° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 90° clock CK90P. The third low-frequency voting device receives the high and low levels of the 180° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 180° clock CK180P. The fourth low-frequency voting device receives the high and low levels of the 270° signal output from the first, second, and third four-phase output clocks as inputs, and outputs the 270° clock CK270P.

[0038] Subsequently, the four-phase quadrature low-frequency clock signals output from the four low-frequency voting units are input into a multimode phase synthesizer. The first input signal of the multimode phase synthesizer is the 0° clock CK0P, the second input signal is the 90° clock CK90P, the third input signal is the 180° clock CK180P, and the fourth input signal is the 270° clock CK270P. This multimode phase synthesizer includes a first PMOS P1, a second PMOS P2, a third PMOS P3, a fourth PMOS P4, a fifth PMOS P5, a sixth PMOS P6, a first NMOS N1, a second NMOS N2, a third NMOS N3, a fourth NMOS N4, a fifth NMOS N5, a sixth NMOS N6, and a first capacitor C1. The gate of the first PMOS P1 is grounded to GND, its source is connected to the power supply, and its drain is connected to the sources of the third PMOS P3 and the fourth PMOS P4. The gate of the second PMOS P2 is connected to the inverse mode control signal. The source is connected to the power supply, and the drain is connected to the source of the fifth PMOS P5 and the sixth PMOS P6. The gate of the third PMOS P3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth PMOS P4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The gate of the fifth PMOS P5 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the sixth PMOS P6 is connected to the 270° clock CK270P, and the drain is connected to the output terminal. The gate of the first NMOS N1 is connected to the power supply, the source is grounded (GND), and the drain is connected to the source of the third NMOS N3 and the fourth NMOS N4. The gate of the second NMOS N2 is connected to the mode control signal Mode, the source is grounded (GND), and the drain is connected to the source of the fifth NMOS N5 and the sixth NMOS N6. The gate of the third NMOS N3 is connected to the 0° clock CK0P, and the drain is connected to the output terminal. The gate of the fourth NMOS N4 is connected to the 180° clock CK180P, and the drain is connected to the output terminal. The fifth NMOS... N5's gate is connected to the 90° clock CK90P, and its drain is connected to the output terminal. The sixth NMOS N6's gate is connected to the 270° clock CK270P, and its drain is connected to the output terminal. One end of the first capacitor C1 is connected to the output terminal, and the other end is grounded to GND.

[0039] See Figure 5 With the mode control signal Mode=1, both the second NMOS N2 and the second PMOS P2 are turned on. At this time, the multimode phase synthesizer is affected by the 4-phase clock signal. Each phase signal generates a current pulse in its positive half-cycle. The 4-phase clock generates 4 mutually staggered current pulses, which are superimposed at the output to generate a 4-fold frequency multiplication, directly generating the required high-frequency clock.

[0040] This invention effectively resists interference such as single-event upsets through a low-frequency voting mechanism, generating a pure orthogonal signal. This signal directly drives the phase synthesizer without using long frequency division or multiplication chains, significantly reducing power consumption and avoiding increased jitter. The phase synthesizer can perform frequency multiplication by 2 or 4 depending on the mode selection, flexibly generating the required high-frequency clock, achieving efficient and configurable clock generation while ensuring radiation resistance.

Claims

1. A high-frequency clock generation method applied to radiation-resistant phase-locked loops, characterized in that, This involves using three 4-phase output clocks to generate 0°, 90°, 180°, and 270° phase signals respectively. Four corresponding low-frequency voters then vote on the high and low levels of the three in-phase signals. Based on the voting results, a synchronized four-phase quadrature low-frequency clock signal is output. This four-phase quadrature low-frequency clock signal is then input to a multimode phase synthesizer. The multimode phase synthesizer selectively performs high-frequency synthesis on the input signal according to the configuration of the mode control signal, directly generating the required high-frequency clock. The low-frequency value of the low-frequency voters is ≤2GHz.

2. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The low-frequency voting device is used to vote on the high and low levels of the three in-phase signals. When at least two of the three in-phase signals are high, a high-level synchronization signal is output; otherwise, a low-level synchronization signal is output.

3. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The three 4-phase output clocks are designated as the first, second, and third 4-phase output clocks, respectively. The four low-frequency voting units are designated as the first, second, third, and fourth low-frequency voting units. The first low-frequency voting unit receives the high and low levels of the 0° signals output from the first, second, and third 4-phase output clocks as inputs. By voting on the high and low levels of the three 0° signals, it outputs the 0° clock (CK0P). The second low-frequency voting unit receives the high and low levels of the 90° signals output from the first, second, and third 4-phase output clocks as inputs, and outputs the 90° clock (CK90P). The third... The low-frequency voter inputs are the high and low levels of the 180° signals output from the first, second, and third four-phase clock outputs, and the output is a 180° clock (CK180P). The fourth low-frequency voter inputs are the high and low levels of the 270° signals output from the first, second, and third four-phase clock outputs, and the output is a 270° clock (CK270P). The multimode phase synthesizer's first input signal is a 0° clock (CK0P), the second input signal is a 90° clock (CK90P), the third input signal is a 180° clock (CK180P), and the fourth input signal is a 270° clock (CK270P), and the output is a high-frequency clock.

4. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 3, characterized in that, The low-frequency voting device includes a first PMOS (P1′), a second PMOS (P2′), a third PMOS (P3′), a fourth PMOS (P4′), a fifth PMOS (P5′), a sixth PMOS (P6′), a first NMOS (N1′), a second NMOS (N2′), a third NMOS (N3′), a fourth NMOS (N4′), a fifth NMOS (N5′), and a sixth NMOS (N6′). The source of the first PMOS (P1′) is connected to the power supply, the drain is connected to the source of the second PMOS (P2′), and the gate is connected to the first input terminal (A) of the low-frequency voting device. The drain of the second PMOS (P2′) is connected to the output terminal of the low-frequency voting device, and the gate is connected to the third input terminal (C). The source of the third PMOS (P3′) is connected to the power supply, the drain is connected to the source of the fourth PMOS (P4′), and the gate is connected to the third input terminal (C) of the low-frequency voting device. The drain of the fourth PMOS (P4′) is connected to the output terminal of the low-frequency voting device, and the gate is connected to the second input terminal (B). The fifth PMOS (P6′) is connected to the power supply, the drain is connected to the source of the fourth PMOS (P4′), and the gate is connected to the third input terminal (C). The drain of the fourth PMOS (P4′) is connected to the output terminal of the low-frequency voting device, and the gate is connected to the second input terminal (B). The source of MOS (P5') is connected to the power supply, the drain is connected to the source of the sixth PMOS (P6'), and the gate is connected to the second input terminal (B) of the low-frequency voter. The drain of the sixth PMOS (P6') is connected to the output terminal of the low-frequency voter, and the gate is connected to the first input terminal (A). The source of the first NMOS (N1') is grounded, the drain is connected to the source of the second NMOS (N2'), and the gate is connected to the third input terminal (C) of the low-frequency voter. The drain of the second NMOS (N2') is connected to the output terminal, and the gate is connected to the first input terminal (A). The source of the third NMOS (N3') is grounded, the drain is connected to the source of the fourth NMOS (N4'), and the gate is connected to the second input terminal (B) of the low-frequency voter. The drain of the fourth NMOS (N4') is connected to the output terminal, and the gate is connected to the third input terminal (C). The source of the fifth NMOS (N5') is connected to ground, the drain is connected to the source of the sixth NMOS (N6'), and the gate is connected to the first input terminal (A) of the low-frequency voter. The drain of the sixth NMOS (N6') is connected to the output terminal, and the gate is connected to the second input terminal (B).

5. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 4, characterized in that, The multimode phase synthesizer selectively synthesizes the input signal by doubling or quadrupling the frequency according to the configuration of the mode control signal to generate the required high-frequency clock.

6. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 5, characterized in that, The multimode phase synthesizer includes a first PMOS (P1), a second PMOS (P2), a third PMOS (P3), a fourth PMOS (P4), a fifth PMOS (P5), a sixth PMOS (P6), a first NMOS (N1), a second NMOS (N2), a third NMOS (N3), a fourth NMOS (N4), a fifth NMOS (N5), a sixth NMOS (N6), and a first capacitor (C1). The gate of the first PMOS (P1) is grounded (GND), its source is connected to the power supply, and its drain is connected to the sources of the third PMOS (P3) and the fourth PMOS (P4). The gate of the second PMOS (P2) is connected to the inverse mode control signal. The source of the first NMOS is connected to the power supply, and the drain is connected to the source of the fifth PMOS (P5) and the sixth PMOS (P6). The gate of the third PMOS (P3) is connected to the 0° clock (CK0P), and the drain is connected to the output terminal. The gate of the fourth PMOS (P4) is connected to the 180° clock (CK180P), and the drain is connected to the output terminal. The gate of the fifth PMOS (P5) is connected to the 0° clock (CK0P), and the drain is connected to the output terminal. The gate of the sixth PMOS (P6) is connected to the 270° clock (CK270P), and the drain is connected to the output terminal. The gate of the first NMOS (N1) is connected to the power supply, the source is grounded (GND), and the drain is connected to the source of the third NMOS (N3) and the fourth NMOS (N4). The gate of the second NMOS (N2) is connected to the mode control signal (Mode), the source is grounded (GND), and the drain is connected to the source of the fifth NMOS (N5) and the sixth NMOS (N6); The gate of the third NMOS (N3) is connected to the 0° clock (CK0P), and the drain is connected to the output terminal. The gate of the fourth NMOS (N4) is connected to the 180° clock (CK180P), and the drain is connected to the output terminal. The gate of the fifth NMOS (N5) is connected to the 90° clock (CK90P), and the drain is connected to the output terminal. The gate of the sixth NMOS (N6) is connected to the 270° clock (CK270P), and the drain is connected to the output terminal. One end of the first capacitor (C1) is connected to the output terminal, and the other end is grounded (GND).

7. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 6, characterized in that, When the mode control signal (Mode) = 0, both the second NMOS (N2) and the second PMOS (P2) are turned off. At this time, the left half of the multimode phase synthesizer is working. Since the fundamental signals of the 0° clock (CK0P) and the 180° clock (CK180P) are out of phase, the odd harmonics of the output current are canceled out, and the remaining even harmonic components achieve frequency doubling.

8. The high-frequency clock generation method applied to a radiation-resistant phase-locked loop according to claim 6, characterized in that, When the mode control signal (Mode) = 1, both the second NMOS (N2) and the second PMOS (P2) are turned on. At this time, the multimode phase synthesizer is affected by the 4-phase clock signal. Each phase signal generates a current pulse in its positive half-cycle. The 4-phase clock generates 4 mutually staggered current pulses, which are superimposed at the output to generate a 4-fold frequency multiplication.

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