A passive gain-shaping noise-shaping successive approximation analog-to-digital converter and method

Abstract

The application discloses a kind of passive gain noise shaping successive approximation type analog-digital converter and method, belong to analog-digital converter technical field.The analog-digital converter includes SAR ADC, switch capacitor module, multiple-input comparator, control unit and digital calibration algorithm, SAR ADC includes CDAC.Switch capacitor module includes C0, C1 and C2, for the voltage of the remainder that plate keeps on CDAC is collected after the end of quantization stage, and successively form first-order integral signal and second-order integral signal;In quantization stage, two C2 capacitors form head-to-tail charge pump, to realize two times passive gain in second-order integral signal path.Multiple-input comparator will input signal, first-order integral signal and second-order integral signal weighted addition.Digital calibration algorithm is based on FFT and SNDR and is calibrated bit by bit to the output weight of SAR ADC.The scheme can enhance noise shaping effect, compensate CDAC mismatch, improve conversion accuracy and energy efficiency.

Description

Technical Field

[0001] This invention belongs to the field of high-efficiency integrated circuit design technology, specifically relating to a passive gain-noise shaping successive approximation analog-to-digital converter and method. Background Technology

[0002] With the development of technologies such as 5G communication, the Internet of Things, wireless sensing, and high-performance computing, emerging electronic systems are placing higher demands on the energy efficiency, conversion accuracy, and bandwidth of analog-to-digital converters (ADCs). Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in medium-resolution and low-power data acquisition scenarios due to their simple structure, high degree of digitization, and low power consumption. However, as resolution increases further, the performance of SAR ADCs is limited by thermal noise, comparator noise, sampling noise, and mismatch in capacitive digital-to-analog converter (CDAC) arrays. Improving these issues by increasing the comparator load, increasing the DAC capacitor size, or increasing the drive capability significantly increases chip area and power consumption, diminishing the original energy efficiency advantages of SAR ADCs.

[0003] While traditional Sigma-Delta ADCs can achieve high accuracy through oversampling and noise shaping, they typically rely on active analog circuitry such as operational transconductance amplifiers and precision comparators. These active circuits consume significant power and are highly sensitive to process technology, supply voltage, and device gain, making them unsuitable for low-voltage, advanced process, and low-power applications. Therefore, traditional Sigma-Delta ADCs struggle to meet the demands of some emerging applications while balancing high accuracy and high energy efficiency.

[0004] The Noise-Shaping Successive Approximation Register Analog-to-Digital Converter (NS-SAR ADC) combines the low-power advantage of SAR ADCs with the noise-shaping capability of Sigma-Delta ADCs. It can shift quantization noise from in-band to out-of-band by feeding back residual information from the previous conversion cycle, thereby improving effective resolution with lower power consumption. Existing NS-SAR ADCs typically achieve noise shaping by introducing loop filters, error feedback structures, passive integration structures, or dynamic amplification structures into the SAR ADC. However, these approaches still have certain shortcomings.

[0005] Existing literature proposes inserting filters into SAR ADCs to achieve first-order shaping of quantization noise, with a noise transfer function of (1-0.64z). -1 This scheme can increase the effective number of bits of an 8-bit SAR ADC by approximately two bits with an oversampling rate of 4, while achieving good energy efficiency. However, this noise shaping technique still requires active circuitry such as transconductance operational amplifiers, resulting in high static power consumption. Furthermore, further performance improvements are limited by process advancements and the gain of analog active circuitry.

[0006] Other literature employs switched-capacitor circuits to achieve passive integration, thus avoiding the use of active circuits such as transconductance operational amplifiers. This passive NS-SAR ADC, using a 10-bit SAR ADC, achieves a high signal-to-noise-and-distortion ratio (SNDR) and a certain bandwidth at an oversampling rate of 4. This approach reduces overall power consumption through low supply voltage and passive circuit structure, and is well-adapted to process evolution. However, due to the lack of effective gain inherent in passive integration, its noise shaping capability is relatively weak, limiting further performance improvements.

[0007] Other literature introduces dynamic gain amplifiers into SAR ADC structures to enhance the noise shaping loop gain. This approach utilizes a dynamic gain amplifier to provide loop gain to the residual signal, improving noise shaping without significantly increasing power consumption and achieving a high SNDR. However, dynamic gain amplifiers are sensitive to variations in process technology, voltage, and temperature, limiting their robustness. Furthermore, circuit stability and consistency remain insufficient as process technology, power supply voltage, and application scenarios change.

[0008] Existing literature has also proposed a second-order NS-SAR ADC with an error feedback structure, which achieves a more complex noise transfer function zero with only minor modifications to the standard SAR architecture, thereby enhancing noise shaping performance. This scheme achieves low power consumption and good noise shaping performance by reusing a dynamic amplifier through a passive finite impulse response path and a comparator with PVT tracking background calibration. However, this feedback method leads to attenuation of the input signal and feedback information, requiring more calibration techniques to achieve optimal performance, thus increasing the system implementation complexity.

[0009] Another paper proposes embedding a closed-loop dynamic amplifier into the loop filter of an NS-SAR ADC, combining the advantages of a closed-loop architecture and dynamic operation. This approach can achieve a good noise transfer function without gain calibration, and obtain high SNDR and low power consumption. However, the closed-loop dynamic amplifier has insufficient response speed, which can limit the overall bandwidth, and its implementation still relies on a relatively complex dynamic amplification structure.

[0010] In summary, existing noise-shaping SAR ADC schemes have achieved certain results in improving resolution and energy efficiency, but the following technical problems still exist: First, schemes using active or dynamic amplifiers are still limited in terms of power consumption, robustness, and process adaptability; second, although the power consumption of simple passive integration schemes is low, their noise shaping capability is insufficient; third, existing feedback methods may lead to attenuation of input signals and feedback information, requiring additional calibration or compensation; fourth, the integrator output has a large weight in traditional CIFF noise-shaping structures, which easily introduces additional comparator noise and power consumption; fifth, CDAC mismatch will reduce conversion linearity and spectral performance, and traditional digital calibration schemes are not well matched with the noise-shaping SAR ADC structure, making it difficult to directly and effectively calibrate its internal mismatch.

[0011] Therefore, there is an urgent need for a new noise-shaping successive approximation analog-to-digital converter (ADC) that can enhance noise shaping capabilities without relying on high-power active amplifiers, reduce the adverse effects of excessive weighting at the integrator output on the noise and power consumption of multi-input comparators, and effectively calibrate CDAC output weight mismatch. This would improve the conversion accuracy and energy efficiency of the ADC while maintaining low power consumption, high robustness, and good process adaptability. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a passive gain noise shaping successive approximation analog-to-digital converter and method to address the shortcomings of the prior art. By using charge pump technology, a passive gain of twice is achieved inside the integrator without attenuating the input and margin information. This is used to solve the technical problems of excessive weight at the integrator output and CDAC mismatch in existing noise-shaping SAR ADCs.

[0013] The present invention adopts the following technical solution: A noise-shaping successive approximation analog-to-digital converter (ADC) includes a SAR ADC, a switched-capacitor module, a multi-input comparator (MIPC), a control unit, and a digital calibration algorithm. The SAR ADC includes a CDAC, which retains the remaining voltage margin after the quantization phase. The switched-capacitor module includes capacitors C0, C1, and C2. The control unit controls C0 to acquire the remaining voltage margin, integrates the acquired voltage on C0 and transfers it to C1 to form a first-order integrated signal, and integrates the remaining first-order integrated signal on C0 on C2 to form a second-order integrated signal. During the quantization phase, the two C2 capacitors form a charge pump connected end-to-end to achieve passive gain in the second-order integrated signal path. The MIPC is used to adjust the input signal... V inThe first-order integral signal and the second-order integral signal are added together with preset weights; the digital calibration algorithm is used to calibrate the output weights of the SAR ADC, and obtain the calibrated digital output result based on the calibrated output weights and the digital code value of the ADC.

[0014] Preferably, the capacitance value of C1 is equal to the capacitance value of CDAC, the capacitance value of C2 is 1 / 2 of the capacitance value of C1, and the capacitance value of C0 is 1 / 3 of the capacitance value of C1.

[0015] Preferably, during the quantization stage, the upper plate voltages of the two C2 capacitors are the same, and the two C2 capacitors form a charge pump connected end to end to achieve twice the passive gain in the second-order integral signal path.

[0016] Preferably, the multi-input comparator is used to make the input signal V in The first-order integral signal and the second-order integral signal are added with weights of 1:4:8 to achieve (1-0.75z) -1 ) 2 The noise transfer function.

[0017] Preferably, the digital calibration algorithm is used to perform FFT on the original output code value of the ADC to be calibrated, obtain a reference value of SNDR, and perform bit-by-bit calibration on the output weight of the SAR ADC according to the change of SNDR.

[0018] Another technical solution of the present invention is a control method for a noise-shaping successive approximation analog-to-digital converter, comprising the following steps: S1. After the quantization phase of the (n-1)th conversion cycle ends, the upper plate of the CDAC of the SAR ADC retains the remaining voltage margin of the conversion. S2, Close switch φ CIFF0 This allows the remaining voltage to be collected onto C0 through charge sharing; S3, Disconnect the switch φ CIFF0 and close switch φ CIFF1 This allows the residual voltage collected on C0 to be transferred to C1 through integration, thus forming a first-order integrated signal. S4. Disconnect the switch φ CIFF1 and close the opening φ CIFF2 This allows the remaining first-order integral signal on C0 to be integrated twice on C2, thus forming a second-order integral signal. S5. During the quantization phase, disconnect the switch φ. CIFF2 and close switch φ N_sample This allows the two C2 capacitors to form a charge pump connected end-to-end, thereby achieving passive gain in the second-order integral signal path. S6, Input signalV in The first-order integral signal and the second-order integral signal are added together with preset weights through a multi-input comparator to obtain the successive approximation conversion result.

[0019] Preferably, the switch φ CIFF0 The switch φ CIFF1 The switch φ CIFF2 and the switch φ N_sample The switching timing is generated by the EOC clock and SAMPLE clock of the SAR ADC through the digital control unit.

[0020] Another technical solution of the present invention is a bit-by-bit weight calibration method for a noise-shaping successive approximation analog-to-digital converter, comprising the following steps: S1. Obtain the raw output code value of the ADC to be calibrated; S2. Perform FFT on the original output code value to obtain the reference value of SNDR; S3. Increase the output weight of the current bit to be calibrated by one step in the positive direction. mu The new digital output result is obtained based on the increased output weight and the digital code value of the ADC; S4. Perform FFT analysis on the new digital output result again to obtain the new SNDR; S5. Determine the weight adjustment direction of the current bit to be calibrated based on whether the new SNDR is increased relative to the reference value of the SNDR. S6. Iteratively adjust the output weight of the current bit to be calibrated along the determined weight adjustment direction until the SNDR decreases, and save the previous output weight as the calibration weight of the current bit to be calibrated. S7. Perform the calibration of each output weight in order from the most significant bit to the least significant bit until all output weights have been calibrated, and obtain the calibration weight vector. S8. Recalibrate the obtained calibration weight vector.

[0021] Preferably, the calibration of each output weight is performed sequentially from the most significant bit to the least significant bit.

[0022] Preferably, after obtaining the calibration weight vector, the obtained calibration weight vector is recalibrated.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects: A noise-shaping successive approximation analog-to-digital converter (ADC) is disclosed, simultaneously protecting the combined relationship of a SAR ADC, switched-capacitor module, multi-input comparator (MIPC), control unit, and digital calibration algorithm. The residual voltage after the quantization stage is retained by the CDAC, and C0, C1, and C2 sequentially perform residual voltage acquisition, first integration, and second integration. A charge pump formed by two C2 capacitors achieves passive gain, allowing the noise-shaping loop to enhance the second-order integral signal without relying on a high-power active amplifier. Combining the weighted summation of the MIPC and the digital calibration algorithm simultaneously improves noise-shaping capability and mitigates the effects of CDAC mismatch, thereby enhancing the ADC's conversion accuracy and energy efficiency.

[0024] Furthermore, the specific capacitor configuration for residual acquisition and integral transfer in the protection switched capacitor module is as follows: C1 has the same capacitance value as CDAC, which is beneficial for matching the margin voltage during the integral transfer process; C2 is half the capacitance of C1, which, together with the subsequent charge pump structure, facilitates the formation of twice the passive gain in the second-order integral signal path; C0 is one-third the capacitance of C1, which is beneficial for controlling the residual signal acquisition and integration ratio, enabling the formation of the required integral relationship under passive circuit conditions, while taking into account noise shaping effect, power consumption, and capacitor area.

[0025] Furthermore, when the voltages on the upper plates of the two C2 capacitors are the same, they are connected end to end to form a charge pump, which can achieve twice the passive gain in the second-order integral signal path. This can improve the strength of the second-order integral signal without the need for a transconductance operational amplifier or dynamic gain amplifier, thereby enhancing the noise shaping capability and avoiding the static power consumption, process sensitivity and robustness issues caused by active amplifiers.

[0026] Furthermore, by making V in The first-order integral signal and the second-order integral signal are added with weights of 1:4:8 to form (1-0.75z). -1 ) 2 The second-order noise transfer function shifts the in-band quantization noise out of the band, which can improve the in-band signal-to-noise ratio. At the same time, the passive gain of the charge pump reduces the input weight pressure of the comparator, which helps to reduce comparator noise and power consumption.

[0027] Furthermore, by performing an FFT on the raw output code value of the ADC to be calibrated to obtain a reference value for SNDR, and then judging the weight adjustment effect based on the change in SNDR, the spectral performance can be directly used as the calibration basis. This method can perform bit-by-bit calibration for output weight deviation caused by CDAC mismatch, reduce nonlinear errors and spurious components, and improve SNDR, SFDR, and effective number of bits.

[0028] A control method for a noise-shaping successive approximation analog-to-digital converter (ADC) involves retaining the margin voltage on the upper plate of the CDAC after the (n-1)th conversion cycle and sequentially controlling φ.CIFF0 φ CIFF1 φ CIFF2 and φ N_sample This allows the residual voltage to be collected, integrated, and formed into a second-order integral signal, which can feed back the residual information from the previous conversion cycle to the subsequent quantization process, thereby achieving noise shaping and improving conversion accuracy.

[0029] Furthermore, by using the EOC clock to determine the timing of residual voltage acquisition after the quantization stage ends, and by using the SAMPLE clock in conjunction with the subsequent sampling and quantization stages, it can be ensured that the charge transfer and charge pump formation of C0, C1, and C2 match the working cycle of the SAR ADC, thereby improving the stability and feasibility of the noise shaping process.

[0030] A bit-by-bit weight calibration method for noise-shaping successive approximation analog-to-digital converters (ADCs) is proposed. First, the original output code value is obtained and the SNDR reference value is obtained through FFT. Then, the output weight of the current bit to be calibrated is perturbed by step size. The adjustment direction is determined based on the new SNDR. When the SNDR decreases, the previous weight is saved as the calibration weight. Through this bit-by-bit search method, a more realistic output weight can be obtained without directly measuring the actual error of each capacitor, thus compensating for CDAC mismatch.

[0031] Furthermore, since the higher-order capacitor weights have a greater impact on the ADC output code value and spectral performance, calibrating the higher-order output weights first can eliminate the main mismatch error first, and then gradually calibrating the lower-order output weights is beneficial to improving the convergence efficiency of the calibration process and making the obtained calibration weight vector more consistent with the hierarchical relationship of the SAR ADC output weights.

[0032] Furthermore, since mismatches also exist in other bits besides the MSB in actual ADC chips, the MSB calibration may include the influence of subsequent low-bit mismatches. By recalibrating the obtained calibration weight vector multiple times, the interference of low-bit mismatches on high-bit calibration results can be gradually reduced, making the final output weights closer to the actual weights and improving the stability and accuracy of digital calibration results.

[0033] In summary, this invention achieves margin voltage acquisition and second-order integration through a switched capacitor module composed of C0, C1, and C2, and utilizes two C2 capacitors to form a charge pump, achieving double passive gain in the second-order integration signal path; at the same time, it combines a bit-by-bit weighted calibration algorithm to compensate for CDAC mismatch, thereby improving the accuracy and energy efficiency of the ADC under the premise of low power consumption and high robustness.

[0034] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the following description of the relative embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the overall structure of the NS-SAR ADC of the present invention; Figure 2 The diagrams show the structure and timing of a switched capacitor circuit, where (a) is a schematic diagram of the switched capacitor circuit structure and (b) is a schematic diagram of the switched capacitor circuit timing. Figure 3 The diagram shows the structure of a three-stage multi-input comparator, where (a) is the margin voltage acquisition, (b) is the first-order signal integration, (c) is the second-order signal integration, and (d) is the quantization summation. Figure 4 This is a schematic diagram of the switching steps in a switched capacitor circuit. Figure 5 This is a schematic diagram of the bitwise weight calibration algorithm structure; Figure 6 This is a schematic diagram of the workflow of the bitwise weight calibration algorithm; Figure 7 Spectrum analysis of SAR ADC signal after noise shaping is turned off; Figure 8 Spectrum analysis of SAR ADC signal after noise shaping is enabled. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0041] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0042] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0043] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0044] This invention provides a passive gain noise-shaping successive approximation analog-to-digital converter (ADC), specifically a second-order improved CIFF noise-shaping SAR ADC employing a bit-by-bit weighted calibration algorithm. This noise-shaping successive approximation ADC includes a SAR ADC, a switched-capacitor module, a multi-input comparator (MIPC), a control unit, and a digital calibration algorithm. The SAR ADC includes a CDAC, which retains the remaining voltage margin after the quantization phase. The switched-capacitor module acquires, integrates, and performs second-order integration on the remaining voltage margin. The MIPC receives the input signal, the first-order integrated signal, and the second-order integrated signal and performs weighted summation. The control unit generates switching control signals based on the SAR ADC's EOC clock and sample clock. The digital calibration algorithm performs bit-by-bit calibration on the SAR ADC's output weights.

[0045] Please see Figure 1 The noise-shaping SAR ADC circuit of this embodiment includes a 10-bit SAR ADC with a sampling rate of 10MHz, a three-stage multi-input comparator, a switched-capacitor module, a control unit, and a digital calibration algorithm. The 10-bit SAR ADC uses a custom-designed unit capacitor to improve the matching degree of the capacitor array and employs tail capacitor reuse technology to reduce the capacitance value of the DAC, thereby reducing power consumption. The switching timing of the switched-capacitor module is generated by the SAR ADC's own EOC clock and SAMPLE clock through the digital control unit.

[0046] Please see Figure 2 The switched capacitor module includes C0, C1, and C2. C1 has the same capacitance as CDAC, C2 has half the capacitance of C1, and C0 has one-third the capacitance of C1. With this capacitor configuration, the switched capacitor module can acquire and integrate the residual voltage from the previous conversion cycle without using active circuits such as transconductance operational amplifiers, and form a passive gain in the second-order integral signal path.

[0047] Please see Figure 3Specifically, taking the nth conversion as an example, after the quantization phase of the (n-1)th conversion cycle ends, the upper plate of the CDAC retains a residual voltage from the conversion. This residual voltage can be understood as the remaining voltage on the upper plate of the CDAC after one conversion; under ideal comparator conditions, this residual voltage corresponds to the sum of all noise after the conversion. Subsequently, the control unit closes switch φ. CIFF0 This allows the residual voltage of the upper plate of the CDAC to be collected onto C0 through charge sharing.

[0048] After C0 completes the residual voltage acquisition, the control unit disconnects switch φ. CIFF0 and close switch φ CIFF1 This allows the residual voltage collected on C0 to be transferred to C1 through integration. Through this process, a first-order integrated signal is generated on C1. Subsequently, the control unit disconnects switch φ. CIFF1 and close switch φ CIFF2 This allows the remaining first-order integral signal on C0 to be integrated twice on C2, thus forming a second-order integral signal.

[0049] When entering the quantization phase, the control unit disconnects switch φ. CIFF2 At this point, the voltages on the upper plates of the two C2 capacitors are the same. Then, the control unit closes switch φ. N_sample This allows the two C2 capacitors to form a charge pump connected end-to-end. This charge pump structure achieves double the passive gain in the second-order integral signal path. Therefore, this embodiment can achieve double the passive gain within the integrator without attenuating the input signal or margin information, thereby enhancing the noise shaping effect.

[0050] The multi-input comparator receives the input signals respectively. V in First-order and second-order integral signals, and make the input signal V in The first-order and second-order integral signals are added together by a multi-input comparator with weights of 1:4:8, thereby achieving (1-0.75z) -1 ) 2 The noise transfer function. Through the above weighting method, the second-order integral signal can participate in the summation at the comparator input with a higher weight, enabling the noise shaping loop to obtain the target feedback relationship. The multi-input comparator adopts a three-stage multi-input comparator structure, and adds a gain stage to reduce comparator noise while achieving a certain degree of isolation.

[0051] Please see Figure 4 CDAC via φ CIFF0 Establish a margin voltage acquisition connection with C0; C0 is connected via φ CIFF1 Establish an integral connection with C1; C0 is connected through φ. CIFF2Establish a quadratic integral connection with C2; the two C2 capacitors are connected through φ N_sample Establish a charge pump connection that connects the two ends. Through the above time-division connection method, the switched capacitor module can complete margin voltage acquisition, integral transfer, and second-order integral signal enhancement under passive conditions.

[0052] This embodiment constructs a second-order improved CIFF noise shaping structure using a switched capacitor module and a multi-input comparator. Compared to the traditional CIFF noise shaping structure, which has a large summation weight and easily introduces additional comparator noise and power consumption, this embodiment achieves passive gain in the second-order integral signal path through C0, C1, and C2 and a charge pump structure. This allows the noise shaping loop to enhance the second-order integral signal without relying on an active amplifier, thereby reducing the pressure on the number of comparator input pairs and comparator noise performance.

[0053] Please see Figure 5 This embodiment also provides a bit-by-bit weight calibration algorithm for the aforementioned noise-shaping SAR ADC. This bit-by-bit weight calibration algorithm is used to directly calibrate the mismatch within the noise-shaping SAR ADC in the digital domain, and is particularly suitable for CDAC output weight mismatch calibration.

[0054] Please see Figure 6 Taking a 10-bit SAR ADC as an example, the bit-by-bit weight calibration algorithm first acquires the original output code value of the ADC to be calibrated at the start of operation, and performs an FFT on the original output code value to obtain a reference value for the SNDR, i.e., using the initial SNDR of the circuit as the reference value. Then, the algorithm calibrates the output weights starting from the most significant bit. Taking MSB capacitor weight calibration as an example, the first bit weight is first increased by one step in the positive direction. mu The new digital output result is obtained based on the changed output weights and the digital code value of the ADC.

[0055] After obtaining the new numerical output, perform FFT analysis on the new output to obtain the new SNDR. If the new SNDR is higher than the reference value, it indicates that the current weight adjustment direction is correct, and the step size should continue to be increased in the positive direction. mu If the new SNDR does not increase or decrease, it indicates that the current adjustment direction is incorrect, and the actual output weights are smaller than the current weights. The weights need to be adjusted by step size. mu Reduce. Therefore, the direction of weight adjustment for the current bit to be calibrated is determined by the change in SNDR.

[0056] After determining the direction of weight adjustment, the output weight of the current bit to be calibrated is iteratively adjusted along that direction until the SNDR decreases. At this point, the previous output weight is considered to be closer to the actual weight, and this previous output weight is saved as the calibration weight of the current bit to be calibrated. After completing the calibration of the current bit, the algorithm calibrates the output weights of each bit sequentially from the most significant bit to the least significant bit until all output weights are calibrated, resulting in the calibration weight vector.

[0057] Since the MSB bit is calibrated first, and in actual ADC chips it's rare to find a situation where there's no mismatch except for the MSB bit, overcalibration may occur when calibrating the MSB bit. This means the resulting weights may contain some of the mismatch effects from subsequent lower-order weights. To reduce this impact, this implementation recalibrates the obtained calibration weight vector after obtaining one round of calibration. In one specific embodiment, the number of iterations can be set to ten. Through multiple rounds of recalibration, the overcalibration effect caused by subsequent weight mismatches during higher-order weight calibration can be reduced, making the final calibration weight vector closer to the actual output weights of the ADC.

[0058] In this embodiment, the digital calibration algorithm can be executed as an off-chip digital calibration algorithm to obtain the calibrated digital output result based on the calibrated output weights and the digital code value of the ADC. In this way, the output weights can be compensated in the digital domain without changing the main structure of the front-end analog circuit, thereby improving the impact of CDAC mismatch on the conversion performance of the noise-shaping SAR ADC.

[0059] This implementation ultimately designs and implements a second-order improved CIFF noise-shaping SAR ADC calibrated using a digital algorithm based on a 55nm standard CMOS process, and completes simulation verification and tape-out testing. Test results show that after calibration, the chip achieves an increase in SNDR from 76dB to 84.2dB, an SFDR of 92dB, an ENOB of 13.7 bits, a core power consumption of 72μW, and a FoMS of 180.6dB, demonstrating good energy efficiency compared to similar circuits.

[0060] In summary, this implementation uses capacitors C0, C1, and C2 in the switched capacitor module to acquire, integrate, and double-integrate the residual voltage of the SAR ADC from the previous conversion cycle. Two capacitors, C2, form a charge pump connected end-to-end, achieving double passive gain in the second-order integration signal path. Simultaneously, a bit-by-bit weight calibration algorithm is used to calibrate the output weights of the SAR ADC bit-by-bit based on changes in FFT and SNDR. Therefore, this implementation can improve the conversion performance of the noise-shaping SAR ADC while maintaining low power consumption and good robustness, and compensate for the impact of CDAC mismatch on the output results.

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0062] Please see Figure 7 The signal analysis spectrum of the SAR ADC is shown after noise shaping is disabled. Figure 7 It can be seen that when noise shaping is not enabled, the SAR ADC mainly relies on its own quantization process to complete the analog-to-digital conversion. The quantization noise, comparator noise, and error components caused by CDAC mismatch generated during the conversion are largely distributed within the signal bandwidth, resulting in a relatively high in-band noise floor. Since the in-band noise cannot be effectively shifted out-of-band, the ADC's signal-to-noise ratio is limited, making it difficult to further improve its effective resolution. These spectral results reflect the performance bottleneck faced by traditional SAR ADCs in high-resolution, low-power application scenarios.

[0063] Please see Figure 8 The signal analysis spectrum of the SAR ADC is shown after noise shaping is enabled. Figure 7 In contrast, after noise shaping is enabled, the switched-capacitor module collects, integrates, and double-integrates the residual voltage from the previous conversion cycle, forming a charge pump connected end-to-end through two C2 capacitors, achieving double passive gain in the second-order integral signal path. The input signal, the first-order integral signal, and the second-order integral signal are further added by a multi-input comparator with weights of 1:4:8, thus achieving the second-order noise shaping effect. Figure 8 As can be seen, the in-band noise is significantly suppressed, the noise energy is transferred to the out-of-band, and the in-band noise level is reduced, indicating that the present invention can effectively improve the dynamic performance of the ADC under low power consumption conditions.

[0064] In summary, addressing the issues of excessive weighting at the integrator output, increased comparator noise and power consumption, and difficulty in effectively calibrating CDAC mismatch in noise-shaping SAR ADCs, this invention presents a passive gain noise-shaping successive approximation analog-to-digital converter and method. A switched-capacitor module composed of C0, C1, and C2 is used to acquire, integrate, and double-integrate the residual voltage from the previous conversion cycle. Two C2 capacitors form a charge pump connected end-to-end, achieving double passive gain in the second-order integration signal path, thereby enhancing the noise-shaping effect without using an active amplifier. A multi-input comparator adds the input signal, the first-order integration signal, and the second-order integration signal with a weighting ratio of 1:4:8 to achieve second-order noise shaping. Furthermore, a bit-by-bit weight calibration algorithm uses FFT and SNDR to determine the bit-by-bit calibration output weights to compensate for CDAC mismatch. Therefore, this invention combines low power consumption, high robustness, high accuracy, and good energy efficiency.

[0065] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A noise-shaping successive approximation analog-to-digital converter, characterized in that, The system includes a SAR ADC, a switched-capacitor module, a multi-input comparator, a control unit, and a digital calibration algorithm. The SAR ADC includes a CDAC, which retains the remaining voltage margin after the quantization phase. The switched-capacitor module includes capacitors C0, C1, and C2. The control unit controls C0 to acquire the remaining voltage margin, integrates the acquired voltage on C0 and transfers it to C1 to form a first-order integrated signal, and integrates the remaining first-order integrated signal on C0 on C2 to form a second-order integrated signal. During the quantization phase, the two C2 capacitors form a charge pump connected end-to-end to achieve passive gain in the second-order integrated signal path. The multi-input comparator is used to enable the input signal... V in The first-order integral signal and the second-order integral signal are added together with preset weights; The digital calibration algorithm is used to calibrate the output weights of the SAR ADC, and obtains the calibrated digital output result based on the calibrated output weights and the digital code value of the ADC.

2. The noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The capacitance of C1 is equal to that of CDAC, the capacitance of C2 is half the capacitance of C1, and the capacitance of C0 is one-third the capacitance of C1.

3. The noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, During the quantization stage, the upper plates of the two C2 capacitors have the same voltage, and the two C2 capacitors form a charge pump connected end to end to achieve twice the passive gain in the second-order integral signal path.

4. The noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The multi-input comparator is used to make the input signal V in The first-order integral signal and the second-order integral signal are added with weights of 1:4:8 to achieve (1-0.75z) -1 ) 2 The noise transfer function.

5. The noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The digital calibration algorithm is used to perform FFT on the original output code value of the ADC to be calibrated, obtain the reference value of SNDR, and perform bit-by-bit calibration on the output weight of the SAR ADC according to the change of SNDR.

6. A control method for a noise-shaping successive approximation analog-to-digital converter, characterized in that, Includes the following steps: S1. After the quantization phase of the (n-1)th conversion cycle ends, the upper plate of the CDAC of the SAR ADC retains the remaining voltage margin of the conversion. S2, close switch φ CIFF0 causing the excess voltage to be harvested onto CO by charge sharing; S3, open the switch φ CIFF0 and close the switch φ CIFF1 causing the residual voltage picked up on Co to be transferred by integration to Cl to form a first order integral signal; S4, open the switch φ CIFF1 and close φ CIFF2 the remaining first order integrated signal on CO is twice integrated on C2 to form a second order integrated signal; S5, in the quantization stage, the switch φ is opened CIFF2 and the switch φ is closed N_sample so that the two C2 capacitors form a back-to-back charge pump to achieve passive gain in the second-order integration signal path; S6, Input signal V in The first-order integral signal and the second-order integral signal are added together with preset weights through a multi-input comparator to obtain the successive approximation conversion result.

7. The control method for a noise-shaping successive approximation analog-to-digital converter according to claim 6, characterized in that, The switch φ CIFF0 The switch φ CIFF1 The switch φ CIFF2 The switch φ N_sample The switching timing of the switches φ 8. A bit-by-bit weight calibration method for a noise-shaping successive approximation analog-to-digital converter, characterized in that, Includes the following steps: S1. Obtain the raw output code value of the ADC to be calibrated; S2. Perform FFT on the original output code value to obtain the reference value of SNDR; S3. Increase the output weight of the current bit to be calibrated by one step in the positive direction. mu The new digital output result is obtained based on the increased output weight and the digital code value of the ADC; S4. Perform FFT analysis on the new digital output result again to obtain the new SNDR; S5. Determine the weight adjustment direction of the current bit to be calibrated based on whether the new SNDR is increased relative to the reference value of the SNDR. S6. Iteratively adjust the output weight of the current bit to be calibrated along the determined weight adjustment direction until the SNDR decreases, and save the previous output weight as the calibration weight of the current bit to be calibrated. S7. Perform the calibration of each output weight in order from the most significant bit to the least significant bit until all output weights have been calibrated, and obtain the calibration weight vector. S8. Recalibrate the obtained calibration weight vector.

9. The bitwise weighted calibration method according to claim 8, characterized in that, The calibration of each output weight is performed sequentially from the most significant bit to the least significant bit.

10. The bitwise weighted calibration method according to claim 8, characterized in that, After obtaining the calibration weight vector, the obtained calibration weight vector is recalibrated.

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