Low-cost dv / dt sampling method and sampling circuit

Abstract

The application relates to the technical field of voltage change rate sampling, and provides a low-cost dv / dt sampling method and a sampling circuit, wherein the sampling method comprises the following steps: setting voltage thresholds; setting a first voltage threshold V1 and a second voltage threshold V2 as reference voltages of two high-speed comparators respectively; comparing a to-be-detected voltage and the voltage thresholds and outputting comparison results; inputting the to-be-detected voltage Vds into the two high-speed comparators simultaneously and comparing the to-be-detected voltage Vds with the corresponding reference voltages respectively; when the to-be-detected voltage Vds reaches the first voltage threshold V1, a first high-speed comparator U1 outputs a pulse signal to trigger an internal timer of a controller to start counting; when the to-be-detected voltage Vds reaches the second voltage threshold V2, a second high-speed comparator U2 outputs a pulse signal to trigger the timer to stop counting, and a time difference At is obtained; and obtaining a dv / dt value; and the controller obtains the dv / dt value according to a formula. The application realizes the purposes of low cost, simplified software and hardware design and easy production of a PCB board.

Description

Technical Field

[0001] This application relates to the technical field of voltage rate of change sampling, and in particular to a low-cost dvdt sampling method and sampling circuit. Background Technology

[0002] In fields such as power electronics and industrial control, accurate sampling of dv / dt (voltage change rate) is a crucial prerequisite for achieving dynamic closed-loop control and gate drive parameter adjustment of equipment, directly affecting the stability and reliability of equipment operation. Currently, there are two main traditional dv / dt sampling methods: one is to use an oscilloscope and probe for sampling, and the other is to use an ADC (analog-to-digital converter) combined with an FPGA (field-programmable gate array) for self-developed acquisition.

[0003] However, the two traditional sampling schemes mentioned above have obvious drawbacks in practical applications: when there are many workstations in the application scenario, the oscilloscope scheme requires multiple oscilloscopes and probes, and the ADC+FPGA self-developed acquisition scheme requires an independent ADC device for each workstation, which will significantly increase the hardware cost of both schemes; at the same time, the signal interaction between the ADC and the FPGA is complex, which not only requires complex hardware and software design, but also requires designing cumbersome signal traces, which increases the PCB (printed circuit board) manufacturing cost and design difficulty, and also increases the development cycle and maintenance cost of the entire sampling system. Summary of the Invention

[0004] To address the problems of high cost, complex hardware and software design, and difficult PCB fabrication in existing dv / dt sampling schemes, this application provides a low-cost dv / dt sampling method and sampling circuit.

[0005] Firstly, this application provides a low-cost DVDT sampling method, which adopts the following technical solution:

[0006] A low-cost dual comparator dv / dt sampling method includes the following steps:

[0007] Set voltage thresholds: Set a first voltage threshold V1 and a second voltage threshold V2, which will be used as reference voltages for the two high-speed comparators, respectively.

[0008] The test voltage Vds is compared with a voltage threshold, and the comparison result is output: The test voltage Vds is simultaneously input into two high-speed comparators and compared with the corresponding reference voltages respectively; when the test voltage Vds reaches the first voltage threshold V1, the first high-speed comparator U1 outputs a pulse signal to trigger the internal timer of the controller to start counting; when the test voltage Vds reaches the second voltage threshold V2, the second high-speed comparator U2 outputs a pulse signal to trigger the timer to stop counting, and the time difference Δt is obtained.

[0009] Obtaining dv / dt values: The controller calculates the dv / dt values ​​according to the formula.

[0010] By adopting the above technical solution, setting dual voltage thresholds and using a high-speed comparator to compare the voltage under test Vds, and using a pulse signal to trigger a timer to count and obtain the time difference Δt, the dv / dt value is finally calculated. The core achieves dv / dt sampling without ADC devices, which simplifies the sampling process, avoids the complex design of traditional ADC sampling schemes, and provides accurate dv / dt sampling data for subsequent dynamic closed-loop control or gate drive parameter adjustment.

[0011] Preferably, the formula is dv / dt=(V2−V1) / △t.

[0012] By adopting the above technical solution, the calculation formula for dv / dt sampling is clarified as dv / dt=(V2−V1) / △t, which ensures the accuracy and standardization of dv / dt numerical calculation, avoids sampling errors caused by unclear calculation methods, guarantees the reliability of sampling results, and enables the sampling data to be directly used in subsequent control or adjustment scenarios.

[0013] Secondly, this application provides a low-cost DVDT sampling method as described in the first aspect above, employing the following technical solution:

[0014] A low-cost dual-comparator dv / dt sampling circuit includes a first high-speed comparator U1, a second high-speed comparator U2, and a controller; the reference terminal of the first high-speed comparator U1 is connected to a first voltage threshold V1, and the reference terminal of the second high-speed comparator U2 is connected to a second voltage threshold V2; the input terminals of the two high-speed comparators are connected to the voltage to be measured Vds; the output terminals of the two high-speed comparators are both connected to the controller, and the controller integrates a timer and a counter.

[0015] The controller is configured to obtain the time difference Δt based on the time difference between the output pulses of the two comparators, and then calculate dv / dt using the formula.

[0016] By adopting the above technical solution and through the reasonable connection between the first high-speed comparator U1, the second high-speed comparator U2 and the controller, a simple dv / dt sampling circuit is constructed, realizing the hardware implementation of the aforementioned sampling method. The controller integrates timers and counters, eliminating the need for additional external timing and counter devices, further simplifying the circuit structure, reducing the number of components, and lowering the complexity of circuit design and hardware costs.

[0017] Preferably, the controller uses an FPGA and implements time difference Δt sampling through an internal ordinary counter.

[0018] By adopting the above technical solution, the controller uses an FPGA and utilizes its internal ordinary counter to achieve time difference Δt sampling, eliminating the need for an external ADC sampling module and dedicated timer. On the one hand, this greatly simplifies the resource usage of the FPGA and reduces the selection cost and development difficulty of the FPGA. On the other hand, the cost of the ordinary counter is much lower than that of the high-speed ADC, further reducing the hardware cost of the entire sampling circuit.

[0019] Preferably, the controller is connected to the two high-speed comparators via a direct pulse signal.

[0020] By adopting the above technical solution, the controller and the two high-speed comparators are connected by a direct pulse signal, which eliminates the complex signal routing between the ADC and the controller. This not only simplifies the design of the PCB board and reduces the cost of PCB manufacturing, but also reduces interference during signal transmission, improves the stability and timeliness of pulse signal transmission, and ensures the accuracy of time difference Δt sampling.

[0021] Preferably, the first voltage threshold V1 and the second voltage threshold V2 are adjustable thresholds.

[0022] By adopting the above technical solution, the first voltage threshold V1 and the second voltage threshold V2 are designed as adjustable thresholds, which enables the sampling circuit to flexibly adapt to different ranges of the voltage to be measured Vds, expands the applicable scenarios of the sampling circuit, eliminates the need to redesign the circuit for different Vds voltage ranges, and improves the versatility and practicality of the sampling circuit.

[0023] Preferably, the response speed of the first high-speed comparator U1 and the second high-speed comparator U2 is not less than 10 ns.

[0024] By adopting the above technical solution, the response speed of the two high-speed comparators is limited to no less than 10ns, ensuring that when the voltage under test Vds reaches the preset threshold, the comparator can output a pulse signal in time, avoiding the time difference Δt sampling error caused by the comparator response delay, effectively improving the accuracy of dv / dt sampling and ensuring the accuracy of the sampling results.

[0025] Preferably, the clock frequency range of the FPGA internal counter is 10MHz~100MHz.

[0026] By adopting the above technical solution, the clock frequency range of the FPGA internal counter is limited to 10MHz~100MHz. The clock frequency can be flexibly adjusted according to the actual sampling accuracy requirements, taking into account both sampling accuracy and circuit power consumption. When high-precision sampling is required, the clock frequency can be increased, and when the accuracy requirement is lower, the clock frequency can be decreased, thereby improving the flexibility and adaptability of the sampling circuit.

[0027] In summary, the present invention has the following beneficial effects:

[0028] 1. Replacing the traditional ADC sampling module with dual high-speed comparators eliminates the procurement cost of ADC devices; at the same time, it simplifies FPGA resource usage and reduces FPGA selection and development costs; the controller and comparators are directly connected, simplifying PCB routing and reducing PCB manufacturing costs, resulting in a significant reduction in overall hardware and design costs.

[0029] 2. No need to design complex interaction logic between the ADC and FPGA, no need for complex signal routing design, which greatly simplifies the hardware structure and software development workload of the sampling circuit, shortens the development cycle, and reduces development difficulty and maintenance costs.

[0030] 3. The response speed of the high-speed comparator is limited to no less than 10ns to avoid sampling errors caused by response delay; the clock frequency of the FPGA internal counter can be flexibly configured to balance sampling accuracy and power consumption; direct pulse signal connection reduces transmission interference and further ensures the accuracy and reliability of sampling results.

[0031] 4. Adjustable voltage thresholds V1 and V2, as well as configurable counter clock frequency, enable the sampling circuit to flexibly adapt to different ranges of the voltage to be measured Vds and different sampling precision requirements, without the need to redesign the circuit for different scenarios, thus improving the practicality and versatility of the sampling circuit.

[0032] 5. The circuit structure is simple, with few components, low software and hardware design difficulty, no need for complicated debugging process, and easy to mass production and practical engineering application. It can be widely used in power electronics, industrial control and other scenarios that require dv / dt sampling, providing accurate sampling data support for subsequent dynamic closed-loop control and gate drive parameter adjustment. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating the steps of a low-cost DVDT sampling method according to this application;

[0034] Figure 2 This is a circuit diagram of a low-cost DVDT sampling circuit according to this application;

[0035] Figure 3 This is a schematic diagram of the relationship between voltage and time in a low-cost dvdt sampling circuit according to this application. Detailed Implementation

[0036] Referring to the accompanying drawings and specific embodiments, the composition, features, and advantages of a low-cost DVDT sampling method and sampling circuit according to this application will be described by way of example below. However, all descriptions should not be construed as limiting this application in any way.

[0037] Furthermore, for any single technical feature described or implied in the embodiments mentioned herein, or any single technical feature shown or implied in the accompanying drawings, this application still allows for any combination or deletion of these technical features (or their equivalents) without any technical obstacle, and thus these further embodiments according to this application should also be considered within the scope of this description.

[0038] It should also be noted that terms such as "setup" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium. Unless otherwise explicitly defined, those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0039] Reference Figure 1 This application provides a dv / dt sampling method based on dual comparators for dv / dt sampling of IGBT modules in industrial control. It is compatible with a measured voltage Vds range of 0~30V, with a sampling accuracy requirement of ≤1%. It can be directly used for dynamic adjustment of IGBT gate drive parameters. The specific implementation steps are as follows:

[0040] Step S1: Set the voltage threshold.

[0041] Based on the range of the voltage to be measured Vds (0~30V) in this embodiment and the sampling accuracy requirements, the first voltage threshold V1=8V and the second voltage threshold V2=23V are set, and the two thresholds are used as the reference voltages of the first high-speed comparator U1 and the second high-speed comparator U2, respectively.

[0042] Step S2: Compare the voltage to be measured with the voltage threshold and output the comparison result.

[0043] This embodiment uses an external multi-turn adjustable resistor (model 3296W-1-103) to flexibly adjust the first voltage threshold V1 and the second voltage threshold V2, with an adjustment range of 5V~25V, adaptable to the Vds sampling requirements of IGBT modules of different specifications. The voltage Vds to be measured from the IGBT module is synchronously connected to the input terminals of two high-speed comparators through a voltage divider circuit. The two high-speed comparators compare the voltage Vds to be measured with their respective reference voltages in real time. The voltage divider resistors can be 100kΩ and 20kΩ to ensure that the voltage input to the comparators is within a safe range. Here, the first voltage threshold V1 = 8V and the second voltage threshold V2 = 23V.

[0044] When the voltage under test Vds rises to 8V, reaching the first voltage threshold V1, the first high-speed comparator U1 outputs a high-level pulse with a pulse width of 100ns, a high level of 3.3V, and a low level of 0V. This pulse signal is directly transmitted to the controller, triggering the controller's internal timer to start counting. When the voltage under test Vds continues to rise to 23V, reaching the second voltage threshold V2, the second high-speed comparator U2 outputs a high-level pulse of the same specification. This pulse signal triggers the timer to stop counting. The controller records the time interval between the two pulse signals through its internal counter, thus obtaining the time difference Δt.

[0045] Step S3: Obtain the dv / dt values.

[0046] The controller uses the formula dv / dt=(V2−V1) / Δt to calculate dv / dt=(23V−8V) / Δt=15V / Δt. The calculated dv / dt value is transmitted to the subsequent gate drive adjustment module through the controller's serial port interface to realize the dynamic adjustment of the IGBT gate drive resistance, thereby suppressing excessive dv / dt and protecting the IGBT module.

[0047] Reference Figure 2 and Figure 3 This application also provides a dv / dt sampling circuit based on dual comparators for implementing the above sampling method, including a first high-speed comparator U1, a second high-speed comparator U2, and a controller. The reference terminal of the first high-speed comparator U1 is connected to a first voltage threshold V1, and the reference terminal of the second high-speed comparator U2 is connected to a second voltage threshold V2; the input terminals of the two high-speed comparators are connected to the voltage to be measured Vds; the output terminals of the two high-speed comparators are both connected to the controller, which integrates a timer and a counter.

[0048] The selection of components, connection methods, and parameter settings of the sampling circuit in this embodiment are as follows: The two high-speed comparators are selected with a response speed of not less than 10ns. In this embodiment, the high-speed comparator model AD8561 is selected as the first high-speed comparator U1 and the second high-speed comparator U2. The response speed of this comparator is 5ns, which is much higher than the limit value. It can ensure that the pulse signal is output in time when Vds reaches the threshold, and avoid the Δt sampling error caused by response delay.

[0049] The comparator operates at 5V, supplied by an external DC power supply, and its output level matches the controller's input level, which is 3.3V, eliminating the need for additional level conversion circuitry.

[0050] The controller uses an FPGA. In this embodiment, the Altera Cyclone IV E series EP4CE6F17C8N FPGA is selected. This FPGA integrates rich logic resources. The internally integrated timers and ordinary counters can meet the sampling requirements of time difference Δt, eliminating the need for external ADC sampling modules and dedicated timers, thus simplifying the FPGA's resource usage and reducing hardware costs. The FPGA operates at 3.3V and has a clock frequency of 50MHz, provided by an external crystal oscillator.

[0051] The clock frequency range of the internal counter in the FPGA is 10MHz~100MHz. In this embodiment, based on the sampling accuracy requirements, the counter clock frequency is initially configured to 50MHz. At this time, the counting accuracy of the counter is 20ns (i.e., 1 / 50MHz), which can meet the sampling accuracy requirement of ≤1%. If higher precision sampling is required, the clock frequency can be adjusted to 100MHz, at which time the counting accuracy is improved to 10ns, and the sampling accuracy can reach 0.5%. If applied to low power consumption scenarios, the clock frequency can be reduced to 10MHz, the counting accuracy is 100ns, and the power consumption of the FPGA is reduced at the same time.

[0052] The outputs of both the first high-speed comparator U1 and the second high-speed comparator U2 are directly connected to the I / O ports of the FPGA through 100Ω current-limiting resistors. This direct pulse signal connection eliminates the need for complex communication interfaces and signal traces such as SPI and I2C between the traditional ADC and the FPGA. This not only simplifies the design of the PCB board and reduces the cost of PCB manufacturing, but also reduces electromagnetic interference during signal transmission, ensuring the stability and timeliness of pulse signal transmission, and further guaranteeing the sampling accuracy of the time difference Δt, which meets the requirements of claim 5.

[0053] The circuits for adjusting the first voltage threshold V1 and the second voltage threshold V2 consist of an adjustable resistor, a fixed resistor, and a reference voltage source. The reference voltage source is a high-precision REF3030 reference source, which outputs a stable 30V voltage as the reference for threshold adjustment. The adjustment circuit for the first voltage threshold V1 consists of a 10kΩ fixed resistor and a 10kΩ multi-turn adjustable resistor connected in series. The sliding end of the adjustable resistor is connected to the reference terminal of the first high-speed comparator U1. By adjusting the resistance value of the adjustable resistor, the first voltage threshold V1 can be continuously adjusted between 5V and 15V. The adjustment circuit for the second voltage threshold V2 consists of a 5kΩ fixed resistor and a 15kΩ multi-turn adjustable resistor connected in series. The sliding end of the adjustable resistor is connected to the reference terminal of the second high-speed comparator U2. This allows the second voltage threshold V2 to be continuously adjusted between 15V and 25V, adapting to the sampling requirements of different ranges of the measured voltage Vds.

[0054] To ensure the stability and reliability of the sampling circuit, a power supply filter circuit, an overvoltage protection circuit, and a signal filter circuit can be added. The power supply filter circuit uses a 0.1μF ceramic capacitor and a 10μF electrolytic capacitor connected in parallel at the power input terminals of the comparator and the FPGA to filter out power supply noise. The overvoltage protection circuit uses a transient suppression diode connected in parallel at the input terminal of the voltage being measured, Vds, to prevent damage to the comparator due to overvoltage. The signal filter circuit uses an RC filter circuit connected between the comparator output terminal and the FPGA input terminal to filter out high-frequency interference in the pulse signal, ensuring the accuracy of the trigger signal.

[0055] To verify whether the sampling method and sampling circuit of this embodiment meet all the limitations of the claims and the actual application requirements, the following debugging and performance verification were performed: By adjusting the adjustable resistors of V1 and V2, the voltage at the reference terminal of the comparator was measured with a multimeter. It was confirmed that V1 could be stably adjusted to 8V and V2 could be stably adjusted to 23V. The voltage fluctuation during the adjustment process was ≤0.1V, which met the stability requirements of threshold adjustment. An analog Vds signal (generated by a function generator with an adjustable rising edge slope) was connected. When the analog Vds rose to 8V, the output terminal of U1 was observed with an oscilloscope, and a high-level pulse with a width of 100ns could be observed. When Vds rose to 23V, U2 output a pulse of the same specification. The pulse was triggered in a timely manner without delay, which met the requirements of comparator response speed. The start and stop control of the timer and the counting function of the counter were implemented through FPGA programming. The Δt value and dv / dt value calculated by the FPGA were output to the computer through the serial port and compared with the time difference measured by the oscilloscope and the theoretical calculation value. The error between the two was adjusted to ≤0.5%, which met the sampling accuracy requirements.

[0056] The sampling accuracy verification results show that when the rising edge slope of the simulated Vds is set to 1.5V / μs (i.e., dv / dt = 1.5V / μs), the theoretical time difference Δt = 15V / 1.5V / μs = 10μs. The Δt obtained by FPGA sampling is 9.98μs, and the calculated dv / dt is 1.503V / μs, with a sampling error of 0.2%, which is less than the preset 1%, meeting the sampling accuracy requirements. In the threshold adjustment verification, when V1 is adjusted to 5V and V2 is adjusted to 15V, the rising edge slope of the simulated Vds is 1V / μs, and the dv / dt calculated by the FPGA is 1.002V / μs, with an error of 0.2%. When V1 is adjusted to 15V and V2 is adjusted to 25V, the rising edge slope of the simulated Vds is 2V / μs, and the calculated dv / dt is 2.005V / μs, with an error of 0.25%, proving that the threshold adjustment function is effective and adaptable to the sampling requirements of different Vds ranges. In the clock frequency adaptation verification, when the FPGA's internal counter clock frequency was adjusted to 100MHz, the counting error was ≤0.1μs and the sampling accuracy was improved to 0.5% when the sampling Δt = 10μs. When adjusted to 10MHz, the counting error was ≤1μs and the sampling accuracy was 1%, while the FPGA's power consumption decreased by 30%, proving that the clock frequency can be flexibly configured, balancing sampling accuracy and power consumption. In the stability verification, the sampling circuit was run continuously for 72 hours, connected to the Vds signal of an actual IGBT module, and the dv / dt values ​​were sampled in real time. The recorded data showed that the sampling result fluctuation was ≤0.3%, with no pulse loss or counting errors, proving that the circuit operates stably and reliably, meeting the requirements of practical engineering applications.

[0057] The sampling method and sampling circuit of this embodiment, through reasonable component selection, parameter configuration and circuit design, realize dv / dt sampling without ADC devices, simplifying hardware and software design, reducing costs, and at the same time having high sampling accuracy and versatility. It can be widely used in various scenarios that require dv / dt sampling in fields such as power electronics and industrial control, effectively solving the pain points of traditional sampling schemes.

[0058] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A low-cost dual-comparator dv / dt sampling method, characterized in that, Includes the following steps: Set voltage thresholds: Set a first voltage threshold V1 and a second voltage threshold V2, which will be used as reference voltages for the two high-speed comparators, respectively. The test voltage Vds is compared with a voltage threshold, and the comparison result is output: The test voltage Vds is simultaneously input into two high-speed comparators and compared with the corresponding reference voltages respectively; when the test voltage Vds reaches the first voltage threshold V1, the first high-speed comparator U1 outputs a pulse signal to trigger the internal timer of the controller to start counting; when the test voltage Vds reaches the second voltage threshold V2, the second high-speed comparator U2 outputs a pulse signal to trigger the timer to stop counting, and the time difference Δt is obtained. Obtaining dv / dt values: The controller calculates the dv / dt values ​​according to the formula.

2. The sampling circuit according to claim 1, characterized in that, The formula is dv / dt=(V2−V1) / △t.

3. A dv / dt sampling circuit for implementing the method as described in claim 1 or 2, characterized in that, It includes a first high-speed comparator U1, a second high-speed comparator U2, and a controller; the reference terminal of the first high-speed comparator U1 is connected to a first voltage threshold V1, and the reference terminal of the second high-speed comparator U2 is connected to a second voltage threshold V2; the input terminals of the two high-speed comparators are connected to the voltage to be measured Vds; the output terminals of the two high-speed comparators are both connected to the controller, and the controller integrates a timer and a counter. The controller is configured to obtain the time difference Δt based on the time difference between the output pulses of the two comparators, and then calculate dv / dt using the formula.

4. The sampling circuit according to claim 3, characterized in that, The controller uses an FPGA and implements time difference Δt sampling through an internal ordinary counter.

5. The sampling circuit according to claim 3, characterized in that, The controller is connected to the two high-speed comparators via a direct pulse signal.

6. The sampling circuit according to claim 3, characterized in that, The first voltage threshold V1 and the second voltage threshold V2 are adjustable thresholds.

7. The sampling circuit according to claim 3, characterized in that, The response speed of the first high-speed comparator U1 and the second high-speed comparator U2 is not less than 10 ns.

8. The sampling circuit according to claim 4, characterized in that, The clock frequency range of the internal counter of the FPGA is 10MHz~100MHz.

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