A second order noise shaping successive approximation analog-to-digital converter

Abstract

The application provides a second-order noise shaping successive approximation register analog-to-digital converter, and relates to the technical field of analog-to-digital conversion.The successive approximation register analog-to-digital converter comprises a split capacitor digital-to-analog converter, a comparator, a second-order noise shaping loop filter and a SAR logic module; the split capacitor digital-to-analog converter is used for sampling and successive approximation quantization of an input signal to generate a quantization residual; two-stage integration capacitors are used for storing and updating an integration state; an active residual amplifier is used for amplification processing to obtain residual information; two-stage residual extraction capacitors are used for temporarily storing the residual information and providing the residual information for the two-stage integration capacitors to update the integration state; the comparator is used for outputting a level decision result; and the SAR logic module is used for controlling the split capacitor digital-to-analog converter to perform capacitor complementary switching. By using the above-mentioned second-order noise shaping successive approximation register analog-to-digital converter, the problems of low noise shaping capability and poor stability are solved.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital conversion technology, and more specifically, to a second-order noise-shaping successive approximation analog-to-digital converter. Background Technology

[0002] Successive approximation register analog-to-digital converters (SAR ADCs) offer advantages such as low power consumption and high energy efficiency, making them widely used in low-power, high-precision scenarios such as IoT sensing and portable medical testing. The conversion accuracy of traditional Nyquist SAR ADCs is easily limited by factors such as quantization noise, comparator input noise, sampling noise, and capacitor array mismatch. Simply increasing the capacitor size of the capacitor-based digital-to-analog converter (CDAC) and reducing comparator noise to increase the effective number of bits would significantly increase chip area and overall dynamic power consumption, making it difficult to balance energy efficiency and high accuracy requirements. To address the pain point of quantization noise limiting accuracy, the industry generally adopts noise shaping techniques combined with oversampling architectures. This involves shifting in-band quantization noise to higher frequency bands, thereby improving the signal-to-noise ratio within the signal bandwidth. Among them, the Cascaded Integrator Feedforward (CIFF) noise-shaping SAR ADC can rely on a multi-level integral network to construct high-order noise-shaping zeros, thereby achieving deep suppression of in-band quantization noise.

[0003] However, existing cascaded integrator-feedforward NS-SAR ADCs have the following drawbacks: For fully passive switched-capacitor integrator noise-shaping SAR ADCs, the residual signal is prone to attenuation during multi-stage charge sharing, resulting in reduced residual utilization efficiency and limited noise shaping capability; For fully active integrators or noise-shaping SAR ADCs with added independent residual amplification links, although the residual amplitude can be improved, additional power consumption is introduced, leading to gain drift under PVT (Process-Voltage-Temperature) conditions, which affects the stability of noise shaping. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a second-order noise-shaping successive approximation analog-to-digital converter to overcome at least one of the above-mentioned defects.

[0005] In a first aspect, embodiments of this application provide a second-order noise-shaping successive approximation analog-to-digital converter. The second-order noise-shaping successive approximation analog-to-digital converter includes a split-capacitor digital-to-analog converter, a second-order noise-shaping loop filter, a comparator, and a SAR logic module. The second-order noise-shaping loop filter includes an active residual amplifier, two stages of residual decimation capacitors, and two stages of integrating capacitors. The two stages of integrating capacitors include a first integrating capacitor and a second integrating capacitor. A split-capacitor digital-to-analog converter is used to sample the input signal, perform successive approximation quantization, and generate quantization residuals. Two-stage integrating capacitors are used to store the integration state. The integration state is updated by sharing the passive charge with the corresponding residual extraction capacitor. The integration state is then fed forward to the comparator to construct a second-order noise shaping loop. The integration state includes a first-stage integration state and a second-stage integration state. The input terminal of the active residual amplifier is connected to the first integrating capacitor, and the output terminal is connected to the two-stage residual decimation capacitor. It is used to amplify the composite signal during the residual decimation stage to obtain the amplified residual information. The composite signal includes the quantization residual output by the split capacitor digital-to-analog converter after the SAR logic module conversion and the first-stage integrating state of the previous cycle. Two-stage residual extraction capacitors are connected to the corresponding integrating capacitors through a noise shaping control switch to temporarily store residual information. During the noise shaping phase, residual information is provided to the two-stage integrating capacitors through passive charge sharing to update the integration state. The input of the comparator is connected to two-stage integrating capacitors to compare the differential voltage after superimposing the quantization residual, the first-stage integration state, and the second-stage integration state, and outputs the level decision result. The SAR logic module is connected to the output of the comparator to receive the level decision result. Based on the level decision result, it controls the split capacitor digital-to-analog converter to perform capacitor complementary switching to complete successive approximation quantization.

[0006] In an optional implementation, the complete conversion cycle sequentially includes a sampling phase, a SAR conversion phase, and a residual decimation phase. In the sampling phase, the sampling timing signal is valid, the split-capacitor digital-to-analog converter completes the sampling of the analog input signal, the two-stage integrating capacitors are reset to the common-mode reference state, and the active residual amplifier is turned off. In the SAR conversion phase, the noise shaping timing signal is valid, the residual decimation capacitor and the corresponding integrating capacitor update the integration state through passive charge sharing, the comparator outputs decision pulses sequentially, and the SAR logic module controls the split-capacitor digital-to-analog converter to complete bit-by-bit quantization. In the residual decimation phase, the residual decimation timing signal is valid, the active residual amplifier is turned on, and the amplified residual information is synchronously stored in the residual decimation capacitor.

[0007] In an optional implementation, the two-stage residual decimation capacitor includes a first residual decimation capacitor and a second residual decimation capacitor. The first residual decimation capacitor is connected to the first integrating capacitor via a first noise shaping control switch and is used to temporarily store the residual information output by the active residual amplifier in the previous cycle. In the noise shaping phase of the current cycle, it performs charge sharing with the first integrating capacitor to form a first-stage integration state. The second residual decimation capacitor is connected to the second integrating capacitor via a second noise shaping control switch and is used to temporarily store the residual information output by the active residual amplifier in the previous cycle. In the noise shaping phase of the current cycle, it performs charge sharing with the second integrating capacitor to update the second-stage integration state.

[0008] In an optional implementation, the first-level integration state of the current period includes the residual information of the current period and the first-level integration state of the previous period; the second-level integration state of the current period includes the residual information of the current period and the second-level integration state of the previous period.

[0009] In an optional implementation, the first equivalent charge sharing coefficient corresponding to the first residual decimation capacitor and the first integration capacitor is determined based on the ratio of the first residual decimation capacitor value to the first capacitor sum value, where the first capacitor sum value is the sum of the first residual decimation capacitor value and the first integration capacitor value; the first-stage integration state is determined based on the product of the first equivalent charge sharing coefficient, the passive gain, and the residual information.

[0010] In an optional implementation, the second equivalent charge sharing coefficient corresponding to the second residual decimation capacitor and the second integration capacitor is determined based on the ratio of the second residual decimation capacitor value to the sum of the second capacitor values, where the sum of the second capacitor values ​​is the sum of the second residual decimation capacitor values ​​and the second integration capacitor values; the second-level integration state is determined based on the sum of the product of the second equivalent charge sharing coefficient, the passive gain, and the residual information, and the second-order historical residual, where the second-order historical residual is determined based on the product of the difference between the preset value and the second equivalent charge sharing coefficient and the second-level integration state of the previous cycle.

[0011] In an optional implementation, the sampling timing signal includes a sampling switch timing signal and a common-mode reset timing signal, wherein the common-mode reset timing signal ends earlier than the sampling switch timing signal.

[0012] In an optional implementation, the split-capacitor digital-to-analog converter includes multiple equivalent common-mode access units. Each equivalent common-mode access unit includes a first capacitor and a second capacitor with equal values. The base plate of the first capacitor is connected to a reference voltage, and the base plate of the second capacitor is grounded. During the sampling phase, the first capacitor and the second capacitor cooperate to form an equivalent common-mode charge effect. During the conversion phase, the first capacitor and the second capacitor at the differential terminals perform complementary switching.

[0013] In an optional implementation, the product of the first equivalent charge sharing coefficient, the passive gain, and the amplification gain of the active residual amplifier is 1.

[0014] In an optional implementation, the product of the second equivalent charge sharing coefficient, the passive gain, and the amplification gain of the active residual amplifier is 1, so that the successive approximation analog-to-digital converter has a second-order noise shaping effect.

[0015] The embodiments of this application bring the following beneficial effects: This application provides a second-order noise-shaping successive approximation analog-to-digital converter (ADC), including a split-capacitor ADC, a second-order noise-shaping loop filter, a comparator, and a SAR logic module. The second-order noise-shaping loop filter includes an active residual amplifier, two stages of residual decimation capacitors, and two stages of integrating capacitors. The two stages of integrating capacitors include a first integrating capacitor and a second integrating capacitor. The split-capacitor ADC is used to sample the input signal, perform successive approximation quantization, and generate quantization residuals. The two stages of integrating capacitors are used to store the integration state, update the integration state through passive charge sharing with the corresponding residual decimation capacitors, and feed the integration state forward to the comparator to construct a second-order noise-shaping loop. The integration state includes a first-stage integration state and a second-stage integration state. The input terminal of the active residual amplifier is connected to the first integrating capacitor, and the output terminal is connected to the two stages of residual decimation capacitors. This is used to amplify the composite signal during the residual decimation stage to obtain amplified residual information. The composite signal includes the quantization residual output by the split-capacitor digital-to-analog converter after conversion by the SAR logic module and the first-stage integration state of the previous cycle. Two-stage residual decimation capacitors are connected to the corresponding integration capacitors through a noise shaping control switch to temporarily store residual information. During the noise shaping phase, passive charge sharing is used to provide residual information to the two-stage integration capacitors to update the integration state. The input of the comparator is connected to the two-stage integration capacitors to compare the differential voltage after superimposing the quantization residual, the first-stage integration state, and the second-stage integration state, and output the level decision result. The SAR logic module is connected to the output of the comparator to receive the level decision result and control the split-capacitor digital-to-analog converter to perform capacitor complementary switching based on the level decision result to complete successive approximation quantization.

[0016] This application embodiment can construct a second-order noise shaping loop by using an active residual amplifier to amplify the residual for a short time, combined with passive charge sharing of two-stage capacitors. On the one hand, the active residual amplifier compensates for the residual attenuation problem of the all-passive architecture, improving the noise shaping depth; on the other hand, the fixed charge sharing coefficient formed by matching the residual decimation capacitor and the integrating capacitor, combined with the amplifier gain to coordinate the loop characteristics, alleviates the loop performance degradation caused by amplifier gain drift. At the same time, the time-sharing operation of the active residual amplifier significantly reduces static power consumption and additional noise, effectively improving the signal-to-noise ratio and effective accuracy of analog-to-digital conversion. Compared with the successive approximation analog-to-digital converters in the prior art, it solves the problems of low noise shaping capability and poor noise shaping stability.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The circuit diagram of the second-order noise-shaping successive approximation analog-to-digital converter provided in the embodiments of this application is shown; Figure 2 A schematic diagram of the switching timing provided in an embodiment of this application is shown; Figure 3 A flowchart of the circuit signal system provided in an embodiment of this application is shown; Figure 4 The simulated signal spectrum of a prior art successive approximation analog-to-digital converter is shown; Figure 5 The simulated signal spectrum of the second-order noise-shaping successive approximation analog-to-digital converter provided in the embodiments of this application is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0021] Please see Figure 1 , Figure 1 This application provides a second-order noise-shaping successive approximation analog-to-digital converter (ADC). For example... Figure 1 As shown in the embodiment of this application, the second-order noise-shaping successive approximation analog-to-digital converter includes: a split-capacitor digital-to-analog converter 100, a second-order noise-shaping loop filter 200, a comparator 300, and a SAR logic module 400. The second-order noise-shaping loop filter 200 includes an active residual amplifier G, two stages of residual decimation capacitors, and two stages of integrating capacitors. The split-capacitor digital-to-analog converter 100, the two stages of residual decimation capacitors, and the two stages of integrating capacitors all adopt a differential symmetrical structure, with positive and negative differential capacitor branches respectively configured.

[0022] The two-stage residual extraction capacitor is denoted as: The two-stage residual decimation capacitor includes the first residual decimation capacitor. Second residual extraction capacitor First residual extraction capacitor This can refer to the first-stage residual decimation capacitor, which includes the first residual decimation capacitor located at the positive terminal of the differential circuit. The first residual decimation capacitor located at the negative terminal of the differential circuit. Second residual extraction capacitor This can refer to the second-stage residual decimation capacitor, which includes the second residual decimation capacitor located at the positive terminal of the differential. The second residual decimation capacitor located at the negative end of the differential circuit. .

[0023] The two-stage integrating capacitor is denoted as: Two-stage integrating capacitor This includes the first integrating capacitor and the second integrating capacitor. The first integrating capacitor is denoted as: First integrating capacitor This can refer to the first-stage integrating capacitor, the first integrating capacitor. Including the first integrating capacitor located at the positive terminal of the differential circuit. The first integrating capacitor located at the negative terminal of the differential circuit. The second integrating capacitor is denoted as: The second integrating capacitor can refer to the second-stage integrating capacitor. Including the second integrating capacitor located at the positive terminal of the differential circuit. The second integrating capacitor located at the negative terminal of the differential circuit. .

[0024] A split-capacitor digital-to-analog converter 100 is used to sample the input signal, perform successive approximation quantization, and generate quantization residuals. Two-stage integrating capacitors are used to store the integration state. The integration state is updated by sharing the passive charge with the corresponding residual extraction capacitor. The integration state is then fed forward to the comparator to construct a second-order noise shaping loop. The integration state includes a first-stage integration state and a second-stage integration state. The input terminal of the active residual amplifier G is connected to the first integrating capacitor, and the output terminal is connected to the two-stage residual decimation capacitor. It is used to amplify the composite signal in the residual decimation stage to obtain the amplified residual information. The composite signal includes the quantization residual output by the split capacitor digital-to-analog converter 100 after the SAR logic module 400 conversion and the first-stage integrating state of the previous cycle. Two-stage residual extraction capacitors are connected to the corresponding integrating capacitors through a noise shaping control switch to temporarily store residual information. During the noise shaping phase, residual information is provided to the two-stage integrating capacitors through passive charge sharing to update the integration state. The noise shaping control switch is denoted as: The noise shaping control switch includes a first noise shaping control switch. Second noise shaping control switch First noise shaping control switch Including the first noise shaping control switch located at the positive terminal of the differential. The first noise shaping control switch located at the positive terminal of the differential circuit. Second noise shaping control switch Including a second noise shaping control switch located at the positive terminal of the differential circuit. The second noise shaping control switch located at the positive terminal of the differential circuit. .

[0025] The input of comparator 300 is connected to two-stage integrating capacitors to compare the differential voltage after superimposing the quantization residual, the first-stage integrating state, and the second-stage integrating state, and outputs the level decision result. The SAR logic module 400 is connected to the output of the comparator 300 to receive the level decision result. Based on the level decision result, it controls the split capacitor digital-to-analog converter 100 to perform capacitor complementary switching to complete successive approximation quantization.

[0026] In one embodiment, the split-capacitor digital-to-analog converter 100 includes a plurality of equivalent common-mode access units 110, each equivalent common-mode access unit including a first capacitor and a second capacitor of equal value, the base plate of the first capacitor being connected to a reference voltage. Connect the second capacitor to ground (GND).

[0027] Specifically, the split-capacitor digital-to-analog converter 100 is not a traditional bridged segmented CDAC, but rather a traditional... -based CDAC and efficient access One capacitor unit is split into two equivalent capacitors, namely a first capacitor and a second capacitor, which together constitute an equivalent common-mode access unit. The base plate of the first capacitor is connected to... (i.e., continue) The base plate of the second capacitor is connected to (i.e., connect to GND).

[0028] Understandably, in a traditional structure, one capacitor is connected to... In this embodiment, the capacitor is split into two equal capacitors, with one equal capacitor reset to... Another capacitor of equal value is reset to GND. Because Then the two equal capacitors are connected respectively After connecting to GND, from the perspective of equivalent charge, it is connected to a capacitor in a traditional structure. The effect is the same, so that in the sampling phase, the first capacitor and the second capacitor work together to form an equivalent common-mode charge effect. The complete conversion cycle of a second-order noise-shaping successive approximation analog-to-digital converter includes the sampling stage, the SAR conversion stage, and the residual extraction stage.

[0029] In one embodiment, the sampling phase may refer to the first working phase of a complete conversion cycle, effectively driven by a sampling timing signal, and used to complete two operations: sampling the differential analog input signal and resetting the capacitor array and two-stage integrating capacitors of the split-capacitor digital-to-analog converter 100 to the common-mode reference state. The sampling timing signal includes a sampling switch timing signal. Common-mode reset timing signal Sampling switch timing signal Common-mode reset timing signal Both are effective, but the common-mode reset timing signal Earlier than the sampling switch timing signal Finish.

[0030] During the sampling phase, the sampling switch timing signal will be used. Setting it to high (active) controls the closing of the sampling switch in the split-capacitor digital-to-analog converter 100, and the differential input signal... , The sampled signal is fed into the split-capacitor CDAC so that the split-capacitor digital-to-analog converter 100 can begin to sample the analog input signal. The entire sampling phase is completed with sample-and-hold, and the complete sampling is only completed at the end of the phase.

[0031] Common-mode reset timing signal Setting it to high (active) controls the reset switch to turn on, thereby resetting the relevant nodes of the two-stage integrating capacitor to the common-mode voltage. When the two ends of the integrating capacitor are at the same potential, the internal charge of the integrating capacitor is completely released, and the voltage is forcibly clamped to... This resets the circuit to the common-mode reference state, clearing the residual charge stored in the previous cycle's integral. This prevents the overlap of offset noise shaping loop coefficients between the old and new integral states, and provides a stable and unified common-mode reference for charge sharing and residual amplification. The reset switch is denoted as: The reset switch includes a first reset switch. and the second reset switch The first reset switch includes a first reset switch located at the differential positive terminal. The first reset switch located at the negative terminal of the differential circuit. The second reset switch includes a second reset switch located at the differential positive terminal. The second reset switch located at the negative terminal of the differential circuit. .

[0032] Noise shaping timing signal When set to low level, the noise shaping control switch is turned off, and the connection between the two-stage integrating capacitor and the two-stage residual extraction capacitor is broken.

[0033] Simultaneously, the residual decimation time signal will be extracted. When set to low level, the residual extraction capacitor is disconnected from the output of the active residual amplifier G, and the pulse timing signal is compared. When set to low, comparator 300 does not perform a decision. The positive residual node... With positive end first-level integral node The first residual extraction capacitor between The first residual decimation capacitor is connected to the output of the active residual amplifier G. It is the same capacitor; negative terminal residual node With the negative end first-level integration node The first residual extraction capacitor between The first residual decimation capacitor is connected to the output of the active residual amplifier G. It's the same capacitor; it's displayed in two different places for easier viewing. Similarly, the capacitors in different locations... This indicates the same capacitor at different locations. It also indicates the same capacitor.

[0034] In this way, only the input signal sampling and circuit initialization are completed during the sampling phase, providing the reference initial conditions for subsequent SAR quantization, noise shaping, and charge sharing.

[0035] In one embodiment, the SAR conversion stage can refer to the stage in which the analog input voltage sampled by the split capacitor digital-to-analog converter 100 is converted into binary digital code through successive approximation binary quantization; at the same time, passive charge sharing is synchronously executed, the two-stage noise shaping state is updated and fed forward to the comparator, and the noise shaping closed-loop operation is completed.

[0036] During the SAR conversion phase, noise-shaping time-series signals are performed. When set to high level (valid), the residual extraction capacitor and the corresponding integration capacitor update the integration state through passive charge sharing.

[0037] For example: the first residual extraction capacitor Through the first noise shaping control switch With the first integrating capacitor The connection is used to temporarily store the residual information of the active residual amplifier G output in the previous cycle, and is used in the noise shaping phase of the current cycle in conjunction with the first integrating capacitor. Perform charge sharing to form the first-level integral state; second residual decimation capacitor. Through the second noise shaping control switch With the second integrating capacitor The connection is used to temporarily store the residual information of the active residual amplifier G output in the previous cycle, and is used in the noise shaping phase of the current cycle in conjunction with the second integrating capacitor. Charge sharing is performed to update the second-stage integration state. As a result, a first-stage integration state is formed on the first integrating capacitor, and a second-stage integration state is formed or updated on the second integrating capacitor. These two integration states act on the comparator input through a capacitor feedforward path, participating in the SAR decision for the current cycle together with the residual signal output from the split-capacitor digital-to-analog converter 100. Specifically, the first-stage integration state of the current cycle includes the residual information of the current cycle and the first-stage integration state of the previous cycle; the second-stage integration state of the current cycle includes the residual information of the current cycle and the second-stage integration state of the previous cycle.

[0038] Comparator 300 outputs decision pulses sequentially. After each level decision by comparator 300, the SAR logic module 400 controls the split capacitor of the current bit to switch complementaryly based on the level decision result. For example, if the current level decision result indicates that the positive terminal voltage is less than the negative terminal voltage, i.e. Then the original base plate in the current position of the negative end is connected The capacitor is switched to GND, and the capacitor originally connected to GND on the base plate in the current position of the positive terminal is switched to... If the level decision results are opposite, then complementary switching in the opposite direction is performed, that is, the first capacitor and the second capacitor at both ends of the differential switch perform complementary switching.

[0039] The input of comparator 300 is superimposed with three signals: the quantization residual voltage generated by the split-capacitor digital-to-analog converter 100 in the current cycle, the feedforward voltage of the first-stage integration state, and the feedforward voltage of the second-stage integration state. These three signals are superimposed to form a differential voltage. (Positive) (Negative end), the comparator receives each time. Pulse comparison only and The magnitude relationship determines the output high and low levels to the SAR logic module 400.

[0040] Because the capacitor arrays at both ends of the differential circuit undergo complementary changes during each switching process, the potentials at both the positive and negative terminals are adjusted. Therefore, the common-mode level at the input of comparator 300 can be maintained close to... The location. This method differs from the traditional -based CDACs have similar common-mode holding effects, but avoid direct transmission from the lower plate of the CDAC. This helps improve the reliability of switches under conditions of low power supply voltage, low temperature, and slow process angle.

[0041] Meanwhile, the SAR logic module 400 controls the split-capacitor digital-to-analog converter 100 to complete bit-by-bit quantization.

[0042] In one embodiment, the residual decimation stage can refer to the working stage after the SAR conversion stage is completed in a single conversion cycle of the analog-to-digital converter, where the residual decimation timing signal is extracted. The active residual amplifier G is briefly turned on to amplify the composite signal of the current cycle's quantized residual superimposed with the first-stage integral state of the previous cycle. The amplified residual information is then stored in two-stage residual decimation capacitors, providing a signal source for passive charge sharing in the noise-shaping phase of the next cycle. During the residual decimation stage, no comparison decision or integral state update is performed.

[0043] During the residual decimation stage, the SAR conversion stage has been completed, and the quantization residual of the current period is retained on the top plate or residual node of the split-capacitor digital-to-analog converter 100. Residual decimation timing signal When set to high level, the active residual amplifier G is turned on. Its input receives the composite signal formed by the quantization residual of the current cycle and the first-stage integral state of the previous cycle, and amplifies it to obtain the amplified residual information. Timing signals are extracted through the residual. When the residual decimation control switch is closed, the output of the active residual amplifier G is connected to the two-stage residual decimation capacitor. The connection synchronously stores the amplified residual information into the two-stage residual extraction capacitors. After the residual extraction is completed, When set to low, the residual extraction capacitor retains the amplified residual information for use in the next cycle. In the phase, it shares charge with the integrating capacitor.

[0044] During the residual extraction stage, comparator 300 is subjected to... Control, residual extraction stage If the signal is low, comparator 300 will fail.

[0045] The following reference Figure 2 This section will introduce the timing relationships between different timing signals.

[0046] Figure 2 A schematic diagram of the switching timing provided in an embodiment of this application is shown, as follows: Figure 2 As shown, S1 represents the sampling stage, S2 represents the SAR conversion stage, and S3 represents the residual extraction stage.

[0047] In one embodiment, in the differential positive end path, the positive end residual node The first integrating capacitor with the positive terminal One end is connected, The other end is connected to the first-level integration node of the positive end. Connection, positive end first-level integration node It is simultaneously connected to the positive input terminal of the active residual amplifier G, and through the second integrating capacitor at the positive terminal. Connect to the positive input of comparator 300.

[0048] In the negative-end path of the difference, the negative-end residual node The first integrating capacitor with the negative terminal One end is connected, The other end and the negative end first-level integration node Connection, negative end first-level integration node It is simultaneously connected to the negative input terminal of the active residual amplifier G, and through the second integrating capacitor. Connect to the negative input terminal of comparator 300.

[0049] The input of the active residual amplifier G is connected to the differential residual signal path consisting of residual nodes (including positive and negative residual nodes) and a first-stage integration node (including positive and negative first-stage integration nodes). The output of the active residual amplifier G is connected to two-stage residual decimation capacitors via a residual decimation control switch. Connection. In the residual decimation phase, the active residual amplifier G stores the amplified residual information into two stages of residual decimation capacitors. The residual decimation control switch is denoted as: Residual extraction control switch Including the first residual extraction control switch Second residual extraction control switch First residual extraction control switch Includes a first residual extraction control switch connected to the first residual extraction capacitor at the positive terminal. The first residual extraction control switch connected to the negative terminal of the first residual extraction capacitor Second residual extraction control switch Includes a second residual extraction control switch connected to the positive terminal of the second residual extraction capacitor. The second residual extraction control switch connected to the negative terminal of the second residual extraction capacitor .

[0050] The positive and negative input terminals of comparator 300 are respectively connected to the positive output node of second-order noise shaping loop filter 200. and negative output node The output nodes of the second-order noise shaping loop filter 200 (including the positive and negative output nodes) simultaneously receive the input residual information, the feedforward signal of the first-stage integration state, and the feedforward signal of the second-stage integration state from the split-capacitor digital-to-analog converter 100. The output of the comparator 300 is connected to the SAR logic module 400, which controls the switching of each split capacitor in the split-capacitor digital-to-analog converter 100 based on the level decision result of the comparator 300.

[0051] In one embodiment, the active process of this application is implemented by an active residual amplifier G.

[0052] The active residual amplifier G operates only during the residual decimation stage. Its function is to amplify the quantization residual of the current cycle and the first-stage integral state of the previous cycle to obtain amplified residual information. This amplified residual information (residual voltage) is stored on the residual decimation capacitor and used to update the integral state in the next cycle. In this embodiment, the amplification gain g of the active residual amplifier G is 10, i.e. Therefore, the active residual extraction process can be expressed as: ,in, This represents the quantization residual after the SAR conversion ends in the nth period. This represents the first-level integral state of the previous cycle.

[0053] In one embodiment, the passive process of this application mainly consists of two parts.

[0054] The first part is the charge redistribution process of the split-capacitor digital-to-analog converter 100, that is, controlling the split capacitor base plate through the SAR logic module 400. It can switch complementaryly with GND to achieve successive approximation quantization.

[0055] The second part is the charge sharing process between the residual descent capacitor and the integrating capacitor, i.e. and The shared charge forms the first-order integral state. and The shared charge forms the second-stage integration state. Since the integration state is stored and updated by the capacitor charge, this part does not require a continuous-time high-power integrator.

[0056] In other words, the active residual amplifier G is responsible for increasing the amplitude of the residual information, while the passive capacitor network is responsible for storing, distributing, and updating the integral state. Together, they form a second-order cascaded integrator feedforward noise shaping loop.

[0057] The following section introduces the correspondence between the integral state and the actual circuit elements.

[0058] First-level integral state Corresponding to the first integrating capacitor , The differential voltage on the plate. The first-stage integral state is controlled by the first residual decimation capacitor during the residual decimation stage. , With the first integrating capacitor , Charge sharing is formed. The first residual extraction capacitor stores the amplified residual information output by the active residual amplifier G in the previous cycle. Therefore, the first-stage integral state reflects the result of the combined effect of active residual extraction and passive charge sharing.

[0059] Second-level integral state Corresponding to the second integrating capacitor , The differential voltage on the capacitor. The second-stage integral state is controlled by the second residual decimation capacitor during the residual decimation phase. , With the second integrating capacitor , Charge sharing is formed. During the update process, the second integrating capacitor retains a portion of the second-level integrating state from the previous cycle. Therefore, the second-level integrating state not only contains the newly injected amplified residual information but also the second-level integrating state from the previous cycle, thus forming the second state variable required for second-order noise shaping.

[0060] Both the first-stage and second-stage integral states are fed forward to the input of comparator 300 via a capacitor connection path. Therefore, this structure belongs to a cascaded integrator-feedforward noise shaping structure.

[0061] In one embodiment, the two integral states of second-order noise shaping are mainly implemented by a first integrating capacitor and a second integrating capacitor. The first-stage integral state corresponds to the first integrating capacitor. , The differential voltage stored above corresponds to the second integrating capacitor in the second-stage integration state. , The differential voltage stored on it.

[0062] First residual extraction capacitor , Used to store the amplified residual information output by the active residual amplifier G into the first integrating capacitor; the second residual extraction capacitor , This is used to store the amplified residual information from the output of the active residual amplifier G into the second integrating capacitor. Therefore, and Together they determine the first-level integral coefficient (i.e., the first equivalent charge sharing coefficient). and Together they determine the second-level integral coefficient (i.e., the second equivalent charge sharing coefficient).

[0063] During the residual extraction phase, the SAR conversion is completed, and the quantization residual of the current period is retained at the output node of the split-capacitor digital-to-analog converter 100, denoted as: The input of the active residual amplifier G is connected to the residual node and the first-stage integrator node of the split-capacitor digital-to-analog converter 100. Therefore, the input signal of the active residual amplifier G is equivalent to the sum of the current cycle residual and the first-stage integrator state of the previous cycle, i.e. Since the gain g of the active residual amplifier G is 10, the amplified residual signal output by the active residual amplifier is: .

[0064] During the residual decimation stage, the residual decimation control switch is closed, causing the output terminals of the active residual amplifier G to be connected to... , , , The amplified residual information is then simultaneously sampled and stored on both the first and second residual extraction capacitors. , The voltage stored above is used to form the first-stage integration state in the next cycle. , The voltage stored above is used to update the second-stage integral state in the next cycle.

[0065] In the noise shaping phase, i.e. During the effective period, the first noise shaping control switch between the first residual extraction capacitor and the first integrating capacitor is closed. At this time, and , and Passive charge sharing occurs, and the amplified residual information is stored in the first integrating capacitor. Let the first equivalent charge sharing coefficient between the first residual extraction capacitor and the first integrating capacitor be: In practical circuits, the first equivalent charge sharing coefficient is determined by... and The capacitance ratio (or and The capacitance ratio is determined by the capacitance. If parasitic capacitance is considered, then... This can be understood as the equivalent integral capacitance including the parasitic capacitance of related nodes.

[0066] Since a differential structure is used, the equivalent passive gain m of the first integration path is 2. Therefore, the differential integration state stored in the first integration capacitor is: .Will Substituting into the previous formula, we get: .set up Then we have: ,so .

[0067] The above equation shows that the differential voltage across the first integrating capacitor realizes the first-stage discrete-time integration state. In other words, the quantization residual of the current period is amplified by the active residual amplifier G, and then... and The passive charge sharing is stored in the first-level integration node, thus forming the first-level integration state. The second-level integration state is formed by... and Charge sharing is achieved. During the effective period, the switch between the second residual extraction capacitor and the second integrating capacitor is closed. At this time, The magnified residual information stored above is injected ,at the same time A portion of the second integral state from the previous cycle, which was originally saved, is retained.

[0068] Let the second equivalent charge sharing coefficient between the second residual decimation capacitor and the second integrating capacitor be: ,in, Depend on and The capacitance ratio (or and The capacitance ratio is determined by the capacitance. Since the second integrating capacitor retains a portion of the original charge after charge sharing, the retention coefficient of the second-level integrating state in the previous cycle is: Therefore, the second-order integral state can be expressed as: ,Will Substituting into the formula, we get: .

[0069] In this embodiment of the application, the following is set Then there is , .therefore, This equation shows that the differential voltage across the second integrating capacitor includes not only the quantization residual of the current cycle and information from the first-stage integrating state, but also the retained terms of the second-stage integrating state from the previous cycle. Therefore, , This corresponds to the second-level integral state in second-order noise shaping.

[0070] From a practical circuit perspective, the first-stage integral state is output from the active residual amplifier G and then... deposit The second-stage integral state is obtained by the output of the same active residual amplifier G via... deposit and superimposed The integral state of the previous cycle is retained. Therefore, in this embodiment, only one active residual amplifier G is needed to drive the two-stage integral state update simultaneously, while the storage and update of the two-stage integral states are mainly accomplished by passive capacitors.

[0071] The first-stage integration state and the second-stage integration state are superimposed on the input of comparator 300 via a capacitor connection path in a feedforward manner. Specifically, the first-stage integration state on the first integrating capacitor and the second-stage integration state on the second integrating capacitor work together at the input of comparator 300, so that the signal actually compared by comparator 300 includes not only the quantization residual of the split capacitor digital-to-analog converter 100 in the current cycle, but also the noise shaping state of the previous cycle. This feedforward summation process corresponds to the cascaded integral feedforward path in the flowchart.

[0072] In summary, the correspondence between each integration state and the actual circuit element in the embodiments of this application is as follows: First-level integration state The charge is generated by the shared charge of the first residual extraction capacitor and the first integrating capacitor, and stored on the first integrating capacitor; the second integration state The charge sharing between the second residual extraction capacitor and the second integrating capacitor is updated and stored on the second integrating capacitor; the active residual amplifier G is responsible for providing amplified residual information, the split capacitor digital-to-analog converter 100 is responsible for generating the quantization residual of the current cycle, and the input of the comparator 300 completes the feedforward summation of the quantization residual of the current cycle and the two-stage integration state.

[0073] In one embodiment, the formula for a general second-order CIFF loop filter is: ; Based on the above cascaded integral feedforward relationship, the second-order noise shaping loop filter 200 of this application embodiment can be expressed as: ; Since the noise transfer function is as follows under the linearization model of the quantizer: Therefore, we can conclude that: ; Further factorization is as follows: ; Therefore, it can be seen that the noise transfer function is in It has a zero point, and at It has another zero point close to the unit circle. Therefore, the embodiments of this application can effectively suppress quantization noise within the signal bandwidth and shape the quantization noise to the out-of-band high-frequency region, achieving a noise shaping effect close to second order.

[0074] The following reference Figure 3 This section will introduce the process of circuit signal processing.

[0075] Figure 3 A flowchart of the circuit signal system provided in an embodiment of this application is shown, such as Figure 3 As shown, This represents the discrete delay operator, which represents a unit delay of one conversion cycle; Indicates the first equivalent charge sharing coefficient; represents the second equivalent charge sharing coefficient; m represents the passive gain of the differential symmetry structure, with a value of 2; g represents the amplification gain of the active residual amplifier G. The input signal IN is processed by two integration branches to obtain the output signal OUT. These two integration branches include a first integration branch 510 and a second integration branch 520. The first integration branch 510 is the first integrating capacitor. The corresponding branch; the second integrating branch 520 is the second integrating capacitor. The corresponding branch road.

[0076] The following reference Figure 4 and Figure 5 This paper will introduce the actual effects of the second-order noise-shaping successive approximation analog-to-digital converter provided in the embodiments of this application.

[0077] Figure 4 The simulated signal spectrum of a prior art successive approximation analog-to-digital converter is shown, such as... Figure 4 As shown, in the simulated signal spectrum of a successive approximation analog-to-digital converter (ADC) in the prior art, the ENOB (Effective Number of Bits) is 9.9. Here, the effective number of bits refers to the equivalent quantization accuracy that the ADC can actually achieve under the test conditions; SNDR (Signal-to-Noise-and-Distortion Ratio) represents the calculated equivalent ideal number of bits. The horizontal axis (frequency) represents the signal frequency, and the vertical axis (Power Spectral Density, PSD) represents the power spectral density.

[0078] Figure 5 The simulated signal spectrum of the second-order noise-shaping successive approximation analog-to-digital converter provided in the embodiments of this application is shown, as follows: Figure 5 As shown in the simulation signal spectrum of the second-order noise-shaping successive approximation analog-to-digital converter provided in the embodiments of this application, noise suppression of nearly 80dB is provided at low frequencies, quantization noise is shifted to the high-frequency part, and the noise slope of the high-frequency part is 40dB / dec. When the OSR (Oversampling Ratio) is 16, the effective number of bits can be increased from 9.9 bits to 17.85 bits.

[0079] As can be seen from behavioral-level spectrum simulation, the active-passive synergistic cascaded integrator-feedforward second-order noise shaping structure proposed in this application can effectively suppress quantization noise within the signal bandwidth and shape the quantization noise to the out-of-band high-frequency region, exhibiting obvious second-order noise shaping characteristics in the spectrum. Simultaneously, the active residual amplifier improves the residual decimation efficiency, and the passive capacitor network is used to store and accumulate the integration state, enhancing the noise shaping effect while reducing dependence on high-power active integrators. Through the coordinated design of residual amplifier gain and capacitor coefficient, the controllability of the noise shaping coefficient and system stability can be improved.

[0080] Therefore, this invention can improve in-band noise suppression and effective conversion accuracy while maintaining the advantages of low power consumption and high energy efficiency of SAR ADC, making it suitable for low power consumption and high precision analog-to-digital conversion applications.

[0081] The second-order noise-shaping successive approximation analog-to-digital converter provided in this application has the following technical effects: First, it balances residual utilization with low system power consumption, resolving the contradiction between performance and power consumption in traditional solutions: By employing an architecture that coordinates an active residual amplifier and a passive capacitor integrator network, the amplifier is only briefly activated during the residual decimation stage. Noise shaping during the remaining quantization and integration stages relies on passive capacitor charge sharing, eliminating the need for a continuously operating high-power active integrator and significantly reducing overall dynamic power consumption. Simultaneously, by amplifying the quantized residual superimposed with the first-stage integration state using an active amplifier, it overcomes the shortcomings of multi-stage charge sharing in fully passive switched-capacitor integrator structures, which leads to gradual residual attenuation and deterioration of shaping capabilities. This significantly improves the effective amplitude and residual utilization efficiency of the residual signal, ensuring full utilization of second-order noise shaping performance.

[0082] Secondly, the noise shaping coefficient offers strong controllability, significantly improving the circuit's PVT robustness: the noise shaping poles and zeros are jointly determined by the amplifier gain and the ratio of the residual decimation capacitor to the integrating capacitor. Precise matching of the shaping coefficient is achieved through static constraints on the capacitor ratio combined with the amplifier's fixed gain, overcoming the limitation of solely relying on amplifier gain to adjust the NTF. Compared to purely active shaping schemes, the capacitor ratio is less affected by process, voltage, and temperature drift, resulting in stronger NTF stability. Under low temperature, slow process angle, and low power supply voltage conditions, there will be no gain drift leading to shaping failure or signal-to-noise ratio degradation.

[0083] Third, the split capacitor structure optimizes the reliability of low-voltage switching and improves conversion linearity: the traditional VCM-based capacitor unit is split into two equivalent capacitors, which are connected separately. and GND, charge equivalent replacement capacitor direct connection Completely avoid CDAC lower plate transmission The problem of insufficient conduction margin in the transmission gate is addressed. Simultaneously, during the successive approximation process, the capacitors switch complementaryly, ensuring the comparator input common-mode level remains stably maintained at [value missing]. Nearby, reduce CDAC setup error, improve SAR conversion linearity and overall working stability under low voltage and low temperature conditions, and adapt to advanced low voltage processes.

[0084] Fourth, it boasts outstanding second-order noise shaping capabilities, effectively improving ADC conversion accuracy: A cascaded integrator-feedforward second-order noise shaping loop is constructed, with two zeros in the NTF (Network Tolerance) within the low-frequency band, significantly suppressing in-band quantization noise and pushing noise energy out of the high-frequency band. Furthermore, only a single active residual amplifier is needed to drive the two-stage integrator state update, reducing the number of active components compared to multi-amplifier high-order shaping schemes, simplifying circuit implementation complexity, and simultaneously reducing comparator input load and additional circuit noise.

[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the systems, devices and units described above can be referred to the corresponding process in the aforementioned second-order noise-shaping successive approximation analog-to-digital converter embodiment, and will not be repeated here.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0089] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A second-order noise-shaping successive approximation analog-to-digital converter, characterized in that, The second-order noise-shaping successive approximation analog-to-digital converter includes a split-capacitor digital-to-analog converter, a second-order noise-shaping loop filter, a comparator, and a SAR logic module. The second-order noise-shaping loop filter includes an active residual amplifier, two stages of residual decimation capacitors, and two stages of integrating capacitors. The two stages of integrating capacitors include a first integrating capacitor and a second integrating capacitor. The split-capacitor digital-to-analog converter is used to sample the input signal, perform successive approximation quantization, and generate quantization residuals. The two-stage integrating capacitor is used to store the integration state, update the integration state by sharing the passive charge with the corresponding residual extraction capacitor, and feed the integration state forward to the comparator to construct a second-order noise shaping loop. The integration state includes a first-stage integration state and a second-stage integration state. The input terminal of the active residual amplifier is connected to the first integrating capacitor, and the output terminal is connected to the two-stage residual extraction capacitor. It is used to amplify the composite signal in the residual extraction stage to obtain the amplified residual information. The composite signal includes the quantization residual output by the split capacitor digital-to-analog converter after the SAR logic module conversion is completed and the first-stage integration state of the previous cycle. The two-stage residual extraction capacitors are connected to the corresponding integrating capacitors through a noise shaping control switch to temporarily store the residual information. In the noise shaping phase, the residual information is provided to the two-stage integrating capacitors through passive charge sharing to update the integration state. The input terminal of the comparator is connected to the two-stage integration capacitor, and is used to compare the differential voltage after superimposing the quantization residual, the first-stage integration state and the second-stage integration state, and output the level decision result. The SAR logic module is connected to the output of the comparator and is used to receive the level decision result and control the split capacitor digital-to-analog converter to perform capacitor complementary switching based on the level decision result in order to complete successive approximation quantization. The complete conversion cycle includes the sampling stage, the SAR conversion stage, and the residual extraction stage in sequence. During the sampling phase, the sampling timing signal is valid, the split-capacitor digital-to-analog converter completes the sampling of the analog input signal, the two-stage integrating capacitor is reset to the common-mode reference state, and the active residual amplifier is turned off. During the SAR conversion phase, the noise shaping timing signal is valid, the residual decimation capacitor and the corresponding integration capacitor update the integration state through passive charge sharing, the comparator outputs decision pulses sequentially, and the SAR logic module controls the split capacitor digital-to-analog converter to complete bit-by-bit quantization. During the residual extraction stage, when the residual extraction timing signal is valid, the active residual amplifier is turned on, and the amplified residual information is synchronously stored in the residual extraction capacitor.

2. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The two-stage residual extraction capacitor includes a first residual extraction capacitor and a second residual extraction capacitor; The first residual extraction capacitor is connected to the first integrating capacitor through the first noise shaping control switch. It is used to temporarily store the residual information output by the active residual amplifier in the previous cycle. In the noise shaping phase of the current cycle, it performs charge sharing with the first integrating capacitor to form the first-stage integration state. The second residual extraction capacitor is connected to the second integrating capacitor through the second noise shaping control switch. It is used to temporarily store the residual information output by the active residual amplifier in the previous cycle. In the noise shaping phase of the current cycle, it performs charge sharing with the second integrating capacitor to update the second-stage integration state.

3. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 2, characterized in that, The first-level integral state of the current period includes the residual information of the current period and the first-level integral state of the previous period; the second-level integral state of the current period includes the residual information of the current period and the second-level integral state of the previous period.

4. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The first equivalent charge sharing coefficient corresponding to the first residual extraction capacitor and the first integration capacitor is determined based on the ratio of the value of the first residual extraction capacitor to the sum of the first capacitors, where the sum of the first capacitors is the sum of the value of the first residual extraction capacitor and the value of the first integration capacitor. The first-level integral state is determined based on the product of the first equivalent charge sharing coefficient, the passive gain, and the residual information.

5. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The second equivalent charge sharing coefficient corresponding to the second residual decimation capacitor and the second integral capacitor is determined based on the ratio of the value of the second residual decimation capacitor to the sum of the values ​​of the second capacitors, where the sum of the second capacitors is the sum of the values ​​of the second residual decimation capacitor and the second integral capacitor. The second-level integral state is determined based on the sum of the product of the second equivalent charge sharing coefficient, the passive gain, and the residual information, and the second-order historical residual. The second-order historical residual is determined based on the product of the difference between the preset value and the second equivalent charge sharing coefficient and the second-level integral state of the previous cycle.

6. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The sampling timing signal includes a sampling switch timing signal and a common-mode reset timing signal, wherein the common-mode reset timing signal ends earlier than the sampling switch timing signal.

7. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The split-capacitor digital-to-analog converter includes multiple equivalent common-mode access units. Each equivalent common-mode access unit includes a first capacitor and a second capacitor with equal values. The base plate of the first capacitor is connected to a reference voltage, and the base plate of the second capacitor is grounded. During the sampling phase, the first capacitor and the second capacitor work together to form an equivalent common-mode charge effect. During the SAR conversion phase, the first capacitor and the second capacitor at both ends of the differential switch perform complementary switching.

8. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 4, characterized in that, The product of the first equivalent charge sharing coefficient, the passive gain, and the amplification gain of the active residual amplifier is 1.

9. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 5, characterized in that, The product of the second equivalent charge sharing coefficient, the passive gain, and the amplification gain of the active residual amplifier is 1, so that the successive approximation analog-to-digital converter has a second-order noise shaping effect.

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