Encoding method, decoding method and apparatus

Abstract

This application provides an encoding method, decoding method, and apparatus to reduce the trap set in a base matrix, thereby reducing the occurrence of error planes and facilitating high-reliability communication. The method includes: a first communication device acquiring a bit sequence to be encoded; the first communication device performing LDPC encoding on the bit sequence to be encoded according to a first base matrix to obtain an encoded bit sequence; wherein the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrix includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of non-zero sub-matrices in each sub-matrix that are not the first matrix is ​​the same, and the first matrix is ​​a matrix where both row weight and column weight are 1; the first communication device outputs the encoded bit sequence.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and an apparatus. Background Technology

[0002] Low-density parity check (LDPC) codes are a type of linear block coding with sparse parity check matrices. They are characterized by flexible structure and low decoding complexity, and have been selected by the 3rd generation partnership project (3GPP) as the coding scheme for 5th generation (5G) data channels.

[0003] 5G LDPC codes exhibit poor performance in ultra-reliable low-latency communication (URLLC) applications, displaying a significant error floor. As the signal-to-noise ratio (SNR) increases, the rate at which the block error rate (BLER) decreases slows, making it unsuitable for high-reliability scenarios. Therefore, optimizing LDPC codes to reduce the error floor is a worthwhile consideration. Summary of the Invention

[0004] This application provides an encoding method, a decoding method, and an apparatus for reducing the trap set in the base matrix, thereby reducing the occurrence of error planes and facilitating high-reliability communication.

[0005] This application provides an encoding method, which can be executed by a first communication device. The first communication device can support LDPC encoding; therefore, the first communication device can also be referred to as an encoding device. This application does not limit the type of the first communication device. For example, the first communication device can be a first communication equipment, or the first communication device can be a component applicable to a first communication equipment. Exemplarily, the first communication equipment can be a terminal device or a network device. In this application, the component can include at least one of a processor, circuit, logic module, software module or software code, chip, or chip system. Possible forms of terminal devices and network devices will be described later, and will not be elaborated here. The method includes: a first communication device acquiring a bit sequence to be encoded; the first communication device performing LDPC encoding on the bit sequence to be encoded according to a first base matrix to obtain an encoded bit sequence; wherein the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrice includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of any non-zero sub-matrices in each sub-matrices in the multiple sub-matrices that are not the first matrix is ​​the same, the first matrix is ​​a matrix with both row weight and column weight of 1; the first communication device outputs the encoded bit sequence.

[0006] Specifically, the first region in the first base matrix comprises multiple submatrices, each submatrice containing multiple submatrices. Any two submatrices in the multiple submatrices have equal column weights, and the number of non-zero submatrices in each submatrice that are not part of the first matrix is ​​the same. The first matrix is ​​a matrix where both row and column weights are 1. This design helps reduce loops that repeatedly pass through the same positions in the first base matrix (a "loop" in a Turner graph refers to a structure that starts from a vertex, follows non-repeating edges, passes through non-repeating vertices, and finally returns to the starting point), thereby reducing the trap set in the base matrix. This reduces the occurrence of error layers in URLLC scenarios or similar scenarios, thus supporting highly reliable communication.

[0007] A second aspect of this application provides a decoding method, which can be executed by a second communication device. The second communication device can support LDPC decoding; therefore, it can also be called a decoding device. This application does not limit the type of the second communication device. For example, the second communication device can be a second communication equipment, or it can be a component applicable to a second communication equipment (the implementation of the component is similar to that described in the first aspect, and will not be repeated here). Exemplarily, the second communication equipment can be a terminal device or a network device. The method includes: the second communication device receiving information to be decoded; the second communication device performing LDPC decoding based on a first base matrix and the information to be decoded to obtain a decoded bit sequence; wherein the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrice includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of non-zero sub-matrices in each sub-matrice in the multiple sub-matrices that are not the first matrix is ​​the same, and the first matrix is ​​a matrix where both row weight and column weight are 1.

[0008] Specifically, the first base matrix includes a first region, which includes multiple sub-matrices. Each sub-matrix includes multiple sub-matrices. Any two sub-matrices in the multiple sub-matrices have equal column weights. The number of non-zero sub-matrices in each sub-matrix that are not the first matrix is ​​the same. The first matrix is ​​a matrix where both row and column weights are 1. This design helps reduce loops that repeatedly pass through the same positions in the first base matrix, thereby reducing the trap set in the base matrix. This reduces the occurrence of error layers in URLLC or similar scenarios, supports highly reliable communication, and reduces decoding complexity.

[0009] Based on the first or second aspect, in one possible implementation, the first region includes region A or a portion of region A of the first basis matrix.

[0010] Based on the first or second aspect, in one possible implementation, the first region includes the B region or a portion of the B region of the first basis matrix.

[0011] Based on the first or second aspect, in one possible implementation, the first region includes the D region or a portion of the D region of the first basis matrix.

[0012] Based on the first or second aspect, in one possible implementation, the first region includes region A and region B of the first basis matrix.

[0013] Based on the first or second aspect, in one possible implementation, the first region includes region A of the first basis matrix and a portion of region B.

[0014] Based on the first or second aspect, in one possible implementation, the first region includes regions A and B, which are portions of the first basis matrix.

[0015] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region A and a portion of region B in the first basis matrix.

[0016] Based on the first or second aspect, in one possible implementation, the first region includes region A and region D of the first basis matrix.

[0017] Based on the first or second aspect, in one possible implementation, the first region includes regions A and D, which are portions of the first basis matrix.

[0018] Based on the first or second aspect, in one possible implementation, the first region includes region A of the first basis matrix and a portion of region D.

[0019] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region A and a portion of region D in the first basis matrix.

[0020] Based on the first or second aspect, in one possible implementation, the first region includes the B region and the D region of the first basis matrix.

[0021] Based on the first or second aspect, in one possible implementation, the first region includes regions B and D, which are portions of the first basis matrix.

[0022] Based on the first or second aspect, in one possible implementation, the first region includes region B of the first basis matrix and a portion of region D.

[0023] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region B and a portion of region D in the first basis matrix.

[0024] Based on the first or second aspect, in one possible implementation, the first region includes region A, region B, and region D of the first basis matrix.

[0025] Based on the first or second aspect, in one possible implementation, the first region includes regions A, B, and D, which are portions of the first basis matrix.

[0026] Based on the first or second aspect, in one possible implementation, the first region includes region A of the first basis matrix, a portion of region B, and region D.

[0027] Based on the first or second aspect, in one possible implementation, the first region includes region A, region B, and a portion of region D of the first basis matrix.

[0028] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region A, a portion of region B, and region D in the first base matrix.

[0029] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region A, region B, and a portion of region D in the first basis moment.

[0030] Based on the first or second aspect, in one possible implementation, the first region includes region A of the first basis matrix, a portion of region B, and a portion of region D.

[0031] Based on the first or second aspect, in one possible implementation, the first region includes a portion of region A, a portion of region B, and a portion of region D in the first base matrix.

[0032] The above illustrates some possible implementations of the first region. Specifically, the first region may include part or all of at least one region from regions A, B, and / or D in the basis matrix. Implementing the first basis matrix occupies the core region of the basis matrix. This helps reduce the trap set of the first basis matrix.

[0033] Based on the first or second aspect, in one possible implementation, the first region includes the first row to the Xth row of the first basis matrix, where X is an integer greater than or equal to 2. This ensures the first basis matrix occupies the core region of the basis matrix, which helps reduce the trap set of the first basis matrix.

[0034] Based on the first or second aspect, in one possible implementation, X = 4, 5, 6, 7, or 8.

[0035] Based on the first or second aspect, in one possible implementation, each column of the multi-column submatrix corresponds to multiple columns of elements in the first region, different column submatrixes correspond to different multiple columns of elements in the first region, and the column weight of each column of elements in different multiple columns is equal.

[0036] In this implementation, the column weights of different submatrices in the multi-column submatrix are equal, which facilitates defining the characteristics between the multi-column submatrices. This reduces the trap set of the first basis matrix.

[0037] Based on the first or second aspect, in one possible implementation, the first matrix is

[0038] In this implementation, for the scheme of obtaining LDPC codes through double lifting, when the lifting value used for the first lifting is 2, the first matrix can be... In other words, the main technical solution of this application lies in specifying which matrix the 1 element in the second basis matrix is ​​expanded into during the first boost, thereby reducing the trap set of the first basis matrix.

[0039] Based on the first or second aspect, in one possible implementation, the first matrix is In this implementation, for the scheme of obtaining LDPC codes through secondary lifting, when the lifting value used for the first lifting is 3, the first matrix can be... In other words, the main technical solution of this application lies in specifying which matrix the 1 element in the second basis matrix is ​​expanded into during the first boost, thereby reducing the trap set of the first basis matrix.

[0040] Based on the first or second aspect, in one possible implementation, the dimension of the first matrix is ​​Z*Z, where Z is the boost value used in the first boost.

[0041] Based on the first or second aspect, in one possible implementation, the first matrix is ​​a diagonal matrix, an anti-diagonal matrix, a cyclic shift matrix of a diagonal matrix, or a cyclic shift matrix of an anti-diagonal matrix.

[0042] Based on the first or second aspect, in one possible implementation, the dimension of the submatrix in each column of the submatrix is ​​2*2, and the number of submatrixes that are the first matrix is ​​the same in each column of the submatrix across multiple columns. Regarding the scheme for obtaining LDPC codes through a second-order lifting, when the lifting value used for the first lifting is 2, the first matrix can be... Therefore, in a multi-column submatrix, the number of submatrices that are the first matrix in each column is the same. For example, the first matrix is... Then, the other matrices in each submatrix, excluding the first matrix, are: For example, the first matrix is Then, the other matrices in each submatrix, excluding the first matrix, are:

[0043] Based on the first or second aspect, in one possible implementation, any non-zero submatrix in each column of the multi-column submatrix is ​​not of the same type as the first matrix; and / or, the number of non-zero submatrixes of the same type in each column of the multi-column submatrix is ​​the same; and / or, the non-zero submatrixes of the same type in each column of the multi-column submatrix are in the same position in each column of the multi-column submatrix; and / or, the non-zero submatrixes of the same type in each column of the multi-column submatrix are not in the same position in each column of the multi-column submatrix.

[0044] In one possible implementation, specifically, each column of the multi-column submatrix includes two types of non-zero submatrixes, namely, an identity matrix and a non-identity matrix.

[0045] By specifying more characteristics of the multi-column submatrices, the number of cycles repeatedly passing through the same positions in the first basis matrix can be further reduced. This, in turn, helps to reduce the trap set of the first basis matrix, thereby reducing the occurrence of error layers and improving reliability.

[0046] Based on the first or second aspect, in one possible implementation, the first region includes a first sub-region B. Within a column of submatrices in the first sub-region B, there are three non-zero submatrices, two of which are identical. In the multiple columns of submatrices within the first sub-region B (excluding the aforementioned column of submatrices), each column contains two non-zero submatrices, which are also identical. This limitation on the sub-region B within the first region helps reduce the trap set of the first basis matrix, thereby reducing the occurrence of error flattening.

[0047] A third aspect of this application provides an encoding method, which can be executed by a first communication device. The first communication device can support LDPC encoding; therefore, the first communication device can also be referred to as an encoding device. This application does not limit the type of the first communication device. For example, the first communication device can be a first communication equipment, or the first communication device can be a component applicable to a first communication equipment. Exemplarily, the first communication equipment can be a terminal device or a network device. In this application, the component can include at least one of a processor, circuit, logic module, software module or software code, chip, or chip system. Possible forms of terminal devices and network devices will be described later, and will not be elaborated here. The method includes: a first communication device performing LDPC encoding based on a first base matrix and the bit sequence to be encoded to obtain an encoded bit sequence; wherein the first base matrix is ​​determined based on a second base matrix and the first shift value corresponding to each column in the second region of the second base matrix, the number of first shift values ​​that are not Y among the first shift values ​​corresponding to multiple columns of the same category in the second region of the second base matrix is ​​the same, Y is an integer greater than or equal to 0 and less than or equal to Z minus one, and Z is the boost value used for the first boost; the first communication device outputs the encoded bit sequence.

[0048] In the above technical solution, the first basis matrix is ​​determined based on the second basis matrix and the first translation value corresponding to each column in the second region of the second basis matrix. The number of first translation values ​​that are not Y among the first translation values ​​corresponding to multiple columns of the same category in the second region of the second basis matrix is ​​the same. This design helps reduce loops that repeatedly pass through the same position in the first basis matrix, thereby reducing the trap set in the first basis matrix. This reduces the occurrence of error layers in URLLC scenarios or similar scenarios, and is beneficial for supporting high-reliability communication.

[0049] This application provides a decoding method in a fourth aspect, which can be executed by a second communication device. The second communication device can support LDPC decoding; therefore, it can also be called a decoding device. This application does not limit the type of the second communication device. For example, the second communication device can be a second communication equipment, or it can be a component applicable to a second communication equipment (the implementation of the component is similar to that described in the first aspect, and will not be repeated here). For example, the second communication equipment can be a terminal device or a network device. The method includes: the second communication device receiving information to be decoded; the second communication device performing LDPC decoding based on a first base matrix and the information to be decoded to obtain a decoded bit sequence; wherein the first base matrix is ​​determined based on a second base matrix and the first shift value corresponding to each column in the second region of the second base matrix, the number of first shift values ​​of the same category in the second region of the second base matrix that are not equal to Y is the same, Y is an integer greater than or equal to 0 and less than or equal to Z minus one, and Z is the boost value used for the first boost.

[0050] In the above technical solution, the first basis matrix is ​​determined based on the second basis matrix and the first translation value corresponding to each column in the second region of the second basis matrix. In the second region of the second basis matrix, the number of first translation values ​​of the same category corresponding to multiple columns that are not Y is the same. This design helps reduce loops that repeatedly pass through the same position in the first basis matrix, thereby reducing the trap set in the first basis matrix. This reduces the occurrence of error layers in URLLC scenarios or similar scenarios, supports highly reliable communication, and reduces decoding complexity.

[0051] Based on the first aspect, in one possible implementation, the method further includes: a first communication device determining a first basis matrix based on a second basis matrix and a first correspondence, where the first correspondence is the correspondence between the first basis matrix and the second basis matrix; or, the first communication device generating a first basis matrix based on the second basis matrix and the first translation value corresponding to each column in the second region of the second basis matrix, where the number of first translation values ​​of the same category in the second region that are not Y is the same, and Y is an integer greater than or equal to 0 and less than or equal to Z minus one. This implementation provides two ways to obtain the first basis matrix. One is to determine the first basis matrix through a preset correspondence. The other is to generate the first basis matrix based on the first translation value corresponding to each column in the second region of the second basis matrix. This enriches the implementation of the scheme.

[0052] Based on the first to fourth aspects, in one possible implementation, the second region includes columns of one or more categories, with multiple columns of the same category having the same column weight. In this implementation, the second region is divided into columns of multiple categories, with different column weights for different categories.

[0053] Based on the first to fourth aspects, in one possible implementation, in the second region, the positions of element 0 and element 1 are the same in multiple columns of the same category.

[0054] Based on the first to fourth aspects, one possible implementation includes one or more categories of columns comprising: one or more categories of information columns and one or more categories of validation columns. In this implementation, the columns are first divided into information columns and validation columns, and then further subdivided into more categories based on column re-division within these two categories.

[0055] Based on the first to fourth aspects, in one possible implementation, in the second region, the first translation values ​​of multiple columns of the same category that are not of the value Y belong to the same category; and / or,

[0056] In the second region, the number of first shift values ​​of the same type is the same among multiple columns of the same category; and / or,

[0057] In the second region, among the first translation values ​​corresponding to multiple columns of the same category, the first translation values ​​of the same type are in the same position among the first translation values ​​corresponding to multiple columns; or...

[0058] In the second region, among the first translation values ​​corresponding to multiple columns of the same category, the positions of the first translation values ​​of the same type within the corresponding first translation values ​​of multiple columns are not the same; or...

[0059] In the second region, the first shift value corresponding to multiple columns of the same category includes two types of elements, with the two first shift values ​​being 0 and non-zero, respectively.

[0060] In this implementation, the characteristics of the first translation values ​​corresponding to multiple columns of the same category in the second region are defined. This helps to reduce the trap set of the first basis matrix.

[0061] Based on the first to fourth aspects, in one possible implementation, the second region includes a second sub-region B, where the two first translation values ​​corresponding to each 2-column of the second sub-region B are the same, and among the three first translation values ​​corresponding to the 3-column of the second sub-region B, two of the first translation values ​​are the same, and the other first translation value is different from the two first translation values.

[0062] Based on the first to fourth aspects, in one possible implementation, the first translation value corresponding to each of the two columns of the second sub-region B is 0.

[0063] Based on the first to fourth aspects, in one possible implementation, the first translation value corresponding to the three columns in the second sub-region B is y, y, 0, where y is an integer greater than 0 and not equal to 0.

[0064] Based on the first to fourth aspects, in one possible implementation, the second basis matrix is ​​BG2; the first translation values ​​corresponding to columns 1 to 6, 8, and 10 of BG2 are all 0; the first translation value corresponding to column 7 of BG2 is 0,0,7; the first translation value corresponding to column 9 of BG2 is 1,1,0; and the first translation value corresponding to column 11 of BG2 is 0,0,1, or 1,0,0, or 0,1,0; or...

[0065] The second basis matrix is ​​BG2; the first translation value corresponding to columns 1 to 6, 8, and 10 of BG2 is 0, the first translation value corresponding to column 7 is 0,0,1, the first translation value corresponding to column 9 is 0,0,0, and the first translation value corresponding to column 11 is 0,0,1, or 1,0,0, or 0,1,0; or...

[0066] The second basis matrix is ​​BG2; the first translation value corresponding to columns 1 to 6, 8 and 10 of BG2 is 0, the first translation value corresponding to column 7 of BG2 is 0, 0, 0, the first translation value corresponding to column 9 of BG2 is 1, 1, 0 or 0, 0, 1, the first translation value corresponding to column 11 of BG2 is 0, 0, 1 or 1, 0, 0 or 0, 1, 0.

[0067] A fifth aspect of this application provides a communication device comprising a plurality of functional modules. The plurality of functional modules interact to implement a method as described in the first aspect, the third aspect, or any possible implementation of the first aspect or the third aspect. Accordingly, the communication device can be the first communication device mentioned in the first aspect or the third aspect.

[0068] Optionally, multiple functional modules include a processing module and a transceiver module. For example, the processing module is used to acquire the bit sequence to be encoded; perform LDPC encoding on the bit sequence to be encoded according to a first base matrix to obtain the encoded bit sequence; wherein the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrix includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, and the number of non-zero sub-matrices in each sub-matrix that are not the first matrix is ​​the same, and the first matrix is ​​a matrix where both row weight and column weight are 1. The transceiver module is used to output the encoded bit sequence.

[0069] The technical effects achieved by the functional modules of the communication device in the fifth aspect of this application can be specifically referred to in the first aspect, the third aspect, or any one or more implementations of the first aspect or the third aspect, and will not be repeated here.

[0070] A sixth aspect of this application provides a communication device comprising a plurality of functional modules. The plurality of functional modules interact to implement a method as described in the second aspect, the fourth aspect, or any possible implementation of the second or fourth aspect. Accordingly, the communication device may be a second communication device as mentioned in the second or fourth aspect.

[0071] Optionally, multiple functional modules include a processing module and a transceiver module. For example, the transceiver module is used to receive the information to be decoded; the processing module is used to perform LDPC decoding based on the first base matrix and the information to be decoded to obtain the decoded bit sequence; wherein, the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrix includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of non-zero sub-matrices in each sub-matrix in the multiple sub-matrices that are not the first matrix is ​​the same, and the first matrix is ​​a matrix in which both row weight and column weight are 1.

[0072] The technical effects achieved by the functional modules of the communication device in the sixth aspect of this application can be specifically referred to in the second aspect, the fourth aspect, or any one or more implementations of the second aspect or the fourth aspect, and will not be repeated here.

[0073] A seventh aspect of this application provides a communication device comprising at least one processor, the at least one processor being configured to execute a computer program stored in a memory to implement the method described in any of the first, third, or third aspects; or, the at least one processor being configured to execute a computer program stored in a memory to implement the method described in any of the second, fourth, or fourth aspects.

[0074] Optionally, the communication device also includes a memory. At least one processor is coupled to the memory.

[0075] The eighth aspect of this application provides a chip or chip system including at least one processor for supporting a communication device in implementing the methods described in any of the first, second, third, and fourth aspects, any implementation of the first aspect, any implementation of the second aspect, any implementation of the third aspect, or any implementation of the fourth or second aspect. For example, the chip may be a baseband chip, a modem chip, a system-on-chip (SoC) chip (e.g., an SoC chip containing a modem core), a system-in-a-package (SIP) chip, or a communication module, etc.

[0076] In one possible design, the chip or chip system may further include a memory for storing program instructions and data necessary for the communication device. The chip system may be composed of chips or may include chips and other discrete devices. Optionally, the chip system may also include interface circuitry that provides program instructions and / or data to the at least one processor.

[0077] The ninth aspect of this application provides a communication device, which includes at least one logic circuit and an input / output interface. The logic circuit is used to implement the method described in any of the first, second, third, and fourth aspects, any of the implementations of the first aspect, the second aspect, the third aspect, or the fourth aspect.

[0078] The tenth aspect of this application provides a computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, when the computer program or instructions are executed by a processor, the method described in any of the first, second, third, and fourth aspects, any implementation of the first aspect, any implementation of the second aspect, any implementation of the third aspect, or any implementation of the fourth aspect is executed.

[0079] The eleventh aspect of this application provides a computer program product containing instructions that, when run on a computer, causes the method described in any implementation of the first aspect, the second aspect, the third aspect, the fourth aspect, any implementation of the first aspect, any implementation of the second aspect, any implementation of the third aspect, or any implementation of the fourth aspect to be executed.

[0080] The twelfth aspect of this application provides a communication system, including a first communication device and a second communication device. The first communication device is used to perform the method in the first aspect, the third aspect, any possible implementation of the first aspect, or any possible implementation of the third aspect. The second communication device is used to perform the method in the second aspect, the fourth aspect, any possible implementation of the second aspect, or any possible implementation of the fourth aspect.

[0081] The technical effects of any of the design methods in aspects five through twelfth can be found in the technical effects of the corresponding design methods in aspects one through four above, and will not be repeated here.

[0082] As described in the above technical solution, the first communication device acquires the bit sequence to be encoded. Then, the first communication device performs LDPC encoding on the bit sequence to be encoded according to the first base matrix to obtain the encoded bit sequence. The first communication device outputs the encoded bit sequence. The first base matrix includes a first region, which includes multiple sub-matrices. Each sub-matrix includes multiple sub-matrices, and the column weights of any two sub-matrices in the multiple sub-matrices are equal. The number of non-zero sub-matrices in each sub-matrix that are not part of the first matrix is ​​the same. The first matrix is ​​a matrix where both row and column weights are 1. This design of the multiple sub-matrices in the first region of the first base matrix helps reduce loops that repeatedly pass through the same positions in the first base matrix, thereby reducing the trap set in the base matrix. This reduces the occurrence of error layers in URLLC scenarios or similar scenarios, and is beneficial for supporting high-reliability communication. Attached Figure Description

[0083] Figure 1 The schematic diagram illustrates the matrix structure shared by the base matrices;

[0084] Figure 2 schematically shown Figure 1 The matrix structure shown illustrates the matrix regions used at different code rates.

[0085] Figures 3-1 to 3-4 The diagram illustrates the result of cyclically shifting a 4x4 identity matrix (to the right) by 1, 2, 3, and 0.

[0086] Figure 4 This diagram illustrates some simulation schematics of URLLC applications;

[0087] Figures 5-7 Schematic diagrams of the communication systems to which this application applies are shown respectively;

[0088] Figure 8 This is a schematic diagram of an embodiment of the encoding and decoding methods of this application;

[0089] Figures 9A to 9D These are some schematic diagrams of the first basis matrix in the embodiments of this application;

[0090] Figure 10A This is a schematic diagram of the second basis matrix in an embodiment of this application;

[0091] Figures 10B to 10G These are some schematic diagrams showing the first translation values ​​corresponding to each column in the second region of the second base matrix in the embodiments of this application;

[0092] Figures 11A-11B These are some schematic diagrams of the second sub-region B in the embodiments of this application;

[0093] Figure 12 This is a schematic diagram of embodiment BG2 of this application;

[0094] Figures 13A to 16C These are some schematic diagrams of the first basis matrix in the embodiments of this application;

[0095] Figure 17 This is a schematic diagram of the communication device according to an embodiment of this application;

[0096] Figure 18 This is another structural schematic diagram of the communication device according to an embodiment of this application;

[0097] Figure 19 This is a schematic diagram of the structure of a terminal device according to an embodiment of this application;

[0098] Figure 20 This is a schematic diagram of the structure of a network device according to an embodiment of this application. Detailed Implementation

[0099] This application provides an encoding method, a decoding method, and an apparatus for reducing the trap set in the base matrix, thereby reducing the occurrence of error planes and facilitating high-reliability communication.

[0100] Before introducing the technical solution of this application, the relevant technical terms involved in this application are explained. It is understood that these explanations are intended to make this application easier to understand and should not be regarded as a limitation on the scope of protection claimed in this application.

[0101] (1) Terminal equipment:

[0102] It can be a wireless terminal device capable of receiving network device scheduling and instruction information. The wireless terminal device can be a device that provides voice and / or data connectivity to the user, or a handheld device with wireless connectivity, or other processing device connected to a wireless modem.

[0103] Terminal equipment can be user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device. Terminal equipment can be a device that provides voice / data connectivity to users, such as a handheld device with wireless connectivity, vehicle-mounted equipment, or vehicle-mounted mobile device. Currently, some examples of terminal devices include: smartphones, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, Internet of Things (IoT) devices, wireless terminals in industrial control, wireless terminals in autonomous driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, and personal digital assistants (PDAs). This application does not limit the scope of terminal devices to include personal assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or terminal devices in future evolved public land mobile networks (PLMNs). In vehicle-to-everything (V2X) communication, a communication terminal mounted on a vehicle is a type of terminal device, and a roadside unit (RSU) can also be considered a terminal device. A drone carrying a communication terminal can also be considered a terminal device. Terminal devices can also be other devices with terminal functions; for example, a terminal device can also be a device that performs terminal functions in device-to-device (D2D) communication.

[0104] The wearable devices mentioned earlier, also known as wearable smart devices or smart wearable devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not just hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific application function and can be used in conjunction with other devices such as smartphones, such as various smart bracelets, smart helmets, and smart jewelry for vital sign monitoring.

[0105] The embodiments of this application do not limit the specific technology or device form used in the terminal device. It is understood that the terminal device may be referred to as a communication device. For example, a terminal device can be understood as a device with terminal functions. For example, the device used to implement the functions of the terminal device can be a terminal; it can also be a device capable of supporting the terminal device in implementing those functions, such as a chip system, hardware circuit, software module, or hardware circuit plus software module. This device can be installed in the terminal device or can be used in conjunction with the terminal device. In the embodiments of this application, the chip system can be composed of chips or may include chips and other discrete devices.

[0106] This chip can be a baseband chip, a modem chip, a system-on-a-chip (SoC) chip, a system-in-a-package (SIP) chip, or a communication module, etc. The chip may include a processor, memory, and a transceiver. The transceiver can be input / output circuitry or a communication interface. The processor can be an integrated processing unit, a microprocessor, or an integrated circuit on the chip.

[0107] (2) Network equipment:

[0108] Network equipment can be devices within a wireless network. For example, network equipment can be a RAN node (or device) that connects terminal devices to the wireless network, and can also be called a base station. Currently, some examples of RAN equipment include: base stations, evolved NodeBs (eNodeBs), gNBs (gNodeBs) in 5G communication systems, transmission reception points (TRPs), evolved Node Bs (eNBs), radio network controllers (RNCs), Node Bs (NBs), home base stations (e.g., home-evolved Node Bs, or home Node Bs (HNBs), base band units (BBUs) or wireless fidelity (Wi-Fi) access points (APs), and terminals performing base station functions in D2D communication. Additionally, in a network architecture, network equipment can include central unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment comprising both CU and DU nodes.

[0109] Optionally, RAN nodes can also be macro base stations, micro base stations, indoor stations, relay nodes, donor nodes, or radio controllers in cloud radio access network (CRAN) scenarios. RAN nodes can also be servers, wearable devices, vehicles, or in-vehicle equipment, or mobile devices mounted on vehicles. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU).

[0110] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with different RAN nodes each implementing a portion of the base station's functions. For example, RAN nodes can be CUs, DUs, CUs (control plane, CP), CUs (user plane, UP), or radio units (RUs). CUs and DUs can be configured separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio equipment or radio units, such as remote radio units (RRUs), active antenna units (AAUs), radioheads (RHs), or remote radio heads (RRHs).

[0111] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open access network (open RAN, O-RAN, or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0112] Communication between access network devices and terminal devices follows a specific protocol layer structure. This protocol layer may include a control plane protocol layer and a user plane protocol layer. The control plane protocol layer may include at least one of the following: radio resource control (RRC) layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, media access control (MAC) layer, or physical (PHY) layer, etc. The user plane protocol layer may include at least one of the following: service data adaptation protocol (SDAP) layer, PDCP layer, RLC layer, MAC layer, or physical layer, etc.

[0113] The correspondence between network elements and their achievable protocol layer functions in the ORAN system can be found in Table 1 below.

[0114] Table 1

[0115] ORAN network elements 3GPP protocol layer functions O-CU-CP RRC+PDCP-Control Plane (PDCP-C) O-CU-UP SDAP+PDCP - User Plane (PDCP-U) O-DU RLC+MAC+PHY-high O-RU PHY-low

[0116] Network devices can be other devices that provide wireless communication functions for terminal devices. The embodiments of this application do not limit the specific technology or form of the network device. For ease of description, the embodiments of this application are not limited.

[0117] Network equipment may also include core network equipment, such as the Mobility Management Entity (MME), Home Subscriber Server (HSS), Serving Gateway (S-GW), Policy and Charging Rules Function (PCRF), and Public Data Network Gateway (PDN gateway or P-GW) in 4th generation (4G) networks; and access and mobility management function (AMF), user plane function (UPF), or session management function (SMF) in 5G networks. Furthermore, this core network equipment may also include other core network equipment in 5G networks and future networks.

[0118] In this application embodiment, the device for implementing the function of the network device can be the network device itself, or it can be any device capable of supporting the network device in implementing that function, such as a chip system, hardware circuit, software module, or hardware circuit plus software module. This device can be installed within the network device or can be used in conjunction with a base station. In the technical solutions provided in this application embodiment, the network device is used as an example to illustrate the technical solutions provided in this application embodiment. In this application embodiment, the chip system can be composed of chips, or it can include chips and other discrete components.

[0119] (3) Configuration and Pre-configuration:

[0120] This application uses both configuration and pre-configuration. Configuration refers to the network device / server sending configuration information or parameter values ​​to the terminal via messages or signaling, so that the terminal device can determine communication parameters or resources for transmission based on these values ​​or information. Pre-configuration is similar to configuration; it can be parameter information or values ​​pre-negotiated between the network device / server and the terminal device, parameter information or values ​​specified by standard protocols for use by the base station / network device or terminal device, or parameter information or values ​​pre-stored in the base station / server or terminal device. This application does not limit this.

[0121] Furthermore, these values ​​and parameters can be changed or updated.

[0122] (4) Low-density parity check (LDPC) code:

[0123] LDPC codes are a channel coding scheme close to Shannon lines, characterized by high performance and low complexity. They have been adopted by 3GPP as the 5G data channel coding scheme. Currently, the main decoding algorithms for LDPC codes are Min-Sum (MS) and Belief Propagation (BP) decoding algorithms. In terms of decoding performance, BP decoding is better, but it requires a larger information storage capacity (m...). c→v The computational method is complex and not conducive to hardware implementation. Therefore, the Offset-MS and Normalized-MS decoding algorithms are currently used in practical communication systems.

[0124] In one possible implementation, both the LDPC encoding and decoding processes are performed based on a parity-check matrix, which is generally generated from the LDPC base matrix. This base matrix can also be called a base graph (BG). The value of a single element (or single position) in the LDPC base matrix can be 0 or 1. A value of 0 represents an empty element, and a value of 1 represents an edge in the base matrix or an association between the corresponding parity check and the corresponding variable. In this application, the column weight can refer to the number of non-zero elements in that column. It should be noted that both the LDPC encoding and decoding processes can also be performed based on a generator matrix; this application does not specifically limit the application's scope.

[0125] The LDPC base matrix includes an information column and a parity column. The parity column includes a core parity column and extended parity columns. The information column corresponds to the information bits in the encoded bit sequence, which can also be called information bits or system bits. The parity column corresponds to the parity bits in the encoded bit sequence, which can also be called parity bits. The core parity column consists of the parity columns in the base matrix whose column weight is greater than 1. The extended parity columns are the other parity columns in the base matrix besides the core parity column.

[0126] Figure 1 The matrix structure of the basis matrix of LDPC is illustrated schematically. For example... Figure 1 As shown, the basis matrix of LDPC includes regions A, B, C, D, and E. Regions A to E can be referred to as submatrices A to E, respectively. Figure 1 As shown, the base matrix is ​​an X-row, Y-column matrix, where X and Y are positive integers. Submatrix A (or region A) corresponds to columns 1 through y1 of the base matrix, and also to rows 1 through x1 of matrix 0, where y1 is a positive integer greater than 1 and less than Y, and x1 is a positive integer greater than 1 and less than X. Submatrix B corresponds to columns y1+1 through y2 of matrix 0, and also to rows 1 through x1 of matrix 0, where y2 is a positive integer greater than y1 and less than Y. Submatrix C corresponds to columns y2+1 through Y of matrix 0, and also to rows 1 through x1 of matrix 0. Submatrix D corresponds to columns 1 through y2 of matrix 0, and also to rows x1+1 through X of matrix 0. Submatrix E corresponds to columns y2+1 through Y of matrix 0, and also to rows x1+1 through X of matrix 0.

[0127] For example, x1 = 4, y1 = 10 or y1 = 22, y2 - y1 = 4.

[0128] Figure 1 In the example shown, the column numbers in the matrix all start from 1. In fact, the column numbers in the matrix can also start from 0. This application may choose one example, without limitation.

[0129] The columns corresponding to submatrix A (i.e., columns 1 to y1) can be information columns, the columns corresponding to submatrix B and submatrix C (i.e., columns y1+1 to Y) can be verification columns, the columns corresponding to submatrix B (i.e., columns y1+1 to y2) can be core verification columns, and the columns corresponding to submatrix C (i.e., columns y2+1 to Y) can be extended verification columns.

[0130] Optionally, the column weight of any column in submatrix B is greater than 1, and the column weight of any column in submatrix C is 0. Alternatively, submatrix B is a non-lower triangular matrix, which means that the values ​​above the diagonal of the matrix are not all 0.

[0131] Figure 2 This schematically illustrates another expression of the basis matrix structure of LDPC. For example... Figure 2 As shown, the base matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region is the highest-rate region within the base matrix, and this high-rate region can include... Figure 1 Submatrices A and B are given. A region of all zeros can be a zero matrix, where every element of the zero matrix is ​​0. A region of all zeros can be... Figure 1 The submatrix C shown. The incremental redundancy region can be a low-bitrate matrix, and the incremental redundancy region can be... Figure 1 The submatrix D shown is a Laptian-like region that can be an identity matrix, which can be... Figure 1 The submatrix E is shown.

[0132] 3GPP defines two types of basis matrices in the 5G data channel coding scheme, called BG1 and BG2 respectively. Both BG1 and BG2 have... Figure 1 or Figure 2 The matrix structure shown.

[0133] Understandable, Figure 1 or Figure 2 The base matrix shown is designed according to the lowest bit rate. Figure 2 In the diagram, multiple pairs of horizontal and vertical dashed black lines diagonally downwards along the Laputa-like region represent different bitrate truncation matrix regions. When higher bitrates are required, truncation can be performed. Figure 1 or Figure 2 A portion of the base matrix shown is used to generate the parity matrix, for example, based on... Figure 1 shown Figure 2 The high-bitrate regions (i.e., submatrix A and submatrix B) shown are used to generate the parity-check matrix. When the bitrate is low, the matrix regions used to generate the parity-check matrix can be... Figure 2 The matrix region after expanding the high bit rate region shown can include not only the high bit rate region, but also at least part of the incremental redundancy region, the all-zero region, or the Laputa-like region.

[0134] (5) Quasi-cyclic low-density parity check (QC-LDPC):

[0135] QC-LDPC code is a type of LDPC code that has a QC structure. QC-LDPC code avoids bad structures such as short loops and improves code distance by setting the translation amount of each block.

[0136] The QC-LDPC code used in practice is represented by a base matrix BG, where elements are either 0 or 1. The 1s in the base matrix BG are expanded into a cyclic shift matrix, and the 0s are expanded into a zero matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained. The BG graphical model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the parity check equation, and F represents the edge relationships. The expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship, corresponding to the number of columns of the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0137] BG can also be written in matrix form as H. BG Based on the basis matrix H BG And the lifting value Zc (lifting size) can be used to transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. Zc can also be called the expansion factor, boost factor, expansion value, expansion coefficient, boost size, etc.

[0138] The lifting process involves transforming matrix H BG The elements in the matrix are promoted to a Zc×Zc square matrix, where 0 is promoted to a Zc×Zc matrix of 0s, and 1 is promoted to an identity matrix (circularly shifted P to the right). i,j The matrix, where P i,j This represents the shifting value (SV) corresponding to the i-th row and j-th column. Taking a 4x4 identity matrix as an example, the results of cyclically shifting (or shifting by values) 1, 2, 3, and 0 (to the right) of this identity matrix are as follows: Figures 3-1 to 3-4 As shown.

[0139] The second-stage LDPC code scheme is introduced below.

[0140] For example, taking the first boost value of 2 as an example, the 1 in the basis matrix BG is expanded to... The zeros are expanded into a 2x2 zero matrix, resulting in matrix BG0. In the second boosting, the 1s in matrix BG0 are expanded into cyclic shift matrices, and the zeros are expanded into a zero matrix of the corresponding size, thus obtaining the check matrix.

[0141] For example, taking the first boost value as 3, we first expand the 1s in the basis matrix BG to... The zeros are expanded into a 3x3 zero matrix, resulting in matrix BG0. In the second lifting process, the 1s in matrix BG0 are expanded into cyclic shift matrices, and the zeros are expanded into a zero matrix of the corresponding size, thus obtaining the check matrix. In this application, the lifting value used in the first lifting is referred to as the first lifting value, and the lifting value used in the second lifting is referred to as the second lifting value.

[0142] 5G LDPC codes exhibit poor performance in URLLC services, showing a significant error floor. URLLC and similar services require high reliability, typically necessitating lower code rates, such as less than half the bit rate. For example, ... Figure 4 As shown, the rate of BLER decreases with increasing signal-to-noise ratio (SNR), making it unsuitable for high-reliability scenarios. Furthermore, optimization is challenging because code length and code rate are highly flexible in wireless transmission, making independent optimization impossible for each scenario. The main problem lies in the presence of numerous trap sets (TS) in parts of the basis matrix, leading to significant error layers. Therefore, optimizing LDPC codes to reduce trap sets and thus error layers is a worthwhile consideration. This application provides a corresponding technical solution to reduce trap sets in the basis matrix, thereby reducing the occurrence of error layers.

[0143] The solution provided in this application will be introduced below in conjunction with application scenarios.

[0144] The method provided in this application can be used in various communication systems. For example, the communication system can be a wireless communication system, a universal mobile telecommunications system (UMTS) system, a long term evolution (LTE) system, a 5th generation (5G) communication system, a wireless fidelity (WiFi) system, a 3rd generation partnership project (3GPP) related communication system, a communication system evolving after 5G, or a system integrating multiple systems, etc. This application does not limit the communication system. 5G can also be referred to as NR, and communication systems evolving after 5G can be called future communication systems. This application can also be applied to three major application scenarios: device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, long term evolution (LTE) systems, and next-generation 5G mobile communication systems. These three application scenarios include enhanced mobile broadband (eMBB), ultra-reliable low-latency communication (URLLC), and enhanced machine-type communication (eMTC).

[0145] Figure 5 A schematic diagram of the communication system is shown. It is understood that... Figure 5 This is merely an illustrative diagram and does not constitute a limitation on the applicable scenarios of the technical solutions provided in this application. Figure 5 As shown, the communication system 1000 may include a radio access network (RAN) 100. Optionally, the communication system 1000 may also include a core network 200 and an Internet 300. The RAN 100 includes at least one RAN node (e.g., ...). Figure 5110a and 110b, collectively referred to as 110, may also include at least one terminal device (such as...). Figure 5 RAN100, denoted as RAN100, comprises RAN nodes 120a-120j, collectively referred to as RAN120. RAN100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 5 (Not shown in the image). Terminal device 120 is connected to RAN node 110 wirelessly, and RAN node 110 is connected to core network 200 wirelessly or via wired connection. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be independent physical devices, or they can be the same physical device that integrates the logical functions of core network equipment and RAN node.

[0146] As mentioned earlier, RAN nodes and core network equipment can be collectively referred to as network equipment. Figure 5 In the communication system shown, terminal devices can communicate with each other, network devices can communicate with each other, and network devices can communicate with each other via wired or wireless means, respectively.

[0147] like Figure 6 As shown, taking a network device as a base station as an example, a base station can perform communication-related services with one or more terminal devices, and different terminal devices can also perform communication-related services.

[0148] Figure 7 This is another schematic diagram of a communication system. Information generated by the source is transmitted through the channel after source coding, channel coding, and modulation by the transmitting device. The receiving device demodulates the received signal to obtain a sequence to be decoded, such as a Log Likelihood Ratio (LLR) sequence. Then, this sequence undergoes channel decoding and source recovery to obtain the decoded information, which is then sent to the destination. The scheme provided in this application can be applied to both the channel coding and channel decoding parts.

[0149] The method provided in this application will now be described using the first and second communication devices in a communication system as examples.

[0150] As described above, the first communication device can support LDPC encoding. The first communication device can be a first communication equipment, or it can be a component within a first communication equipment. Similarly, as described above, the second communication device can support LDPC decoding. The second communication device can be a second communication equipment, or it can be a component within a second communication equipment. The first communication equipment can be a transmitting device, and the second communication equipment can be a receiving device. The implementation of the component is similar to the first aspect described above, and will not be repeated here.

[0151] This application does not limit the types of the first and second communication devices. For example, the first and second communication devices can be different terminal devices in a communication system, or they can be different network devices in a communication system, or they can be a terminal device and a network device in a communication system, or they can be a network device and a terminal device in a communication system, respectively. Optionally, the first and second communication devices transmit data wirelessly.

[0152] The technical solution of this application is described below with reference to specific embodiments.

[0153] Figure 8 This is a schematic diagram illustrating one embodiment of the encoding and decoding methods described in this application. Please refer to [link / reference]. Figure 8 The method includes the following steps.

[0154] 801. The first communication device acquires the bit sequence to be encoded.

[0155] The bit sequence to be encoded can be a binary sequence obtained by the first communication device converting the data to be transmitted. The bit sequence to be encoded can be a non-all-zero sequence. The bit sequence to be encoded can contain an information bit sequence, which can be a payload information bit sequence or a bit sequence containing payload information bits and cyclic redundancy check (CRC) bits.

[0156] 802. The first communication device performs LDPC encoding on the bit sequence to be encoded according to the first base matrix to obtain the encoded bit sequence.

[0157] The first base matrix comprises a first region. The first region comprises multiple submatrices, each submatrice containing multiple submatrices, with any two submatrices having equal column weights. The number of non-zero submatrices in each submatrice within the multiple submatrices is the same. The first matrix is ​​a matrix where both row and column weights are 1. It should be noted that the column weight of each submatrice within these multiple submatrices refers to its column weight within the first region, not its column weight within the first base matrix.

[0158] In this system, the dimension of each submatrix is ​​equal to Z*Z, where Z is the first lift value used in the initial lift. Each submatrix in this system corresponds to multiple columns of elements in the first region, and different submatrixes correspond to different columns of elements in the first region, with each column having the same weight.

[0159] For example, such as Figure 9AAs shown, Z is 2, and the multiple submatrices include submatrices from the 1st to the 3rd column. In each of the 1st to 3rd submatrices, each submatrix corresponds to two columns of elements in the first region, with different submatrices corresponding to different two columns of elements. For example... Figure 9A As shown, the first column of the submatrix corresponds to the first and second columns of the first region. The first column element is 1,0,1,0,0,1,0,0. The second column element is 0,1,0,1,1,0,0,0. It can be seen that the column weight of the first and second columns is equal, both being 3. The second column of the submatrix corresponds to the third and fourth columns of the first region. The third column element is 0,1,1,0,1,0,0,0. The fourth column element is 1,0,0,1,0,1,0,0. It can be seen that the column weight of the third and fourth columns is also 3. The third column of the submatrix corresponds to the fifth and sixth columns of the first region. The fifth column element is 1,0,0,1,1,0,0,0, and the sixth column element is 0,1,1,0,0,1,0,0, both being 3. As can be seen from the above, the column weights of the corresponding multiple columns in each submatrix are equal, and the column weights of the multiple columns in the first region corresponding to different submatrixes are equal.

[0160] In this implementation, the column weights of different submatrices within the multi-column submatrix are equal. Characteristics between the multi-column submatrices are defined, thereby reducing the trap set of the first basis matrix.

[0161] Understandably, the first matrix is ​​one of the matrix types of Z where the row weight and column weight are all 1.

[0162] In one possible implementation, the first lift value Z is 2, and the first matrix is... That is, two types of matrices with both row and column weights of 1 include... The first matrix is ​​one of these two types of matrices where both row and column weights are 1.

[0163] For example, such as Figure 9A As shown, the multi-column submatrix includes submatrices from the 1st to the 3rd column, with the first matrix being... In each of the submatrices from the 1st to the 3rd column, the number of submatrices in which any non-zero submatrix is ​​not the first matrix is ​​1.

[0164] For example, such as Figure 9A As shown, the multi-column submatrix includes submatrices 4 through 6. The first matrix is... In each of the submatrices from the 4th to the 6th column, the number of submatrices in which any non-zero submatrix is ​​not the first matrix is ​​2.

[0165] From the above Figure 9AIt can be seen that the first region may include a first group of multi-column matrices and a second group of multi-column submatrices. The first group of multi-column submatrices includes submatrices from column 1 to column 3. The second group of multi-column submatrices includes submatrices from column 4 to column 6. Specifically, the column weights of submatrices from column 1 to column 3 are equal, and no non-zero submatrix in any of the submatrices from column 1 to column 3 is equal to 0. The number of submatrices is equal. The column weights of submatrices from the 4th to the 6th column are equal, and no non-zero submatrix in any column from the 4th to the 6th column is zero. The number of submatrices is equal.

[0166] It should be noted that the above Figure 9A The example shown illustrates the technical solution of this application by using a first region comprising two sets of multi-column sub-matrices. In practical applications, the first region in this application comprises at least one set of multi-column sub-matrices, and the specific details are not limited.

[0167] It should be noted that the above Figure 9A The example shown illustrates this by assuming that the column weights of each submatrix in the first group of multi-column submatrices are equal to those in the second group of multi-column submatrices. In practical applications, the column weights of each submatrix in different groups of multi-column submatrices within the first region may not be equal; no specific limitation is imposed.

[0168] In another possible implementation, the first lift value is 3, and the first matrix is In other words, the six types of matrices with both row and column weights of 1 include: The first matrix is ​​one of the six types of matrices where both row and column weights are 1.

[0169] For example, such as Figure 9B As shown, the multi-column submatrix includes submatrices from the 1st to the 3rd column, with the first matrix being... In each of the submatrices from the 1st to the 3rd column, the number of submatrices in which any non-zero submatrix is ​​not the first matrix is ​​1.

[0170] For example, such as Figure 9B As shown, the first region of the multi-column submatrix includes the 4th to 6th columns of the submatrix, and the first matrix is... In each of the submatrices from the 4th to the 6th columns, the number of submatrices in which any non-zero submatrix is ​​not the first matrix is ​​2.

[0171] From the above Figure 9BIt can be seen that the first region may include a first group of multi-column submatrices and a second group of multi-column submatrices. The first group of multi-column submatrices includes submatrices from column 1 to column 3. The second group of multi-column submatrices includes submatrices from column 4 to column 6. Specifically, the column weights of submatrices from column 1 to column 3 are equal, and no non-zero submatrix in any of the submatrices from column 1 to column 3 is equal to 0. The number of submatrices is equal. The column weights of submatrices from the 4th to the 6th columns are equal, and no non-zero submatrix in any of the submatrices from the 4th to the 6th columns is zero. The number of submatrices is equal.

[0172] It should be noted that the above Figure 9B The example shown illustrates the technical solution of this application by using a first region comprising two sets of multi-column sub-matrices. In practical applications, the first region in this application comprises at least one set of multi-column sub-matrices, and the specific details are not limited.

[0173] It should be noted that the above Figure 9B The example shown illustrates this by assuming that the column weights of each submatrix in the first group of multi-column submatrices are equal to those in the second group of multi-column submatrices. In practical applications, the column weights of each submatrix in different groups of multi-column submatrices within the first region may not be equal; no specific limitation is imposed.

[0174] In this implementation, for the scheme of obtaining LDPC codes through double lifting, when the lifting value used for the first lifting is 2, the first matrix can be... When the first boost uses a boost value of 3, the first matrix can be... In other words, the technical solution of this application specifies which matrix the 1-element in the second base matrix is ​​expanded to during the first boost. This design helps reduce special types of loops, such as loops that repeatedly pass through the same position in the first base matrix. This, in turn, helps reduce the trap set of the first base matrix. Consequently, in URLLC scenarios or similar scenarios, it can reduce the occurrence of error planes, which is beneficial for supporting high-reliability communication.

[0175] Optionally, the submatrixes in each column of this multi-column submatrix have a dimension of 2*2, and the number of submatrixes that are the first matrix is ​​the same in each column of this multi-column submatrix. For example, such as Figure 9A As shown, the first region includes sub-matrices from the 1st to the 3rd column, and the first matrix is... The number of submatrices in each of the submatrices from the first to the third column where any non-zero submatrix is ​​the first matrix is ​​2.

[0176] Optionally, in a multi-column submatrix, any non-zero submatrix in each column of the submatrix is ​​not a first matrix and the matrix types are the same.

[0177] For example, such as Figure 9B As shown, the multi-column submatrix includes submatrices from the 1st to the 3rd column. The first matrix is... In the first to third submatrices, each non-zero submatrix that is not a subset of the first matrix has a type of 1, i.e., it is a submatrix.

[0178] For example, such as Figure 9B As shown, the multi-column submatrix includes submatrices from the 4th to the 6th column. The first matrix is... In the submatrices from the 4th to the 6th columns, each non-zero submatrix that is not a subset of the first matrix has two possible values, which means it is a submatrix. submatrix

[0179] Optionally, in a multi-column submatrix, each column of the submatrix contains the same number of non-zero submatrices of the same type.

[0180] For example, such as Figure 9B As shown, the multi-column submatrix includes submatrices from column 1 to column 3. Within each of the submatrices from column 1 to column 3, the submatrix is... The quantity is 1, and the submatrix is The number is 2, and the submatrix is The quantity is 1.

[0181] For example, a multi-column submatrix includes submatrices from the 4th to the 6th column. Within each of these submatrices, the submatrix is... The quantity is 1, and the submatrix is The quantity is 1, and the submatrix is The quantity is 1, and the submatrix is The quantity is 1.

[0182] Optionally, in a multi-column submatrix, the non-zero submatrixes of the same type in each column of the submatrix are in the same position in each column of the submatrix.

[0183] For example, such as Figure 9C As shown, the multi-column submatrix includes submatrices from column 1 to column 3. Within each of the submatrices from column 1 to column 3, the submatrix... The positions are the same in each column of the submatrix, the submatrix They occupy the same position in each submatrix. For example, such as... Figure 9D As shown, the multi-column submatrix includes submatrices from column 1 to column 3. Within each of the submatrices from column 1 to column 3, the submatrix... The positions are the same in each column of the submatrix, the submatrix They are in the same position in each submatrix.

[0184] Optionally, in a multi-column submatrix, the non-zero submatrix of the same kind in each column of the submatrix may be in different positions within each column of the submatrix.

[0185] For example, such as Figure 9A As shown, the multi-column submatrix includes submatrices from column 1 to column 3. Within each of the submatrices from column 1 to column 3, the submatrix... The position in each column of the submatrix is ​​different, the submatrix The position is different in each submatrix.

[0186] Optionally, each column of a multi-column submatrix may include two types of non-zero submatrices, namely, an identity matrix and a non-identity matrix. For example, such as... Figure 9D As shown, the multi-column submatrix includes submatrices from column 1 to column 3. Each submatrix includes an identity matrix. Non-identity matrix That is, each column of submatrix includes only two types of non-zero submatrixes.

[0187] In this implementation, by specifying more features of the multiple submatrices, the number of cycles repeatedly passing through the same positions in the first basis matrix can be further reduced. This, in turn, helps to reduce the trap set of the first basis matrix, thereby reducing the occurrence of error layers and improving reliability.

[0188] Optionally, the first region includes a first sub-region B. In one column of submatrices within the first sub-region B, there are three non-zero submatrices, two of which are identical. In the multiple columns of submatrices within the first sub-region B (excluding the aforementioned column), each column contains two non-zero submatrices, which are also identical. For example, the first sub-region B could be... Figure 1 The first subregion B is shown. In the first subregion B, this one column of submatrix corresponds to multiple columns of elements in the first region, and the column weight of each element in these multiple columns is 3. In the first subregion B, excluding the aforementioned one column of submatrix, each column of submatrix corresponds to multiple columns of elements in the first region, and the column weight of each element in these multiple columns is 2.

[0189] Optionally, the first basis matrix may include the above. Figure 1 The area shown is part or all of the base matrix.

[0190] Optionally, the first region comprises the first row to the Xth row of the first base matrix. X is an integer greater than or equal to 2. For example, the first region can occupy most of the first base matrix. For example, X = 4, 5, 6, 7, or 8.

[0191] Optionally, the first region includes region A of the first basis matrix or region A that includes a portion of the first basis matrix; or,

[0192] The first region includes a B region comprising the first basis matrix, or a B region comprising a portion of the first basis matrix; or,

[0193] The first region includes the D region of the first basis matrix or includes a portion of the D region of the first basis matrix; or...

[0194] The first region includes regions A and B of the first basis matrix; or,

[0195] The first region includes region A of the first basis matrix and part of region B; or,

[0196] The first region includes portions of regions A and B in the first basis matrix; or,

[0197] The first region includes a portion of region A and a portion of region B in the first basis matrix; or,

[0198] The first region includes regions A and D of the first basis matrix; or,

[0199] The first region includes portions of regions A and D in the first basis matrix; or,

[0200] The first region includes region A of the first basis matrix and part of region D; or,

[0201] The first region includes a portion of region A and a portion of region D in the first basis matrix; or,

[0202] The first region includes regions B and D of the first basis matrix; or,

[0203] The first region includes a portion of region B and region D of the first basis matrix; or,

[0204] The first region includes region B of the first basis matrix and part of region D; or,

[0205] The first region includes a portion of region B and a portion of region D in the first basis matrix; or,

[0206] The first region includes regions A, B, and D of the first basis matrix; or,

[0207] The first region includes portions of regions A, B, and D in the first basis matrix; or,

[0208] The first region includes region A of the first basis matrix, part of region B, and region D; or,

[0209] The first region includes regions A and B of the first basis matrix and part of region D; or,

[0210] The first region includes a portion of region A, a portion of region B, and region D in the first basis matrix; or,

[0211] The first region includes a portion of region A, region B, and a portion of region D in the first basis matrix; or,

[0212] The first region includes region A of the first basis matrix, part of region B, and part of region D; or,

[0213] The first region includes a portion of region A, a portion of region B, and a portion of region D in the first basis matrix.

[0214] Optionally, the first basis matrix is ​​determined based on the second basis matrix. Alternatively, for practical implementation, the first basis matrix may be stored in the first communication device.

[0215] The following describes two possible implementations of the first communication device determining the first basis matrix based on the second basis matrix.

[0216] Implementation method 1: The first communication device generates the first basis matrix based on the first translation value corresponding to each column in the second region of the second basis matrix.

[0217] The second region comprises columns of one or more categories, with multiple columns of the same category having the same column weight. Specifically, the first communication device increases the elements in the second region according to the increase value used in the first increase to obtain the first region in the aforementioned first base matrix.

[0218] Optionally, in the second region, elements 0 and 1 in multiple columns of the same category are in the same position. For example, ... Figure 10AAs shown, the second region comprises 12 columns. Columns 1-3 belong to one category, columns 4-6 to another, columns 7-9 to yet another, and columns 10-12 to yet yet another. In columns 1-3, the first element of each column is 0, and the second through fourth elements are all 1. In columns 4-6, the second element of each column is 0, and the first, third, and fourth elements are all 1. In columns 7-9, the third element of each column is 0, and the first, second, and fourth elements are all 1. In columns 10-12, the fourth element of each column is 0, and the first through third elements are all 1. In other words, the first basis matrix is ​​represented by a Tanner graph. In the second region, the variable nodes corresponding to multiple columns of the same category have the same connection relationship with the check nodes in the Tanner graph. That is, the column categories can be divided according to the column connection relationships. Columns with the same join relationship must have the same column weight, but columns with the same weight do not necessarily have the same join relationship.

[0219] Optionally, the columns of one or more categories include: one or more information columns of one or more categories, and one or more validation columns of one or more categories. In this implementation, the columns are first divided into information columns and validation columns, and then further subdivided into more categories based on column refactoring within these two categories.

[0220] Optionally, the second region includes, for example: Figure 1 The matrix shown includes some or all of its regions. For example, the second region includes, for instance, a portion of the matrix shown. Figure 1 Region A in the matrix shown. For example, the second region includes, for instance, region A... Figure 1 Region B in the matrix shown. For example, the second region includes, for instance, region B... Figure 1 The matrix shown includes a portion of region A. For example, the second region includes, for instance, a portion of region A. Figure 1 The matrix shown includes a portion of region B. For example, the second region includes, for instance, a portion of region B. Figure 1 Regions A and B are shown.

[0221] In the second region, the number of first shift values ​​(not equal to Y) for columns of the same category is the same, where Y is an integer greater than or equal to 0 and less than or equal to Z-1. Z is the boost value used for the first boost. The first shift value for each column refers to the first shift value corresponding to the element 1 in that column. The first shift value corresponding to the element 0 in the second region is defaulted to 0, and subsequent shift values ​​corresponding to element 0 are not represented. For example, the second region includes columns 1 to 9, where columns 1, 3, and 8 belong to one category; columns 2, 7, and 9 belong to another category; and columns 4, 5, and 6 belong to yet another category. Figure 10BAs shown, the first translation value corresponding to column 1 is 1,1,0; the first translation value corresponding to column 3 is 1,0,1; the first translation value corresponding to column 8 is 1,0,1; the first translation value corresponding to column 4 is 0,1,0; the first translation value corresponding to column 5 is 0,0,1; the first translation value corresponding to column 6 is 0,0,1; the first translation value corresponding to column 2 is 0,1,2; the first translation value corresponding to column 7 is 0,1,2; and the first translation value corresponding to column 9 is 1,2,0. Figure 10B In the text, "-1" indicates that the first translation value corresponding to the 0 element in the second region is 0.

[0222] Therefore, we can see that the number of non-zero first translation values ​​in each of columns 1, 3, and 8 is the same, that is, 2. The number of non-zero first translation values ​​in each of columns 4, 5, and 6 is the same, that is, 2. The number of non-zero first translation values ​​in each of columns 2, 7, and 9 is the same, that is, 1.

[0223] Optionally, in the second region, the first shift values ​​of multiple columns of the same category that are not equal to Y belong to the same category. For example, the second region includes columns 1 to 9, where columns 1 to 3 belong to one category, columns 4 to 6 belong to another category, and columns 7 to 9 belong to yet another category. Figure 10C As shown, the first translation values ​​for column 1 are 1, 2, 0; for column 2, 0, 1, 2; for column 3, 2, 0, 1; for column 4, 1, 1, 0; for column 5, 0, 1, 1; for column 6, 1, 0, 1; for column 7, 0, 1, 2; for column 8, 2, 1, 0; and for column 9, 1, 2, 0. Therefore, the elements with a non-zero first translation value in columns 1 to 3 are 1, 2; the elements with a non-zero first translation value in columns 7 to 9 are 1, 2; and the elements with a non-zero first translation value in columns 4 to 6 are 1. Figure 10C In the text, "-1" indicates that the first translation value corresponding to the 0 element in the second region is 0.

[0224] Optionally, in the second region, the number of first shift values ​​of the same type among multiple columns of the same category is the same. For example, the second region includes columns 1 to 9, where columns 1 to 3 belong to one category, columns 4 to 6 belong to another category, and columns 7 to 9 belong to yet another category. Figure 10DAs shown, the first shift value corresponding to column 1 is 1, 2, 0; the first shift value corresponding to column 2 is 0, 1, 2; the first shift value corresponding to column 3 is 2, 0, 1; the first shift value corresponding to column 4 is 2, 1, 0; the first shift value corresponding to column 5 is 2, 0, 1; the first shift value corresponding to column 6 is 0, 2, 1; the first shift value corresponding to column 7 is 0, 1, 2; the first shift value corresponding to column 8 is 2, 0, 1; and the first shift value corresponding to column 9 is 1, 2, 0. Therefore, it can be seen that the number of elements with values ​​of 0, 1, and 2 in the first shift value corresponding to each category of columns is the same. Figure 10D In the text, "-1" indicates that the first translation value corresponding to the 0 element in the second region is 0.

[0225] Optionally, in the second region, elements of the same type in the first shift values ​​corresponding to multiple columns of the same category will have the same position in the first shift values ​​corresponding to multiple columns. For example, the second region includes columns 1 to 9, where columns 1 to 3 belong to one category, columns 4 to 6 belong to another category, and columns 7 to 9 belong to yet another category. Figure 10E As shown, the first translation value for each column from column 1 to column 3 is 1, 2, or 0. The translation values ​​"1", "2", and "0" are in the same position in different columns. The same applies to columns 4 to 6 and columns 7 to 9, so they will not be described in detail here.

[0226] Optionally, in the second region, the first shift values ​​of the same category across multiple columns of the same type are positioned differently within the corresponding first shift values. For example, the second region includes columns 1 to 9, where columns 1 to 3 belong to one category, columns 4 to 6 to another, and columns 7 to 9 to yet another. Figure 10F As shown, the first translation values ​​for column 1 are 1, 2, 0; for column 2, 0, 1, 2; and for column 3, 2, 0, 1. It can be seen that the translation values ​​"1", "2", and "0" are in different positions in different columns. The same applies to columns 4 through 6 and columns 7 through 9, which will not be elaborated further here.

[0227] Optionally, in the second region, the first shift value corresponding to multiple columns of the same category includes two types of first shift values, which can be 0 or non-zero. For example, the second region includes columns 1 to 9, where columns 1 to 3 belong to one category, columns 4 to 6 belong to another category, and columns 7 to 9 belong to yet another category. Figure 10G As shown, the first shift value for column 1 is 1,1,0; the first shift value for column 2 is 0,1,0; and the first shift value for column 3 is 1,0,1. It can be seen that columns of the same category contain two types of elements: 0 and 1.

[0228] Optionally, the second region includes a second sub-region B. In the second sub-region B, each of the two columns corresponding to the second sub-region has the same two first translation values. In the second sub-region B, among the three first translation values ​​corresponding to the three columns, two of the first translation values ​​are the same, and the third first translation value is different from the two first translation values. For example, ... Figure 11A or Figure 11B As shown, the second subregion B contains a double-diagonal structure. The second subregion B includes one triple column (i.e., a column with a weight of 3), and the remaining columns of the second subregion B are all double columns (i.e., columns with a weight of 2). More specifically, the two first translation values ​​corresponding to each double column in the second subregion B are the same. For example, the first translation value corresponding to each double column in the second subregion B is 0. One triple column in the second subregion corresponds to three first translation values, where two of the first translation values ​​are the same, and the third first translation value is different from the other two. For example, the first translation value corresponding to the triple column in the second subregion B is y, y, 0, where y is an integer greater than 0 and less than or equal to 2*Z. For example, y = 1. After lifting, the second subregion B becomes the first subregion B in the first basis matrix.

[0229] Optionally, the second basis matrix is ​​BG2 from the fifth-generation communication protocol. BG2 is as follows: Figure 12 As shown. In one possible example, the first translation values ​​corresponding to columns 1 to 6, 8, and 10 of BG2 are all 0; the first translation value corresponding to column 7 of BG2 is 0,0,1; the first translation value corresponding to column 9 of BG2 is 1,1,0; the first translation value corresponding to column 11 of BG2 is 0,0,1, or 1,0,0, or 0,1,0; and the first translation values ​​corresponding to columns 12 to 14 are all 0. For example, if the first lift uses a lift value Z of 2, the first basis matrix obtained after translating BG2 is as follows. Figures 13A to 13C As shown. For example, as Figure 13A The first basis matrix shown includes a first region, which in turn includes submatrices in columns 1, 2, 4, 5, and 10. Each submatrix in these columns corresponds to two columns of elements in the first region. Different submatrices correspond to different columns, and the weight of each column is 3. In other words, the column weights of different submatrices in these columns are equal. No non-zero submatrix in any of these columns is... The number of submatrices is equal. In other words, any non-zero submatrix in each of the 1st, 2nd, 4th, 5th, and 10th columns is... The number of submatrices is equal.

[0230] In another possible example, the first translation values ​​corresponding to columns 1 through 6, 8, and 10 of BG2 are all 0; the first translation value corresponding to column 7 of BG2 is 0,0,1; the first translation value corresponding to column 9 of BG2 is 0,0,0; and the first translation value corresponding to column 11 of BG2 is 0,0,1, 1,0,0, or 0,1,0. For example, if the first lift uses a lift value Z of 2, the first basis matrix obtained after translating BG2 is as follows. Figures 14A to 14C As shown. For example, as Figure 14A The first basis matrix shown includes a first region, which comprises submatrices in columns 1, 2, 4, 5, 9, and 10. Each submatrix in these columns corresponds to two columns of elements in the first region, with different columns corresponding to different columns. The column weight of each element in these columns is 3. In other words, the column weights of different submatrices in these columns are equal. No non-zero submatrix in any of these columns is... The number of submatrices is equal. In other words, any non-zero submatrix in each of the 1st, 2nd, 4th, 5th, 9th, and 10th columns is... The number of submatrices is equal.

[0231] In another possible example, the first translation values ​​corresponding to columns 1 through 6, 8, and 10 of BG2 are all 0; the first translation value corresponding to column 7 of BG2 is 0, 0, 0; the first translation value corresponding to column 9 of BG2 is 1, 1, 0; and the first translation value corresponding to column 11 of BG2 is 0, 0, 1, or 1, 0, 0, or 0, 1, 0. For example, if the first lift uses a lift value Z of 2, the first basis matrix obtained after translating BG2 is as follows. Figures 15A to 15C As shown. For example, as Figure 15AThe first basis matrix shown includes a first region, which comprises submatrices in columns 3, 6, 8, 12, and 13. Each submatrix in columns 3, 6, 8, 12, and 13 corresponds to two columns of elements in the first region. Different submatrices correspond to different two columns of elements, and the column weight of each element in these columns is 2. In other words, the column weights of different submatrices in columns 3, 6, 8, 12, and 13 are equal. No non-zero submatrix in any of the submatrices in columns 3, 6, 8, 12, and 13 is... The number of submatrices is equal. In other words, any non-zero submatrix in each of the 3rd, 6th, 8th, 12th, and 13th columns is... The number of submatrices is equal.

[0232] In another possible implementation, the first translation values ​​corresponding to columns 1 through 6, 8, and 10 of BG2 are all 0; the first translation value corresponding to column 7 of BG2 is 0, 0, 0; the first translation value corresponding to column 9 of BG2 is 0, 0, 1; and the first translation value corresponding to column 11 of BG2 is 0, 0, 1, or 1, 0, 0, or 0, 1, 0. For example, if the first lift uses a lift value Z of 2, the first basis matrix obtained after translating BG2 is as follows: Figures 16A to 16C As shown. For example, as Figure 16A The first basis matrix shown includes a first region, which comprises submatrices in columns 3, 6, 8, 12, 13, and 14. Each submatrix in these columns corresponds to two columns of elements in the first region, with different columns corresponding to different columns. The column weight of each element in these columns is 2. In other words, the column weights of different submatrices in these columns are equal. Furthermore, no non-zero submatrix in any of these columns is a 0. The number of submatrices is equal. In other words, any non-zero submatrix in each of the 3rd, 6th, 8th, 12th, 13th, and 14th columns is... The number of submatrices is equal.

[0233] Therefore, by setting the first translation value for each column in BG2, the trap set of the first basis matrix can be reduced, thereby reducing the occurrence of erroneous flat layers.

[0234] Implementation method 2: The first communication device determines the first basis matrix based on the second basis matrix and the first correspondence.

[0235] Here, the first correspondence is the correspondence between the first basis matrix and the second basis matrix. Optionally, the first correspondence can be indicated by a table. The first communication device can quickly determine the first basis matrix corresponding to the second basis matrix by looking up the table.

[0236] After obtaining the bit sequence to be encoded, the first communication device can perform LDPC encoding on the bit sequence to be encoded based on the first basis matrix to obtain the encoded bit sequence. The encoded bit sequence can also be called the encoded codeword.

[0237] In one possible implementation, the first communication device generates a parity check matrix based on a first basis matrix. For example, the first communication device determines the parity check matrix based on the second shift value corresponding to each column of the first basis matrix and the first basis matrix. Then, the first communication device performs LDPC encoding on the bit sequence to be encoded based on the parity check matrix to obtain the encoded bit sequence. Optionally, the first communication device can convert the parity check matrix into a generator matrix, and then use the generator matrix and the bit sequence to be encoded to generate the encoded bit sequence.

[0238] The encoded bit sequence may include information bits, or it may include information bits and redundant bits. The redundant bits may include parity bits, or it may include parity bits and padding bits.

[0239] 803. The first communication device outputs the encoded bit sequence. Correspondingly, the second communication device receives the information to be decoded.

[0240] After obtaining the encoded bit sequence, the first communication device can transmit the encoded bit sequence. This application does not limit the method by which the first communication device transmits the encoded bit sequence. Taking a chip in a first communication device as an example, the first communication device can transmit the encoded bit sequence through the chip's I / O ports. Optionally, the first communication device can then transmit the encoded bit sequence through an antenna. Taking a first communication device with an antenna as an example, for instance, if the first communication device is a first communication device, the first communication device can transmit the encoded bit sequence through the antenna.

[0241] After the first communication device sends the encoded bit sequence, the encoded bit sequence is transmitted to the second communication device via the channel. The second communication device can decode the received encoded bit sequence; therefore, this application refers to the encoded bit sequence received by the second communication device as the information to be decoded.

[0242] Optionally, the channel may include a wireless channel. Since the encoded bit sequence may change in the channel (e.g., due to noise or fading), the encoded bit sequence transmitted by the first communication device and the decoded information received by the second communication device may differ. The decoded information received by the second communication device can be understood as an encoded bit sequence containing noise.

[0243] This application does not limit the method by which the second communication device receives the information to be decoded. Taking the second communication device as a chip in a second communication device as an example, the second communication device can receive the information to be decoded through an antenna, and then the second communication device can receive the information to be decoded through the chip's I / O ports. Taking the second communication device having an antenna as an example, for instance, if the second communication device is a second communication device, the second communication device can receive the information to be decoded through the antenna.

[0244] 804. The second communication device performs LDPC decoding based on the first base matrix and the information to be decoded to obtain the decoded bit sequence.

[0245] The encoding method used by the first communication device for the bit sequence to be encoded and the decoding method used by the second communication device for the information to be decoded can correspond to each other.

[0246] In one possible implementation, the encoding and decoding methods correspond to each other, which may be based on the same type of codeword. For example, both the encoding and decoding methods are based on LDPC codes, or in other words, the encoding and decoding methods are LDPC encoding and LDPC decoding, respectively. The correspondence between LDPC encoding and LDPC decoding may also include the LDPC encoding and LDPC decoding being based on the same parity-check matrix. For example, the parity-check matrix used by the second communication device to perform LDPC decoding is the same as the parity-check matrix used by the first communication device to perform LDPC encoding. The parity-check matrix is ​​determined based on a first base matrix. The method for obtaining the first base matrix is ​​described in the foregoing related introduction and will not be repeated here.

[0247] In this embodiment, a first communication device acquires a bit sequence to be encoded. Then, the first communication device performs LDPC encoding on the bit sequence to be encoded according to a first base matrix to obtain the encoded bit sequence. The first communication device outputs the encoded bit sequence. The first base matrix includes a first region, which includes multiple sub-matrices. Each sub-matrice includes multiple sub-matrices, and any two sub-matrices in the multiple sub-matrices have equal column weights. The number of non-zero sub-matrices in each sub-matrice that are not part of the first matrix is ​​the same. The first matrix is ​​a matrix where both row and column weights are 1. It is understood that the characteristics of the multiple sub-matrices in the first region of the first base matrix, designed in this way, can help reduce loops that repeatedly pass through the same positions in the first base matrix, thereby reducing the trap set in the base matrix. This can reduce the occurrence of error layers in URLLC scenarios or similar scenarios, and is beneficial for supporting high-reliability communication.

[0248] The communication device involved in this application is described below.

[0249] Figure 17 This is a schematic diagram of the communication device according to an embodiment of this application. Please refer to... Figure 17 The communication device 1700 includes a transceiver module 1701 and a processing module 1702.

[0250] In one possible implementation, the communication device 1700 is a first communication device, or a component (e.g., a chip), module, or unit having the first communication device. For example, the communication device 1700 may be the first communication device described above.

[0251] Communication device 1700 can be used to perform the above. Figure 8 For details regarding the execution of all or all steps of the functions of the first communication device in the illustrated embodiment, please refer to the foregoing. Figure 8 The relevant descriptions in the illustrated embodiments.

[0252] In another possible implementation, the communication device 1700 is a second communication device, or has components (e.g., chips), modules, or units within a second communication device. For example, the communication device 1700 may be the second communication device described above.

[0253] Communication device 1700 can be used to perform the above. Figure 8 For details regarding the execution of all or all steps of the second communication device function in the illustrated embodiment, please refer to the foregoing. Figure 8 The relevant descriptions in the illustrated embodiments.

[0254] The processing module 1702 is used for data processing. The transceiver module 1701 is used to implement the corresponding communication functions.

[0255] Optionally, the transceiver module 1701 may include a sending module and a receiving module. The sending module is used to perform the sending operation in the above method embodiments. The receiving module is used to perform the receiving operation in the above method embodiments.

[0256] It should be noted that the communication device 1700 may include a transmitting module but not a receiving module. Alternatively, the communication device 1700 may include a receiving module but not a transmitting module. Specifically, it depends on whether the above-described scheme executed by the communication device 1700 includes both transmitting and receiving actions.

[0257] Optionally, the communication device 1700 may further include a storage module, which can be used to store instructions and / or data. The processing module 1702 can read the instructions and / or data in the storage module so that the communication device 1700 can implement the aforementioned method embodiments.

[0258] In one possible implementation, the communication device 1700 can be used to perform the actions performed by the first communication device in the above embodiment. The processing module 1702 is used to perform processing-related operations on the first communication device side in the above method embodiment. The transceiver module 1701 is used to perform receiving-related operations on the first communication device side in the above method embodiment.

[0259] For example, the communication device 1700 is used to execute the following scheme:

[0260] Processing module 1702 is used to obtain the bit sequence to be encoded; perform LDPC encoding on the bit sequence to be encoded according to the first base matrix to obtain the encoded bit sequence; wherein, the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrix includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of any non-zero sub-matrices in each sub-matrix in the multiple sub-matrices that are not the first matrix is ​​the same, and the first matrix is ​​a matrix with both row weight and column weight of 1;

[0261] The transceiver module 1701 is used to output the encoded bit sequence.

[0262] For example, the communication device 1700 is used to execute the following scheme:

[0263] Processing module 1702 is used to perform LDPC encoding based on the first base matrix and the bit sequence to be encoded to obtain the encoded bit sequence; wherein, the first base matrix is ​​determined based on the second base matrix and the first shift value corresponding to each column in the second region of the second base matrix, and the number of first shift values ​​that are not Y in the first shift values ​​corresponding to multiple columns of the same category in the second region of the second base matrix is ​​the same, where Y is an integer greater than or equal to 0 and less than or equal to 2*Z, and Z is the boost value used for the first boost;

[0264] The transceiver module 1701 is used to output the encoded bit sequence.

[0265] In another possible implementation, the communication device 1700 can be used to perform the actions performed by the second communication device in the above embodiment. The processing module 1702 is used to perform processing-related operations on the second communication device side in the above method embodiment. The transceiver module 1701 is used to perform receiving-related operations on the second communication device side in the above method embodiment.

[0266] For example, the communication device 1700 is used to execute the following scheme:

[0267] The transceiver module 1701 is used to receive information to be decoded;

[0268] Processing module 1702 is used to perform LDPC decoding based on the first base matrix and the information to be decoded to obtain the decoded bit sequence; wherein, the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrix includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, the number of any non-zero sub-matrices in each sub-matrix that are not the first matrix is ​​the same, and the first matrix is ​​a matrix in which both row weight and column weight are 1.

[0269] For example, the communication device 1700 is used to execute the following scheme:

[0270] The transceiver module 1701 is used to receive information to be decoded;

[0271] Processing module 1702 is used to perform LDPC decoding based on the first base matrix and the information to be decoded to obtain the decoded bit sequence; wherein, the first base matrix is ​​determined based on the second base matrix and the first shift value corresponding to each column in the second region of the second base matrix, and the number of first shift values ​​that are not Y in the first shift values ​​corresponding to multiple columns of the same category in the second region of the second base matrix is ​​the same, where Y is an integer greater than or equal to 0 and less than or equal to 2*Z, and Z is the boost value used for the first boost.

[0272] For other implementation methods, please refer to the preceding text. Figure 7 The relevant descriptions in the embodiments shown in Figure 10 will not be repeated here.

[0273] It should be understood that the specific procedures for each module to perform the above-mentioned corresponding processes have been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0274] The processing module 1702 in the above embodiments can be implemented by at least one processor or processor-related circuitry. The transceiver module 1701 can be implemented by a transceiver or transceiver-related circuitry. The transceiver module 1701 can also be referred to as a communication module or communication interface. The storage module can be implemented by at least one memory.

[0275] This application also provides another communication device. Figure 18 This is another structural schematic diagram of the communication device according to an embodiment of this application. Please refer to... Figure 18 The communication device 1800 includes a processor 1801.

[0276] Optionally, the communication device 1800 may also include a memory 1802.

[0277] Optionally, the communication device 1800 may also include a transceiver 1803.

[0278] In one possible implementation, the processor 1801, memory 1802, and transceiver 1803 are connected via a bus, and the memory 1802 stores computer instructions.

[0279] In one possible implementation, when the communication device 1800 is a first communication device, or a component within the first communication device (e.g., a chip, chip system, module, processing unit, control unit, or circuit), the communication device 1800 can be used to perform the steps performed by the first communication device in the above method embodiments, as described in the relevant descriptions in the above method embodiments.

[0280] In another possible implementation, when the communication device 1800 includes a second communication device, or is a component within the second communication device (e.g., a chip, chip system, module, processing unit, control unit, or circuit), the communication device 1800 can be used to perform the steps performed by the second communication device in the above method embodiments, as described in the relevant descriptions in the above method embodiments.

[0281] Of the two implementation methods mentioned above, the aforementioned Figure 17 The processing module 1702 in the illustrated embodiment may be the processor 1801, as described above. Figure 17 The transceiver module 1701 in the illustrated embodiment can be the transceiver 1802.

[0282] This application also provides a communication device 1900, which can be a terminal device, a processor in the terminal device, or a chip. The communication device 1900 can be used to perform the operations performed by the first communication device or the second communication device in the above method embodiments.

[0283] When the communication device 1900 is a terminal device Figure 19A simplified structural diagram of a terminal device is shown. (For example...) Figure 19 As shown, the terminal device includes a processor, a memory, and a transceiver. The memory can store computer program code, and the transceiver includes a transmitter 1931, a receiver 1932, radio frequency circuitry (not shown), an antenna 1933, and input / output devices (not shown).

[0284] The processor is mainly used to process communication protocols and communication data; control terminal devices; execute software programs; and process data from software programs.

[0285] Memory is mainly used to store software programs and data.

[0286] Radio frequency (RF) circuits are mainly used for the conversion between baseband signals and RF signals, as well as for the processing of RF signals.

[0287] Antennas are primarily used for transmitting and receiving radio frequency signals in the form of electromagnetic waves.

[0288] Input / output devices can include touchscreens, displays, or keyboards. They are primarily used to receive user input and output data to the user. It should be noted that some types of terminal devices may not have input / output devices.

[0289] When data needs to be transmitted, the processor performs baseband processing on the data to be transmitted and outputs a baseband signal to the radio frequency (RF) circuit. The RF circuit then processes the baseband signal and transmits it outwards as electromagnetic waves via an antenna. When data is sent to the terminal device, the RF circuit receives the RF signal through the antenna. The RF circuit converts the RF signal back into a baseband signal and outputs it to the processor. The processor converts the baseband signal back into data and processes that data. For ease of explanation, Figure 19 Only one memory, processor, and transceiver are shown in the illustration. In actual terminal devices, there may be one or more processors and one or more memories. Memory may also be referred to as storage medium or storage device, etc. Memory may be set up independently of the processor or integrated with the processor; this application does not limit this.

[0290] In this embodiment, the antenna and radio frequency circuit with transceiver function can be regarded as the transceiver module of the terminal device, and the processor with processing function can be regarded as the processing module of the terminal device.

[0291] like Figure 19 As shown, the terminal device includes a processor 1910, a memory 1920, and a transceiver 1930. The processor 1910 can also be referred to as a processing unit, processing board, processing module, or processing device. The transceiver 1930 can also be referred to as a transceiver unit, transceiver, or transceiver device.

[0292] Optionally, the device in transceiver 1930 used to implement the receiving function can be considered a receiving module, and the device in transceiver 1930 used to implement the transmitting function can be considered a transmitting module. That is, transceiver 1930 includes a receiver and a transmitter. A transceiver may sometimes be called a transceiver unit, transceiver module, or transceiver circuit, etc. A receiver may sometimes be called a receiver unit, receiving module, or receiving circuit, etc. A transmitter may sometimes be called a transmitter, transmitting module, or transmitting circuit, etc.

[0293] Processor 1910 is used to perform the above Figure 8 The processing actions on the side of the first or second communication device in the illustrated embodiment. Transceiver 1930 is used to perform the above-described actions. Figure 8 The transmitting and receiving operations on the first or second communication device side in the illustrated embodiment.

[0294] It should be understood that Figure 19 This is merely an example and not a limitation; the terminal device described above, which includes a transceiver module and a processing module, may not rely on... Figure 17 or Figure 18 The structure shown.

[0295] When the communication device 1900 is a chip, the chip includes a processor and a transceiver. The processor can be a processing module integrated on the chip, a microprocessor, or an integrated circuit. The transceiver can be an input / output circuit or a communication interface. In the above method embodiments, the transmitting operation of the first or second communication device can be understood as the output of the chip, and the receiving operation of the first or second communication device in the above method embodiments can be understood as the input of the chip.

[0296] Optionally, the communication device 1900 may also include a memory, which may be a memory built into the chip or a memory connected to the chip.

[0297] This application also provides a communication device 2000, which can be a network device or a chip. The communication device 2000 can be used to perform the above-described... Figure 8 The operations performed by the first or second communication device in the illustrated embodiments.

[0298] When the communication device 2000 is a network device, such as a base station. Figure 20 A simplified schematic diagram of a base station structure is shown. The base station includes parts 2010, 2020, and 2030.

[0299] The 2010 section is mainly used for baseband processing and controlling the base station; the 2010 section is usually the control center of the base station, which can usually be called a processor, and is used to control the base station to perform the processing operations on the first communication device or the second communication device side in the above method embodiments.

[0300] The 2020 section is primarily used to store computer program code and data.

[0301] Section 2030 is primarily used for transmitting and receiving radio frequency (RF) signals, as well as converting RF signals to baseband signals. Section 2030 is commonly referred to as a transceiver module, transceiver, transceiver circuit, or transceiver unit. The transceiver module of section 2030, also known as a transceiver or transceiver unit, includes antenna 2033 and RF circuitry (not shown in the figure), where the RF circuitry is mainly used for RF processing. Optionally, the device in section 2030 that implements the receiving function can be considered a receiver, and the device that implements the transmitting function can be considered a transmitter; that is, section 2030 includes receiver 2032 and transmitter 2031. The receiver can also be called a receiving module, receiver circuit, or receiving circuit, and the transmitter can be called a transmitting module, transmitter, or transmitting circuit.

[0302] The 2010 and 2020 sections may include one or more single boards, each of which may include one or more processors and one or more memories. The processors are used to read and execute programs in the memories to implement baseband processing functions and control the base station. If multiple single boards exist, they can be interconnected to enhance processing capabilities. As an optional implementation, multiple single boards may share one or more processors, multiple single boards may share one or more memories, or multiple single boards may simultaneously share one or more processors.

[0303] For example, in one implementation, the transceiver module of part 2030 is used to perform... Figure 8 The transmit / receive related processes are performed by the first or second communication device in the illustrated embodiment. The processor in section 2010 is used to execute... Figure 8 The illustrated embodiments describe processes related to processing performed by the first or second communication device.

[0304] It should be understood that Figure 20 This is for illustrative purposes only and not as a limitation. The network devices mentioned above, including processors, memory, and transceivers, may not depend on... Figure 17 or Figure 18 The structure shown.

[0305] When the communication device 2000 is a chip, the chip includes a processor and a transceiver. The processor is an integrated processor, microprocessor, or integrated circuit on the chip. The transceiver can be an input / output circuit or a communication interface. In the above method embodiments, the transmitting operation of the first or second communication device can be understood as the output of the chip, and the receiving operation of the first or second communication device in the above method embodiments can be understood as the input of the chip.

[0306] Optionally, the communication device 2000 may also include a memory, which may be a memory built into the chip or a memory connected to the chip.

[0307] This application also provides a communication system, which includes a first communication device and a second communication device. The first communication device is used to perform, for example, Figure 8 The first communication device shown includes all or part of the steps of the first communication device. The second communication device is used to perform, as... Figure 8 All or part of the steps of the second communication device shown.

[0308] This application also provides a computer program product including computer instructions, which, when run on a computer, causes the computer to perform the above-described actions. Figure 8 The method of the embodiment shown.

[0309] This application also provides a computer-readable storage medium, including computer instructions, which, when executed on a computer, cause the computer to perform the above-described actions. Figure 8 The method of the embodiment shown.

[0310] This application also provides a chip device, including a processor, for calling a computer program or computer instructions stored in a memory, so that the processor executes the above-described... Figure 8 The method of the embodiment shown.

[0311] Optionally, the processor is coupled to the memory via an interface.

[0312] Optionally, the chip device may also include a memory in which computer programs or computer instructions are stored.

[0313] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or one or more devices used to control the above. Figure 8The illustrated embodiment is an integrated circuit for program execution of the method. The memory mentioned above may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0314] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0315] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0316] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0317] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the part of the technical solution that makes an essential contribution, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0318] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An encoding method, characterized in that, The method includes: Obtain the bit sequence to be encoded; The bit sequence to be encoded is encoded using low-density parity-check (LDPC) encoding based on the first base matrix to obtain the encoded bit sequence. The first base matrix includes a first region, which includes multiple sub-matrices. Each sub-matrix includes multiple sub-matrices. Any two sub-matrices in the multiple sub-matrices have the same column weight. The number of non-zero sub-matrices in each sub-matrix that are not the first matrix is ​​the same. The first matrix is ​​a matrix with both row weight and column weight of 1. Output the encoded bit sequence.

2. The method according to claim 1, characterized in that, The size of the first matrix is ​​Z*Z, where Z = 2 or Z = 3.

3. The method according to claim 1 or 2, characterized in that, The first matrix is ​​a diagonal matrix, an anti-diagonal matrix, a cyclic shift matrix of a diagonal matrix, or a cyclic shift matrix of an anti-diagonal matrix.

4. The method according to any one of claims 1 to 3, characterized in that, The first matrix is or 5. The method according to any one of claims 1 to 3, characterized in that, The first matrix is 6. The method according to any one of claims 1 to 5, characterized in that, The first region includes region A of the first basis matrix; or, the first region includes regions A and B of the first basis matrix.

7. The method according to any one of claims 1 to 6, characterized in that, The first region includes the first row to the Xth row of the first base matrix, where X = 4, 5, 6, 7, or 8.

8. The method according to any one of claims 1 to 7, characterized in that, Each column of the submatrix corresponds to multiple columns of elements in the first region, and different column submatrixes correspond to different multiple columns of elements in the first region. The column weight of each column of the different multiple columns of elements is equal.

9. The method according to any one of claims 1 to 8, characterized in that, The dimension of the submatrix in each column of the submatrix is ​​2*2, and the number of submatrixes in each column of the multi-column submatrix that are the first matrix is ​​the same.

10. The method according to any one of claims 1 to 9, characterized in that, In the multi-column submatrix, any non-zero submatrix in each column is not of the same type as the first matrix; and / or, In the multi-column submatrix, each column of the submatrix contains the same number of non-zero submatrices of the same type; and / or, In the multi-column submatrix, the non-zero submatrices of the same type in each column of the submatrix are in the same position within each column; and / or, Each column of the multi-column submatrix includes two types of non-zero submatrixes, namely, an identity matrix and a non-identity matrix.

11. The method according to any one of claims 1 to 10, characterized in that, The first region includes a first sub-region B. In a column of submatrixes in the first sub-region B, there are three non-zero submatrixes, two of which are the same non-zero submatrixes. In the multiple columns of submatrixes in the first sub-region B, excluding the column of submatrixes, each column contains two non-zero submatrixes, and the two non-zero submatrixes are the same non-zero submatrixes.

12. The method according to any one of claims 1 to 11, characterized in that, The method further includes: The first basis matrix is ​​determined based on the correspondence between the second basis matrix and the first basis matrix, where the first correspondence is the relationship between the first basis matrix and the second basis matrix; or... The first base matrix is ​​generated based on the second base matrix and the first translation value corresponding to each column in the second region of the second base matrix. The number of first translation values ​​that are not Y among the first translation values ​​corresponding to multiple columns of the same category in the second region is the same. Y is an integer greater than or equal to 0 and less than or equal to Z minus one. Z is the boost value used in the first boost.

13. The method according to claim 12, characterized in that, The second region includes columns of one or more categories, with multiple columns of the same category having the same column weight.

14. The method according to claim 13, characterized in that, In the second region, the positions of element 0 and element 1 are the same in multiple columns of the same category.

15. The method according to claim 13 or 14, characterized in that, The columns of the one or more categories include: one or more information columns of the categories, and one or more verification columns of the categories.

16. The method according to any one of claims 11 to 14, characterized in that, In the second region, the first translation values ​​of multiple columns of the same category that are not equal to Y belong to the same category; and / or, In the second region, the number of first shift values ​​of the same type is the same among multiple columns of the same category; and / or, In the second region, the first translation values ​​of the same type among multiple columns of the same category are in the same position within the first translation values ​​corresponding to the multiple columns; and / or, In the second region, the first translation values ​​corresponding to multiple columns of the same category include two types of first translation values, which are 0 and non-zero, respectively.

17. The method according to any one of claims 12 to 16, characterized in that, The second region includes a second sub-region B, which includes a triple column. All columns other than the triple column are double columns. The two first translation values ​​corresponding to each double column of the second sub-region B are the same. Among the three first translation values ​​corresponding to the triple column, two of the first translation values ​​are the same, and the third first translation value is different from the two first translation values.

18. The method according to claim 17, characterized in that, The first translation value corresponding to each of the two columns in the second sub-region B is 0.

19. The method according to claim 17 or 18, characterized in that, The first translation value corresponding to the 3-column in the second sub-region B is y, y, 0, where y is an integer greater than 0 and less than or equal to 2*Z, and Z is the boost value used for the first boost.

20. The method according to any one of claims 12 to 19, characterized in that, The second basis matrix is ​​BG2 in the fifth-generation communication protocol; the first translation value corresponding to columns 1 to 6, 8, and 10 of BG2 is 0, the first translation value corresponding to column 7 of BG2 is 0,0,1, the first translation value corresponding to column 9 of BG2 is 1,1,0, and the first translation value corresponding to column 11 of BG2 is 0,0,1, or 1,0,0, or 0,1,0; or... The second basis matrix is ​​BG2; the first translation value corresponding to columns 1 to 6, 8, and 10 of BG2 is 0, the first translation value corresponding to column 7 of BG2 is 0,0,1, the first translation value corresponding to column 9 of BG2 is 0,0,0, and the first translation value corresponding to column 11 of BG2 is 0,0,1, or 1,0,0, or 0,1,0; or... The second basis matrix is ​​BG2; the first translation value corresponding to columns 1 to 6, 8 and 10 of BG2 is 0, the first translation value corresponding to column 7 of BG2 is 0, 0, 0, the first translation value corresponding to column 9 of BG2 is 1, 1, 0 or 0, 0, 1, the first translation value corresponding to column 11 of BG2 is 0, 0, 1 or 1, 0, 0 or 0, 1, 0.

21. A decoding method, characterized in that, The method includes: Receive the information to be decoded; Low-density parity-check (LDPC) decoding is performed based on the first base matrix and the information to be decoded to obtain the decoded bit sequence; wherein, the first base matrix includes a first region, the first region includes multiple sub-matrices, each sub-matrice includes multiple sub-matrices, any two sub-matrices in the multiple sub-matrices have equal column weights, and the number of non-zero sub-matrices in each sub-matrices that are not the first matrix is ​​the same, and the first matrix is ​​a matrix in which both row weight and column weight are 1.

22. The method according to claim 21, characterized in that, The size of the first matrix is ​​Z*Z, where Z = 2 or Z = 3.

23. The method according to claim 21 or 22, characterized in that, The first matrix is ​​a diagonal matrix, an anti-diagonal matrix, a cyclic shift matrix of a diagonal matrix, or a cyclic shift matrix of an anti-diagonal matrix.

24. The method according to any one of claims 21 to 23, characterized in that, The first matrix is or 25. The method according to any one of claims 21 to 23, characterized in that, The first matrix is or 26. The method according to any one of claims 21 to 25, characterized in that, The first region includes region A of the first basis matrix; or, the first region includes regions A and B of the first basis matrix.

27. The method according to any one of claims 21 to 26, characterized in that, The first region includes the first row to the Xth row of the first base matrix, where X = 4, 5, 6, 7, or 8.

28. The method according to any one of claims 21 to 27, characterized in that, Each column of the submatrix corresponds to multiple columns of elements in the first region, and different column submatrixes correspond to different multiple columns of elements in the first region. The column weight of each column of the different multiple columns of elements is equal.

29. The method according to any one of claims 21 to 28, characterized in that, The dimension of the submatrix in each column of the submatrix is ​​2*2, and the number of submatrixes in each column of the multi-column submatrix that are the first matrix is ​​the same.

30. The method according to any one of claims 21 to 29, characterized in that, In the multi-column submatrix, any non-zero submatrix in each column is not of the same type as the first matrix; and / or, In the multi-column submatrix, each column of the submatrix contains the same number of non-zero submatrices of the same type; and / or, In the multi-column submatrix, the non-zero submatrices of the same type in each column of the submatrix are in the same position within each column; and / or, Each column of the multi-column submatrix includes two types of non-zero submatrixes, namely, an identity matrix and a non-identity matrix.

31. The method according to any one of claims 21 to 30, characterized in that, The first region includes a first sub-region B. In a column of submatrixes in the first sub-region B, there are three non-zero submatrixes, two of which are the same non-zero submatrixes. In the multiple columns of submatrixes in the first sub-region B, excluding the column of submatrixes, each column contains two non-zero submatrixes, and the two non-zero submatrixes are the same non-zero submatrixes.

32. The method according to any one of claims 21 to 31, characterized in that, The method further includes: The first basis matrix is ​​determined based on the correspondence between the second basis matrix and the first basis matrix, where the first correspondence is the relationship between the first basis matrix and the second basis matrix; or... The first base matrix is ​​generated based on the second base matrix and the first translation value corresponding to each column in the second region of the second base matrix. The number of first translation values ​​that are not Y among the first translation values ​​corresponding to multiple columns of the same category in the second region is the same. Y is an integer greater than or equal to 0 and less than or equal to Z minus one. Z is the boost value used in the first boost.

33. The method according to claim 32, characterized in that, In the second region, the first translation values ​​of multiple columns of the same category that are not equal to Y belong to the same category; and / or, In the second region, the number of first shift values ​​of the same type is the same among multiple columns of the same category; and / or, In the second region, the first translation values ​​of the same type among multiple columns of the same category are in the same position within the first translation values ​​corresponding to the multiple columns; and / or, In the second region, the first translation values ​​corresponding to multiple columns of the same category include two types of first translation values, which are 0 and non-zero, respectively.

34. The method according to claim 32 or 33, characterized in that, The second region includes a second sub-region B, which includes a triple column. All columns other than the triple column are double columns. The two first translation values ​​corresponding to each double column of the second sub-region B are the same. Among the three first translation values ​​corresponding to the triple column, two of the first translation values ​​are the same, and the third first translation value is different from the two first translation values.

35. The method according to claim 34, characterized in that, The first translation value corresponding to each of the two columns in the second sub-region B is 0.

36. The method according to claim 34 or 35, characterized in that, The first translation value corresponding to the 3-column in the second sub-region B is y, y, 0, where y is an integer greater than 0 and less than or equal to 2*Z, and Z is the boost value used for the first boost.

37. A communication device, characterized in that, It includes at least one processor, said at least one processor being configured to perform the method as claimed in any one of claims 1 to 20, or said at least one processor being configured to perform the method as claimed in any one of claims 21 to 36.

38. The communication device according to claim 37, characterized in that, The communication device further includes at least one memory, the at least one processor being configured to execute a computer program or computer instructions stored in the at least one memory to perform the method as described in any one of claims 1 to 20; or, The at least one is used to execute a computer program or computer instructions in at least one memory to perform the method as described in any one of claims 21 to 36.

39. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a communication device, implement the method as described in any one of claims 1 to 36.

40. A computer program product, characterized in that, It includes a computer program or instructions that, when executed by a computer, implement the method as described in any one of claims 1 to 36.

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