Unified receiver architecture for multiple wireless protocols

Abstract

The title of this invention is "Unified receiver architecture for multiple wireless protocols." In one embodiment, a receiver includes a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, a mixer to down-convert the RF signal to an intermediate frequency (IF) signal, a programmable gain amplifier (PGA) to amplify the IF signal, a first digitizer coupled to the PGA to digitize the IF signal into a first digitized signal when the RF signal belongs to a first wireless protocol, a second digitizer coupled to the PGA to digitize the IF signal into a second digitized signal when the RF signal belongs to a second wireless protocol, and a controller to direct the IF signal to the first digitizer via a first path when the first wireless protocol is active and to direct the IF signal to the second digitizer via a second path when the second wireless protocol is active.

Description

Background Technology

[0001] In a radio receiver, an input radio frequency (RF) signal is received via an antenna. The signal is then processed in the receiver's signal processing path. Typical receiving operations include amplification, down-conversion, filtering, and digitization to obtain a digitized signal, which can then be digitally processed, such as by demodulation for a specific modulation technique.

[0002] Different wireless protocols have different requirements for parameters such as throughput, sensitivity, and jamming requirements. For protocols with higher requirements for these or other parameters, receivers are designed for higher performance, which typically results in larger chip area and higher power consumption.

[0003] It is possible for multiple wireless protocols to share a common receiver. However, when protocols with higher and lower performance requirements share a common receiver, that receiver is not optimally designed for the lower-performance wireless protocol, partly due to its high power consumption. Generally speaking, the receiver is over-designed for at least the requirements of the lower-performance protocol, unnecessarily increasing power consumption. Summary of the Invention

[0004] In one aspect, a receiver includes: a low-noise amplifier (LNA) for receiving and amplifying a radio frequency (RF) signal; a mixer for down-converting the RF signal to an intermediate frequency (IF) signal; a programmable gain amplifier (PGA) coupled to the mixer for amplifying the IF signal; a first digitizer coupled to the PGA for digitizing the IF signal into a first digitized signal when the RF signal belongs to a first wireless protocol; a second digitizer coupled to the PGA for digitizing the IF signal into a second digitized signal when the RF signal belongs to a second wireless protocol; and a controller for directing the IF signal to the first digitizer via a first path when the first wireless protocol is active, and directing the IF signal to the second digitizer via a second path when the second wireless protocol is active.

[0005] In one implementation, the receiver further includes a switching circuit module, and the controller is configured to control the switching circuit module to: direct an IF signal to a first digitizer via a first path when a first wireless protocol is active; and direct an IF signal to a second digitizer via a second path when a second wireless protocol is active.

[0006] In one implementation, the first path includes a filter coupled between the PGA and the first digitizer, and the second path includes a direct path between the PGA and the second digitizer.

[0007] In this implementation: a first digitizer has a first power consumption level; and a second digitizer has a second power consumption level lower than the first power consumption level. The first digitizer may be a wideband analog-to-digital converter (ADC), and the second digitizer may be a narrowband ADC. The controller may be configured to disable at least the first digitizer when a second wireless protocol is active. In one implementation, the second digitizer is further used to digitize sensor information when the first wireless protocol is active.

[0008] In implementation, the receiver further includes: a first demodulator coupled to a first digitizer, the first demodulator being configured to demodulate a first digitized signal according to a first demodulation scheme; and a second demodulator coupled to a second digitizer, the second demodulator being configured to demodulate a second digitized signal according to a second demodulation scheme. The receiver may also include: a first power detector coupled to an input of an LNA, the first power detector being configured to output a first detection signal in response to an RF signal exceeding a first threshold; and a second power detector coupled to an output of the first digitizer, the second power detector being configured to output a second detection signal in response to the first digitized signal exceeding a second threshold, wherein a controller is configured to control at least one gain component of the receiver based at least in part on the first detection signal or the second detection signal. The receiver may also include a third power detector coupled to an output of a PGA, wherein the third power detector is active when a second wireless protocol is active.

[0009] In another aspect, a method includes: when a first wireless protocol is active, configuring a unified receiver via a controller to provide a down-converted signal to a first path of the unified receiver, the first path including a filter for filtering the down-converted signal and a first digitizer for digitizing the filtered down-converted signal into a first digital signal; and when a second wireless protocol is active, configuring the unified receiver via a controller to provide a second path of the unified receiver with the down-converted signal, the second path including a second digitizer for digitizing the down-converted signal into a second digital signal.

[0010] In one implementation, the method further includes: configuring a unified receiver in response to mode information, the mode information indicating whether a first radio protocol or a second radio protocol is active. The method may also include: dynamically reconfiguring the unified receiver from providing down-converted signals to a second path in response to updated mode information indicating the activity of a second radio protocol.

[0011] In one implementation, configuring the unified receiver may include: controlling switching circuit modules coupled to a first path and a second path, the switching circuit modules being used to receive down-converted signals from a common path of the unified receiver, the common path being used to receive radio frequency (RF) signals and down-convert the RF signals to down-converted signals, the common path being active when a first radio protocol is active and when a second radio protocol is active. Configuring the unified receiver may include: configuring a first digitizer to have a first power consumption level when a first mode of the first radio protocol is active; and configuring the first digitizer to have a second power consumption level, the second power consumption level being less than the first power consumption level, when a second mode of the first radio protocol is active.

[0012] In one implementation, the method further includes: processing the down-converted signal in a first path at a first power consumption level; and processing the down-converted signal in a second path at a second power consumption level, the second power consumption level being less than the first power consumption level.

[0013] In another aspect, a wireless device includes: an antenna for transmitting and receiving RF signals; and an integrated circuit (IC) coupled to the antenna. The IC may include: an LNA for receiving and amplifying the received RF signals; a mixer for down-converting the received RF signals to a second frequency signal; an amplifier coupled to the mixer for amplifying the second frequency signal; a first path including a filter for filtering the second frequency signal and a first digitizer coupled to the filter to digitize the filtered second frequency signal into a first digitized signal; a second path including a second digitizer for digitizing the second frequency signal into a second digitized signal; a first demodulator coupled to the first path for demodulating the first digitized signal; a second demodulator coupled to the second path for demodulating the second digitized signal; and a controller for directing the second frequency signal to the first path when a first wireless protocol is active, and directing the second frequency signal to the second path when a second wireless protocol is active.

[0014] In one implementation, the controller is used to disable the filter and the first digitizer when the second wireless protocol is active. The second digitizer can be configured to digitize sensor information when the first wireless protocol is active and to digitize a second frequency signal into a second digitized signal when the second wireless protocol is active. The second digitizer operates at a lower power consumption level than the first digitizer. Attached Figure Description

[0015] Figure 1 This is a block diagram of a device with a unified receiver architecture according to an embodiment.

[0016] Figure 2A This is a block diagram of a receiver configured in a first mode according to an embodiment.

[0017] Figure 2B This is a block diagram of a receiver configured in a second mode according to an embodiment.

[0018] Figure 3 This is a block diagram of a receiver configured in a third mode according to an embodiment.

[0019] Figure 4 This is a flowchart of a method according to an embodiment.

[0020] Figure 5 This is a block diagram of a representative integrated circuit according to an embodiment.

[0021] Figure 6 This is a high-level graph of the network according to an embodiment. Detailed Implementation

[0022] In various embodiments, a unified receiver architecture is provided that can be used for communication with multiple wireless protocols. Such protocols may have different requirements for various parameters, with one wireless protocol having higher performance requirements for one or more of linearity, noise performance, congestion tolerance, etc., resulting in higher power consumption during receiver operation for that protocol. However, when implementing activity for another wireless protocol with more relaxed requirements for one or more of these parameters (e.g., degraded sensitivity, lower tolerance to high congestion levels, and / or similar sensitivity in much lower bandwidths) for lower power, the receiver can be dynamically configured to operate at a lower power level.

[0023] In this embodiment, a unified receiver architecture can be dynamically controlled based on the active wireless protocol to optimize performance for that protocol, thereby achieving lower power consumption where possible for lower-power wireless protocols. In this way, a single unified receiver architecture that can be optimized for use by multiple wireless protocols is provided.

[0024] As an example, a unified receiver architecture can be used in conjunction with a variety of packet-based wireless protocols such as Wi-Fi, Bluetooth™ (classic or low power), Zigbee™, and many other Internet of Things (IoT) protocols. Implementations are applicable to receivers for both constant amplitude modulated signals (such as Frequency Shift Keying (FSK), Gaussian Frequency Shift Keying (GFSK), Minimum Frequency Shift Keying (MSK)) and / or other IoT standards, as well as non-constant amplitude modulated signals (such as OFDM).

[0025] For the purposes of this discussion, a receiver operating in Wi-Fi operating mode according to a given IEEE 802.11 specification (such as any of the IEEE 802.11a / b / g / n / ac / ax / be specifications, typically from MCS0 to MCS11 or higher, if applicable) will be used as an example of a high-performance wireless protocol, while the same receiver operating in Bluetooth operating mode (Bluetooth Classic or Bluetooth Low Energy) will be used as an example of a low-performance wireless protocol already optimized for low power. However, it should be understood that embodiments are not limited to these examples, and receivers may operate in high and low performance modes according to other wireless protocols.

[0026] Generally, for high-performance wireless protocols, receivers are designed for high throughput at elevated sensitivity levels in the presence of strong congestion. These requirements necessitate radio receiver designs with low noise figures and high linearity supported by wide bandwidth. Such requirements result in high current consumption. In contrast, receivers for low-power wireless protocols have less stringent requirements for all of the above specifications (or similar requirements in much narrower bandwidths), and are designed to optimize operation with reduced current consumption in a tradeoff of performance. As used herein, the terms “high” and “low” are used in conjunction with the discussion of performance requirements and / or power, and are used to indicate the relative level of such parameters.

[0027] In one or more embodiments, the design requirements for different wireless protocols are independent of each other, and a unified receiver architecture is provided for operation in both high-performance and low-power wireless protocols without performance compromises in each mode. To this end, the controller is adapted to dynamically configure the unified receiver for a given operating mode. For example, when a low-power wireless protocol (such as Bluetooth) is active, the controller configures the receiver in a low-current mode to meet the requirements of protocols with significantly reduced current consumption (e.g., approximately 70% lower than in high-performance mode). Conversely, when a high-performance wireless protocol (such as Wi-Fi) is active, the controller configures the receiver in a higher-current mode to meet the requirements of that protocol. In some implementations, in high-performance mode, the controller may further configure the receiver to reduce power consumption for a specific activity in high-performance mode, such as beacon purposes (e.g., lower MCS conditions for IEEE 802.11b and for IEEE 802.11a / g / n / ac / ax / be, typically from MCS0 to MCS4). In a particular operation, this lower-power operation can reduce power consumption by approximately 25%.

[0028] Now for reference Figure 1 This illustrates a block diagram of a device with a unified receiver architecture according to an embodiment. Figure 1As shown, receiver 100 is a radio receiver applicable in any type of wireless device. In various embodiments, antenna 102 receives input RF signals and provides them to matching circuitry 105. In one embodiment, matching circuitry 105 may be implemented as an LC circuit having at least one series-coupled inductor and a parallel-coupled capacitor. In another embodiment, matching circuitry 105 may be implemented as a discrete component suitable for use on a circuit board, such that matching circuitry 105 is outside the circuit module within an integrated circuit having additional circuitry of receiver 100.

[0029] like Figure 1 As shown, the RF signal is coupled via pins 106, 108 and junction line 107 to a circuit module of receiver 100 implemented on an integrated circuit (IC). The RF signal can be attenuated via an attenuator circuit module, which can be implemented as, for example, a passive gain network including a capacitor C4 and a resistor R1 coupled in parallel. In different embodiments, one or more of these RC components can be dynamically controlled to control the amount of attenuation, such that this front-end attenuator circuit module is considered one of a plurality of gain components of receiver 100, namely a first gain control region of receiver 100. While embodiments are not limited to this, in one particular embodiment, this attenuator circuit module can provide a controllable gain from -15 dB to 9 dB (e.g., in 2 dB steps per update). In one embodiment, resistor R1 can be dynamically controlled to adjust the gain setting of the first gain control region.

[0030] like Figure 1 As further shown, an on-chip matching circuit module presenting optimal impedance at pin 108 can be implemented using an inductor L1 and a parallel-coupled capacitor C1. As further shown, another parallel-coupled capacitor C2 can be implemented as a programmable tuning capacitor for bandgap tuning. After any attenuation in the attenuator circuit module, the RF signal is supplied to a low-noise amplifier (LNA) 120, which, depending on the implementation, can be a current-mode low-noise transconductance amplifier (LNTA) or a voltage-mode LNA. As used herein, unless otherwise specifically stated, the terms "low-noise amplifier" and "LNA" encompass both current-mode LNTA and voltage-mode LNA. As shown, multiple units 120, also referred to as "slices," can be employed. 0-n To implement the LNA120. Depending on the desired gain, slice 120 can be enabled. 0-n One or more of them are used to amplify the input RF signal.

[0031] like Figure 1As further shown, the capacitive attenuator is coupled to the input of LNA 120, which can be implemented using a series-coupled capacitor C3 and a programmable parallel-coupled capacitor C4. After amplification in LNA 120, the RF signal is provided to mixer 125 through coupling capacitor CC.

[0032] In various embodiments, mixer 125 can be implemented as a composite passive mixer (and therefore in Figure 1 The middle part is shown as mixer 125 I,Q It should be understood that, as used herein, the composite circuit module and other components shown may be referred to by unsubscripted designations, and the discussion of a given signal path (e.g., an I or Q signal path) is equally applicable to other signal paths. It should also be noted that other implementations of the mixer are possible and may include active mixers. Mixer 125 is configured to downconvert an RF signal to a lower frequency signal, such as an intermediate frequency (IF) signal having separate in-phase and quadrature portions (i.e., provided to the I and Q portions of the I and Q signal paths, respectively).

[0033] exist Figure 1 In the embodiment shown, the passive mixer 125 can be implemented using switches (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) controlled by mixing signals (e.g., local oscillator (LO) signals output from a local oscillator). As shown, differential baseband I and Q signals at IF can be generated in each path of the I and Q signal paths via mixing signals LO_IP, LO_IN and LO_QP, LO_QN. From there, the IF signal is provided to... Figure 1 In this embodiment, a programmable gain amplifier (PGA) is implemented as a transimpedance amplifier (TIA) 130. The TIA 130 consists of an operational amplifier and a feedback filter, which is formed by a capacitor Ctia and a resistor Rtia (e.g., a first-order filter function). The TIA 130 operates to convert the mixer IF current into a voltage signal. In other implementations, the PGA may be implemented as a voltage-mode PGA. As used herein, unless otherwise stated, the terms "programmable gain amplifier" and "PGA" encompass both current-mode TIA and voltage-mode PGA.

[0034] It should be noted that LNA 120, mixer 125, and TIA 130 constitute a second gain control region of receiver 100. While embodiments are not limited to this, in one particular embodiment, this second gain control region may have a controllable gain ranging from 0 dB to 33 dB (e.g., with a nominal step size of 2 dB).

[0035] Still referencing Figure 1The controller 170 can dynamically control the nodes at the output of the TIA 130 to switch the signal to a path selected from two different paths from the receiver 100, depending on the active wireless protocol. To this end, the controller 170 is operable to configure the receiver 100 to pass the IF signal output from the TIA 130 to a circuit module on one of the two selectable paths, namely, to the first path 155, which can be implemented as a high-performance signal processing path. I,Q The component, or passed to a second path that can be implemented as a low-power signal processing path 142 I,Q The components. To achieve this control, controller 170 can dynamically control one path to be active and the other path to be de-energized. In this way, the inactive path provides high impedance when turned off, thus not loading the active path. In another implementation, controller 170 can be coupled to a switching circuit module it controls to direct the IF signal to one of the first and second paths. Although Figure 1 Although not specifically shown, it should be understood that this switching circuit module can be implemented as coupled to node 141. I,Q Multiple MOSFETs are used, and operated under the control of controller 170, to direct the IF signal output from TIA 130 to a given path among these multiple paths. Of course, other types of switching circuit modules or other control mechanisms can be used in other implementations.

[0036] exist Figure 1 In the specific embodiment shown, the first path 155 may include a circuit module for processing signals of a high-performance wireless protocol, such as the Wi-Fi protocol. Conversely, the second path 142 may include a circuit module for processing signals of a less demanding wireless protocol, such as a given low-power wireless protocol, such as one or more of Bluetooth or Wi-Fi protocols. Of course, while these specific wireless protocols are used to describe the embodiments for the purposes of discussion, it is to be understood that the embodiments are not limited to this, and in other implementations, these different paths may be used to process signals of other wireless protocols.

[0037] When the high-performance wireless protocol is active and communication is in progress, the controller 170 configures the first signal path 155 to be active by coupling the output of the TIA 130 to a low-pass filter (LPF) 145 for low-pass filtering. In one embodiment, the LPF 145 may be implemented using a biquad filter. Although for ease of use... Figure 1The LPF 145 is not shown in the illustration, but it may include a PGA for controlling the gain of the dual second-order filters. In an embodiment, the LPF 145 constitutes a third gain control region of the receiver 100. While embodiments are not limited to this, in one particular embodiment, this third gain control region may have a controllable gain between -10 dB and 20 dB (e.g., with a step size of 2 dB). Note that in Figure 1 In its implementation, it can be achieved using an RC component (i.e., resistor R). AAF and capacitor C AAF This is used to perform additional anti-aliasing filtering.

[0038] The filtered IF signal output from the LPF 145 is provided to the digitizer, namely the analog-to-digital converter (ADC) 150. I,Q The ADC150 can be implemented as a high-performance ADC, typically a wideband ADC, such as a successive approximation register (SAR) ADC. However, in other implementations, such as those for 2G cellular networks, the high-performance ADC can be implemented as a narrowband ADC, such as a delta-sigma ADC. The digitized output of the ADC150 (WIFIADC_OUT) is provided to a demodulator (which can be implemented in a digital signal processor (DSP) for ease of use). Figure 1 (Illustration shown in the image).

[0039] When the low-power wireless protocol is active and communication is in progress, controller 170 configures the second signal path 142 to be active and disables the first path 155 (and / or the control switch circuit module) to couple the output of TIA 130 to the second ADC 140. I,Q In one or more embodiments, ADC 140 may be implemented as a narrowband ADC and may consume less power than ADC 150. For example, ADC 140 may be implemented as a delta-sigma ADC or another low-power ADC. In one particular implementation, ADC 140 is an auxiliary ADC (separate from ADC 150) used in high-performance wireless protocols such as Wi-Fi to digitize temperature information, which is then used to perform temperature compensation of the crystal oscillator during such Wi-Fi operation. In this way, the auxiliary ADC that is already present and used during Wi-Fi mode is repurposed as part of the signal processing path for low-power mode, thereby further reducing chip area.

[0040] Therefore, when a lower power wireless protocol is active, ADC 140 is controlled to become part of the second path 142 to digitize the IF signal output from TIA 130. The digitized output (LPWADC_OUT) of ADC 140 is provided to the demodulator (for ease of use). Figure 1 (Illustration shown in the diagram). Note that this demodulator is configured for a given low-power wireless protocol, and in one case, it can be implemented in the same DSP as a high-performance demodulator. Although in Figure 1 The embodiments are shown in this high-level manner, but many variations and alternatives are possible.

[0041] Now for reference Figure 2A A block diagram of a receiver according to an embodiment is shown. Figure 2A As shown, receiver 200 is a unified receiver architecture configured for high-performance mode. It should also be understood that, for ease of illustration, only a single orthogonal path is shown.

[0042] Receiver 200 receives an input RF signal (RX_In) (e.g., from an antenna). The RF signal is provided to an attenuator, which... Figure 2A In some embodiments, the attenuator is implemented as a passive gain network, for example, including a capacitor (C2) and a resistor (R1) coupled in parallel. In different embodiments, one or more of these RC components can be dynamically controlled to control the amount of attenuation, such that the attenuator is considered one of the gain components of receiver 200, namely the first gain control region 211 of receiver 200. While embodiments are not limited to this, in one particular embodiment, the attenuator can provide a controllable gain from -15dB to 9dB (e.g., with approximately 2dB steps per update). In one embodiment, resistor R1 and / or capacitor C2 can be dynamically controlled to adjust the gain setting of the first gain control region 211.

[0043] After any attenuation in this front-end attenuator, the RF signal is supplied to the LNA 220, which, depending on the implementation, can be a current-mode LNA or a voltage-mode LNA. Although in Figure 2A In this embodiment, it is shown as a single-ended LNA, but other implementations can use a differential LNA to differentially process the RF signal. After being amplified in LNA 220, the RF signal is provided to mixer 225, which down-converts the RF signal to a lower frequency signal, such as an IF signal. Although in Figure 2A In this embodiment, a single-balanced passive mixer is shown; however, other implementations with a differential LNA can employ a double-balanced passive mixer to handle the differential output from the LNA. From there, the IF signal is provided to the PGA, which... Figure 2A In the embodiment, it is implemented as a TIA (formed by amplifier 230 and feedback filter, the feedback filter being composed of capacitor C). TIA and resistor R TIAForming (e.g., a first-order filtering function). The TIA 230 operates to convert the mixer IF current into a voltage signal. In other implementations, the PGA can be implemented as a voltage-mode PGA.

[0044] It should be noted that LNA 220, mixer 225, and TIA 230 constitute a second gain control region 221 of receiver 200. While embodiments are not limited to this, in one particular embodiment, the second gain control region 221 may have a controllable gain ranging from 0 dB to 33 dB (e.g., with a nominal step size of 2 dB). In one or more embodiments, for operation in high-performance mode, components of the second gain control region 221 may be configured for high performance and therefore higher power consumption. For example, in one implementation, the second gain control region 221 may consume approximately 8 mA of current during high-performance operation.

[0045] Still referencing Figure 2A The output of TIA 230 is provided to switching circuit 235. Although shown in high definition in Figure 2, it should be understood that switching circuit 235 can be implemented using multiple MOSFETs or other switches, which can be controlled to pass the IF signal output from TIA 230 to LPF 245. Figure 2A In this embodiment, a dual second-order filter is used. In other implementations, such switching circuit modules can be avoided by presenting the inactive path as a high impedance when turned off.

[0046] exist Figure 2A The image shows only this single path with LPF 245 coupled to switch circuit 235; to understand this, see the following regarding... Figure 3 Furthermore, at least one additional signal processing path is also coupled to the switching circuit 235 for use in low-power mode. To control the switching of the switching circuit module 235, a controller 270 exists, which is described in further detail below.

[0047] Although for convenience Figure 2A The LPF 245 is not shown in the illustration, but it may include a PGA for controlling the gain of the dual second-order filter. In the illustrated embodiment, the LPF 245 constitutes a third gain control region 241. While embodiments are not limited to this, in one particular embodiment, the third gain control region 241 may have a controllable gain between -10 dB and 20 dB (e.g., with a step size of 2 dB). Note that in Figure 2A In its implementation, it can be achieved using an RC component (i.e., resistor R). AAF and capacitor C AAFThis is used to perform additional anti-aliasing filtering. In one or more embodiments, for operation in high-performance mode, components of the third gain control region 241 may be configured for high performance and therefore higher power consumption. For example, in one implementation, the third gain control region 241 may consume approximately 4.5 mA of current during high-performance operation.

[0048] Still referencing Figure 2A The filtered IF signal output from the LPF 245 is provided to the ADC 250, which can be configured to digitize signals from high-performance wireless protocols such as Wi-Fi signals. In one implementation, for operation in high-performance mode, the ADC 250 can be configured for wideband operation, for example, with a bandwidth of 10 / 20 / 40 MHz. In this implementation, the ADC 250 may consume approximately 4 mA of current during high-performance operation.

[0049] The digitized output (WiFi_ADC_Out) of ADC 250 is provided to DSP 260, which includes a Wi-Fi demodulator for demodulating digital signals. In an embodiment, DSP 260 may also analyze the channel-filtered output to determine Received Signal Strength Indication (RSSI) information, which may be used in certain situations to perform fine-tuning of one or more gain components in the gain components.

[0050] Still referencing Figure 2A The attenuated RF signal is further provided to a first peak detector 215, which operates as a wideband detector to compare the power of the RF signal output from the attenuator circuit module with a first threshold. The first peak detector 215 is operable to sense the input signal at RF and provide an estimate of the undesired blocking signal that deviates from the desired signal. For example, the deviation might be 400MHz, and the blocking signal might be 80MHz wide. Therefore, the first peak detector 215 primarily helps improve out-of-band blocking performance and coexistence. When the RF signal level exceeds this threshold, the peak detector 215 outputs an activity detection signal RFPKD to the controller 270, which can perform gain control based at least in part on this information.

[0051] Figure 2AA digital peak detector 255 coupled to the output of ADC 250 is also shown. Although shown as separate components, it should be understood that in some embodiments, ADC 250 may perform peak detection as part of digitization, essentially making this peak detection "free" (e.g., when ADC 250 is implemented as a SAR ADC). This digital peak detector can be used to detect saturation levels because it includes blocking signal information (since it is located before the channel selection filter in DSP 260). Digital peak detector 255 operates to compare this digital output with another threshold. As discussed above, when the digital signal level exceeds this threshold, peak detector 255 outputs an activity detection signal DIGPKD to controller 270.

[0052] Through the example gain controllability described above for the first, second, and third gain control regions, the receiver can have a total controllable gain (Gtotal) of 87 dB, ranging from -25 dB to 62 dB. More specifically, each of the individual controllable gain control regions can have maximum gain settings of 9 dB, 33 dB, and 20 dB, respectively (corresponding to max(G1,G2,G3)). Also note that... Figure 2A This discussion enumerates the independent gain control regions as "first," "second," and "third" gain control regions. It should be understood that this enumeration is merely for convenience and discussion purposes, and these different regions can be enumerated in different ways.

[0053] In some embodiments, controller 270 may be implemented as a dedicated microcontroller or other programmable hardware control circuitry, such as a general-purpose processor or other programmable logic. In other cases, controller 270 may be implemented using other hardware circuitry modules, firmware, software, and / or combinations thereof to determine the operating mode of receiver 200.

[0054] like Figure 2A As shown, controller 270 (e.g., from a processor) receives mode information that identifies the operating mode of receiver 200, i.e., a given active communication protocol. Based at least in part on the mode information, controller 270 is configured to control switching circuit module 235 such that the output of TIA 230 is routed to LNA 245 when a high-performance mode (e.g., Wi-Fi mode) is active. Alternatively, controller 270 disables the low-power path, which presents as a high impedance such that the TIA output is routed to LNA 245. In addition to controlling switching circuit module 235 via the path selection signal shown, controller 270 can also appropriately configure the various components discussed above for high-performance operation by setting appropriate bandwidth, power levels, etc.

[0055] The controller 270 is also configured to control the gain settings of various gain components within the receiver 200 based on the detection outputs from one or more of the peak detectors 215 and 255. Furthermore, it should be understood that the controller 270 can perform this gain control efficiently within a small time window (e.g., entirely within the preamble portion of the data communication) without losing the payload data of the communication.

[0056] As further shown, controller 270 includes storage device 275, which in embodiments may be implemented as a non-volatile storage device or other non-transitory storage medium. Non-volatile storage device 275 may store code or other instructions that, when executed, cause controller 275 to perform the configuration operations described herein, and to further perform gain control, for example, using gain control information stored in one or more tables present in non-volatile storage device 275.

[0057] In some embodiments, it is further possible to configure a unified receiver for lower power operation when in high-performance mode. For example, for certain types of Wi-Fi communication (such as for beacon operation), it is possible to operate the receiver at a lower power level. Now refer to Figure 2B The diagram shows a block diagram of a receiver according to another embodiment.

[0058] Generally, receiver 200' is configured to... Figure 2A The receiver 200 is the same, and therefore the above discussion applies. However, for the purpose of lower power operation in high-performance mode, a controllable RC component may be present to provide filtering for the TIA 230. Therefore, in Figure 2B In the diagram, these RC components are shown as programmable capacitors and resistors, respectively.

[0059] Still Figure 2B In this embodiment, controller 270 may be appropriately configured with one or more components to reduce power consumption. For example, the second gain control region 221 may be controlled to operate at a lower power consumption (e.g., approximately 6.5 mA). Similarly, the LPF 245 of the third gain control region 241 may operate at a lower power consumption (e.g., approximately 2.5 mA). Finally, ADC 250 may also be configured to operate at a lower power consumption level (e.g., approximately 3 mA). With this power controllability, receiver 200' may operate with approximately 25% lower current consumption than receiver 200, because in this low-power mode, various components can operate with degraded but permissible performance.

[0060] The unified receiver architecture according to the embodiments can also be configured to operate in a low-power mode, such as for purposes such as Bluetooth communication. Reference now is made to... Figure 3This illustrates a block diagram of a receiver according to another embodiment. More specifically, receiver 300 is a uniform receiver configured for operation in a low-power mode. Generally, receiver 300 may include many of the same components as receiver 200, and therefore (regarding the designation '300' series, not...) Figure 2A The '200' series does not specifically discuss such components.

[0061] However, it should be noted that, Figure 3 In this embodiment, receiver 300 is configured to provide a second signal processing path coupled to the output of switching circuit module 340. As shown, this path includes a low-power wireless (LPW) ADC 350, which in this embodiment may be implemented as a delta-sigma ADC. Unlike the wideband-operating ADC 250, ADC 350 can be configured for narrowband operation (e.g., 2MHz), thus saving current while providing a higher dynamic range. The resulting digitized output (LPWADC_OUT) is provided to LPW demodulator 360, which in this embodiment may be implemented in a DSP that also includes a Wi-Fi demodulator 260.

[0062] Generally speaking, the remaining part of the signal processing path of receiver 300 is related to... Figure 2A The receiver 200 is identical. However, it should be noted that in the low-power configuration, instead of a digital peak detector, the IF peak detector 335 provides power information to the controller 370. The peak detector 335 operates as a wideband detector to compare this IF signal power with a second threshold (Pth2). The peak detector 235 operates to estimate the 80MHz channel along with filtering from the TIA 330. Located at the output of the TIA 330, the peak detector 335 provides an indication of clearance limits and can sense the saturation of adjacent channel interference (ACI) and alternative ACI (AACI). As discussed above, when the IF signal level exceeds this threshold, the peak detector 335 outputs an activity detection signal IFPKD to the controller 270.

[0063] In various implementations, such as compared to receiver 200, at least some components of receiver 300 can operate at significantly reduced power consumption levels. For example, the second gain control region 321 can consume approximately 4 mA, or approximately less than half the power consumption in receiver 200. It should also be noted that receiver 300 has no LPF, thus saving power. Figure 2AThe power consumption of the third gain control region 241 is reduced. Furthermore, using a narrowband ADC (e.g., 2MHz bandwidth instead of 20MHz bandwidth), approximately 0.5mA of current consumption occurs with ADC 350. As a result, the overall power consumption level of receiver 300 is approximately 70% lower than that of receiver 200.

[0064] In at least one implementation, the desired increase in attenuation range to accommodate the limited programmability of the TIA 330 can be achieved via capacitor C2 present in the first gain control region 311. However, for the purpose of gain programmability, a controllable RC component can be present to maintain the same narrow bandwidth in the TIA 330. Therefore, in Figure 3 In the diagram, these RC components are shown as programmable capacitors and resistors, respectively. Additionally, it should be noted that the components of the first signal processing path used in high-performance mode (i.e., LPF 245 and ADC 250) can be disabled during low-power mode to avoid their power consumption.

[0065] Now for reference Figure 4 A flowchart illustrating a method according to an embodiment is shown. More specifically as follows: Figure 4 As shown, method 400 is a method for dynamically configuring a unified receiver architecture for operation in a selected mode among multiple modes. While these different modes may differ in different implementations, for the purposes of discussion, it is assumed that at least a high-performance mode and a low-power mode exist. Method 400 can be executed by a controller, which can be implemented on a single integrated circuit having receiver circuitry modules. Therefore, method 400 can be executed by this controller alone and / or in conjunction with firmware and / or software.

[0066] Method 400 begins at block 410, where mode information is received in the controller. This mode information can be received from the host processor and includes an indication of a given wireless protocol to be activated. In some cases, this mode information may take the form of time-slicing scheduling, where different time windows are allocated to different wireless protocols, for example, a given periodic interval for each of multiple protocols. At block 415, the controller may determine the active protocol based at least in part on this mode information. Based on this determination, it is determined at diamond block 420 whether a high-performance mode is active. If so, control proceeds to block 430, where the controller may cause the switching circuit module (if present) to direct the IF signal output from the PGA to a first path of the receiver with the wideband digitizer. For example, return to reference. Figure 1 This broadband digitizer is the ADC 150, which is implemented as a SAR ADC.

[0067] Still referencing Figure 4Next, in diamond box 435, it is determined whether the high-power mode is active in this high-performance mode. Note that this high-power mode can be used for Wi-Fi data communication in one example. In such cases, control moves to box 440, where one or more components of the receiver are configured for higher-power operation. For example, one or more of the dual second-order filters and the ADC can be configured for higher-power operation. Conversely, if it is determined that no high-power mode is specified, for example, in the case where Wi-Fi beacon operation is to occur, control moves to box 445, where one or more components can be configured for lower-power operation. Continuing with the same example, the dual second-order filters and the ADC can be configured for lower-power operation.

[0068] In either case, the receiver is thus appropriately configured for a given operating mode, and accordingly, control is transferred to box 480 for processing the input RF signal in the receiver.

[0069] Still referencing Figure 4 If no high-performance mode is specified, control transitions from diamond-shaped box 420 to box 450, where the controller causes the switching circuit module (if present) to direct the IF signal output from the PGA to a second path of the receiver with a narrowband digitizer. For example, refer back to [reference]. Figure 1 This narrowband digitizer is an ADC 140, implemented as a delta-sigma ADC. Subsequently, in block 460, one or more components of the receiver are configured for low-power operation. For example, the dual second-order filters and the ADC can be disabled, and other components such as an LNA, mixer, and / or TIA can be configured for lower-power operation. With this appropriate receiver configuration for lower-power operation, control moves to block 480 for processing the input RF signal.

[0070] As further shown, it can be determined in diamond box 470 whether to initiate a mode change. Such a mode change may occur in response to the termination of a given time slice in time-slice operation or in response to the reception of updated mode information. As shown, control returns to box 415, where operations can be performed as discussed above to reconfigure the unified receiver architecture for the selected operating mode. It should be understood that, although in Figure 4 The embodiments are shown in this high-level manner, but many variations and alternatives are possible.

[0071] Now for reference Figure 5 This diagram shows a block diagram of a representative integrated circuit 500 including a power control circuit module as described herein. Figure 5In the embodiments shown, integrated circuit 500 may be, for example, a multi-mode wireless transceiver operable according to one or more wireless protocols, or other devices that can be used in various use cases. In one or more embodiments, Figure 5 The circuit module of the integrated circuit 500 shown can be implemented on a single semiconductor die, or on separate dies with other IP blocks required for wireless communication, MCU computing, external flash memory, and / or to perform various functions.

[0072] Integrated circuit 500 may be included in a range of devices, but for the purposes of discussion, it may be incorporated into an IoT device. In the illustrated embodiment, integrated circuit 500 includes a memory system 510, which may include volatile storage devices such as RAM and non-volatile memory such as flash memory. Flash memory is a non-transitory storage medium that can store instructions and data. As described herein, these instructions include instruction sets that, when executed, cause control circuit modules to configure a unified receiver architecture for selected wireless protocols among a plurality of wireless protocols, for example, in a time-slicing manner, and to perform power control of various gain control elements, at least in part, based on peak detector output.

[0073] like Figure 5 As further shown, the memory system 510 may store a first code 5051 for performing receiver configuration control and a second code 5052 for performing power control as described herein. The integrated circuit 500 may also include a memory controller 590.

[0074] The memory system 510 is coupled via a bus 550 to one or more digital cores 520. The digital cores 520 may include one or more cores and / or microcontrollers that act as processing units of an integrated circuit, and the digital cores 520 may perform power control and configuration operations as described herein. The digital cores 520 may also be coupled to a clock generator 530, which may provide one or more phase-locked loops or other clock generator circuit modules to generate various clocks for use by the circuit modules of the IC.

[0075] As further shown, IC 500 further includes a power circuit module 540. Depending on the specific implementation, additional circuit modules may be present to provide various functionalities and interaction with external devices. Such circuit modules may include an interface circuit module 560, which provides a digital communication interface with additional circuit modules, such as another IC that may be coupled to IC 500 via link 595. IC 500 may also include a security circuit module 570 for implementing wireless security technologies.

[0076] In addition, such as Figure 5As shown, a transceiver circuit module 580 may be provided to transmit and receive wireless signals, for example, according to one or more of the following local or wide-area wireless communication schemes: Matter, Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. It should be understood that although this high-level view is used, many variations and alternatives are possible.

[0077] As described above, the IC described herein can be implemented in a variety of different devices. Now refer to... Figure 6 This illustrates a high-level graph of a network according to an embodiment. Figure 6 As shown, network 600 includes various devices, including IoT and other wireless devices, which may include a unified receiver architecture as described herein.

[0078] exist Figure 6 In embodiments, the wireless mesh network 605 exists, for example, having multiple wireless devices 610 0-n In the building. As shown, a wireless device 610 (which may be an IoT or other wireless device) is coupled to an access point 630, which in turn communicates with a remote service provider 660 via a wide area network 650 (e.g., the Internet). To understand, although in Figure 6 The embodiments are shown in this high-level manner, but many variations and alternatives are possible.

[0079] The embodiments provide a current-optimized receiver architecture that can be used in both high-performance and low-performance modes. In this way, a single, unified receiver architecture is provided that does not compromise performance in each mode, thereby breaking down trade-offs between conflicting design paradigms.

[0080] While this disclosure has described a limited number of implementations, many modifications and variations will be apparent to those skilled in the art upon which this disclosure is made. The appended claims are intended to cover all such modifications and variations.

Claims

1. A receiver, comprising: A low-noise amplifier (LNA) is used to receive and amplify radio frequency (RF) signals; A mixer is used to downconvert the RF signal to an intermediate frequency (IF) signal; A programmable gain amplifier (PGA) coupled to the mixer is used to amplify the IF signal; A first digitizer coupled to the PGA is used to digitize the IF signal into a first digitized signal when the RF signal belongs to a first wireless protocol; A second digitizer coupled to the PGA is used to digitize the IF signal into a second digitized signal when the RF signal belongs to a second wireless protocol; as well as A controller is configured to direct the IF signal to the first digitizer via a first path when the first wireless protocol is active, and to direct the IF signal to the second digitizer via a second path when the second wireless protocol is active.

2. The receiver as claimed in claim 1, further comprising a switching circuit module, wherein, The controller is used to control the switching circuit module to: When the first wireless protocol is active, the IF signal is directed to the first digitizer via the first path; as well as When the second wireless protocol is active, the IF signal is directed to the second digitizer via the second path.

3. The receiver as claimed in claim 1, wherein, The first path includes a filter coupled between the PGA and the first digitizer.

4. The receiver as claimed in claim 3, wherein, The second path includes a direct path between the PGA and the second digitizer.

5. The receiver as claimed in claim 1, wherein: The first digitizer has a first power consumption level; and The second digitizer has a second power consumption level that is lower than the first power consumption level.

6. The receiver as claimed in claim 5, wherein: The first digitizer includes a wideband analog-to-digital converter (ADC); and The second digitizer includes a narrowband ADC.

7. The receiver as claimed in claim 5, wherein, The controller is used to disable at least the first digitizer when the second wireless protocol is active.

8. The receiver as claimed in claim 1, wherein, The second digitizer is further used to digitize sensor information when the first wireless protocol is active.

9. The receiver of claim 1, further comprising: A first demodulator coupled to the first digitizer, the first demodulator being used to demodulate the first digitized signal according to a first demodulation scheme; as well as A second demodulator coupled to the second digitizer, the second demodulator being used to demodulate the second digitized signal according to a second demodulation scheme.

10. The receiver of claim 1, further comprising: A first power detector coupled to the input of the LNA, the first power detector being used to output a first detection signal in response to the RF signal exceeding a first threshold; as well as A second power detector coupled to the output of the first digitizer, the second power detector being configured to output a second detection signal in response to the first digitized signal exceeding a second threshold, wherein the controller is configured to control at least one gain component of the receiver based at least in part on the first detection signal or the second detection signal.

11. The receiver of claim 10, further comprising a third power detector coupled to the output of the PGA, wherein, The third power detector is active when the second wireless protocol is active.

12. A method comprising: When the first wireless protocol is active, the unified receiver is configured via the controller to provide a down-converted signal to a first path of the unified receiver, the first path including a filter for filtering the down-converted signal and a first digitizer for digitizing the filtered down-converted signal into a first digital signal. as well as When the second wireless protocol is active, the controller configures the unified receiver to provide the down-converted signal to the unified receiver via a second path, the second path including a second digitizer for digitizing the down-converted signal into a second digital signal.

13. The method of claim 12, further comprising: The unified receiver is configured in response to mode information used to indicate whether the first wireless protocol or the second wireless protocol is active.

14. The method of claim 13, further comprising: In response to updated mode information indicating the activity of the second wireless protocol, the unified receiver is dynamically reconfigured from providing the down-converted signal to the first path to providing the down-converted signal to the second path.

15. The method of claim 12, wherein, The configuration of the unified receiver includes: a switching circuit module that controls the coupling to the first path and the second path, the switching circuit module being used to receive the down-converted signal from the common path of the unified receiver, the common path being used to receive radio frequency signals and down-convert the radio frequency signals into the down-converted signal, the common path being active when the first wireless protocol is active and when the second wireless protocol is active.

16. The method of claim 12, wherein, Configuring the unified receiver includes: When the first mode of the first wireless protocol is active, the first digitizer is configured to have a first power consumption level; and When the second mode of the first wireless protocol is active, the first digitizer is configured to have a second power consumption level, which is lower than the first power consumption level.

17. The method of claim 12, further comprising: The down-converted signal is processed in the first path at a first power consumption level; as well as The down-converted signal is processed in the second path at a second power consumption level that is lower than the first power consumption level.

18. A wireless device, comprising: Antennas are used to transmit radio frequency (RF) signals and to receive RF signals. as well as An integrated circuit (IC) coupled to the antenna, the IC comprising: A low-noise amplifier (LNA) is used to receive and amplify the received RF signal; A mixer is used to downconvert the received RF signal into a second frequency signal; An amplifier coupled to the mixer is used to amplify the second frequency signal; The first path includes a filter for filtering the second frequency signal and a first digitizer coupled to the filter to digitize the filtered second frequency signal into a first digitized signal; The second path includes a second digitizer for digitizing the second frequency signal into a second digitized signal; A first demodulator coupled to the first path is used to demodulate the first digitized signal; A second demodulator coupled to the second path is used to demodulate the second digitized signal; and A controller is configured to direct the second frequency signal to the first path when a first wireless protocol is active, and to direct the second frequency signal to the second path when a second wireless protocol is active.

19. The wireless device of claim 18, wherein, The controller is used to disable the filter and the first digitizer when the second wireless protocol is active.

20. The wireless device of claim 18, wherein, The second digitizer is used to digitize sensor information when the first wireless protocol is active, and to digitize the second frequency signal into the second digitized signal when the second wireless protocol is active. The second digitizer operates at a lower power consumption level than the first digitizer.

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