FPGA-based method, device and equipment for digital signal processing of a repeater, and a storage medium

Abstract

The application discloses a kind of based on FPGA's repeater digital signal processing method, device, equipment and storage medium, the method comprises: based on the highest effective bit distribution of current signal to be processed of preset statistical window is carried out statistics, obtains high bit interval distribution probability and compares with preset margin threshold, obtains dynamic margin evaluation result;According to dynamic margin evaluation result determines current gain compensation strategy, using preset gain control algorithm according to current gain compensation strategy is carried out gain compensation to current signal to be processed, obtains compensated signal;To compensated signal executes bit cutting operation, obtains after processing signal and bit cutting quantization error, bit cutting quantization error is used to be superimposed to the output signal of processing module in next sampling point after feedback filtering to obtain next signal to be processed.The application realizes the adaptive power calibration and noise shaping of each level node in signal processing link under the condition of not demodulation, effectively maintains the signal-to-noise ratio of repeater output signal.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a digital signal processing method, apparatus, device and storage medium for a repeater based on FPGA. Background Technology

[0002] Digital repeaters are widely used in coverage enhancement scenarios of wireless communication systems. Their basic operation involves down-converting the received radio frequency signal, digitally processing it, and then up-converting and amplifying it before forwarding. Unlike communication terminals, digital repeaters do not demodulate the signal; instead, they use non-demodulated digital signal processing to complete the relay amplification. In engineering implementation, to meet the processing requirements of multi-standard and multi-bandwidth signals, repeaters typically use a Field-Programmable Gate Array (FPGA) to construct a multi-stage digital signal processing link, including decimation filtering, digital down-conversion, sub-band filtering, digital up-conversion, and interpolation modules. Due to the limitations of FPGA resources and power consumption, these processing modules are generally implemented using fixed-point arithmetic. In this multi-stage link, after each processing module completes its operation, the expanded bit width needs to be truncated to match the input bit width requirements of subsequent modules. Simultaneously, sampling rate conversion operations such as decimation and interpolation cause changes in signal power, requiring gain compensation at the corresponding nodes to restore the signal power level. The aforementioned truncation and gain compensation are necessary operations after each stage of processing, namely the power calibration process of the output signal of each processing module. The implementation method directly affects the signal-to-noise ratio maintenance capability of the signal during transmission in the link.

[0003] In existing FPGA digital processing solutions for repeaters, the post-processing steps of each processing module in the FPGA link typically involve decimating or interpolating the signal to achieve fixed gain compensation, while truncation operations simply discard the lower bits. However, in peak-to-average power ratio (PAPR) signal scenarios, this fixed compensation method easily leads to signal overflow at intermediate nodes, resulting in clipping distortion and additional quantization noise. Furthermore, the quantization error generated by direct truncation is correlated in multi-stage cascaded processing. This correlated error accumulates in the signal passband in subsequent stages, causing the noise floor to gradually rise. Consequently, the signal-to-noise ratio (SNR) of the final output signal after the FPGA link has passed through multiple processing modules (and corresponding post-processing steps) is significantly degraded. Therefore, a SNR preservation method is needed that can adaptively control the gain and suppress the accumulation of quantization noise during the post-processing steps of each processing module in a multi-stage FPGA link. Summary of the Invention

[0004] The main objective of this application is to provide a digital signal processing method, apparatus, device, and storage medium for repeaters based on FPGA, aiming to solve the technical problem of signal-to-noise ratio degradation caused by existing FPGA digital processing methods for repeaters.

[0005] To achieve the above objectives, this application proposes a digital signal processing method for repeaters based on FPGA, the method comprising: Based on a preset statistical window, the distribution of the most significant bit of the current signal to be processed is statistically analyzed to obtain the probability of the high bit interval distribution. The high-level interval distribution probability is compared with the preset margin threshold to obtain the dynamic margin evaluation result; Based on the dynamic margin assessment results, a gain compensation decision is determined according to a preset gain control algorithm, and the current signal to be processed is gain compensated according to the gain compensation decision to obtain the compensated signal. A truncation operation is performed on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module in the next sampling period after feedback filtering to obtain the next signal to be processed.

[0006] In one embodiment, the step of statistically analyzing the distribution of the most significant bit of the current signal to be processed based on a preset statistical window to obtain the probability of the high-bit interval distribution includes: The position of the most significant bit of each sample value corresponding to the current signal to be processed is detected within the preset statistical window, wherein the preset statistical window includes several sample points of the current signal to be processed; The number of sampling points whose most significant bit position is within a preset high-bit interval is counted. The preset high-bit interval has an upper limit parameter and a lower limit parameter. The upper limit parameter is determined based on the difference between the preset maximum bit width and the reserved peak margin. The lower limit parameter is determined based on the difference between the preset maximum bit width and the maximum allowable margin. The probability of the high-order interval distribution is determined based on the ratio of the number of sampling points to the total number of sampling points in the preset statistical window.

[0007] In one embodiment, the step of comparing the high-order interval distribution probability with a preset margin threshold to obtain a dynamic margin evaluation result includes: Detect whether there is a saturation overflow event within the preset statistical window, and compare the high-level interval distribution probability with a preset margin threshold, wherein the preset margin threshold includes a preset low margin threshold and a preset high margin threshold; When the probability of the high-order interval distribution is lower than the preset low margin threshold, it is determined to be a state of excess margin. When the probability of the high-order interval distribution is higher than the preset high margin threshold or when the saturation overflow event occurs, it is determined to be a state of insufficient margin.

[0008] In one embodiment, the compensated signal has a target amplitude, and the step of determining the current gain compensation strategy based on the dynamic margin evaluation result includes: When the dynamic margin assessment result indicates an insufficient margin state, the current gain compensation strategy is determined to be a rapid attenuation strategy. When the dynamic margin assessment result indicates an excess margin state, the current gain compensation strategy is determined to be a slow ramp-up strategy. The fast attenuation strategy is a strategy that adjusts the current signal to be processed in a single step according to the shift amount and the multiplication coefficient to achieve the target amplitude; the slow ramp-up strategy is a strategy that adjusts the current signal to be processed in multiple steps according to the shift amount and the multiplication coefficient to achieve the target amplitude.

[0009] In one embodiment, the step of performing gain compensation on the current signal to be processed using a preset gain control algorithm according to the current gain compensation strategy to obtain a compensated signal includes: The target most significant bit position is determined based on the target amplitude, and the shift amount is determined based on the difference between the current signal most significant bit position and the target most significant bit position. Multiplication coefficients are selected from a pre-stored coefficient set, which covers the range from unity gain to a preset maximum fine-tuning gain. Each coefficient in the pre-stored coefficient set corresponds to a preset step gain value and is stored in a fixed-point format. Perform a shift operation on the current signal to be processed according to the shift amount to obtain a coarse adjustment signal; Perform a multiplication operation on the coarse adjustment signal according to the multiplication coefficients to obtain the compensated signal; The shift operation and the multiplication operation are performed in accordance with the current gain compensation strategy.

[0010] In one embodiment, after the step of performing a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error, the method includes: The truncation quantization error is filtered by a feedback filter with high-pass characteristics to obtain the filtered error, and the filtered error is stored in the error adjustment register. The filtered error is superimposed onto the output signal of the processing module at the next sampling point through the error adjustment register to obtain the next signal to be processed.

[0011] In one embodiment, the step of superimposing the filtered error onto the output signal of the processing module at the next sampling point through the error adjustment register to obtain the next signal to be processed includes: When the target amplitude corresponding to the compensated signal changes, the ratio of the target amplitude to the changed target amplitude is calculated. Multiply the filtered error value in the error adjustment register by the ratio to obtain the adjusted truncation error; The adjusted truncation error is superimposed on the output signal of the processing module at the next sampling point to obtain the next signal to be processed.

[0012] Furthermore, to achieve the above objectives, this application also proposes an FPGA-based digital signal processing device for repeaters, the device comprising: The probability statistics module is used to statistically analyze the distribution of the most significant bit of the current signal to be processed based on a preset statistical window, and obtain the probability of the high bit interval distribution. The dynamic margin assessment module is used to compare the high-level interval distribution probability with a preset margin threshold to obtain the dynamic margin assessment result. The gain compensation module is used to determine the gain compensation decision according to the dynamic margin evaluation result and the preset gain control algorithm, and to perform gain compensation on the current signal to be processed according to the gain compensation decision to obtain the compensated signal. The signal truncation module performs a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module in the next sampling period after feedback filtering to obtain the next signal to be processed.

[0013] Furthermore, to achieve the above objectives, this application also proposes an FPGA-based digital signal processing device for repeaters, the device comprising: a memory, a processor, and an FPGA-based digital signal processing program for repeaters stored in the memory and executable on the processor, the FPGA-based digital signal processing program for repeaters being configured to implement the steps of the FPGA-based digital signal processing method for repeaters as described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, storing an FPGA-based repeater digital signal processing program. When the FPGA-based repeater digital signal processing program is executed by a processor, it implements the steps of the FPGA-based repeater digital signal processing method described above.

[0015] This application discloses a digital signal processing method for a repeater based on an FPGA. The method includes: statistically analyzing the distribution of the most significant bit of the current signal to be processed based on a preset statistical window to obtain the probability of the high-bit interval distribution; comparing the probability of the high-bit interval distribution with a preset margin threshold to obtain a dynamic margin evaluation result; determining the current gain compensation strategy based on the dynamic margin evaluation result; using a preset gain control algorithm to perform gain compensation on the current signal to be processed according to the current gain compensation strategy to obtain a compensated signal; performing a truncation operation on the compensated signal to obtain a processed signal and a truncation quantization error, wherein the truncation quantization error is used to superimpose the output signal of the processing module at the next sampling point after feedback filtering to obtain the next signal to be processed.

[0016] Because this application can dynamically evaluate signal margin based on the statistical distribution of the most significant bit and adaptively determine gain compensation decisions based on the evaluation results, it avoids the peak-to-average power ratio (PAPR) signal overflow problem caused by fixed gain compensation based on decimation or interpolation multiples. Simultaneously, by superimposing the truncation quantization error after feedback filtering onto the output signal of the processing module at the next sampling point, the quantization noise spectrum is shifted out of band, suppressing the cumulative effect of quantization error within the signal passband in multi-stage cascaded processing. Therefore, this application achieves adaptive power calibration and noise shaping at each stage of the signal processing link without demodulation, effectively maintaining the signal-to-noise ratio (SNR) of the repeater output signal. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the first embodiment of the FPGA-based digital signal processing method for repeaters in this application. Figure 2 This is a flowchart illustrating the second embodiment of the FPGA-based digital signal processing method for repeaters in this application. Figure 3 This is a diagram representing the coefficient set of this application; Figure 4 This is a flowchart illustrating the third embodiment of the FPGA-based digital signal processing method for repeaters in this application. Figure 5 This is a schematic diagram of the entire process of the FPGA-based digital signal processing method for repeaters in this application; Figure 6 This is the state transition diagram for the adaptive gain control of this application; Figure 7 This is a schematic diagram of the module structure of the FPGA-based digital signal processing device for repeaters in this application; Figure 8 This is a schematic diagram of the structure of the FPGA-based digital signal processing device for repeaters in this application.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] This application provides an FPGA-based digital signal processing method for repeaters, referencing... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the FPGA-based digital signal processing method for repeaters according to this application. In this embodiment, the method includes steps S10 to S40: Step S10: Based on the preset statistical window, perform statistics on the distribution of the most significant bit of the current signal to be processed to obtain the probability of the high bit interval distribution.

[0024] It should be noted that the method of this embodiment can be applied to the output node of the processing module of the FPGA multi-stage digital signal processing link (hereinafter referred to as "FPGA link") in a digital repeater. The functional module may include at least one of a digital down-conversion module, a decimation filter module, a sub-band filter module, an interpolation filter module, and a digital up-conversion module. The execution entity of the method of this embodiment can be an adaptive power calibration unit configured in the FPGA link. This calibration unit can be deployed in hardware logic at the output of each functional module. The following description uses this calibration unit as an example to illustrate this embodiment.

[0025] It should be understood that in the FPGA processing chain, after each functional module completes its internal calculations, the bit width of its output signal has usually expanded to exceed the input bit width requirements of subsequent modules. Furthermore, operations such as decimation or interpolation can cause the signal power to deviate from the ideal level. Therefore, power calibration and truncation processing of the signal are required at the output node of each functional module.

[0026] Understandably, the signal to be processed can be a digital signal output by a functional module after internal processing. The calibration unit can statistically analyze the amplitude distribution of the signal within a time window and determine whether the current signal power is in the ideal high-level range by observing the position distribution of the most significant bit (MSB).

[0027] The length of the preset statistical window can be configured according to the system sampling rate, for example, set to 1024 sampling points. Within this preset statistical window, the calibration unit detects the MSB position of each sampled value and calculates the percentage of sampling points where the MSB falls within a preset high-order interval. This percentage is then determined as the high-order interval distribution probability. This high-order interval distribution probability reflects the relative magnitude of the overall amplitude level of the current signal to be processed within the statistical window, facilitating subsequent dynamic margin judgment of the current signal to be processed.

[0028] Furthermore, to specifically explain how to determine the high-order interval and statistically obtain the distribution probability of the high-order interval, step S10 also includes: steps S101~S103: Step S101: Detect the position of the most significant bit of each sample value corresponding to the current signal to be processed within the preset statistical window, wherein the preset statistical window includes several sample points of the current signal to be processed.

[0029] It should be noted that the signal to be processed is a digital signal, which can be represented as a fixed-point number in binary representation. The MSB is the non-zero bit with the highest weight in the exponent value, that is, the highest bit position of 1 in binary representation.

[0030] Specifically, the calibration unit can detect the amplitude of the current signal to be processed and determine the position of its MSB. Taking the detection process of a sampling point of the current signal to be processed within a preset statistical window as an example, for example, for a signal to be processed with a sampling value of 1000, its binary representation is 11 1110 1000, then its MSB is bit 9.

[0031] The calibration unit can repeat this detection operation for each sampling point within the window to obtain the MSB position sequence of each sampling point.

[0032] Step S102: Count the number of sampling points whose most significant bit position is within a preset high bit interval. The preset high bit interval has an upper limit parameter and a lower limit parameter. The upper limit parameter is determined based on the difference between the preset maximum bit width and the reserved peak margin. The lower limit parameter is determined based on the difference between the preset maximum bit width and the maximum allowable margin.

[0033] It should be noted that the preset high-level range can be dynamically defined according to the safety margin requirements of the system design. This preset high-level range includes two boundary parameters: an upper limit parameter to prevent signal overflow clipping, and a lower limit parameter to prevent the signal from being too small, which would cause significant quantization noise.

[0034] For example, let's take a signed number where each fixed point in the signal to be processed is represented as an 18-bit (bit0~bit18) number. The highest bit, bit18, is used as the sign bit, so the maximum bit width of the signal corresponds to 2^17.

[0035] If the design reserves a safety margin of 2 bits for the peak value, i.e., 2^12, then the amplitude corresponding to the upper limit parameter is 2^(17-2), i.e., 2^15=32768, and the corresponding MSB is bit 15.

[0036] If the design signal occupies at least 5 effective bit widths, i.e., the maximum allowable margin is 5 bits, then the amplitude corresponding to the lower limit parameter is 2^(17-5), i.e., 2^12=4096, and the corresponding MSB is bit12.

[0037] Therefore, the preset amplitude range of the high-level interval is 2^12. abs(x) < 2^15, meaning the preset safe range is [4096~32767], and the corresponding MSB is located in the range [bit12, bit14]. Signals falling into this range can ensure a high effective bit width (not less than 12 bits) while retaining a peak margin of about 12dB to avoid peak-to-average power ratio (PAPR) signal clipping.

[0038] In a specific implementation, the calibration unit can compare the MSB of each detected sampling point with the aforementioned preset high-order interval and count the number of sampling points within the preset high-order interval.

[0039] Step S103: Determine the high-order interval distribution probability based on the ratio of the number of sampling points to the total number of sampling points in the preset statistical window.

[0040] It should be noted that the calibration unit can divide the number of sampling points in the preset high range obtained from the aforementioned statistics by the total number of sampling points in the preset statistical window (e.g., 1024) to obtain a probability value between 0 and 1.

[0041] For example, if the signal to be processed has 1024 sampling points within a preset statistical window, and the MSB of 800 of these sampling points falls into a preset high-order interval, then the probability distribution of the high-order interval is 800 / 1024, approximately 0.78. This probability value quantifies the proportion of time the signal to be processed is within the ideal amplitude range within the statistical window, providing a quantitative basis for subsequent dynamic margin assessment.

[0042] Step S20: Compare the high-level interval distribution probability with the preset margin threshold to obtain the dynamic margin evaluation result.

[0043] It should be noted that, in order to determine whether the signal to be processed is too large (insufficient margin) or too small (excessive margin) based on the calculated high-order interval distribution probability, this high-order interval distribution probability can be compared with multiple preset thresholds, and combined with whether an overflow event occurs within the window, the probability value is transformed into a state judgment result with clear physical meaning, namely, a dynamic margin assessment result.

[0044] The preset margin threshold can include a preset low margin threshold and a preset high margin threshold. Taking an 18-bit system as an example, the low margin threshold can be set to 5%, and the high margin threshold can be set to 30%. In addition, the calibration unit can also detect whether there is a saturation overflow event within the current statistical window, that is, whether the amplitude of any sampling point exceeds the maximum range that the fixed-point number can represent.

[0045] Furthermore, to specifically explain the judgment logic of different margin states (insufficient margin, excessive margin) included in the dynamic margin assessment results, step S20 also includes: steps S201~S203: Step S201: Detect whether there is a saturation overflow event within the preset statistical window, and compare the high-order interval distribution probability with the preset margin threshold, wherein the preset margin threshold includes a preset low margin threshold and a preset high margin threshold.

[0046] It should be noted that the calibration unit can perform two checks: overflow detection, which scans all sampling points in the statistical window to determine whether the amplitude of any sampling point reaches or exceeds the maximum representation range of the fixed-point number; and probability comparison detection, which compares the probability distribution of the high-bit interval with the low margin threshold (e.g., 5%) and the high margin threshold (e.g., 30%) respectively.

[0047] Step S202: When the distribution probability of the high-order interval is lower than the preset low margin threshold, it is determined to be a state of excess margin.

[0048] It should be noted that an excess margin indicates that the overall amplitude of the signal to be processed is too small. When the probability of the high-order interval distribution is lower than the low margin threshold (e.g., 5%), it means that the highest significant bit of most sampling points within the window has not reached the preset high-order interval, that is, the amplitude of the signal is generally too low.

[0049] At this point, the effective bit width of the signal to be processed is insufficient, which may result in a degraded signal-to-noise ratio due to an excessively large quantization step size relative to the signal amplitude and a high proportion of quantization noise. Therefore, the calibration unit can determine that the current node is in a state of excessive margin, and subsequent gain needs to be increased to improve the signal amplitude.

[0050] Step S203: When the distribution probability of the high-level interval is higher than the preset high margin threshold or when the saturation overflow event exists, it is determined to be a state of insufficient margin.

[0051] It should be noted that the insufficient margin state indicates that the overall amplitude of the signal to be processed is too large or has already undergone clipping. This insufficient margin state is triggered by two conditions: Condition 1: If the probability of the high-level interval distribution is higher than the high margin threshold (e.g., 30%), it indicates that within the statistical window, the vast majority of sampling points are already in the preset high-level interval or even close to the full range. At this time, there is little room for the signal to continue to increase, and the risk of overflow is high. Condition two: At least one saturation overflow event occurs within the window. Since saturation overflow directly corrupts the signal waveform, causing irreversible clipping distortion, and the harmonics generated by clipping interfere with adjacent frequency bands, overflow events have the highest priority. In practical applications, the calibration unit can immediately trigger insufficient margin determination upon detecting a single saturation overflow event, without waiting for the probability threshold condition.

[0052] It should also be noted that if the probability distribution of the high-order interval is between the low margin threshold and the high margin threshold, and there is no overflow event within the window, it can be determined as a normal state. At this time, the amplitude of the current signal to be processed is within the ideal range, and there is no need to adjust the gain.

[0053] In practical implementation, through the above judgment, the calibration unit can obtain the dynamic margin assessment result of the current signal to be processed within the preset statistical window. The dynamic margin assessment result can be one of three states: "excess margin", "normal", or "insufficient margin". In addition, the calibration unit can have a built-in state machine to maintain the dynamic margin assessment result corresponding to each window, thereby reflecting the degree and direction of deviation of the amplitude of the current signal to be processed from the fixed-point representation range.

[0054] Step S30: Determine the current gain compensation strategy based on the dynamic margin evaluation result, and use a preset gain control algorithm to perform gain compensation on the current signal to be processed according to the current gain compensation strategy to obtain the compensated signal.

[0055] It should be noted that the aforementioned dynamic margin assessment results include three states: "excess margin," "normal," or "insufficient margin." The calibration unit can first determine which gain compensation strategy should be adopted based on the above dynamic margin assessment results. Gain compensation strategies can be divided into: gain attenuation strategy and gain ramp-up strategy.

[0056] In addition, a hysteresis comparison mechanism can be introduced into this gain compensation strategy: the gain adjustment is triggered only when the amplitude of the current signal to be processed deviates from the preset threshold for multiple statistical windows, thereby preventing frequent gain jumps caused by instantaneous signal fluctuations.

[0057] Specifically, when the dynamic margin assessment result is insufficient within multiple statistical windows, the current gain compensation strategy can be determined to be a gain attenuation strategy; when the dynamic margin assessment result is excessive within multiple statistical windows, the current gain compensation strategy can be determined to be a ramp-up strategy; when the dynamic margin assessment result is normal within multiple windows, the current gain can be maintained, i.e., no gain compensation strategy is executed.

[0058] Furthermore, if a saturation overflow event occurs within any statistical window, the calibration unit can directly execute the aforementioned gain attenuation strategy triggered by insufficient margin without waiting for multiple statistical windows.

[0059] It should also be noted that, based on the preset gain control algorithm, specific gain compensation parameters can be calculated. These gain compensation parameters are expressed in the form of a combination of shift amount and multiplication coefficient.

[0060] In addition, during the FPGA link process, there are gain effects such as quantizing the original decimal filter coefficients to introduce additional gain, and the gain of the interpolation filter changing according to the interpolation factor. After calculating the specific gain compensation parameters based on the preset gain control algorithm, the gain deviation value caused by the above-mentioned gain effects can be additionally added.

[0061] It should be understood that, based on the aforementioned preset high-level range, a target compensation gain G can be set to represent the target amplitude of the supplemented signal. This target compensation gain G can satisfy the condition that G is approximately equal to 2 raised to the power of K multiplied by... That is, represented as G 2^K· .

[0062] The shift amount K achieves coarse gain adjustment, and the multiplication coefficient... To achieve fine-tuning of the gain.

[0063] In practical implementation, the calibration unit can calculate and determine K and based on the preset target amplitude. The specific values ​​are then used to obtain the specific gain compensation parameters. Following the aforementioned current gain compensation strategy, shift and multiplication operations are sequentially performed on the current signal to be processed: first, the signal is shifted left or right according to the shift amount K to achieve coarse adjustment; then, the multiplication coefficients are used to perform the multiplication operations. A multiplication operation is performed on the shifted signal to achieve fine-tuning, and finally the compensated signal is obtained.

[0064] Step S40: Perform a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module at the next sampling point after feedback filtering to obtain the next signal to be processed.

[0065] It should be noted that after the aforementioned gain compensation, the bit width of the compensated signal has been further expanded. For example, the processing module itself may have expanded the bit width from 18 bits to 36 bits, and after left shift and multiplication operations, the bit width is further increased. In order to match the input bit width requirements of subsequent processing modules (usually consistent with the current module's input bit width, such as 18 bits), the calibration unit needs to perform a truncation operation on the compensated signal.

[0066] The specific method of the truncation operation is as follows: the calibration unit retains the high-order part of the compensated signal (the value of the processing module at the current sampling point), and then outputs the high-order part as the processed signal (the effective value of the processing module at the current sampling point) to the next-level processing module.

[0067] Meanwhile, the discarded low-order bits are defined as the truncation quantization error of the compensated signal. This truncation quantization error represents the amount of information lost in this truncation operation.

[0068] Furthermore, the calibration unit can also process the truncation quantization error through a feedback filter and then superimpose it onto the output signal of the processing module at the next sampling point. If this processing module is the module from which the current signal to be processed originates, then the truncation quantization error can be combined with the new signal to be processed, thereby changing the spectral characteristics of the error, shifting the quantization noise energy from the low-frequency band to the high-frequency band, and suppressing the cumulative effect of quantization noise in the signal passband.

[0069] In this way, the processed signal can be normally transmitted to the next level processing module to continue the subsequent digital signal processing flow, while the truncation quantization error affects the signal to be processed at the next sampling point through the feedback path, realizing the reuse of truncation loss information.

[0070] This embodiment dynamically assesses the signal margin status by statistically analyzing the distribution of the most significant bit and comparing high and low bit thresholds. It quantizes the signal status into three states: "excess margin," "normal," and "insufficient margin." Based on whether the margin is insufficient or excessive, it triggers a differential gain compensation strategy, avoiding the peak-to-average power ratio (PAPR) signal overflow problem caused by fixed gain compensation based on decimation or interpolation factors in traditional methods. Simultaneously, by feeding back the truncation quantization error to the output signal of the processing module at the next sampling point to obtain the next signal to be processed, the quantization noise spectrum is gradually shifted out of band, suppressing the cumulative effect of quantization error within the signal passband during multi-stage cascaded processing.

[0071] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 , Figure 2This is a flowchart illustrating the second embodiment of the FPGA-based digital signal processing method for repeaters in this application.

[0072] In this embodiment, to specifically illustrate how to determine the current gain compensation strategy and perform gain compensation, step S30 specifically includes: steps S301~S306: Step S301: When the dynamic margin assessment result indicates an insufficient margin state, the current gain compensation strategy is determined to be a rapid attenuation strategy.

[0073] Step S302: When the dynamic margin assessment result indicates an excess margin state, the current gain compensation strategy is determined to be a slow ramp-up strategy.

[0074] It should be understood that the aforementioned gain decay strategy and gain ramp-up strategy can be specifically defined as a fast decay strategy and a slow ramp-up strategy.

[0075] The fast attenuation strategy can be a strategy that adjusts the current signal to be processed in a single step based on the shift amount and multiplication coefficients to achieve the target amplitude. Under the fast attenuation strategy, the calibration unit can directly calculate the required shift amount and multiplication coefficients based on the difference between the MSB of the current signal to be processed at the current sampling point and the target MSB corresponding to the target amplitude, and complete the gain adjustment in one step.

[0076] Since this rapid decay strategy can be completed within a single statistical window, it can prioritize the elimination of overflow risk and prevent clipping distortion from causing irreversible damage to the signal.

[0077] The slow ramp-up strategy can be a strategy that adjusts the current signal to be processed in multiple stages according to the shift amount and multiplication coefficient to achieve the target amplitude. Under the slow ramp-up strategy, the calibration unit does not directly adjust the value of the current signal to be processed at the current sampling point to the target value. Instead, the adjustment process is decomposed into multiple stages. Each stage only adjusts a small step amount. Each time stage can correspond to one or more sampling points, so as the sampling points move forward step by step, the target amplitude is gradually approached.

[0078] Since broadband OFDM signals such as LTE / NR have a high peak-to-average power ratio, excessive gain abrupt changes at a single sampling point may cause bit errors during subsequent demodulation. Therefore, applying this slow ramp-up strategy can avoid the impact of gain abrupt changes on the synchronous tracking of subsequent demodulation equipment.

[0079] In its implementation, the calibration unit first determines the current gain compensation strategy based on the aforementioned dynamic margin assessment results: When the margin is deemed insufficient, it indicates that the current signal amplitude is too large or has overflowed, requiring a rapid reduction in gain to avoid clipping distortion; therefore, the current gain compensation strategy is determined to be a rapid attenuation strategy. When the margin is deemed excessive, it indicates that the current signal amplitude is too small and the effective bit width is insufficient, requiring an increase in gain to enhance the signal amplitude; therefore, the current gain compensation strategy is determined to be a slow ramp-up strategy. When the state is deemed normal, no gain adjustment is required, and the calibration unit maintains the current gain compensation parameters unchanged.

[0080] Step S303: Determine the position of the target most significant bit based on the target amplitude, and determine the shift amount based on the difference between the current signal most significant bit position and the target most significant bit position.

[0081] It should be noted that if the compensated signal has a target amplitude and a corresponding target MSB, then the target MSB can be set based on the median value of the aforementioned preset high-order interval.

[0082] For example, if the preset high-order interval is [4096~32767], the corresponding MSB is [bit12, bit14]. Then the median value is bit14.

[0083] It should be understood that the calibration unit first detects the MSB of the current signal to be processed, that is, it detects the amplitude of the current sampling point and determines its corresponding MSB. For example, if the amplitude of the current signal to be processed is 1000, its binary representation MSB is the 9th bit.

[0084] Next, the calibration unit calculates the difference between the target MSB position and the current signal MSB position. Taking the above value as an example, the target MSB position is bit 14, the current signal MSB position is bit 9, the difference is 5 bits, then the target shift is bit 5.

[0085] It should also be noted that under the slow ramp-up strategy, the shift amount is not executed all at once, but is broken down into multiple stages, with each stage executing only a portion of the shift amount. For example, the target shift amount of 5 can be broken down into 5 stages, with each stage shifting by 1 bit, and the next stage is entered only after each stage is completed. Under the fast decay strategy, the shift amount is executed all at once.

[0086] Step S304: Select multiplication coefficients from the pre-stored coefficient set, which covers the range from unity gain to a preset maximum fine-tuning gain. Each coefficient in the pre-stored coefficient set corresponds to a preset step gain value and is stored in a fixed-point format.

[0087] It should be noted that shift operations can only achieve gain multiples raised to powers of 2 (i.e., shift amounts such as 1x, 2x, 4x, 8x, etc.), and cannot achieve continuous gain values. Furthermore, at the power level, each 1-bit increase in signal amplitude increases signal power by 6dB, affecting the demodulation performance of subsequent processing modules. Therefore, in this embodiment, the calibration unit can introduce multiplication coefficients. Fine-tuning is performed to fill in the gain within 6dB, thereby compensating for the residual gain that the shift operation cannot accurately represent.

[0088] It should be understood that the calibration unit can pre-store a set of coefficients that can cover the range from unity gain (i.e., a gain factor of 1) to a preset maximum fine-tuning gain. For example... Figure 3 As shown, Figure 3 This is a diagram representing the coefficient set of this application.

[0089] Depend on Figure 3 It can be seen that the preset maximum fine-tuning gain can be set to the linear gain factor corresponding to 5.9dB, which is approximately 1.974 times. The linear gains in this coefficient set can be evenly distributed according to preset steps (such as 0.1dB steps), for example, from 0dB, 0.1dB, 0.2dB... up to 5.9dB, with a total of 60 dB values ​​corresponding to 60 linear gain values. Each linear gain value can be stored in fixed-point format.

[0090] The calibration unit selects the most suitable linear gain value as the multiplication coefficient from the pre-stored coefficient set based on the current gain compensation strategy, the difference between the current sampling point amplitude of the signal to be processed and the target amplitude, and the numerical limit of the shift amount imposed by the shift operation. Taking the slow climb strategy as an example, the calibration unit selects coefficients in incremental increments at each adjustment level. For example, starting from the coefficient corresponding to 0dB (i.e., unity gain), it successively selects coefficients corresponding to 0.1dB, 0.2dB, and so on, until it reaches the maximum fine-tuning range (5.9dB) under the current shift amount. At this point, the shift amount is increased again, and the multiplication coefficient is reset to unity gain, starting a new round of coefficient increments.

[0091] Step S305: Perform a shift operation on the current signal to be processed according to the shift amount to obtain a coarse adjustment signal.

[0092] It should be noted that the calibration unit can perform a left or right shift operation on the current signal to be processed based on the aforementioned determined shift amount (a gain factor raised to the power of 2). When the shift amount is positive, a left shift is performed to amplify the gain; when the shift amount is negative, a right shift is performed to attenuate the gain.

[0093] Specifically, the shift operation can be performed according to the current gain compensation strategy: under the fast decay strategy, all shift operations are completed at once; under the slow climb strategy, only the shift operation allocated for the current stage is completed (for example, if the target of the current stage is a shift of 1, then only a left shift of 1 bit is performed).

[0094] Step S306: Perform a multiplication operation on the coarse adjustment signal according to the multiplication coefficients to obtain the compensated signal.

[0095] It should be noted that the calibration unit can perform a multiplication operation on the coarse adjustment signal obtained by shifting, based on the multiplication coefficients selected above. This multiplication operation can multiply the coarse adjustment signal by the multiplication coefficients, compensating for the residual gain that the shift operation cannot precisely achieve, and finally obtaining the compensated signal.

[0096] Specifically, the multiplication operation is also performed according to the current gain compensation strategy: under the fast decay strategy, the target multiplication coefficient is used directly to perform a single multiplication; under the slow climb strategy, the multiplication is performed according to the multiplication coefficient selected in the current stage, and gradually adjusted in subsequent stages as the coefficient increases.

[0097] It should be understood that, through the synergy of the aforementioned shift and multiplication operations, the calibration unit achieves both coarse and fine gain adjustments: the shift operation accomplishes significant gain adjustments with extremely low resource overhead, while the multiplication operation achieves fine compensation of residual gain with high precision. Under a slow ramp-up strategy, the two work together to achieve multi-stage, gradual gain approximation; under a fast decay strategy, they work together to achieve single, rapid gain adjustments.

[0098] Furthermore, under the rapid decay strategy, the shift amount K, which is a gain factor raised to the power of 2, and the corresponding multiplication coefficient can be directly calculated from the target amplitude. Then, shift and multiplication operations are directly performed on the current sampling point corresponding to the current signal to be processed to obtain the compensated signal.

[0099] Under the slow climb strategy, this embodiment can take the current signal MSB as bit 9 and the target MSB as bit 14, that is, the target shift amount as bit 5, as an example to illustrate the process of performing shift and multiplication operations using the slow climb strategy: The amplitude of the signal to be processed is currently 1000, and it needs to be amplified to the target amplitude of 2^14 = 16384. Therefore, the gain is 16.384 times, which can be expressed as 2^5 (K=5) or 2^4·1.024 (K=4). =1.024).

[0100] Considering that sudden gain changes (e.g., K=4, K=5) during a single gain adjustment can affect subsequent demodulation results, a slow ramp-up strategy can be applied, gradually adjusting the gain in multiple stages: keeping K constant, so that... Gradually increase from 1.0 to 1.974 (60 steps, with a step size of 0.1dB per step); after reaching this value, increment K by 1. Reset back to 1.0.

[0101] The calibration unit can execute the above-mentioned slow ramp-up strategy during the process of the processing module outputting multiple sampling points corresponding to the current signal to be processed, until the current signal to be processed reaches the aforementioned target amplitude and the compensated signal is obtained.

[0102] This embodiment can adaptively select a fast attenuation strategy or a slow ramp-up strategy based on the dynamic margin evaluation results. Under the slow ramp-up strategy, the gain adjustment process is decomposed into multiple small-step stages through the step-by-step coordination of shift amount and multiplication coefficient, avoiding the abrupt impact of a single large gain adjustment on the signal waveform. Under the fast attenuation strategy, the overflow risk is eliminated first by single adjustment, effectively preventing clipping distortion. At the same time, through the gain compensation structure of shift and multiplication coordination, the multiplier resource occupation is significantly reduced while ensuring high-precision gain control.

[0103] Based on the first and second embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to the first and second embodiments described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4 , Figure 4 This is a flowchart illustrating the third embodiment of the FPGA-based digital signal processing method for repeaters in this application.

[0104] In this embodiment, to specifically illustrate how to achieve the feedback superposition of truncation quantization errors, after step S40, the following steps are also included: S501~S502: Step S501: The truncation quantization error is filtered by a feedback filter with high-pass characteristics to obtain the filtered error, and the filtered error is stored in the error adjustment register.

[0105] It should be noted that the calibration unit performs a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error. The processed signal can be output to the next processing module for further processing, while the truncation quantization error can be entered into the error feedback path for noise shaping.

[0106] It should be understood that the calibration unit first inputs the truncation quantization error to a feedback filter with high-pass characteristics. The function of this feedback filter is to change the spectral distribution of the truncation quantization error, shifting the error energy from the low-frequency band (the passband where the signal is located) to the high-frequency band (outside the band), thereby reducing the impact of quantization noise on the signal-to-noise ratio within the signal passband.

[0107] This feedback filter can be implemented as a first-order differential filter, with the input-output relationship being: the filtered error equals the truncation quantization error of the current sampling point minus the truncation quantization error of the previous sampling point. This first-order differential filter has high-pass characteristics, meaning that low-frequency components are attenuated while high-frequency components are preserved.

[0108] After the truncation quantization error is passed through this filter, the DC and low-frequency components in the error signal can be suppressed, while the high-frequency components are relatively enhanced. Since the effective energy of wireless communication signals is concentrated in the low-frequency band, while the high-frequency band usually does not carry useful signals or can be filtered out by subsequent filters, the quantization noise is effectively reduced on the signal quality through the above spectrum shifting process.

[0109] Next, after obtaining the filtered error, the calibration unit can store it in the error adjustment register. This error adjustment register can be a dedicated storage unit used to save the filtered error value of the current sampled circuit for use in subsequent sampling points. The bit width of this error adjustment register can be matched with the bit width of the truncation quantization error to avoid additional quantization loss.

[0110] Step S502: The filtered error is superimposed onto the output signal of the processing module at the next sampling point through the error adjustment register to obtain the next signal to be processed.

[0111] It should be understood that the above superposition operation can occur at the output of the processing module before the input of this calibration unit. That is, the filtered error is added to the new output signal of the processing module at the next sampling point, and the result of the addition is used as the current signal to be processed at the next sampling point and enters the calibration unit, returning to the statistical and processing flow of step S10.

[0112] It should also be noted that the above processing module is the module that outputs the current signal to be processed, that is, the same processing module from which the current signal to be processed originates. This processing module will generate a new output signal at the next sampling point, and the calibration unit will add the filtered error to this new output signal to obtain the next signal to be processed.

[0113] Through the aforementioned feedback mechanism, truncation quantization error can be re-injected into the signal path and affect the signal's statistical characteristics in subsequent sampling periods. Because the feedback filter has high-pass characteristics, the injected error is mainly distributed in the high-frequency band of the spectrum, thus achieving spectral shifting of quantization noise and suppressing the accumulation of error within the signal passband.

[0114] Further, step S502 specifically includes: steps S5021~S5023: Step S5021: When the target amplitude corresponding to the compensated signal changes, calculate the ratio of the target amplitude to the changed target amplitude.

[0115] It should be noted that the calibration unit determines the gain compensation strategy and performs gain adjustment based on the dynamic margin evaluation results. When the gain compensation parameters change, the target amplitude of the compensated signal will also change accordingly.

[0116] For example, under a slow climb strategy, when the multiplication coefficient... After increasing to the maximum value corresponding to 5.9dB (approximately 1.974 times), the K value increases from 0 to 1, at which point the gain doubles and the target amplitude also doubles accordingly.

[0117] When the target amplitude changes, the magnitude of the filtered error value stored in the error adjustment register no longer matches the signal magnitude under the new gain. Directly adding the original error value to the new signal may result in an error that is too large or too small relative to the new signal, causing loop oscillation or a decrease in noise shaping effect. Therefore, this embodiment further introduces a gain linkage mechanism: First, the calibration unit detects whether the target amplitude of the compensated signal has changed. The change in the target amplitude is caused by the change in the gain compensation parameters. The calibration unit can determine whether the target amplitude has changed by monitoring whether the current gain compensation strategy is consistent with the previous gain compensation strategy.

[0118] When a change in the target amplitude is detected, the calibration unit can calculate the ratio of the target amplitude before the change to the target amplitude after the change. This ratio reflects the magnitude of the gain adjustment.

[0119] For example, if the gain changes from G_old to G_new, the ratio is G_new divided by G_old. This applies when the K value changes from 0 to 1, and the multiplication coefficient... In a scenario where the gain is reset to unity gain, the gain multiplier changes from approximately 1.974x to 2x (K=1, =1.0), the ratio is 2 divided by 1.974, which is approximately 1.013, meaning the change is very small; under the fast decay strategy, if the gain decreases directly from 4 times to 1 times, the ratio is 1 divided by 4, which is 0.25.

[0120] Step S5022: Multiply the filtered error value in the error adjustment register by the ratio to obtain the adjusted truncation error.

[0121] It should be understood that the calibration unit can multiply the currently stored filtered error value in the error adjustment register by the aforementioned calculated ratio to obtain the adjusted truncation error. This achieves proportional scaling of the error value, making its magnitude match the signal magnitude under the new gain.

[0122] For example, if the gain is reduced to 0.25 of the original value, the error value can also be adjusted accordingly to 0.25 of the original error value. Furthermore, when this adjusted truncation error is subsequently superimposed on a new signal, the ratio of the adjusted truncation error to the signal remains consistent with that before scaling, allowing for a smooth transition of the loop state.

[0123] Furthermore, when computational resources are limited in the calibration unit, a simplified version of the linkage mechanism can be used: when the shift amount K changes, the multiplication coefficient... When the value remains unchanged or changes only slightly, scaling can be performed based solely on the change in the shift amount, i.e., the scaling factor is 2 to the power of (K_new minus K_old), thereby reducing the computational resource consumption of the calibration unit.

[0124] Step S5023: The adjusted truncation error is superimposed on the output signal of the processing module at the next sampling point to obtain the next signal to be processed.

[0125] In the specific implementation, the calibration unit adds the adjusted truncation error to the output signal of the processing module at the next sampling point. The summed result then enters the calibration unit as the next signal to be processed, returning to step S10. Simultaneously, the adjusted truncation error can also be written back to the error adjustment register for continued use as a historical error value in subsequent sampling periods.

[0126] Through the aforementioned gain linkage mechanism, the calibration unit can ensure that the error feedback loop remains stable even when the gain compensation parameters change frequently, thereby avoiding loop oscillation or a decrease in noise shaping effect caused by the mismatch between the error value and the signal magnitude.

[0127] Furthermore, this can be referenced here. Figure 5 This document provides a complete explanation of the application process. Figure 5 This is a schematic diagram of the entire process of the FPGA-based digital signal processing method for repeaters in this application.

[0128] Depend on Figure 5 As can be seen, the entire process of the method in this application can be summarized as follows: the input signal (the signal to be processed) is split into two paths, the main signal stream and the control path, by a splitter.

[0129] In the main signal stream, the signal passes through a coarse adjustment shifter, a fine adjustment multiplier, and a truncation in sequence before being output; In the control path, the signal enters the MSB occupancy rate statistics unit to perform the most significant bit distribution statistics, and the statistical results are sent to the gain control state machine (including hysteresis logic). The gain control state machine outputs coarse adjustment control signals and fine adjustment control signals based on the dynamic margin evaluation results, which control the shift amount of the coarse adjustment shifter and the multiplication coefficient of the fine adjustment multiplier, respectively.

[0130] The quantization error generated when the truncation device performs the truncation operation is filtered by the error feedback filter (written as "noise shaping" in the figure) and stored in the error adjustment register. It is then linked with the gain control state machine through the linkage controller: when the gain compensation parameter is switched, the linkage controller scales the historical error value in the error adjustment register proportionally to obtain the adjusted truncation error.

[0131] Ultimately, the adjusted truncation error can be added to the input signal of the next sampling period, forming a closed-loop feedback.

[0132] By implementing the calibration unit to achieve the coordinated operation of the main signal flow and control path, the method of this application can realize a complete signal-to-noise ratio maintenance mechanism of "statistics, decision-making, adjustment, and feedback" at each processing node.

[0133] Furthermore, you can also refer to this section. Figure 6 The adaptive gain compensation process based on different states in the dynamic margin assessment results is explained. Figure 6 This is the state transition diagram for the adaptive gain control in this application.

[0134] Depend on Figure 6 It can be seen that the preset gain control algorithm in the steps can be implemented using a four-state hysteresis state machine. This state machine includes a steady-state monitoring state, a gain increase preparation state, a gain decrease preparation state, and an update and synchronization state.

[0135] In steady-state monitoring, the calibration unit continuously monitors the dynamic margin assessment results. When the signal within the window is in a normal state, the state machine remains in steady-state monitoring and clears the internal counter. When multiple consecutive statistical windows detect a signal that is too small (i.e., excessive margin), the state machine jumps to the gain increase preparation state and begins accumulating the trigger count for gain adjustment. When multiple consecutive statistical windows detect a signal that is too large (i.e., insufficient margin) or hardware saturation overflow occurs, the state machine directly jumps to the gain decrease preparation state to prioritize avoiding clipping distortion.

[0136] In the gain increase preparation state, the state machine continues to monitor the margin status of the subsequent window. If the signal returns to normal, the state machine jumps back to the steady-state monitoring state and resets the counter; if the counter reaches the preset threshold, indicating that the signal is continuously too low and the trigger condition has been met, the state machine jumps to the update and synchronization state to perform gain adjustment. Similarly, in the gain decrease preparation state, if the signal returns to normal, the state machine jumps back to the steady-state monitoring state; if the counter reaches the threshold or hardware saturation overflow occurs, the state machine jumps to the update and synchronization state.

[0137] In the update and synchronization state, the calibration unit calculates the new shift amount and multiplication coefficients based on the current margin status, updates the gain compensation parameters, and synchronously adjusts the historical error values ​​in the error feedback loop. After the update is completed, the state machine enters a new monitoring cycle, jumps back to the steady-state monitoring state, and continues the next round of dynamic margin monitoring and adjustment.

[0138] This embodiment utilizes a feedback filter with high-pass characteristics to filter truncation quantization errors, shifting quantization noise energy from the low-frequency band of the signal passband to a high-frequency band that can be filtered out by subsequent filters. This effectively suppresses the cumulative effect of quantization errors within the band during multi-stage cascaded processing, thereby reducing the negative impact of truncation operations on the signal-to-noise ratio. Simultaneously, through a gain linkage mechanism, the historical error value in the error adjustment register is scaled proportionally when the target amplitude changes, ensuring the stability of the error feedback loop during gain switching and avoiding loop oscillation.

[0139] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the FPGA-based digital signal processing method for repeaters in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0140] In addition, this application also provides an FPGA-based digital signal processing device for repeaters, such as... Figure 6 As shown, Figure 7 This is a schematic diagram of the module structure of the FPGA-based digital signal processing device for a repeater in this application. Figure 7 It is known that the device includes: The probability statistics module 701 is used to perform statistics on the distribution of the most significant bit of the current signal to be processed based on a preset statistical window, and to obtain the probability of the high bit interval distribution. The dynamic margin assessment module 702 is used to compare the high-level interval distribution probability with the preset margin threshold to obtain the dynamic margin assessment result. The gain compensation module 703 is used to determine the current gain compensation strategy based on the dynamic margin evaluation result, and to perform gain compensation on the current signal to be processed according to the current gain compensation strategy using a preset gain control algorithm to obtain the compensated signal. The signal truncation module 704 performs a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module in the next sampling period after feedback filtering to obtain the next signal to be processed.

[0141] This embodiment can dynamically evaluate signal margin based on the statistical distribution of the most significant bit (LSB) and adaptively determine gain compensation decisions based on the evaluation results. This avoids the peak-to-average power ratio (PAPR) signal overflow problem caused by fixed gain compensation based on decimation or interpolation factors. Simultaneously, by superimposing the truncation quantization error after feedback filtering onto the output signal of the processing module at the next sampling point, the quantization noise spectrum is shifted out of band, suppressing the cumulative effect of quantization error within the signal passband during multi-stage cascaded processing. Therefore, this embodiment achieves adaptive power calibration and noise shaping at each stage of the signal processing link without demodulation, effectively maintaining the signal-to-noise ratio (SNR) of the repeater output signal.

[0142] This application also provides an FPGA-based digital signal processing device for repeaters. The FPGA-based digital signal processing device for repeaters includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the FPGA-based digital signal processing method for repeaters in the first embodiment described above.

[0143] The following is for reference. Figure 8 , Figure 8 This is a schematic diagram of the structure of the FPGA-based digital signal processing device for repeaters according to this application. The FPGA-based digital signal processing device for repeaters in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable media players (PMPs), and fixed terminals such as digital TVs and desktop computers. Figure 8 The FPGA-based repeater digital signal processing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0144] like Figure 8As shown, the FPGA-based repeater digital signal processing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the FPGA-based repeater digital signal processing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the FPGA-based repeater digital signal processing equipment to exchange data wirelessly or via wired communication with other devices. Although the figure shows an FPGA-based repeater digital signal processing equipment with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented alternatively.

[0145] The FPGA-based digital signal processing device for repeaters provided in this application employs the FPGA-based digital signal processing method for repeaters described in the above embodiments, and can solve the technical problems of FPGA-based digital signal processing for repeaters. Compared with the prior art, the beneficial effects of the FPGA-based digital signal processing device for repeaters provided in this application are the same as the beneficial effects of the FPGA-based digital signal processing method for repeaters provided in the above embodiments, and other technical features in this FPGA-based digital signal processing device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0146] This application also provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the FPGA-based repeater digital signal processing method in the above embodiments.

[0147] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0148] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described FPGA-based repeater digital signal processing method, thereby solving the technical problems of the FPGA-based repeater digital signal processing method. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the FPGA-based repeater digital signal processing method provided in the above embodiments, and will not be repeated here.

[0149] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other elements in the process, method, article, or system that includes that element.

[0150] The above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. They are only some embodiments of this application and do not limit the scope of this application. All equivalent structural transformations made based on the technical concept of this application and the content of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the protection scope of this application.

Claims

1. A digital signal processing method for repeaters based on FPGA, characterized in that, The method includes: Based on a preset statistical window, the distribution of the most significant bit of the current signal to be processed is statistically analyzed to obtain the probability of the high bit interval distribution. The high-level interval distribution probability is compared with the preset margin threshold to obtain the dynamic margin evaluation result; The current gain compensation strategy is determined based on the dynamic margin assessment results. A preset gain control algorithm is used to perform gain compensation on the current signal to be processed according to the current gain compensation strategy to obtain the compensated signal. A truncation operation is performed on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module at the next sampling point after feedback filtering to obtain the next signal to be processed.

2. The method as described in claim 1, characterized in that, The step of statistically analyzing the distribution of the most significant bit of the current signal to be processed based on a preset statistical window to obtain the probability of the high-bit interval distribution includes: The position of the most significant bit of each sample value corresponding to the current signal to be processed is detected within the preset statistical window, wherein the preset statistical window includes several sample points of the current signal to be processed; The number of sampling points whose most significant bit position is within a preset high-bit interval is counted. The preset high-bit interval has an upper limit parameter and a lower limit parameter. The upper limit parameter is determined based on the difference between the preset maximum bit width and the reserved peak margin. The lower limit parameter is determined based on the difference between the preset maximum bit width and the maximum allowable margin. The probability of the high-order interval distribution is determined based on the ratio of the number of sampling points to the total number of sampling points in the preset statistical window.

3. The method as described in claim 1, characterized in that, The step of comparing the high-level interval distribution probability with a preset margin threshold to obtain a dynamic margin evaluation result includes: Detect whether there is a saturation overflow event within the preset statistical window, and compare the high-level interval distribution probability with a preset margin threshold, wherein the preset margin threshold includes a preset low margin threshold and a preset high margin threshold; When the probability of the high-order interval distribution is lower than the preset low margin threshold, it is determined to be a state of excess margin. When the probability of the high-order interval distribution is higher than the preset high margin threshold or when the saturation overflow event occurs, it is determined to be a state of insufficient margin.

4. The method as described in claim 1, characterized in that, The compensated signal has a target amplitude, and the step of determining the current gain compensation strategy based on the dynamic margin evaluation result includes: When the dynamic margin assessment result indicates an insufficient margin state, the current gain compensation strategy is determined to be a rapid attenuation strategy. When the dynamic margin assessment result indicates an excess margin state, the current gain compensation strategy is determined to be a slow ramp-up strategy. The fast attenuation strategy is a strategy that adjusts the current signal to be processed in a single step according to the shift amount and the multiplication coefficient to achieve the target amplitude; the slow ramp-up strategy is a strategy that adjusts the current signal to be processed in multiple steps according to the shift amount and the multiplication coefficient to achieve the target amplitude.

5. The method as described in claim 4, characterized in that, The step of performing gain compensation on the current signal to be processed using a preset gain control algorithm according to the current gain compensation strategy to obtain the compensated signal includes: The target most significant bit position is determined based on the target amplitude, and the shift amount is determined based on the difference between the current signal most significant bit position and the target most significant bit position. Multiplication coefficients are selected from a pre-stored coefficient set, which covers the range from unity gain to a preset maximum fine-tuning gain. Each coefficient in the pre-stored coefficient set corresponds to a preset step gain value and is stored in a fixed-point format. Perform a shift operation on the current signal to be processed according to the shift amount to obtain a coarse adjustment signal; Perform a multiplication operation on the coarse adjustment signal according to the multiplication coefficients to obtain the compensated signal; The shift operation and the multiplication operation are performed in accordance with the current gain compensation strategy.

6. The method as described in claim 1, characterized in that, After the step of performing a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error, the following steps are included: The truncation quantization error is filtered by a feedback filter with high-pass characteristics to obtain the filtered error, and the filtered error is stored in the error adjustment register. The filtered error is superimposed onto the output signal of the processing module at the next sampling point through the error adjustment register to obtain the next signal to be processed.

7. The method as described in claim 6, characterized in that, The step of superimposing the filtered error onto the output signal of the processing module at the next sampling point through the error adjustment register to obtain the next signal to be processed includes: When the target amplitude corresponding to the compensated signal changes, the ratio of the target amplitude to the changed target amplitude is calculated. Multiply the filtered error value in the error adjustment register by the ratio to obtain the adjusted truncation error; The adjusted truncation error is superimposed on the output signal of the processing module at the next sampling point to obtain the next signal to be processed.

8. A repeater digital signal processing device based on FPGA, characterized in that, The device includes: The probability statistics module is used to statistically analyze the distribution of the most significant bit of the current signal to be processed based on a preset statistical window, and obtain the probability of the high bit interval distribution. The dynamic margin assessment module is used to compare the high-level interval distribution probability with a preset margin threshold to obtain the dynamic margin assessment result. The gain compensation module is used to determine the current gain compensation strategy based on the dynamic margin evaluation result, and to perform gain compensation on the current signal to be processed according to the current gain compensation strategy using a preset gain control algorithm to obtain the compensated signal. The signal truncation module performs a truncation operation on the compensated signal to obtain the processed signal and the truncation quantization error. The truncation quantization error is used to be superimposed on the output signal of the processing module in the next sampling period after feedback filtering to obtain the next signal to be processed.

9. A repeater digital signal processing device based on FPGA, characterized in that, The device includes: a memory, a processor, and an FPGA-based repeater digital signal processing program stored in the memory and executable on the processor. When executed by the processor, the FPGA-based repeater digital signal processing program implements the FPGA-based repeater digital signal processing method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores an FPGA-based digital signal processing program for a repeater. When the FPGA-based digital signal processing program is executed by a processor, it implements the FPGA-based digital signal processing method for a repeater as described in any one of claims 1 to 7.

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