Short wave channel simulator and simulation method thereof

Abstract

The application discloses a short-wave channel simulator and a simulation method thereof, wherein the simulator comprises a signal acquisition module, a signal processing module and a signal radio frequency module connected in sequence; the signal acquisition module is used for collecting signals of multiple analog channels, and the collected digital signals are transmitted to the signal processing module for channel simulation processing, including gain adjustment, time delay processing, Doppler frequency shift and frequency spread processing and additive white Gaussian noise superposition; finally, the signals subjected to the channel simulation processing are subjected to up-conversion mixing, and radio frequency signals are output, so that the simulator can be directly connected with a baseband side signal modulator, the shortcoming that a traditional channel simulator cannot output radio frequency signals is made up, the simulator has a wider bandwidth, can perform multi-channel parallel processing, is higher in precision and lower in cost.

Description

Technical Field

[0001] This invention relates to the field of cable technology, and in particular to a shortwave channel simulator and its simulation method. Background Technology

[0002] Shortwave communication, with its unique ionospheric reflection characteristics, plays a vital role in emergency communications, military communications, and other fields. As a key tool for evaluating and testing the performance of shortwave communication equipment, it can simulate various characteristics of actual shortwave channels, such as multipath propagation, fading, and Doppler shift. However, existing shortwave channel simulators have the following shortcomings in terms of signal bandwidth and transmission channels: Common shortwave channel simulators typically use baseband signals with a bandwidth of 0-3kHz, which is insufficient for testing broadband signal transmission. Furthermore, the transmission channel type is usually a single-channel analog input, resulting in low channel accuracy and susceptibility to noise from analog components. In addition, to achieve direct RF-level output and high-precision simulation, traditional high-end RF channel simulators often employ expensive dedicated hardware architectures, significantly increasing the barriers to development and testing. While some traditional devices aim to save costs, they cannot directly output RF signals and require an additional modulator for integrated receiver testing, making them inconvenient to use. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing technologies by proposing a shortwave channel simulator and its simulation method, which can directly realize baseband to radio frequency signal modulation, has a wider bandwidth, can perform multi-channel parallel processing, and is not only more accurate but also less expensive.

[0004] The technical solution to achieve the objective of this invention is: A shortwave channel simulator includes a signal acquisition module, a signal processing module, and a signal radio frequency module connected in sequence. The signal acquisition module includes an acquisition FPGA processor and a multi-channel A / D analog-to-digital converter connected thereto, used to acquire signals from multiple analog channels and transmit the acquired digital signals to the signal processing module; The signal processing module includes a core processor and a PCIe Ethernet controller connected thereto; the core processor is used to run channel simulation algorithms to perform channel simulation processing on the received digital signals, including gain adjustment, time delay processing, Doppler frequency shift and frequency spread processing, and additive white Gaussian noise superposition. The signal radio frequency module includes an orthogonal upconverter and a modulation FPGA processor; the modulation FPGA processor is used to control the orthogonal upconverter to perform upconversion and mixing on the baseband signal after channel simulation processing, and output radio frequency signal.

[0005] Furthermore, the multi-channel A / D analog-to-digital converter is connected to the acquisition FPGA processor via a TDM bus; the acquisition FPGA processor implements a first Ethernet port through a first PHY chip, and interacts with the signal processing module through the first Ethernet port.

[0006] Furthermore, the chip model of the acquisition FPGA processor is XC7A35T, the chip model of the multi-channel A / D analog-to-digital converter is ADS1278, and the model of the first PHY chip is RTL8201.

[0007] Furthermore, the core processor uses an RK3588 chip, which integrates two independent GMAC controllers. One GMAC controller connects to a second PHY chip to establish a second Ethernet port for connecting to a signal acquisition module. The other GMAC controller connects to a third PHY chip to establish a third Ethernet port, which connects to a first network transformer as a digital input channel for inputting multiple digital audio data.

[0008] Furthermore, the second and third PHY chips are model YT8531S, and the first network transformer is model HX5001NL.

[0009] Furthermore, the PCIE Ethernet controller is model YT6802, which integrates two independent gigabit GMACs and gigabit PHYs to realize a fourth Ethernet port and a fifth Ethernet port. The fourth Ethernet port is connected to the radio frequency modulation module, and the fifth Ethernet port is connected to the second network transformer as a control interface for users to configure parameters.

[0010] Furthermore, the chip model of the orthogonal upconverter is CBM99D57BQ, and the chip model of the modulation FPGA processor is XC7K325T.

[0011] A simulation method for a shortwave channel simulator as described above includes the following steps: Step S1: Obtain the input signal x(t) and split it into two paths. One path is passed through a bandpass filter to obtain the I signal, denoted as... The other path, after undergoing Hilbert transform and then passing through a bandpass filter, yields the Q signal, represented as... The complex signal e(t) is generated by merging the two signals. , Where j is the imaginary unit, meaning that this is the imaginary part of the complex value; Step S2: Based on the configured number of multipaths N, the gain ρ of each path k k and delay τ kBy superimposing Doppler effect and Gaussian white noise, multipath transmission simulation is performed on the complex signal e(t) to generate the baseband signal s(t). , Where n(t) is the Gaussian white noise signal, c k (t) represents a zero-mean stationary Gaussian random noise signal simulating Doppler spread and Doppler shift; Step S3: Perform quadrature modulation on the baseband signal s(t), decomposing the baseband signal s(t) into its real part s I (t) and imaginary part s Q (t), real part s I (t) multiplied by cosine carrier imaginary part s Q (t) multiplied by a sinusoidal carrier wave Finally, the signals are summed to generate the radio frequency signal Sm(t) and output. .

[0012] Furthermore, in step S2, the Gaussian white noise signal n(t) satisfies a Gaussian distribution: ,

[0013] Where n is the instantaneous amplitude of the noise, The noise variance is the average power P of the noise. n Its relationship with the average signal power Ps and the signal-to-noise ratio SNR is as follows: .

[0014] Furthermore, in step S2, the Doppler effect is simulated using a power spectral density function; the power spectral density ∅(f) of the noise signal ck(t) is represented by the Gaussian white noise power spectral density N0 passing through a filter with a response of |H(f)|. , The Doppler of path k |H(f)| is defined as: , D sh D is the Doppler frequency shift value for path k. sp Let be the Doppler diffusion value for path k, and satisfy .

[0015] By adopting the above technical solution, the present invention has the following beneficial effects:

[0016] (1) The signal acquisition module of this invention has a multi-channel A / D analog-to-digital converter, which can realize the acquisition of signals from multiple analog channels and realize the performance test of frequency diversity shortwave receivers; the baseband signal is converted into an RF signal through the signal RF module and transmitted, which can be directly connected to the baseband side signal modulator, solving the shortcomings of traditional channel simulators that cannot directly output RF signals, and facilitating the integrated performance test of shortwave receivers; the multi-channel A / D converter at the acquisition end improves the sampling rate, and through the computing power support of the processing end and the broadband quadrature modulation at the RF end, a wider bandwidth is achieved; in addition, by combining baseband analog and RF modulation, the requirements for computing performance are reduced, thereby achieving low cost and miniaturized design, and adopting digital signal processing, the performance is stable and reliable, less affected by device interference, and the test accuracy is improved.

[0017] (2) The present invention modulates the simulated signal onto the radio frequency carrier for output. Through the complete link of complexization, parallel multipath processing, noise superposition, and orthogonal upconversion, a high-precision shortwave channel physical layer simulation is realized in hardware. It can not only simulate static attenuation and delay, but also reproduce the dynamic Doppler spread characteristics unique to the shortwave channel through the Gaussian spectrum shaping algorithm. It is more suitable for evaluating the demodulation performance of shortwave receivers in complex ionospheric environments.

[0018] (3) This invention pushes the complex channel simulation operation down to the digital domain, leaving only the final modulation stage in the radio frequency domain, thereby achieving the best balance between performance and cost; digital processing is used from signal acquisition to channel modeling, ensuring consistency in long-term testing; the combination of RK3588 core processor, FPGA processor and dedicated radio frequency chip replaces the existing expensive pure radio frequency vector signal source solution, which greatly reduces hardware cost and equipment size. Attached Figure Description

[0019] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a structural block diagram of the shortwave channel simulator of the present invention; Figure 2 This is a flowchart of the simulation method of the present invention. Detailed Implementation

[0020] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0021] The shortwave channel simulator in this embodiment is as follows: Figure 1As shown, it includes a signal acquisition module, a signal processing module, and a signal radio frequency module connected in sequence. The signal acquisition module acquires signals from multiple analog channels and transmits the acquired digital signals to the signal processing module for channel simulation processing, including gain adjustment, time delay processing, Doppler frequency shift and frequency spread processing, and additive white Gaussian noise superposition. Finally, the signal after channel simulation processing is up-converted and mixed to output a radio frequency signal, which can be directly connected to the baseband-side signal modulator. This overcomes the shortcomings of traditional channel simulators that cannot output radio frequency signals, has a wider bandwidth, and can perform multi-channel parallel processing. It is not only more accurate but also less expensive.

[0022] Specifically, the signal acquisition module includes an acquisition FPGA processor and a multi-channel A / D converter connected to it via a TDM bus. The acquisition FPGA processor implements a first Ethernet port through a first PHY chip and interacts with the signal processing module through the first Ethernet port. In this embodiment, the acquisition FPGA processor is model XC7A35T, the multi-channel A / D converter has 8 channels and can acquire signals from 8 analog channels, with a maximum sampling rate of 48kHz, and its chip model is ADS1278. The first PHY chip is model RTL8201.

[0023] The signal processing module includes a core processor and connected components such as a PCIe Ethernet controller, a second PHY chip, a third PHY chip, an eMMC memory, an LPDDR memory, and auxiliary circuits including power supply and clock. The core processor runs channel simulation algorithms, performing channel simulation processing on the received digital signals, including gain adjustment, delay processing, Doppler frequency shift and spread processing, and additive white Gaussian noise superposition. In this embodiment, the core processor uses an RK3588 chip, which integrates two independent GMAC controllers. One GMAC controller connects to the second PHY chip, providing a second Ethernet port for connecting to the signal acquisition module; the other GMAC controller connects to the third PHY chip, providing a third Ethernet port. This third Ethernet port connects to the first network transformer as a digital input channel for inputting multiple channels of digital audio data. The second and third PHY chips are model YT8531S, the first network transformer is model HX5001NL, the eMMC memory is model KLM64GEME-B041, and the LPDDR memory is model K4F6E304HB-MGCH.

[0024] The PCIe Ethernet controller uses the YT6802 chip, which integrates two independent gigabit GMACs and gigabit PHYs to provide a fourth and fifth Ethernet port. The fourth Ethernet port connects to the RF modulation module, and the fifth Ethernet port connects to the second network transformer as a control interface for user parameter configuration.

[0025] The signal RF module includes a quadrature upconverter and a modulation FPGA processor. The quadrature upconverter uses a CBM99D57BQ chip, and the modulation FPGA processor uses an XC7K325T chip. The modulation FPGA processor controls the quadrature upconverter to upconvert and mix the baseband signal after channel simulation processing, and outputs the RF signal.

[0026] This embodiment achieves performance testing of a frequency diversity shortwave receiver by acquiring signals from multiple analog channels. The baseband signal is converted into an RF signal via a signal RF module, allowing direct connection to the baseband-side signal modulator. This overcomes the limitation of traditional channel simulators that cannot output RF signals, facilitating integrated performance testing of the shortwave receiver. Furthermore, the sampling rate is increased through a multi-channel A / D converter at the acquisition end. Combined with the computing power of the processing end and wideband quadrature modulation at the RF end, this approach abandons the traditional narrowband analog approach and achieves a wider bandwidth.

[0027] This embodiment also provides a method for signal simulation using the aforementioned shortwave channel simulator, such as... Figure 2 As shown, the specific steps include:

[0028] Step S1: Obtain the input signal x(t) and split it into two paths. One path is passed through a bandpass filter with a bandwidth of 20kHz to filter out out-of-band noise and retain the effective signal, obtaining the real part I signal, represented as: Another path, after undergoing Hilbert transform, shifts all frequency components of the signal by 90 degrees, and then processes it through a 20kHz bandpass filter to obtain the imaginary part Q signal, represented as... The complex signal e(t) is generated by merging the two signals. , Here, j is the imaginary unit, which means that this is the imaginary part of the complex value.

[0029] Step S2: Based on the configured number of multipaths N, the gain ρ of each path k k and delay τ k By superimposing Doppler effect and Gaussian white noise, multipath transmission simulation is performed on the complex signal e(t) to generate the baseband signal s(t). , Where n(t) is the Gaussian white noise signal, c k (t) represents a zero-mean stationary Gaussian random noise signal simulating Doppler spread and Doppler shift, and e(t−τk) represents the signal of the k-th path arriving τk later than the direct signal because the path is longer; The Gaussian white noise signal n(t) follows a Gaussian distribution: , Where n is the instantaneous amplitude of the noise, The noise variance is the average power P of the noise. n Its relationship with the average signal power Ps and the signal-to-noise ratio SNR is as follows: ; The Doppler effect is simulated using the power spectral density function; the power spectral density ∅(f) of the noise signal ck(t) is expressed as the Gaussian white noise power spectral density N0 passing through a filter with response |H(f)|. , The Doppler of path k |H(f)| is defined as: , D sh D is the Doppler frequency shift value for path k. sp Let be the Doppler diffusion value for path k, and satisfy .

[0030] Step S3: Perform quadrature modulation on the baseband signal s(t), decomposing the baseband signal s(t) into its real part s I (t) and imaginary part s Q (t), real part s I (t) multiplied by cosine carrier imaginary part s Q (t) multiplied by a sinusoidal carrier wave Finally, the signals are summed to generate the radio frequency signal Sm(t) and output. .

[0031] To facilitate user use, this implementation also provides six commonly used shortwave channel models as specified by the ITU (International Telecommunication Union), which users can directly call upon. Their parameters are as follows: Channel Model 1 Delay (ms) 0 / / / Path gain 1 / / / Doppler shift (Hz) 0 / / / Doppler extension (Hz) 0 / / / Channel Model 2 Delay (ms) 0 1 / / Path gain 1 0.5 / / Doppler shift (Hz) 0 0 / / Doppler extension (Hz) 0 0.1 / / Channel Model 3 Delay (ms) 0 0.7 1.5 2.2 Path gain 1 0.7 0.5 0.25 Doppler shift (Hz) 0.1 0.2 0.5 1.0 Doppler extension (Hz) 0.1 0.5 1.0 2.0 Channel Model 4 Delay (ms) 0 2 / / Path gain 1 1 / / Doppler shift (Hz) 0 0 / / Doppler extension (Hz) 1 1 / / Channel Model 5 Delay (ms) 0 4 / / Path gain 1 1 / / Doppler shift (Hz) 0 0 / / Doppler extension (Hz) 2 2 / / Channel Model 6 Delay (ms) 0 2 4 6 Path gain 0.5 1 0.25 0.0625 Doppler shift (Hz) 0 1.2 2.4 3.6 Doppler extension (Hz) 0.1 2.4 4.8 7.2

[0032] This embodiment combines baseband simulation with radio frequency modulation, significantly reducing the computational performance requirements and achieving low-cost and miniaturized design. It also employs digital signal processing, ensuring stable and reliable performance with minimal susceptibility to device noise drift and interference, thus improving test accuracy. Users configure the multipath number N and path gain ρ of the channel simulator via the control interface. k Multipath delay τ k Doppler frequency shift D sh Doppler diffusion D sp The channel model is configured using signal-to-noise ratio (SNR). The channel simulator simulates the transmission of the collected input signal according to the channel model and finally modulates the simulated signal onto the radio frequency carrier for output. Through a complete link of complexization, parallel multipath processing, noise superposition, and orthogonal upconversion, high-precision shortwave channel physical layer simulation is achieved in hardware. It can not only simulate static attenuation and delay, but also accurately reproduce the dynamic Doppler spread characteristics unique to shortwave channels through Gaussian spectrum shaping algorithm, making it more suitable for evaluating the demodulation performance of shortwave receivers in complex ionospheric environments.

[0033] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A shortwave channel simulator, characterized in that: It includes a signal acquisition module, a signal processing module, and a signal radio frequency module connected in sequence; The signal acquisition module includes an acquisition FPGA processor and a multi-channel A / D analog-to-digital converter connected thereto, used to acquire signals from multiple analog channels and transmit the acquired digital signals to the signal processing module; The signal processing module includes a core processor and a PCIe Ethernet controller connected thereto; the core processor is used to run channel simulation algorithms to perform channel simulation processing on the received digital signals, including gain adjustment, time delay processing, Doppler frequency shift and frequency spread processing, and additive white Gaussian noise superposition. The signal radio frequency module includes an orthogonal upconverter and a modulation FPGA processor; The modulation FPGA processor is used to control the quadrature upconverter to upconvert and mix the baseband signal after channel simulation processing, and output the radio frequency signal.

2. A shortwave channel simulator according to claim 1, characterized in that: The multi-channel A / D analog-to-digital converter is connected to the acquisition FPGA processor via a TDM bus; the acquisition FPGA processor implements a first Ethernet port through a first PHY chip and interacts with the signal processing module through the first Ethernet port.

3. A shortwave channel simulator according to claim 2, characterized in that: The acquisition FPGA processor uses an XC7A35T chip, the multi-channel A / D converter uses an ADS1278 chip, and the first PHY chip uses an RTL8201 chip.

4. A shortwave channel simulator according to claim 1, characterized in that: The core processor uses an RK3588 chip, which integrates two independent GMAC controllers. One GMAC controller connects to a second PHY chip to create a second Ethernet port for connecting to a signal acquisition module. The other GMAC controller connects to a third PHY chip to create a third Ethernet port, which connects to a first network transformer as a digital input channel for inputting multiple digital audio data.

5. A shortwave channel simulator according to claim 4, characterized in that: The second and third PHY chips are model YT8531S, and the first network transformer is model HX5001NL.

6. A shortwave channel simulator according to claim 1, characterized in that: The PCIE Ethernet controller is model YT6802, which integrates two independent gigabit GMACs and gigabit PHYs to realize a fourth Ethernet port and a fifth Ethernet port. The fourth Ethernet port is connected to the radio frequency modulation module, and the fifth Ethernet port is connected to the second network transformer as a control interface for users to configure parameters.

7. A shortwave channel simulator according to claim 1, characterized in that: The chip model of the orthogonal upconverter is CBM99D57BQ, and the chip model of the modulation FPGA processor is XC7K325T.

8. A simulation method for a shortwave channel simulator as described in any one of claims 1 to 7, characterized in that: Includes the following steps: Step S1: Obtain the input signal x(t) and split it into two paths. One path is passed through a bandpass filter to obtain the I signal, denoted as... The other path, after undergoing Hilbert transform and then passing through a bandpass filter, yields the Q signal, represented as... The complex signal e(t) is generated by merging the two signals. ， Where j is the imaginary unit; Step S2: According to the configured number of multipath N, the gain p of each path k k And the delay τ k And superimpose Doppler effect and Gaussian white noise, the complex signal e(t) is simulated by multipath transmission, and the baseband signal s(t) is generated, ， Where n(t) is the Gaussian white noise signal, c k (t) represents a zero-mean stationary Gaussian random noise signal simulating Doppler spread and Doppler shift; Step S3: Perform quadrature modulation on the baseband signal s(t), decomposing the baseband signal s(t) into its real part s I (t) and imaginary part s Q (t), real part s I (t) multiplied by cosine carrier imaginary part s Q (t) multiplied by a sinusoidal carrier wave Finally, the signals are summed to generate the radio frequency signal Sm(t) and output. 。 9. The simulation method according to claim 8, characterized in that: In step S2, the Gaussian white noise signal n(t) follows a Gaussian distribution. ， Where n is the instantaneous amplitude of the noise, The noise variance is the average power P of the noise. n Its relationship with the average signal power Ps and the signal-to-noise ratio SNR is as follows: 。 10. The simulation method according to claim 8, characterized in that: In step S2, the Doppler effect is simulated using a power spectral density function; the power spectral density ∅(f) of the noise signal ck(t) is represented by the Gaussian white noise power spectral density N0 passing through a filter with a response of |H(f)|. ， The Doppler of path k |H(f)| is defined as: ， D sh D is the Doppler frequency shift value for path k. sp Let be the Doppler diffusion value for path k, and satisfy . .

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