Multi-band frequency generation cooperative calibration method and system based on radio frequency analog chip

Abstract

The application discloses a multi-band frequency generation cooperative calibration method and system based on a radio frequency analog chip, two local oscillator signals are generated by using double phase-locked loops in the chip; in response to a synchronous trigger, a frequency divider is uniformly reset, and an initial phase relationship is established; the two local oscillator signals are mixed by internal loop back, low-pass filtered to obtain difference frequency signals, and the phase is extracted by FFT to calculate a non-fuzzy relative phase difference; the deviation is obtained by comparing with a target phase difference, and a compensation value is calculated according to the step precision of digital phase compensation; the local oscillator phase is adjusted by writing into a register through SPI to complete closed-loop calibration. The initial phase relationship is established by synchronous reset, the phase is measured by internal loop back mixing, and closed-loop compensation is realized, the problems of random initial phase of double-band local oscillator, external calibration and complex hardware are solved, automatic cooperative calibration is realized in the chip, external test equipment and compensation circuit are not needed, the design complexity and cost are reduced, the start-up time is shortened, and the phase difference is stably controlled in the preset tolerance.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and specifically to a multi-band frequency generation and collaborative calibration method and system based on radio frequency analog-to-digital chips. Background Technology

[0002] As a core component of multi-band RF systems, the RF analog-to-digital converter (ADC) chip's built-in dual-band local oscillator signal source directly determines the system's frequency accuracy, phase consistency, and overall performance. In applications with stringent phase requirements, such as phased array radar, multi-channel receivers, and synchronous communication, the initial phase difference between the two local oscillator signals must be precisely controlled within a preset range; otherwise, serious problems such as beam pointing deviation, decreased receiver sensitivity, and synchronization loss will occur.

[0003] Currently, dual-band local oscillator signals in RF analog-to-digital chips are typically implemented using two independent phase-locked loop (PLL) frequency synthesizers, with the two PLLs sharing the same external reference clock signal. However, due to inherent differences in the power-on timing, internal circuit delays, and output divider reset times of the two PLLs, even when operating based on the same reference clock, the initial phases of the two local oscillator signals are random, making it impossible to guarantee a fixed phase relationship. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a multi-band frequency generation and collaborative calibration method based on an RF analog-to-digital chip. By establishing the initial phase relationship between two local oscillators through synchronous reset, the mixing and phase measurement are completed using the internal loop path of the chip, and the local oscillator phase is adjusted in a closed loop according to the phase deviation. This method can solve the problems of random initial phase of dual-band local oscillators, the need for external manual calibration, high hardware complexity, and the inability to perform internal closed-loop calibration in the prior art. It can automatically complete the initial phase collaborative calibration of dual-band local oscillator signals within the RF analog-to-digital chip without the need for additional external test equipment and additional compensation circuits, reducing hardware design complexity and system cost, shortening system startup time, and achieving internal closed-loop calibration within the chip, thus stabilizing and controlling the phase difference between the two local oscillator signals within a preset tolerance.

[0005] This invention provides a multi-band frequency generation and collaborative calibration method based on an RF analog-to-digital chip, comprising the following steps: S1: Receive a reference clock signal; a first phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a first-band local oscillator signal according to the reference clock signal; a second phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a second-band local oscillator signal according to the reference clock signal. S2: In response to the system synchronization trigger signal, the radio frequency analog-to-digital chip resets the frequency dividers on the output paths of the first frequency band local oscillator signal and the second frequency band local oscillator signal to a preset initial counting state, and establishes an initial phase relationship between the first frequency band local oscillator signal and the second frequency band local oscillator signal; S3: The first frequency band local oscillator signal and the second frequency band local oscillator signal are input to the same internal mixer through the internal loopback path. After mixing and low-pass filtering, the difference frequency signal is obtained. The phase of the difference frequency signal is extracted by fast Fourier transform operation. Based on the unified initial phase reference, the unambiguous actual relative phase difference between the first frequency band local oscillator signal and the second frequency band local oscillator signal is calculated according to the phase value of the difference frequency signal. S4: Compare the actual relative phase difference with the preset target phase difference to obtain the phase deviation. Based on the phase deviation and the digital phase compensation step accuracy of the local oscillator channel corresponding to the RF analog-to-digital chip, calculate the compensation value that needs to be written into the digital phase compensation register of the corresponding local oscillator channel. S5: Write the compensation value into the digital phase compensation register through the serial peripheral interface, adjust the phase of the corresponding local oscillator channel according to the compensation value, until the initial phase calibration is completed and the two calibrated local oscillator signals enter the normal working state.

[0006] Furthermore, step S1 includes: The externally input reference clock signal is sent to the dedicated clock buffer built into the RF analog-to-digital chip; The reference clock signal is bandpass filtered by the input stage circuit of the clock buffer to remove low-frequency noise and high-frequency interference from the input signal. The filtering reference clock signal is edge-shaped by the shaping stage circuit of the clock buffer, converting the non-ideal square wave into a standard square wave signal with steep rising and falling edges. The driving capability of the shaped reference clock signal is enhanced by the driver stage circuit of the clock buffer, so that it can stably drive two independent phase-locked loop frequency synthesizers at the same time. The processed reference clock signal is simultaneously output to the reference clock input terminals of the first phase-locked loop frequency synthesizer and the second phase-locked loop frequency synthesizer.

[0007] Furthermore, step S2 includes: Receive system synchronization trigger signals sent by external systems; The system synchronization trigger signal is sent to the built-in synchronization trigger of the RF analog-to-digital chip for synchronization with the reference clock signal, eliminating the metastability risk between the trigger signal and the reference clock. A global synchronous reset signal, strictly aligned with the rising edge of the reference clock signal, is generated by a synchronous flip-flop. The global synchronization reset signal is simultaneously sent to the first output divider on the first frequency band local oscillator signal output path and the second output divider on the second frequency band local oscillator signal output path; This ensures that both output dividers receive the reset command simultaneously at the rising edge of the same reference clock.

[0008] Furthermore, step S2 also includes: The reset target count state of the two output frequency dividers is pre-configured to a zero count state via register configuration; After receiving the global synchronization reset signal, the first and second output frequency dividers immediately clear all bits of the internal counter. After the reset is complete, both output frequency dividers start from the all-zero counting state simultaneously and divide the phase-locked loop output signal according to their respective division ratios; This ensures that the local oscillator signals of the first and second frequency bands are simultaneously and continuously output from the same phase zero point within the first reference clock cycle after the reset is completed.

[0009] Furthermore, the step of inputting the first frequency band local oscillator signal and the second frequency band local oscillator signal into the same internal mixer through an internal loopback path includes: Generate an internal loopback test enable command, and control the first multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the local oscillator signal in the first frequency band according to the internal loopback test enable command. Control the operation of the second multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the second frequency band local oscillator signal; Control the first multiplexer switch to switch the local oscillator signal of the first frequency band to the first dedicated loopback test channel inside the chip; The second multiplexer switch is controlled to switch the second frequency band local oscillator signal to the second dedicated loopback test channel inside the chip. The local oscillator signal of the first frequency band is input to the first input terminal of the internal mixer through the first dedicated loopback test channel; The second frequency band local oscillator signal is input to the second input terminal of the internal mixer through the second dedicated loopback test channel.

[0010] Furthermore, the low-pass filtering of the mixing signal includes: Based on the preset frequency of the local oscillator signal in the first frequency band and the preset frequency of the local oscillator signal in the second frequency band, the difference frequency signal frequency of the two local oscillator signals is calculated in advance. The cutoff frequency of the programmable low-pass filter built into the RF analog-to-digital chip can be set to a value higher than the difference frequency signal frequency by configuring the register. The mixed signal, which includes sum frequency, difference frequency and spurious components, output from the internal mixer is input to the programmable low-pass filter. High-frequency and low-frequency components, as well as out-of-band spurious interference components, are filtered out in the mixing signal by a programmable low-pass filter. The programmable low-pass filter outputs a pure difference frequency signal containing only the difference frequency component.

[0011] Furthermore, step S3 includes: Select a Hanning window function suitable for phase measurement from the preset window function library; Collect time-domain sampling data of the difference frequency signal of a preset length; The time-domain sampled data of the acquired difference frequency signal are multiplied point by point with the Hanning window function; Complete the time-domain windowing processing of the difference frequency signal; Suppressing the inherent spectral leakage phenomenon in Fast Fourier Transform (FFT) operations improves the accuracy and stability of subsequent phase extraction.

[0012] Furthermore, step S4 includes: Perform a fixed-point Fast Fourier Transform operation on the time-domain data of the windowed difference frequency signal; Obtain the complex form of discrete spectrum data corresponding to the difference frequency signal; Calculate the amplitude value corresponding to each frequency point in the discrete spectrum data; Search for the frequency point with the largest amplitude value in the discrete spectrum data; this frequency point is the frequency point corresponding to the difference frequency signal. Extract the complex phase value corresponding to the maximum amplitude frequency point as the original phase value of the difference frequency signal.

[0013] Furthermore, step S5 includes: The valid digital compensation value is written into the digital phase compensation register of the corresponding local oscillator channel through the serial peripheral interface. Wait for the preset phase-locked loop stabilization time to allow the output phase of the local oscillator channel to complete the adjustment and enter a stable state; Repeat the phase difference detection procedure to measure the actual relative phase deviation between the two local oscillator signals; Determine whether the phase deviation obtained from this measurement is within the preset allowable range. If the phase deviation is not within the preset allowable range, repeat the compensation value calculation and phase adjustment steps. If the phase deviation is within the preset allowable range, the phase difference detection step is performed again for verification. When the phase deviations obtained from two consecutive measurements are both within the preset allowable range, the initial phase calibration is considered complete. Generate a calibration completion flag signal, disconnect the internal loopback test path, restore the external output paths of the two local oscillator signals, and bring the two local oscillator signals into normal working condition.

[0014] The present invention also provides a multi-band frequency generation and collaborative calibration system based on an RF analog-to-digital chip, the system comprising: A high-precision reference clock source is used to provide a high-precision reference clock signal; The radio frequency analog-to-digital chip is electrically connected to the high-precision reference clock source and integrates a first phase-locked loop frequency synthesizer, a second phase-locked loop frequency synthesizer, a mixer, a low-pass filter, an analog-to-digital converter, a system synchronization trigger interface, a digital phase compensation register, and a built-in temperature sensor. The calibration control unit is electrically connected to the RF analog-to-digital chip via a high-speed serial interface and a serial peripheral interface, and internally integrates non-volatile memory and multiple process processing modules. The system initialization and synchronization control module is used to control the system power-on initialization process, generate and send the system synchronization trigger signal, and control the synchronous reset operation of the two local oscillator signal dividers. The loopback sampling control module is used to control the on / off state of the loopback path inside the RF analog-to-digital chip, configure the operating parameters of the mixer and analog-to-digital converter, and complete the acquisition and transmission of the difference frequency signal. The initial phase calibration module is used to perform phase difference measurement, compensation value calculation and register writing operations to complete the initial phase calibration of the two local oscillator signals; The temperature compensation control module is used to periodically read the chip temperature data, determine whether the temperature change exceeds the threshold, and perform indexing and writing operations for the temperature compensation value. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a multi-band frequency generation and collaborative calibration method based on an RF analog-to-digital chip in an embodiment of the present invention; Figure 2 This is a schematic diagram of the initial phase calibration method for multi-band radio frequency analog-to-digital chips in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a multi-band frequency generation and collaborative calibration system based on an RF analog-to-digital chip in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0018] Please refer to Figure 1 This invention provides a multi-band frequency generation and collaborative calibration method based on an RF analog-to-digital chip, comprising the following steps: S1: Receive a reference clock signal; a first phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a first-band local oscillator signal according to the reference clock signal; a second phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a second-band local oscillator signal according to the reference clock signal. Specifically, step S1 includes: The externally input reference clock signal is fed into a dedicated clock buffer built into the RF analog-to-digital chip. This dedicated clock buffer is a circuit module integrated within the RF analog-to-digital chip, whose main function is to receive, process, and distribute clock signals. The buffer can be implemented using, for example, CMOS or bipolar processes, designed to provide high fan-out capability, low jitter, and accurate clock signal transmission. Its role is to provide a stable input interface for subsequent clock processing and to isolate the load effects that external clock signals may introduce, ensuring the integrity of the clock signal.

[0019] The reference clock signal undergoes bandpass filtering at the input stage of the clock buffer to remove low-frequency noise and high-frequency interference. This is achieved through various methods, including on-chip integrated passive RC filters, LC filters, or active G_m-C filters. Its function is to selectively allow signals within a specific frequency range while attenuating noise and interference below or above that range, ensuring a high signal-to-noise ratio and purity of the clock signal entering subsequent processing stages.

[0020] The shaping stage circuit of the clock buffer performs edge shaping on the filtered reference clock signal, converting the non-ideal square wave into a standard square wave signal with steep rising and falling edges. The shaping stage circuit of the clock buffer is responsible for reshaping the waveform of the filtered clock signal. This can be achieved by integrating circuits such as Schmitt triggers, high-speed comparators, or limiting amplifiers. Its function is to convert non-standard square wave signals, which may have insufficiently steep rising and falling edges or unsatisfactory duty cycles, into standard square wave signals with fast rising and falling edges and stable high and low levels, thereby providing clear and reliable clock trigger edges for digital circuits.

[0021] The driver stage circuit of the clock buffer enhances the driving capability of the shaped reference clock signal, enabling it to stably drive two independent phase-locked loop frequency synthesizers simultaneously. This is achieved by integrating multiple large-scale CMOS inverter chains, push-pull output stages, or differential drivers. Its function is to ensure that the processed reference clock signal can drive multiple loads.

[0022] The processed reference clock signal is simultaneously output to the reference clock inputs of both the first and second phase-locked loop (PLL) frequency synthesizers. Through the chip's internal low-skew clock tree network or a dedicated clock distributor, it is ensured that the same high-quality reference clock signal arrives at both independent PLL frequency synthesizers simultaneously with minimal skew and jitter. This synchronous distribution mechanism is fundamental to achieving initial phase consistency between the two local oscillator signals, guaranteeing that both PLLs begin operation under the same clock reference.

[0023] By performing multi-stage processing on the input external reference clock signal, the quality of the reference clock signal is optimized, providing a reliable reference basis for the two phase-locked loops to generate stable and accurate local oscillator signals of different frequency bands, thereby ensuring the overall accuracy of subsequent multi-frequency band local oscillator phase collaborative calibration.

[0024] The dedicated clock buffer built into the RF analog-to-digital chip can be specifically designed as an integrated circuit module implemented using low-jitter CMOS technology. The input stage circuit of the clock buffer can employ an on-chip integrated passive RC network or an active G_m-C filter, with its center frequency optimized according to the system's required reference clock frequency to effectively filter out out-of-band noise. The shaping stage circuit can consist of a multi-stage high-speed CMOS inverter chain combined with Schmitt triggers, ensuring that the rise and fall times of the output signal are both less than 1 nanosecond, thus providing a clear digital clock edge. The driver stage circuit can employ a multi-stage parallel CMOS inverter or differential driver, providing sufficient current drive capability to ensure that signal integrity is not affected when driving two phase-locked loop (PLL) frequency synthesizers. The processed reference clock signal is simultaneously distributed to the reference clock inputs of the first and second PLL frequency synthesizers through a carefully designed low-skew clock tree network within the chip, ensuring that the skew between the clock signals received by the two PLLs is less than 5 picoseconds, thereby maximizing clock synchronization.

[0025] Through the above technical solution, this application effectively solves the problems of poor quality of external reference clock signals and insufficient driving capability leading to instability in the operation of the two-channel PLL frequency synthesizers and damage to the frequency and phase accuracy of the local oscillator signal. By performing bandpass filtering, edge shaping, and driving capability enhancement processing on the reference clock signal inside the RF analog-to-digital chip, the reference clock signal provided to the two-channel PLL frequency synthesizers is ensured to have high purity, steep edges, and sufficient driving capability. This significantly improves the generation quality and stability of the first-band local oscillator signal and the second-band local oscillator signal, providing a reliable foundation for subsequent initial phase relationship establishment and accurate phase difference measurement. This ensures the accuracy and reliability of the entire multi-band frequency generation collaborative calibration method, meets the requirements of application scenarios with strict phase requirements, and simplifies external circuit design.

[0026] S2: In response to the system synchronization trigger signal, the radio frequency analog-to-digital chip resets the frequency dividers on the output paths of the first frequency band local oscillator signal and the second frequency band local oscillator signal to a preset initial counting state, and establishes an initial phase relationship between the first frequency band local oscillator signal and the second frequency band local oscillator signal.

[0027] For details, please refer to Figure 2 Step S2 includes: S21: Receive system synchronization trigger signal sent by an external system.

[0028] Radio frequency analog-to-digital chips (RF analog-to-digital chips) receive synchronization commands from external control systems through their dedicated input pins or general-purpose input / output (GPIO) ports. This signal can be a single pulse or a sustained level signal, and its function is to initiate or coordinate specific operations within the chip, such as the synchronous reset of a local oscillator divider.

[0029] S22: The system synchronization trigger signal is sent to the built-in synchronization trigger of the RF analog-to-digital chip for synchronization with the reference clock signal, eliminating the metastability risk between the trigger signal and the reference clock.

[0030] Synchronous flip-flops utilize the stable periodicity of a reference clock signal to sample and delay the asynchronous input system's synchronous trigger signal, ensuring that their output signal is strictly synchronized with the reference clock signal. This effectively avoids metastability caused by asynchronous signals directly acting on synchronous logic, i.e., the flip-flop output remaining in an uncertain state for too long, thus triggering erroneous behavior in subsequent circuits.

[0031] S23: A global synchronous reset signal aligned with the rising edge of the reference clock signal is generated by a synchronous flip-flop; After processing by the synchronous flip-flop, a reset signal is generated that is precisely aligned with the rising edge of the reference clock signal in time. This signal is synchronous, stable, and has well-defined timing characteristics, and can serve as a unified reset source for all modules within the chip that require synchronous reset.

[0032] S24: Simultaneously send the global synchronization reset signal to the first output divider on the first frequency band local oscillator signal output path and the second output divider on the second frequency band local oscillator signal output path.

[0033] The synchronous reset signal is distributed to two independent output dividers via a low-skew wiring network or a dedicated clock / reset tree structure within the chip. This distribution mechanism aims to minimize delay differences along the signal transmission path, ensuring that the signals arrive at the two dividers almost simultaneously.

[0034] S25: Enables both output dividers to receive the reset command simultaneously at the rising edge of the same reference clock.

[0035] Ensure that the first and second output dividers receive and respond to the reset command simultaneously when the same valid edge (e.g., rising edge) of the reference clock arrives, thereby achieving precise synchronous reset operation.

[0036] The RF analog-to-digital chip can be configured with a synchronous flip-flop consisting of two cascaded D flip-flops. The system synchronization trigger signal sent from an external system is first input to the D terminal of the first D flip-flop, whose clock terminal is connected to a reference clock signal. The Q terminal output of the first D flip-flop is then connected to the D terminal of the second D flip-flop, whose clock terminal is also connected to the reference clock signal. Thus, after two reference clock cycles, the synchronous version of the system synchronization trigger signal is output from the Q terminal of the second D flip-flop, forming a global synchronization reset signal strictly aligned with the rising edge of the reference clock signal. To ensure that this global synchronization reset signal can be sent simultaneously to the first and second output dividers, a dedicated low-skew reset signal distribution network can be used internally. This network consists of matched buffers and equal-length wiring to minimize signal transmission delay differences. For example, a reset signal driver can be used, whose output is connected to the reset input terminals of the first and second output dividers via two physically matched traces, respectively.

[0037] By sending the external system's synchronization trigger signal to the built-in synchronization flip-flop of the RF analog-to-digital chip for synchronization processing, a global synchronization reset signal strictly aligned with the rising edge of the reference clock signal is generated. This signal is then simultaneously sent to two output dividers, ensuring that both dividers receive the reset command at the same rising edge of the reference clock. This fundamentally eliminates the initial phase randomness caused by reset timing deviations, providing a reliable timing basis for establishing a precise and controllable initial phase relationship between the first and second frequency band local oscillator signals. This significantly improves the accuracy and stability of multi-band frequency generation and collaborative calibration.

[0038] Specifically, step S2 also includes: The reset target count state of the two output frequency dividers is pre-configured to a zero count state via register configuration; Upon receiving the global synchronization reset signal, the first and second output frequency dividers immediately clear all bits of their internal counters. When the first and second output frequency dividers receive the global synchronization reset signal, they immediately perform a clearing operation, setting all bits of their internal counters to logic zero. Internally, a synchronous reset logic can be designed within the frequency divider to directly drive the counter clearing port when the global synchronization reset signal is valid, ensuring that it completes the clearing at the next clock edge.

[0039] After the reset is complete, both output frequency dividers start from the all-zero counting state simultaneously and divide the PLL output signal according to their respective division ratios. Once the internal counter is cleared, the first and second output frequency dividers will start from this unified all-zero counting state and divide the output signal from their respective PLL frequency synthesizers according to their respective preset division ratios.

[0040] This ensures that the first and second frequency band local oscillator signals are simultaneously and continuously output from the same phase zero point within the first reference clock cycle after reset. By ensuring that the two frequency dividers start dividing from a unified all-zero counting state, it is possible to ensure that their respective output first and second frequency band local oscillator signals both start from a common, predefined phase zero point within the first reference clock cycle after reset. This means that the initial phases of the two local oscillator signals are strictly aligned, eliminating random initial phase differences.

[0041] During the initialization phase of the RF analog-to-digital converter (ADC), the calibration control unit can send configuration commands to the ADC via a high-speed serial interface. These commands are written into specific configuration registers within the ADC, such as the "divider reset target configuration register." For the first and second output dividers, their corresponding register bit fields are set to binary "00...00," indicating a zero-count state. When the system needs to perform initial phase calibration of the local oscillator signal, the system synchronization trigger signal is input through the ADC's system synchronization trigger interface. This signal is processed by the chip's internal synchronization flip-flops to generate a global synchronization reset signal that is strictly aligned with the rising edge of the reference clock signal. This global synchronization reset signal is simultaneously sent to the reset control logic within the first and second output dividers. On the next rising edge of the reference clock after receiving the global synchronization reset signal, the counters within both dividers are immediately forced to zero. For example, if the dividers use binary counters, the flip-flop outputs of all count bits will be set low. After the reset is complete, the two frequency dividers immediately start counting and dividing the input signal from a counter value of 0. Based on the frequency output by their respective phase-locked loop frequency synthesizers and the preset division ratio (e.g., the first output divider has a division ratio of N1, and the second output divider has a division ratio of N2), they begin counting and dividing the input signal. Since they both start counting from 0 and the reset actions are synchronized, the starting points of the first and second cycle of their respective first-band local oscillator signals will be strictly aligned, allowing them to continuously output from the same phase zero point simultaneously within the first reference clock cycle after the reset.

[0042] S3: The first frequency band local oscillator signal and the second frequency band local oscillator signal are input to the same internal mixer through the internal loopback path. After mixing and low-pass filtering, the difference frequency signal is obtained. The phase of the difference frequency signal is extracted by fast Fourier transform operation. Based on the unified initial phase reference, the unambiguous actual relative phase difference between the first frequency band local oscillator signal and the second frequency band local oscillator signal is calculated according to the phase value of the difference frequency signal.

[0043] Specifically, the step of inputting the first frequency band local oscillator signal and the second frequency band local oscillator signal into the same internal mixer through an internal loopback path includes: An internal loopback test enable command is generated. Based on this command, the first multiplexer switch inside the RF analog-to-digital chip is activated to disconnect the external output pin of the first frequency band local oscillator signal. This explicitly instructs the chip to enter the internal signal path configuration state required for phase calibration. Controlling the first multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the first frequency band local oscillator signal means that the first multiplexer switch, which acts as an electronic switch within the RF analog-to-digital chip for switching the output path of the first frequency band local oscillator signal, is activated upon receiving the internal loopback test enable command. Its function is to disconnect the first frequency band local oscillator signal from the default external output pin, preventing signal flow to the outside, thereby ensuring signal integrity and preparing for the establishment of the internal loopback path.

[0044] Control the operation of the second multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the second frequency band local oscillator signal; The first multiplexer switches the first frequency band local oscillator signal to the first dedicated loopback test channel inside the chip. The first multiplexer further switches the output path of the first frequency band local oscillator signal to the first preset dedicated loopback test channel inside the chip. This channel is a dedicated signal transmission path designed inside the chip for phase calibration purposes. Its characteristics include a short path, good impedance matching, and small parasitic parameters, aiming to minimize additional phase errors and losses introduced during signal transmission.

[0045] The second multiplexer switches the second frequency band local oscillator signal to the second dedicated loopback test channel inside the chip. After disconnecting the external output pin, the second multiplexer switches the output path of the second frequency band local oscillator signal to the preset second dedicated loopback test channel inside the chip. This channel is also a dedicated signal transmission path designed for phase calibration purposes, and has similar optimized characteristics to the first dedicated loopback test channel to ensure that the phase error introduced by the two local oscillator signals during internal transmission is minimized and controllable.

[0046] The first frequency band local oscillator signal is input to the first input terminal of the internal mixer via a dedicated loopback test channel. Once the first frequency band local oscillator signal is switched to the dedicated loopback test channel, the channel directly routes the signal to the first input terminal of the RF analog-to-digital converter (ADC) inside the chip. This direct connection method avoids environmental interference and impedance mismatch problems that may be encountered when the signal is transmitted outside the chip, ensuring that the first frequency band local oscillator signal enters the mixer with its original phase characteristics.

[0047] The second-band local oscillator signal is input to the second input terminal of the internal mixer via a second dedicated loopback test channel. This design ensures that the relative phase relationship of the two local oscillator signals will not be unnecessarily interfered with or changed due to differences in the external transmission path before entering the mixer for phase comparison, thus laying the foundation for subsequent accurate phase difference measurement.

[0048] When performing multi-band frequency generation and collaborative calibration on an RF analog-to-digital converter (ADC), the internal loopback path can be established in the following way. The calibration control unit can write a preset configuration word into a specific register of the RF ADC via a serial peripheral interface. This configuration word is the internal loopback test enable instruction. For example, bit 0 of register address 0x100 can be set to 1 to enable the internal loopback test mode. When the chip receives this instruction, its internal digital control logic drives the first and second multiplexer switches. These switches can be an RF CMOS switch array integrated inside the chip. Specifically, the first multiplexer switch first disconnects the first band local oscillator signal from the external RF_OUT1 pin of the chip and switches the signal to an internal microstrip line or coplanar waveguide structure, which is the first dedicated loopback test channel. Similarly, the second multiplexer switch disconnects the second band local oscillator signal from the external RF_OUT2 pin of the chip and switches it to the second dedicated loopback test channel. These two dedicated loopback test channels are designed with tightly matched propagation delay and impedance characteristics to ensure that the phase difference introduced by the two local oscillator signals during internal transmission is minimized. Ultimately, the output of the first dedicated loopback test channel is directly connected to the LO input of the internal mixer, while the output of the second dedicated loopback test channel is directly connected to the RF input of the internal mixer. In this way, the two local oscillator signals are precisely routed to the mixer for phase comparison without leaving the chip package, thus providing a high-precision signal source for subsequent phase difference measurement and calibration.

[0049] By implementing loopback path switching for the local oscillator signal within the RF analog-to-digital chip, the relative phase relationship between the two local oscillator signals is ensured to remain unchanged during phase measurement due to external traces, interfaces, or environmental factors. This allows the signal received by the mixer to accurately reflect the phase characteristics of the local oscillator signal within the chip, significantly improving the accuracy of difference frequency signal phase extraction. This provides a reliable foundation for subsequent phase deviation calculation and digital phase compensation, ultimately guaranteeing the accuracy and reliability of multi-band local oscillator phase calibration.

[0050] Specifically, the low-pass filtering of the mixing signal includes: Based on the preset frequencies of the first and second band local oscillator signals, the difference frequency of the two local oscillator signals is pre-calculated; before the actual filtering operation, the precise frequency of the target difference frequency signal is determined. Its purpose is to provide an accurate basis for the subsequent parameter settings of the programmable low-pass filter, avoiding blind configuration. Specifically, this can be achieved through a software algorithm, where the difference frequency is obtained by performing a simple subtraction operation based on the preset local oscillator frequency value in the calibration control unit.

[0051] The cutoff frequency of the programmable low-pass filter built into the RF analog-to-digital chip is set to a value higher than the difference frequency signal frequency by configuring the register; the mixed signal containing the sum frequency component, difference frequency component and spurious components output from the internal mixer is input to the programmable low-pass filter; the high-frequency sum frequency component and out-of-band spurious interference components in the mixed signal are filtered out by the programmable low-pass filter; the programmable low-pass filter outputs a clean difference frequency signal containing only the difference frequency component.

[0052] When performing low-pass filtering on a mixed signal, the following steps can be followed. First, the calibration control unit stores multiple preset frequency combinations of the first and second band local oscillator signals. When phase calibration is required, the system selects the appropriate local oscillator frequency combination based on the current operating mode; for example, the preset frequency of the first band local oscillator signal is 10 GHz, and the preset frequency of the second band local oscillator signal is 9.9 GHz. The processor of the calibration control unit immediately calculates the difference frequency of the two local oscillator signals to be 100 MHz. Next, the calibration control unit sends a configuration command to the programmable low-pass filter inside the RF analog-to-digital chip via the Serial Peripheral Interface (SPI). This command sets the filter's cutoff frequency to, for example, 120 MHz based on the calculated 100 MHz difference frequency. The programmable low-pass filter built into the RF analog-to-digital chip can be a fifth-order Butterworth filter, whose cutoff frequency can be adjusted in steps via internal digital control words. Subsequently, after the internal mixer mixes the first-band local oscillator signal and the second-band local oscillator signal, its output signal contains a 20GHz sum frequency component, a 100MHz difference frequency component, and other spurious components. This mixed signal is routed to a programmable low-pass filter configured with a cutoff frequency of 120MHz. The filter effectively attenuates the 20GHz sum frequency component and other spurious components above 120MHz. Ultimately, the signal output from the programmable low-pass filter is a clean signal primarily containing a 100MHz difference frequency component, with its high-frequency sum frequency component and out-of-band spurious interference significantly suppressed. This clean difference frequency signal is then fed into an analog-to-digital converter for digitization, followed by Fast Fourier Transform (FFT) phase extraction.

[0053] By pre-calculating the difference frequency signal frequency and adaptively configuring the cutoff frequency of the programmable low-pass filter, the target difference frequency signal is ensured to pass through completely and without loss, while efficiently filtering out high-frequency and low-frequency components as well as out-of-band spurious interference. This significantly improves the purity of the difference frequency signal, providing a high-quality input signal for subsequent fast Fourier transform phase extraction. This greatly improves the accuracy of calculating the unambiguous actual relative phase difference between the first and second frequency band local oscillator signals, thereby ensuring the accuracy and reliability of the entire multi-band frequency generation and collaborative calibration method. This dynamic adaptive filtering strategy allows the initial phase calibration of the local oscillator signal to adapt to application scenarios with different frequency combinations, enhancing the system's flexibility and robustness.

[0054] Specifically, step S3 includes: Select a Hanning window function suitable for phase measurement from the preset window function library, and collect time-domain sampling data of the difference frequency signal of preset length; The time-domain sampled data of the acquired difference frequency signal is multiplied point by point with the Hanning window function. The point-by-point multiplication operation means multiplying each sampling point in the time-domain sampled data sequence of the difference frequency signal with each point in the coefficient sequence of the corresponding Hanning window function.

[0055] Complete the time-domain windowing processing of the difference frequency signal; Suppressing the inherent spectral leakage phenomenon in Fast Fourier Transform (FFT) operations improves the accuracy and stability of subsequent phase extraction.

[0056] In the calibration control unit of the RF analog-to-digital chip, a digital signal processor (DSP) or a field-programmable gate array (FPGA) module can be integrated to perform phase extraction of the difference frequency signal. A window function library, containing coefficient tables for various window functions such as the Hanning window and Hamming window, is pre-stored in the non-volatile memory of the DSP or FPGA. When phase measurement is required, the calibration control unit sends a command to the DSP / FPGA to load the coefficient sequence of the Hanning window function from the window function library. Simultaneously, the analog-to-digital converter (ADC) inside the RF DSP samples the low-pass filtered difference frequency signal at a preset sampling rate (e.g., 100MHz) and converts the continuous analog signal into digital time-domain sampled data of a preset length (e.g., 1024 points). This data can be stored in the internal RAM of the DSP / FPGA. The DSP / FPGA then performs point-by-point multiplication, multiplying the time-domain sampled data of the difference frequency signal stored in RAM with the loaded Hanning window function coefficient sequence at corresponding positions.

[0057] For example, if the nth sample value of the difference frequency signal is S[n] and the nth coefficient of the Hanning window function is W[n], then the windowed data is S_w[n] = S[n] * W[n]. After multiplying all sample points, the time-domain windowing processing of the difference frequency signal is completed. This windowed data will be used as input to the Fast Fourier Transform (FFT) module inside the DSP / FPGA for spectrum analysis, thereby obtaining more accurate phase information of the difference frequency signal.

[0058] By introducing time-domain windowing, and especially by selecting the Hanning window function suitable for phase measurement, spectral leakage is effectively suppressed. This results in a more concentrated main lobe and significantly reduced sidelobe energy in the difference frequency signal after Fast Fourier Transform, thereby greatly improving the accuracy and stability of subsequent phase extraction. In the entire multi-band frequency generation and collaborative calibration method, accurate difference frequency signal phase extraction is a crucial step in calculating the unambiguous actual relative phase difference. The implementation of this scheme ensures that the calculated actual relative phase difference is more reliable and accurate, thus providing a solid foundation for subsequent phase deviation calculation and the writing of digital phase compensation values. Ultimately, this enables the initial phase calibration between the first and second band local oscillator signals to achieve higher accuracy, effectively avoiding system performance degradation caused by phase errors.

[0059] S4: Compare the actual relative phase difference with the preset target phase difference to obtain the phase deviation. Based on the phase deviation and the digital phase compensation step accuracy of the local oscillator channel corresponding to the RF analog-to-digital chip, calculate the compensation value that needs to be written into the digital phase compensation register of the corresponding local oscillator channel. Specifically, step S4 includes: A fixed-point Fast Fourier Transform is performed on the windowed difference frequency signal time-domain data to obtain the complex form discrete spectrum data corresponding to the difference frequency signal. The amplitude value corresponding to each frequency point in the discrete spectrum data is calculated. The frequency point with the largest amplitude value is searched in the discrete spectrum data, and this frequency point is the frequency point corresponding to the difference frequency signal. The complex phase value corresponding to the frequency point with the largest amplitude is extracted as the original phase value of the difference frequency signal.

[0060] Within the digital signal processing module of the RF analog-to-digital chip, a dedicated hardware accelerator or programmable gate array (FPGA) can be used to implement the Fast Fourier Transform (FFT) operation. For example, a 1024-point or 2048-point FFT processor can be configured to process the time-domain sampled data of the difference frequency signal after processing with the Hanning window function. The discrete spectrum data output by this FFT processor can be stored in internal registers or memory in complex form, with each frequency point corresponding to a complex number containing real and imaginary parts. Subsequently, an amplitude calculation unit can calculate the amplitude value of each complex point in parallel or serially, for example, by using a lookup table or hardware multipliers and adders to perform square and square root operations. A peak detection logic unit can iterate through these amplitude values ​​and record the maximum amplitude value and its corresponding frequency index. Finally, a phase calculation unit can calculate the original phase value of the difference frequency signal based on the real and imaginary parts of the complex number corresponding to the maximum amplitude frequency point by calling a hardware implementation of an arctangent function (such as `atan2`). These calculation results can be stored in specific registers for subsequent phase difference calculations and compensation value generation.

[0061] This precise frequency positioning and phase extraction mechanism ensures high accuracy of the original phase value of the obtained difference frequency signal, providing a reliable foundation for subsequent calculation of the unambiguous actual relative phase difference between the first and second frequency band local oscillator signals. Ultimately, this scheme significantly improves the accuracy and stability of the initial phase calibration of multi-band local oscillator signals, enabling it to meet the requirements of application scenarios with extremely stringent phase consistency requirements, such as phased array radars and multi-channel receivers.

[0062] S5: Write the compensation value into the digital phase compensation register through the serial peripheral interface, adjust the phase of the corresponding local oscillator channel according to the compensation value, until the initial phase calibration is completed and the two calibrated local oscillator signals enter the normal working state.

[0063] Specifically, step S5 includes: The valid digital compensation value is written to the digital phase compensation register of the corresponding local oscillator channel through the serial peripheral interface; the digital compensation value calculated by the external controller is efficiently and accurately transmitted to the digital phase compensation register inside the RF analog-to-digital chip.

[0064] The preset phase-locked loop (PLL) stabilization time is used to allow the local oscillator channel's output phase to complete adjustment and reach a stable state; this is the time required for the PLL frequency synthesizer's output phase to adjust from the old state to the new state and reach stability. This waiting time is set to ensure that the PLL has fully responded to the phase adjustment command and its output phase has stabilized at the new target value before subsequent phase measurements are performed, thus guaranteeing the accuracy and reliability of subsequent measurement results.

[0065] Repeat the phase difference detection procedure to measure the actual relative phase deviation between the two local oscillator signals; Determine whether the phase deviation obtained from this measurement is within the preset allowable range. If the phase deviation is not within the preset allowable range, repeat the compensation value calculation and phase adjustment steps. If the phase deviation is within the preset allowable range, the phase difference detection step is performed again for verification. When the phase deviations obtained from two consecutive measurements are both within the preset allowable range, the initial phase calibration is considered complete. Generate a calibration completion flag signal, disconnect the internal loopback test path, restore the external output paths of the two local oscillator signals, and bring the two local oscillator signals into normal working condition.

[0066] The RF analog-to-digital (ADC) chip can integrate an SPI controller as a serial peripheral interface to receive valid digital compensation values ​​sent by an external calibration control unit. This compensation value can be a 12-bit two's complement representing -2048 to +2047 phase step units, and is written into the digital phase compensation registers of the first and second phase-locked loop (PLL) frequency synthesizers within the RF ADC chip, for example, named "PHASE_OFFSET_REG_1" and "PHASE_OFFSET_REG_2". After writing the compensation value, the system can wait for a preset PLL stabilization time, such as 150 microseconds, to ensure the PLL output phase is completely stable. Subsequently, the calibration control unit will trigger the phase measurement engine within the RF ADC chip again to re-execute the phase difference detection step, measuring the actual relative phase deviation between the two local oscillator signals. The system's preset allowable range can be set to ±0.3 degrees. If the measured phase deviation exceeds this range, the calibration control unit will recalculate the compensation value based on the new measurement results, write it back to the corresponding digital phase compensation register via the SPI interface, and repeat the above process. If the measured phase deviation is within ±0.3 degrees, the system will not immediately determine that the calibration is complete, but will trigger another phase difference detection step for verification. Only when the phase deviations measured twice consecutively are within ±0.3 degrees will the calibration control unit determine that the initial phase calibration is complete, and send a command to the RF analog-to-digital chip to generate a calibration completion flag signal (for example, pull a GPIO pin high). At the same time, the control chip's internal multiplexer switch will disconnect the internal loopback test path, restore the external output paths of the two local oscillator signals, and allow the two local oscillator signals to enter normal working state. Example 2

[0067] Please refer to Figure 3The present invention also provides a multi-band frequency generation and collaborative calibration system based on an RF analog-to-digital chip, the system comprising: a high-precision reference clock source 10, an RF analog-to-digital chip 20, and a calibration control unit 30.

[0068] The high-precision reference clock source 10 is used to provide a high-precision reference clock signal as a unified reference for the generation of the two local oscillator signals, avoiding additional phase deviations introduced by the error of the reference signal itself.

[0069] The RF analog-to-digital chip 20 is electrically connected to the high-precision reference clock source 10. It integrates a first phase-locked loop frequency synthesizer, a second phase-locked loop frequency synthesizer, a mixer, a low-pass filter, an analog-to-digital converter, a system synchronization trigger interface, a digital phase compensation register, and a built-in temperature sensor. It integrates local oscillator generation, phase detection, and adjustment functions into a single chip, reducing delay and interference differences caused by external discrete components and wiring. The calibration control unit 30 is electrically connected to the RF analog-to-digital chip 20 via a high-speed serial interface and a serial peripheral interface. Internally, it integrates non-volatile memory and multiple process modules. The system initialization and synchronization control module 40 controls the system power-on initialization process, generates and sends a system synchronization trigger signal, and controls the synchronous reset operation of the two local oscillator signal dividers, ensuring that the dividers reset to a preset initial counting state at a unified time, thereby establishing the initial phase reference for the two local oscillator signals. The loopback sampling control module 50 controls the on / off state of the internal loopback path of the RF analog-to-digital chip 20, configures the operating parameters of the mixer and analog-to-digital converter, and inputs the first and second frequency band local oscillator signals to the mixer through the internal loopback path. After mixing and low-pass filtering, the difference frequency signal is obtained. The system completes the acquisition and transmission of the signal; the initial phase calibration module 60 performs phase difference measurement, compensation value calculation and register writing operations. It extracts the phase of the difference frequency signal through fast Fourier transform operation, calculates the unambiguous actual relative phase difference in combination with a unified initial phase reference, compares the phase difference with the preset target phase difference to obtain the phase deviation, calculates the compensation value based on the phase deviation and the digital phase compensation step accuracy, and writes the compensation value into the digital phase compensation register through the serial peripheral interface to adjust the local oscillator channel phase until the initial phase calibration is completed; the temperature compensation control module 70 periodically reads the chip temperature data of the built-in temperature sensor, determines whether the temperature change exceeds the threshold, performs the indexing and writing operation of the temperature compensation value, and dynamically corrects the phase shift caused by temperature drift.

[0070] By using the system synchronous trigger interface and the synchronous reset mechanism of the two local oscillator signal dividers, the phase randomness caused by the difference in the reset timing of the dividers is eliminated from the chip power-on initialization stage. At the same time, relying on the loopback path, mixer, and digital phase compensation register integrated inside the RF analog-to-digital chip 20, a closed-loop calibration process is constructed to achieve accurate measurement and digital compensation of the phase difference. Specifically, the system initialization and synchronization control module 40 generates a system synchronous trigger signal to ensure that the two dividers reset at the same time, establishing a unified initial phase reference; the loopback sampling control module 50 activates the internal loopback path of the chip to avoid interference introduced by external testing and ensure the accuracy of the difference frequency signal acquisition; the initial phase calibration module 60 calculates the unambiguous actual relative phase difference based on the phase of the difference frequency signal and performs high-precision step adjustment through the digital phase compensation register to bring the phase deviation to within the preset tolerance; the temperature compensation control module 70 maintains the phase stability under long-term working conditions through periodic temperature monitoring and compensation value writing.

[0071] Furthermore, the high-precision reference clock source 10 provides a stable benchmark, the integrated design of the RF analog-to-digital chip 20 eliminates external path differences, and the modular process of the calibration control unit 30 ensures the automation and repeatability of the calibration operation. Compared with traditional independent phase-locked loop solutions, this system effectively solves the problem of initial phase randomness, enabling the two local oscillator signals to maintain a preset fixed phase relationship over a long period of time. This significantly improves the frequency accuracy and phase consistency of the RF analog-to-digital chip 20 in high-precision applications such as phased array radar. At the same time, the configuration of non-volatile memory ensures that calibration parameters are not lost when power is off, simplifying the system usage process.

[0072] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0073] Furthermore, the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multi-band frequency generation and collaborative calibration method based on an RF analog-to-digital chip, characterized in that, Includes the following steps: S1: Receive a reference clock signal; a first phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a first-band local oscillator signal according to the reference clock signal; a second phase-locked loop frequency synthesizer based on an RF analog-to-digital chip generates a second-band local oscillator signal according to the reference clock signal. S2: In response to the system synchronization trigger signal, the radio frequency analog-to-digital chip resets the frequency dividers on the output paths of the first frequency band local oscillator signal and the second frequency band local oscillator signal to a preset initial counting state, and establishes an initial phase relationship between the first frequency band local oscillator signal and the second frequency band local oscillator signal; S3: The first frequency band local oscillator signal and the second frequency band local oscillator signal are input to the same internal mixer through the internal loopback path. After mixing and low-pass filtering, the difference frequency signal is obtained. The phase of the difference frequency signal is extracted by fast Fourier transform operation. Based on the unified initial phase reference, the unambiguous actual relative phase difference between the first frequency band local oscillator signal and the second frequency band local oscillator signal is calculated according to the phase value of the difference frequency signal. S4: Compare the actual relative phase difference with the preset target phase difference to obtain the phase deviation. Based on the phase deviation and the digital phase compensation step accuracy of the local oscillator channel corresponding to the RF analog-to-digital chip, calculate the compensation value that needs to be written into the digital phase compensation register of the corresponding local oscillator channel. S5: Write the compensation value into the digital phase compensation register through the serial peripheral interface, adjust the phase of the corresponding local oscillator channel according to the compensation value, until the initial phase calibration is completed and the two calibrated local oscillator signals enter the normal working state.

2. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S1 includes: The externally input reference clock signal is sent to the dedicated clock buffer built into the RF analog-to-digital chip; The reference clock signal is bandpass filtered by the input stage circuit of the clock buffer to remove low-frequency noise and high-frequency interference from the input signal. The filtering reference clock signal is edge-shaped by the shaping stage circuit of the clock buffer, converting the non-ideal square wave into a standard square wave signal with steep rising and falling edges. The driving capability of the shaped reference clock signal is enhanced by the driver stage circuit of the clock buffer, so that it can stably drive two independent phase-locked loop frequency synthesizers at the same time. The processed reference clock signal is simultaneously output to the reference clock input terminals of the first phase-locked loop frequency synthesizer and the second phase-locked loop frequency synthesizer.

3. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S2 includes: Receive system synchronization trigger signals sent by external systems; The system synchronization trigger signal is sent to the built-in synchronization trigger of the RF analog-to-digital chip for synchronization with the reference clock signal, eliminating the metastability risk between the trigger signal and the reference clock. A global synchronous reset signal, strictly aligned with the rising edge of the reference clock signal, is generated by a synchronous flip-flop. The global synchronization reset signal is simultaneously sent to the first output divider on the first frequency band local oscillator signal output path and the second output divider on the second frequency band local oscillator signal output path; This ensures that both output dividers receive the reset command simultaneously at the rising edge of the same reference clock.

4. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S2 also includes: The reset target count state of the two output frequency dividers is pre-configured to a zero count state via register configuration; After receiving the global synchronization reset signal, the first and second output frequency dividers clear all bits of the internal counter. After the reset is complete, both output frequency dividers start from the all-zero counting state simultaneously and divide the phase-locked loop output signal according to their respective division ratios; This ensures that the local oscillator signals of the first and second frequency bands are simultaneously and continuously output from the same phase zero point within the first reference clock cycle after the reset is completed.

5. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, The step of inputting the first frequency band local oscillator signal and the second frequency band local oscillator signal into the same internal mixer through an internal loopback path includes: Generate an internal loopback test enable command, and control the first multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the local oscillator signal in the first frequency band according to the internal loopback test enable command. Control the operation of the second multiplexer switch inside the RF analog-to-digital chip to disconnect the external output pin of the second frequency band local oscillator signal; Control the first multiplexer switch to switch the local oscillator signal of the first frequency band to the first dedicated loopback test channel inside the chip; The second multiplexer switch is controlled to switch the second frequency band local oscillator signal to the second dedicated loopback test channel inside the chip. The local oscillator signal of the first frequency band is input to the first input terminal of the internal mixer through the first dedicated loopback test channel; The second frequency band local oscillator signal is input to the second input terminal of the internal mixer through the second dedicated loopback test channel.

6. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, The low-pass filtering of the mixed signal includes: Based on the preset frequency of the local oscillator signal in the first frequency band and the preset frequency of the local oscillator signal in the second frequency band, the difference frequency signal frequency of the two local oscillator signals is calculated in advance. The cutoff frequency of the programmable low-pass filter built into the RF analog-to-digital chip can be set to a value higher than the difference frequency signal frequency by configuring the register. The mixed signal, which includes sum frequency, difference frequency and spurious components, output from the internal mixer is input to the programmable low-pass filter. High-frequency and low-frequency components, as well as out-of-band spurious interference components, are filtered out in the mixing signal by a programmable low-pass filter. The programmable low-pass filter outputs a pure difference frequency signal containing only the difference frequency component.

7. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S3 includes: Select a Hanning window function suitable for phase measurement from the preset window function library; Collect time-domain sampling data of the difference frequency signal of a preset length; The time-domain sampled data of the acquired difference frequency signal are multiplied point by point with the Hanning window function; Complete the time-domain windowing processing of the difference frequency signal; Suppressing the inherent spectral leakage phenomenon in Fast Fourier Transform (FFT) operations improves the accuracy and stability of subsequent phase extraction.

8. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S4 includes: Perform a fixed-point Fast Fourier Transform operation on the time-domain data of the windowed difference frequency signal; Obtain the complex form of discrete spectrum data corresponding to the difference frequency signal; Calculate the amplitude value corresponding to each frequency point in the discrete spectrum data; Search for the frequency point with the largest amplitude value in the discrete spectrum data; this frequency point is the frequency point corresponding to the difference frequency signal. Extract the complex phase value corresponding to the maximum amplitude frequency point as the original phase value of the difference frequency signal.

9. The multi-band frequency generation and collaborative calibration method for RF analog-to-digital chips according to claim 1, characterized in that, Step S5 includes: The valid digital compensation value is written into the digital phase compensation register of the corresponding local oscillator channel through the serial peripheral interface. Wait for the preset phase-locked loop stabilization time to allow the output phase of the local oscillator channel to complete the adjustment and enter a stable state; Repeat the phase difference detection procedure to measure the actual relative phase deviation between the two local oscillator signals; Determine whether the phase deviation obtained from this measurement is within the preset allowable range. If the phase deviation is not within the preset allowable range, repeat the compensation value calculation and phase adjustment steps. If the phase deviation is within the preset allowable range, the phase difference detection step is performed again for verification. When the phase deviations obtained from two consecutive measurements are both within the preset allowable range, the initial phase calibration is considered complete. Generate a calibration completion flag signal, disconnect the internal loopback test path, restore the external output paths of the two local oscillator signals, and bring the two local oscillator signals into normal working condition.

10. A multi-band frequency generation and collaborative calibration system based on an RF analog-to-digital chip, characterized in that, The system for performing the method according to any one of claims 1 to 9, the system comprising: A high-precision reference clock source is used to provide a high-precision reference clock signal; The radio frequency analog-to-digital chip is electrically connected to the high-precision reference clock source and integrates a first phase-locked loop frequency synthesizer, a second phase-locked loop frequency synthesizer, a mixer, a low-pass filter, an analog-to-digital converter, a system synchronization trigger interface, a digital phase compensation register, and a built-in temperature sensor. The calibration control unit is electrically connected to the RF analog-to-digital chip via a high-speed serial interface and a serial peripheral interface, and internally integrates non-volatile memory and multiple process processing modules. The system initialization and synchronization control module is used to control the system power-on initialization process, generate and send the system synchronization trigger signal, and control the synchronous reset operation of the two local oscillator signal dividers. The loopback sampling control module is used to control the on / off state of the loopback path inside the RF analog-to-digital chip, configure the operating parameters of the mixer and analog-to-digital converter, and complete the acquisition and transmission of the difference frequency signal. The initial phase calibration module is used to perform phase difference measurement, compensation value calculation and register writing operations to complete the initial phase calibration of the two local oscillator signals; The temperature compensation control module is used to periodically read the chip temperature data, determine whether the temperature change exceeds the threshold, and perform indexing and writing operations for the temperature compensation value.

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