A radio frequency signal correction method and system for 5G communication devices

Abstract

This invention discloses a method and system for radio frequency (RF) signal calibration of 5G communication equipment. The method includes generating a dwell calibration RF signal composed of idle, phase-hold, amplitude-step, frequency-dwell, and power-dwell segments in sequence and saving a segment reference table; then extracting the coupled readback signal via a coupler, calculating the sampling amplitude, phase, frequency offset, power reading, and current value of the hardware register; calculating the propagation delay using the amplitude transition position between the idle and phase-hold segments and correcting the segment boundaries to cut out the effective sampling interval; calculating the amplitude difference, phase difference, frequency offset, and power compression state of the segments, determining the deviation attributed to the controlled object based on the amplitude difference direction, power compression state, phase alignment, and cumulative state, generating correction values, and sequentially writing them into the hardware registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-calibration unit. This invention improves RF calibration efficiency and amplitude-phase consistency of the transmitted signal.

Description

Technical Field

[0001] This invention relates to the field of radio frequency communication signal processing technology, and in particular to a radio frequency signal correction method and system for 5G communication equipment. Background Technology

[0002] The field of radio frequency (RF) communication signal processing technology involves the generation, frequency conversion, power amplification, coupling detection, amplitude and phase measurement, and parameter calibration of RF signals in 5G millimeter-wave communication equipment. Traditional RF signal calibration methods and systems for 5G communication equipment involve a baseband processor generating a reference signal, which is then converted into a millimeter-wave RF output via a digital-to-analog converter, up-converter, filter, and power amplifier. A coupler extracts a feedback signal from the transmit link and sends it to a down-conversion channel or vector signal analysis unit. The processor calculates the correction amount based on the amplitude, phase, frequency, and power deviations between the reference signal and the feedback signal, and writes the correction amount into the control parameters of a digital pre-calibration unit, gain controller, phase shifter, or frequency synthesizer.

[0003] Existing RF link calibration methods mostly rely on conventional continuous frequency sweeps or single-point readings. Segment boundaries and link propagation delays are difficult to align, amplitude, phase, frequency, and power response are mixed into the same observation results, deviation directions in low and high amplitude states lack segmented references, compression changes during high power dwell are difficult to identify in a timely manner, control register writing is based on bias experience adjustment, it is difficult to match the dynamic error characteristics of multiple states coexisting, it is easy to cause confusion in the judgment of deviation sources, repeated trial and error of correction amount, decreased calibration efficiency, and affected transmission signal consistency and stability. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for radio frequency signal correction for 5G communication devices.

[0005] The technical solution adopted in this invention is:

[0006] A method and system for radio frequency (RF) signal correction in 5G communication equipment is disclosed. The RF transmission link of the 5G communication equipment includes, in sequence, a digital-to-analog converter module, an up-conversion module, a gain controller, a phase shifter, a frequency synthesizer, a power amplifier, and a coupler located at the output end. The method includes the following steps:

[0007] Based on the calibration task, a dwell calibration RF signal consisting of an idle segment, a phase hold segment, an amplitude step segment, a frequency dwell segment, and a power dwell segment is generated and input into the digital-to-analog converter module; at the same time, a segment reference table is established based on the calibration task. The segment reference table records the boundary time, target amplitude, target phase, target frequency, target power, and deviation judgment threshold determined by the target data for each segment.

[0008] The resident calibration RF signal is output through the RF transmit link, and then the coupler at the output end extracts the coupled RF signal. The coupled RF signal is then frequency-shifted and sampled and held according to the local oscillator reference signal by the down-conversion channel to generate the coupled readback signal. The sampling amplitude, sampling phase, sampling frequency offset, and coupling power reading of the coupled readback signal are read synchronously, as well as the current control values ​​of the hardware control registers of the frequency synthesizer, phase shifter, gain controller and digital pre-calibration unit.

[0009] Locate the sampling amplitude transition position between the idle segment and the phase-holding segment in the coupled readback signal (sampling amplitude sequence), calculate the time difference between the sampling amplitude transition position and the starting boundary time of the phase-holding segment in the segment reference table as the propagation delay, perform same-direction translation correction on all segment boundary times in the segment reference table based on the propagation delay, and cut out the effective sampling interval of each dwelling segment between the corrected boundary times.

[0010] Based on the effective sampling interval of each dwell segment, the amplitude difference between the sampling amplitude and the target amplitude, the phase difference between the sampling phase and the target phase, the sampling frequency offset between the sampling frequency and the target frequency, and the power compression state between the sampling power and the target power are calculated for each dwell segment.

[0011] The deviation attribution result is determined based on the direction of the amplitude difference between the low-amplitude dwell segment and the high-amplitude dwell segment, the power compression state under high power conditions, the same-direction state of the phase difference across segments, and the cumulative state of the phase difference. The deviation attribution result is used to select a controlled object from the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit.

[0012] Based on the deviation attribution results, the frequency tuning correction value, phase control correction value, gain control correction value, and pre-correction compensation value are written into the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit, respectively, to adjust the RF parameters of the corresponding hardware.

[0013] Furthermore, the implementation of generating the resident calibration RF signal and establishing the segment reference table includes:

[0014] Obtain calibration task parameters, determine the no-load duration, phase hold duration, amplitude step duration, frequency dwell duration, and power dwell duration based on the calibration task parameters, and establish a segment time series and generate segment boundary times in the order of no-load segment, phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment.

[0015] Based on the time series of segments, target amplitude, target phase, target frequency and target power are written into each segment, and deviation judgment thresholds are determined according to the changes in target amplitude, target frequency and target power between adjacent segments to generate a segment reference table.

[0016] Furthermore, the implementation of determining the deviation judgment threshold from the target data includes:

[0017] Obtain the target amplitude, target phase, target frequency, and target power for each segment, and determine the allowable amplitude deviation range, the allowable phase deviation range, the allowable frequency deviation range, and the allowable power compression range corresponding to the target amplitude, the target phase, the target frequency, and the target power, respectively.

[0018] Establish the correspondence between each segment and the deviation judgment threshold based on the allowable amplitude deviation range, allowable phase deviation range, allowable frequency deviation range, and allowable power compression range, and write the correspondence into the segment reference table.

[0019] Furthermore, the implementation of generating the coupled readback signal includes:

[0020] The coupled RF signal output from the coupler is input into the downconversion channel, and the coupled RF signal is frequency-shifted and sampled and held according to the local oscillator reference signal to generate a coupled readback signal;

[0021] The coupled readback signal is subjected to amplitude envelope extraction, phase expansion processing and frequency offset estimation, and the power detection interface and hardware control bus are read simultaneously to determine the sampling amplitude, sampling phase, sampling frequency offset, coupled power reading and the current control value of the hardware control register.

[0022] Furthermore, the method also includes validity screening of the coupled readback signal, as detailed below:

[0023] Based on the gain state of the downconversion channel and the quantization range of the analog-to-digital converter in the downconversion channel, determine the upper clipping threshold and the lower flooding threshold;

[0024] Each sampling point in the sampling sequence of the coupled readback signal is compared with the upper pruning threshold and the lower flooding threshold. Sampling points whose sampling signal values ​​are greater than the upper pruning threshold or less than the lower flooding threshold are marked as invalid. Sampling points whose number of consecutive valid sampling points reaches the minimum statistical number of the dwell segment are retained as valid readback sampling sequences.

[0025] Furthermore, the implementation of locating the sampling amplitude transition position and calculating the propagation delay includes:

[0026] Based on the target amplitude change direction from the idle segment to the phase-holding segment, the sampling moment in the sampling amplitude sequence of the coupled readback signal where the amplitude continuously increases and reaches the amplitude transition confirmation threshold is found, and this is taken as the sampling amplitude transition position.

[0027] The propagation delay is obtained by subtracting the sampling amplitude transition position from the starting boundary time of the phase-preserving segment in the segment reference table.

[0028] Furthermore, the calculation of amplitude difference, phase difference, sampling frequency offset, and power compression state for each dwell segment includes:

[0029] Obtain the effective sampling interval of each dwell segment and the target amplitude, target phase, target frequency and target power in the segment reference table;

[0030] Within each valid sampling interval, sampling points adjacent to the boundary are removed, and stable statistics are performed on the remaining sampling points to obtain representative values ​​of segment amplitude, segment phase, segment frequency offset, and segment power.

[0031] The segment amplitude representative value, segment phase representative value, segment frequency offset representative value, and segment power representative value are compared with the corresponding target data to generate amplitude difference, phase difference, sampling frequency offset, and power compression status.

[0032] Furthermore, the process of determining the phase difference in the same direction state and the phase difference accumulation state includes:

[0033] The sampling phase within the effective sampling interval of the phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment is obtained, and the phase difference of the sampling phase of each segment is calculated according to the target phase in the segment reference table to generate the segment phase difference of each dwell segment.

[0034] Compare the phase difference direction of adjacent dwelling segments. When the number of segments with the same direction reaches the same direction determination threshold, the phase difference is determined to be in the same direction. Accumulate the change in the phase difference of segments according to the execution order of dwelling segments. When the accumulated change reaches the accumulated determination threshold, the phase difference is determined to be in the accumulated state.

[0035] Furthermore, the generation and writing of frequency tuning correction values, phase control correction values, gain control correction values, and pre-correction compensation values ​​include:

[0036] Obtain the deviation attribution result, the current control value of the hardware control register, the sampling frequency offset, the phase difference, the amplitude difference, and the power compression status. Based on the deviation attribution result, determine the corresponding controlled object and convert the corresponding deviation amount into the register control increment to generate a correction record to be written.

[0037] Based on the correction record to be written, frequency tuning correction values, phase control correction values, gain control correction values, and pre-correction compensation values ​​are generated respectively;

[0038] The correction values ​​are written to the corresponding hardware control registers in the order of writing the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit.

[0039] Furthermore, the present invention also discloses a radio frequency signal correction system for 5G communication devices, which applies the aforementioned radio frequency signal correction method for 5G communication devices. The system includes:

[0040] The calibration signal generation module is used to generate a dwell calibration RF signal consisting of an idle segment, a phase hold segment, an amplitude step segment, a frequency dwell segment, and a power dwell segment in sequence according to the calibration task, and input it into the digital-to-analog converter module; at the same time, it establishes a segment reference table according to the calibration task, which records the boundary time, target amplitude, target phase, target frequency, target power, and deviation judgment threshold determined by the target data for each segment;

[0041] The coupling readback acquisition module is used to acquire the coupled readback signal formed by the coupler after the resident calibration RF signal is output through the transmit link and then through the down-conversion channel, and to determine the sampling amplitude, sampling phase, sampling frequency offset, coupling power reading and the current control value of the hardware control register.

[0042] The delay correction module is used to calculate the propagation delay based on the sampling amplitude transition position between the idle segment and the phase-preserving segment, and to extract the effective sampling interval of each dwelling segment based on the boundary times of each segment in the propagation delay correction segment reference table.

[0043] The deviation attribution analysis module is used to calculate the amplitude difference, phase difference, sampling frequency offset and power compression state based on the effective sampling interval, and to determine the deviation attribution results of the frequency synthesizer, phase shifter, gain controller and digital pre-correction unit according to the amplitude difference direction between the low amplitude dwell segment and the high amplitude dwell segment, the power compression state under the high power state, the phase difference in the same direction state and the phase difference accumulation state.

[0044] The correction writing module is used to generate frequency tuning correction values, phase control correction values, gain control correction values ​​and pre-correction compensation values ​​according to the deviation assignment results, and write them sequentially into the hardware control registers of the frequency synthesizer, phase shifter, gain controller and digital pre-correction unit.

[0045] The present invention adopts the above technical solution and has the following beneficial effects compared with the prior art:

[0046] (1) This invention constructs a sequential dwell calibration RF signal comprising no-load, phase hold, amplitude step, frequency dwell, and power dwell, and pre-stores the boundary time, target amplitude, target phase, target frequency, and target power of each segment, providing a unified physical reference for the time delay alignment and multi-dimensional deviation separation of the subsequent readback signal. The propagation delay is inferred by using the sampling amplitude transition position between the no-load segment and the phase hold segment, and all boundary times in the segment reference table are shifted in the same direction to correct the time, so that the effective sampling interval of each dwell segment is precisely aligned with the actual readback signal in time, eliminating the interference of link propagation delay on segment boundary positioning, thereby ensuring the time consistency of amplitude, phase, frequency, and power measurements.

[0047] (2) This invention calculates the amplitude difference, phase difference, sampling frequency offset, and power compression state separately within the effective sampling interval. Based on the direction of the amplitude difference between the low-amplitude dwell segment and the high-amplitude dwell segment, the power compression state under high power conditions, the same-direction state of the phase difference across segments, and the cumulative state, it distinguishes multiple link error sources that were originally mixed in a single readback observation, thus achieving accurate deviation positioning of four types of hardware controlled objects: frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit. This invention avoids the repeated trial-and-error adjustments caused by the confusion of deviation sources in traditional methods, and significantly shortens the calibration convergence time.

[0048] (3) This invention generates frequency tuning correction values, phase control correction values, gain control correction values, and pre-calibration compensation values ​​according to the deviation attribution results, and writes them sequentially into the corresponding hardware control registers, forming a complete RF calibration link from signal generation, coupling readback, delay correction, deviation separation to register closed-loop writing. This invention effectively improves the amplitude and phase consistency, frequency stability, and power linearity of the 5G communication equipment transmit link, reduces nonlinear compression distortion under high-power operating conditions, and improves the overall efficiency and reliability of RF calibration. Attached Figure Description

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments;

[0050] Figure 1 This is a flowchart illustrating a radio frequency signal correction method for 5G communication devices according to the present invention.

[0051] Figure 2 This is a schematic diagram of the structure of a radio frequency signal correction system for 5G communication equipment according to the present invention;

[0052] Figure 3 This is a schematic diagram illustrating the composition of the calibration radio frequency signal in this invention;

[0053] Figure 4This is a schematic diagram illustrating the generation and writing process of the frequency tuning correction value, phase control correction value, gain control correction value, and pre-correction compensation value in this invention.

[0054] Figure 5 This is a schematic diagram illustrating the principle of register-controlled increment in this invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0056] like Figures 1 to 5 As shown, this invention discloses a method and system for radio frequency (RF) signal calibration of 5G communication equipment. In practical applications, for example, during the continuous RF transmission calibration operation of a 5G communication equipment's transmit link, the baseband calibration control logic injects a resident calibration RF signal into the RF transmit link. This resident calibration RF signal undergoes digital-to-analog conversion, up-conversion, phase shifting, gain control, power amplification, and output coupling to form a readback coupled RF signal. The down-conversion channel generates a coupled readback signal based on a source reference signal. The calibration control logic determines the source of deviation based on the correspondence between the coupled readback signal and the segment reference table, and writes the correction value into the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-calibration unit. The method of this invention includes the following steps.

[0057] S1: Generate a dwell calibration RF signal consisting of an unloaded segment, a phase hold segment, an amplitude step segment, a frequency dwell segment, and a power dwell segment in sequence, and save the resulting segment reference table.

[0058] like Figure 3As shown, the dwell calibration RF signal refers to the RF excitation signal generated in a fixed segment sequence within the same calibration task. It includes an empty segment that does not carry effective transmit energy, a phase-holding segment for maintaining phase reference, an amplitude step segment for forming an amplitude change observation object, a frequency dwell segment for observing frequency offset, and a power dwell segment for observing power compression state. Each segment forms a continuous time series on the baseband side, maintaining the segment order after output via the transmit link. The segment reference table is a data object generated and saved synchronously with the dwell calibration RF signal, carrying the boundary times of each segment, target amplitude, target phase, target frequency, target power, and deviation judgment thresholds determined by the target data. The segment boundary times indicate the start and end positions of each segment within the calibration task; the target amplitude, target phase, target frequency, and target power serve as readback comparison benchmarks; and the deviation judgment thresholds define the judgment boundaries for different deviation states entering the attribution analysis. After generation, the segment reference table is written to the calibration task storage area and is continuously called during subsequent readback acquisition, delay correction, effective interval slicing, deviation attribution, and correction writing stages.

[0059] S101: Obtain calibration task parameters, determine the no-load duration, phase hold duration, amplitude step duration, frequency dwell duration, and power dwell duration based on the calibration task parameters, and establish a segment time series in the order of no-load segment, phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment to generate segment boundary times.

[0060] The calibration task parameters are configuration data read by the RF calibration control logic when the calibration task is started. These parameters originate from the device's factory configuration, the current transmit link operating mode, the calibration task type, and the allowed states of the hardware registers. This configuration data is not directly output as a calculation result; instead, it is used to determine the relative position of each segment in the task time series and the segment switching order. The idle duration is used to retain the readback background when the transmit link has no effective excitation, facilitating subsequent identification of amplitude transitions when moving from an idle segment to a phase-holding segment. The phase-holding duration is used to form a phase comparison interval under a fixed phase reference. The amplitude step duration is used to form an amplitude difference direction judgment interval. The frequency dwell duration is used to form a frequency offset representative value observation interval. The power dwell duration is used to form a power compression state judgment interval.

[0061] When establishing the segment time series, continuous boundary fields are generated according to the segment order already enabled in the calibration task parameters. Each boundary field records the switching position of adjacent segments and the segment identifier to which it belongs. The segment identifier is a data field in the segment reference table used to distinguish between idle segments, phase-hold segments, amplitude-step segments, frequency-stayed segments, and power-stayed segments. It maintains the same recording relationship with the corresponding target amplitude, target phase, target frequency, and target power. If there is no valid boundary record from the previous task when the calibration task starts, the initial boundary fields are generated based on the current calibration task parameters. If there is a boundary record left from the previous task but inconsistent with the current hardware operating state, the boundary fields are regenerated with the current calibration task parameters, and the old boundary record is marked in the task record as not participating in this calibration.

[0062] S102: Based on the segment time series, write the target amplitude, target phase, target frequency and target power for each segment, and determine the deviation judgment threshold according to the change in target amplitude, target frequency and target power between adjacent segments, and generate a segment reference table.

[0063] The target amplitude is the amplitude target field that each segment should maintain at the transmit link input side; the target phase is the phase reference field used for phase comparison of each segment; the target frequency is the frequency reference field corresponding to the frequency-residing segment; and the target power is the power reference field corresponding to the power-residing segment. The above target data originates from calibration task parameters, the current operating mode of the RF link, and the hardware's allowable control range, and is written to the segment reference table along with the segment identifier. When writing the target data, the field source identifier is retained. This identifier indicates whether the target data comes from task configuration, hardware status reading, or the device calibration configuration table. Subsequent deviation analysis reads the field source identifier simultaneously when reading the target data to avoid using historical target data that is incompatible with the current task.

[0064] The deviation judgment threshold is a rule field associated with and stored in the segment reference table, and is not disclosed in the embodiment as an isolated value. The allowable amplitude deviation range is derived from the transmit link amplitude control allowable status, the coupling readback channel gain status, and the amplitude target field of the current calibration task. The allowable phase deviation range is derived from the target phase field of the phase-holding segment, the phase shifter control resolution, and the phase unwinding processing status. The allowable frequency deviation range is derived from the target frequency field, the local oscillator reference signal status, and the frequency synthesizer's allowable tuning boundary. The allowable power compression range is derived from the target power field, the power detection interface status, and the calibration configuration of the power amplification link. The above allowable ranges are written into the segment reference table as threshold fields, which include the source category, applicable segment, update conditions, valid status, and subsequent call location. The target amplitude change, target frequency change, and target power change between adjacent segments are used to determine which segments should enter the amplitude difference direction judgment, frequency offset judgment, and power compression judgment, and the corresponding judgment rules are bound to the segment identifier to form the input for subsequent deviation attribution analysis.

[0065] S2: Obtain the coupled readback signal formed by the coupler after the resident calibration RF signal is output through the transmit link and then through the down-conversion channel, and determine the sampling amplitude, sampling phase, sampling frequency offset, coupling power reading and the current control value of the hardware control register.

[0066] The coupled readback signal refers to the readback sampling sequence formed after being extracted from the output of the transmit link via a coupler, entering the down-conversion channel, and undergoing sample-and-hold processing. The sampling amplitude describes the amplitude envelope of the readback sampling sequence, the sampling phase describes the unfolded phase of the readback sampling sequence relative to the reference phase, the sampling frequency offset describes the offset of the readback sampling sequence relative to the target frequency, the coupled power reading comes from the power detection interface, and the current control value of the hardware control register comes from the hardware control bus. These readback parameters are associated and stored under the same calibration task identifier, enabling subsequent delay correction and deviation attribution stages to read corresponding data according to the same task link.

[0067] S201: Obtain the coupled RF signal extracted from the output of the transmit link by the coupler, input the coupled RF signal into the downconversion channel, and perform frequency shifting and sampling and holding on the coupled RF signal according to the local oscillator reference signal to generate a coupled readback signal.

[0068] A coupler is positioned on the readback path at the output of the transmit link to extract the coupled RF signal corresponding to the transmit link state from the output RF signal. After the coupled RF signal enters the down-conversion channel, the down-conversion channel performs frequency shifting based on the local oscillator reference signal, ensuring the readback signal falls within the sampling processing range. The sample-and-hold process generates a sampling sequence with a continuous task identifier for the shifted signal. This sampling sequence maintains the same task source as the segment time series in the segment reference table. If the down-conversion channel fails to obtain a valid local oscillator reference state, a reference anomaly status identifier is added to the current sampling sequence, and the sequence is prevented from entering the deviation attribution analysis; only the acquisition record used for tracing is retained.

[0069] After the coupled readback signal is generated, the sampling sequence simultaneously carries the acquisition trigger source, channel gain status, sampling status identifier, and task identifier. The acquisition trigger source is used to confirm that the sequence comes from the currently residing calibration RF signal and not from other transmission tasks. The channel gain status is used for subsequent validity screening. The sampling status identifier is used to record whether the sample hold is complete. The task identifier is used to establish an association with the segment reference table, power detection interface readings, and the current control value of the hardware control register. If a segment is missing, sampling is interrupted, or the task identifier is inconsistent during the sample hold process, a readback anomaly status is generated. The anomaly status is written into the calibration task record and serves as the basis for subsequent correction write blocking.

[0070] S202: Perform amplitude envelope extraction, phase expansion processing, and frequency offset estimation on the coupled readback signal, and simultaneously read the power detection interface and hardware control bus to determine the sampling amplitude, sampling phase, sampling frequency offset, coupled power reading, and the current control value of the hardware control register.

[0071] Amplitude envelope extraction uses the sampled sequence of the coupled readback signal as the processing object to generate a sampled amplitude sequence corresponding to the sampling points. Phase unrolling processing uses the same sampled sequence and the local oscillator reference phase as input, eliminating intra-segment breaks caused by phase boundary crossings according to the sampling order, and generating a sampled phase sequence. Frequency offset estimation uses the continuous change state of the sampled phase with the sampling order and the target frequency field as input to form a sampled frequency offset record. All the above processing results retain the same time alignment relationship as the original sampled sequence, so that amplitude, phase, and frequency offset data can be obtained synchronously when subsequently selecting effective sampling intervals.

[0072] The power detection interface reads the coupled power reading corresponding to the transmit link coupling path, while the hardware control bus reads the current control values ​​of the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-calibration unit. The current control values ​​refer to the register states already written to each controlled object before the calibration task is executed, used as the writing reference for determining the control increment when generating subsequent correction values. If the power detection interface returns an incomplete status, the power compression state enters a pending confirmation state; amplitude, phase, and frequency offsets can still continue to form intermediate records, but power-related writes are not performed on the digital pre-calibration unit during the correction writing phase. If the hardware control bus read fails, the current calibration task generates a register read exception status and stops generating the correction records to be written.

[0073] S203: Obtain the gain status of the downconversion channel, the quantization range of the analog-to-digital converter, and the sampling sequence of the coupled readback signal. Determine the upper clipping threshold and the lower flooding threshold based on the gain status and quantization range, and compare each sampling point in the sampling sequence with the upper clipping threshold and the lower flooding threshold respectively.

[0074] Gain status refers to the channel amplification state recorded during sampling in the downconversion channel. Quantization range is the sampling boundary that the analog-to-digital converter can effectively represent for the input sampled signal. The upper clipping threshold is used to identify sampling points where the sampling amplitude is limited by the upper boundary of the channel and loses its true amplitude difference. The lower overwhelming threshold is used to identify sampling points where the sampling amplitude is covered by noise background or the lower boundary of quantization and cannot be used for stable statistics. These thresholds are derived from the channel gain status, quantization range, and device sampling configuration table, and are stored as a validity filtering rule field. They are used only as a basis for judging the sampling point status and are not used as independent calibration output.

[0075] When filtering the validity of the sampling sequence, each sampling point generates a valid state, an upper limit pruning state, or a lower limit flooding state. Sampling points above the upper limit pruning threshold are marked as invalid sampling points, and sampling points below the lower limit flooding threshold are also marked as invalid sampling points. When the number of consecutive valid sampling points reaches the rule requirement corresponding to the minimum statistical quantity of the dwell segment, the consecutive valid sampling points are retained and a valid readback sampling sequence is generated. The minimum statistical quantity of the dwell segment is a rule field associated with the segment baseline table, derived from the equipment sampling configuration and stability statistical requirements, serving as the boundary for whether to allow entry into the segment representative value determination stage. If there are insufficient valid readback sampling sequences within a dwell segment, the dwell segment generates a valid interval insufficient state, and the subsequent deviation attribution stage treats the segment as an abnormal flow, not using it for correction writing of the corresponding controlled object.

[0076] S3: Determine the propagation delay based on the sampling amplitude transition position between the idle segment and the phase-preserving segment, and based on the propagation delay, correct the boundary times of each segment in the segment reference table, and cut out the effective sampling interval of each dwelling segment.

[0077] Propagation delay is the time offset between the formation of the baseband segment boundary of the dwell calibration RF signal and the appearance of the corresponding amplitude transition in the coupled readback signal. This state is determined by the correspondence between the sampling amplitude transition position when the idle segment enters the phase-holding segment and the start boundary time of the phase-holding segment in the segment reference table. After the propagation delay is determined, the boundary times of each segment in the segment reference table are shifted in the same direction to establish the same sampling time reference between the readback sampling sequence and the segment reference table. The effective sampling interval refers to the statistical interval within the segment formed between the corrected segment boundaries after removing adjacent sampling points and retaining continuous effective sampling points. Its output serves as the input for the determination stages of amplitude difference, phase difference, sampling frequency offset, and power compression state.

[0078] S301: Obtain the end boundary time of the idle segment and the start boundary time of the phase-holding segment from the sampling amplitude and segment reference table. Based on the target amplitude change direction from the idle segment to the phase-holding segment, find the sampling time in the sampling amplitude where the amplitude continuously increases and reaches the amplitude transition confirmation threshold, and generate the sampling amplitude transition position.

[0079] The sampling amplitude transition position refers to the segment switching observation position formed when the readback sampling amplitude changes from an idle state to a phase-holding state. When locating this position, the states of sampling points adjacent to this switching relationship are read from the sampling amplitude sequence, using the end boundary time of the idle segment and the start boundary time of the phase-holding segment as references. The target amplitude change direction is derived from the target amplitude fields of the idle segment and the phase-holding segment in the segment reference table, used to determine the search direction and transition trend. The amplitude transition confirmation threshold is derived from the deviation judgment threshold and validity screening rules in the segment reference table, used to exclude false transitions caused by noise jitter, pruning, or submersion.

[0080] During the search process, the continuously rising state is formed by the amplitude state changes of adjacent valid sampling points. Only when the sampling point maintains the same direction of amplitude change as the target and meets the transition confirmation rule is the corresponding sampling time recorded as the sampling amplitude transition position. If multiple candidate transition positions exist, the candidate positions for delay determination are selected according to the order matching relationship with the start boundary time of the phase-holding segment, and the reason for not selecting a candidate is recorded. If no sampling amplitude transition position that meets the transition confirmation rule is found, the current calibration task enters the delay cannot be confirmed state, and subsequent register correction writes based on this task are not performed. The coupled readback signal and segment reference table are retained for fault tracing.

[0081] S302: Determine the time difference between the sampling amplitude transition position and the starting boundary time of the phase-holding segment to obtain the propagation delay. Based on the propagation delay, perform a same-direction translation correction on the boundary times of each segment in the segment reference table, and cut out the effective sampling interval of each dwelling segment between the corrected boundary times of each segment.

[0082] When the propagation delay is determined, the sampling amplitude transition position is used as the observation position for segment switching on the readback side, and the start boundary time of the phase-holding segment is used as the segment switching position on the reference side, forming the delay state within the same calibration task. The propagation delay is written into the correction field of the segment reference table and bound to the task identifier. When correcting the segment boundary time, each segment boundary maintains its original sequence and segment interval relationship, and is only shifted in the same direction according to the propagation delay, so that the corrected boundary time matches the sampling time reference of the coupled readback signal.

[0083] When selecting a valid sampling interval, the corrected segment boundary time, valid readback sampling sequence, and boundary-adjacent sampling point rejection rules are read. The boundary-adjacent sampling point rejection rules are used to exclude transitional sampling states during segment switching and are derived from the sample-and-hold state, down-conversion channel response state, and valid interval rules in the segment reference table. Each resident segment forms an independent valid sampling interval, and the segment identifier, start and end boundaries, valid sampling point status, rejection reason, and subsequent call identifier are stored in the interval record. If a segment cannot generate a valid sampling interval due to insufficient valid sampling points, that segment will not enter the corresponding representative value determination process, and an insufficient valid interval status will be output to the deviation attribution stage.

[0084] S4: As Figure 4 As shown, the amplitude difference, phase difference, sampling frequency offset, and power compression state are determined based on the effective sampling interval. The deviation attribution results of the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit are determined according to the amplitude difference direction between the low amplitude dwell segment and the high amplitude dwell segment, the power compression state under the high power state, the phase difference in the same direction state, and the phase difference accumulation state.

[0085] Amplitude difference is the deviation between the segment amplitude representative value and the corresponding target amplitude in the segment reference table, indicating the direction and type of deviation of the amplitude control link relative to the target amplitude. Phase difference is the deviation between the segment phase representative value and the target phase, indicating the phase deviation caused by the phase control link or frequency offset. Sampling frequency offset is the offset relative to the target frequency within the effective sampling interval related to frequency dwell. Power compression state is the state relationship between the segment power representative value, the target power, and the power compression rule, used to identify the nonlinear compression performance of the transmit link in the power dwell segment. Deviation attribution result is a state record used to indicate whether the deviation should be corrected by the frequency synthesizer, phase shifter, gain controller, or digital pre-correction unit, and it serves as input for the correction writing stage after its generation.

[0086] S401: Obtain the effective sampling interval of each dwelling segment and the target amplitude, target phase, target frequency and target power in the segment reference table. Remove the sampling points adjacent to the boundary in each effective sampling interval, and perform stable statistics on the remaining sampling points to obtain the segment amplitude representative value, segment phase representative value, segment frequency offset representative value and segment power representative value.

[0087] Stability statistics refer to the process of consistently organizing the states of retained sampling points within the effective sampling interval and outputting representative values ​​for each segment that represent the readback state of that segment. The segment amplitude representative value is derived from the stable state of the sampling amplitude within the effective sampling interval; the segment phase representative value is derived from the stable state of the sampled phase after phase expansion; the segment frequency offset representative value is derived from the stable state of the sampled frequency offset record; and the segment power representative value is derived from the alignment result of the coupled power reading with the corresponding segment interval. Stability statistics do not use boundary transition sampling points, nor do they use sampling points marked as clipped, submerged, reference anomaly, or sampling interrupted.

[0088] When determining the representative value, the segment identifier and target data fields of the valid sampling interval are read, and a correspondence is established between the segment representative value and the target data. If there are duplicate records, inconsistent time sequences, or mismatches with the task identifier among the remaining sampling points within the valid sampling interval, a sampling record consistency check is performed first. One valid record consistent with the sampling order is retained among duplicate records, and the remaining duplicate records are written with an exception description. Sampling points with inconsistent time sequences are not included in the representative value determination. Sampling points with mismatched task identifiers are excluded and their source is recorded as abnormal. The segment representative value obtained after consistency check enters the difference and status judgment process.

[0089] S402: Compare the segment amplitude representative value, segment phase representative value, segment frequency offset representative value, and segment power representative value with the corresponding target data respectively, generate amplitude difference, phase difference, sampling frequency offset, and power compression status, and output the deviation assignment result based on the amplitude difference, phase difference, sampling frequency offset, and power compression status.

[0090] The comparison process uses the segment reference table as a unified reference source. Amplitude comparison reads the target amplitude and the allowable amplitude deviation range, outputting the direction of the amplitude difference and the amplitude deviation status. Phase comparison reads the target phase and the allowable phase deviation range, outputting the direction of the phase difference and the phase deviation status. Frequency comparison reads the target frequency and the allowable frequency deviation range, outputting the sampling frequency offset status. Power comparison reads the target power and the allowable power compression range, outputting the power compression status. Different physical quantities are not directly mixed for comparison; each status is determined within its respective target field and rule field, and then read in a fixed order by the deviation attribution rule.

[0091] The deviation attribution rules take sampling frequency offset, phase difference, amplitude difference, and power compression status as inputs. Sampling frequency offset enters the frequency synthesizer deviation judgment path to identify whether the frequency synthesizer tuning state deviates from the target frequency. Phase difference enters the phase shifter deviation judgment path, and, combined with the phase difference in the same direction state and the phase difference accumulation state, distinguishes between fixed phase deviation and phase drift caused by frequency offset. Amplitude difference enters the gain controller deviation judgment path, and, combined with the amplitude difference direction between the low-amplitude dwell segment and the high-amplitude dwell segment, identifies gain control deviation. Power compression status enters the digital pre-correction unit deviation judgment path, and, combined with the compression performance under high power conditions, identifies pre-correction compensation requirements. If multiple deviation states occur simultaneously in the same segment, an attribution record is generated according to a fixed processing order of frequency offset, phase difference, amplitude difference, and power compression, and the source segment and triggering rules for each state are retained in the attribution record.

[0092] S403: Acquire the sampled phase within the effective sampling interval of the phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment, and determine the phase difference of the sampled phase of each segment based on the target phase in the segment reference table, generating the segment phase difference of each dwell segment.

[0093] The segment phase difference is input using the sampled phase after phase expansion and referenced to the target phase in the segment reference table. Phase-holding segments are used to establish a reference phase deviation observation object; amplitude-step segments are used to observe whether the phase deviates synchronously during amplitude changes; frequency-dwelling segments are used to observe the phase change state caused by frequency offset; and power-dwelling segments are used to observe whether the phase maintains the same direction of deviation under power state changes. Each dwelling segment generates a segment phase difference within its own effective sampling interval and associates and saves the segment phase difference with the segment identifier, target phase source, and effective interval state.

[0094] If a resident segment lacks a valid sampling interval, the phase difference value of that segment is marked as unusable and will not participate in the direction comparison with adjacent segments or in the cumulative state determination. If there is a reference anomaly in the phase unrolling process, the corresponding segment's phase difference value will not enter the deviation attribution path, and the reference anomaly state will be passed to the correction writing stage to block the writing of phase control correction values. If the phase difference value source is complete, the phase difference values ​​of each segment will enter the same-direction state and cumulative state determination process according to the execution order of the resident segments.

[0095] S404: Compare the phase difference direction of adjacent dwelling segments. When the number of segments with the same direction reaches the same direction determination threshold, the phase difference is determined to be in the same direction. Accumulate the change in the phase difference of segments according to the execution order of dwelling segments. When the accumulated change reaches the accumulated determination threshold, the phase difference is determined to be in the accumulated state.

[0096] The phase difference in the same direction state indicates that the phase deviation directions of multiple dwelling segments remain consistent. The direction comparison between adjacent dwelling segments is based on the direction identifier of the segment phase difference, and is not directly mixed with amplitude, frequency, or power states. The phase difference in the same direction state is output when the number of segments with consistent directions reaches the rule requirement corresponding to the same-direction determination threshold. The same-direction determination threshold is derived from the phase determination rule field in the segment reference table. This field is generated by the calibration task configuration and phase preservation requirements, stored in the segment reference table, and called during the phase attribution determination phase.

[0097] The phase difference accumulation state indicates that the phase difference changes continuously along the execution sequence of the dwelling segments. The change in segment phase difference is organized according to the execution sequence of the dwelling segments, and the accumulation judgment threshold comes from the phase accumulation rule field in the segment reference table. If the accumulated change state reaches the judgment boundary corresponding to the rule field, the phase difference accumulation state is output. The phase difference in the same direction state tends to support the fixed deviation assignment of the phase shifter, while the phase difference accumulation state tends to support the assignment of frequency synthesizer deviation or frequency-related phase drift. If both exist simultaneously, the deviation assignment rule first combines the sampled frequency offset state to confirm whether the frequency synthesizer assignment is valid, and then generates a phase shifter assignment record for the remaining phase deviation.

[0098] S405: Determine the deviation assignment results of the frequency synthesizer, phase shifter, gain controller and digital pre-correction unit based on the amplitude difference direction between the low amplitude dwell segment and the high amplitude dwell segment, the power compression state under high power state, the phase difference in the same direction state and the phase difference accumulation state.

[0099] The low-amplitude dwell segment and the high-amplitude dwell segment are amplitude observation segments distinguished by the target amplitude field in the segment reference table. The direction of the amplitude difference between the two is used to determine whether the gain control deviation remains consistent with the target amplitude change. If both the low-amplitude dwell segment and the high-amplitude dwell segment exhibit the same amplitude deviation direction, the deviation attribution result records the gain controller deviation. If the amplitude deviation related to the power state only occurs in the high-amplitude dwell segment, and the power dwell segment also exhibits a power compression state, the deviation attribution result prioritizes recording the digital pre-calibration unit compensation requirement, and the gain controller correction remains in a pending confirmation state.

[0100] The power compression state under high-power conditions is jointly determined by the segment power representative value of the power dwell segment, the target power field, and the power compression rule. This state is used to identify the nonlinear effects of the power amplification link on amplitude and phase during high-power dwell. The phase difference in the same direction state, the phase difference accumulation state, and the sampling frequency offset state are used to distinguish between phase shifter deviation and frequency synthesizer deviation. The deviation assignment result is written to the calibration task record with fields such as controlled object identifier, deviation category, source segment, participation rule, valid state, and subsequent correction object. If there are conflicts in the deviation assignment results, the executable assignment is retained in a fixed order of sampling frequency offset, phase deviation, amplitude deviation, and power compression, and the assignments that are delayed are marked as pending review to avoid the same readback anomaly driving conflicting register writes at the same time.

[0101] S5: Generate frequency tuning correction values, phase control correction values, gain control correction values, and pre-correction compensation values ​​according to the deviation assignment results, and write them sequentially into the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit.

[0102] Frequency tuning correction values ​​are control records written to the frequency synthesizer to adjust its tuning state. Phase control correction values ​​are control records written to the phase shifter to adjust its phase control state. Gain control correction values ​​are control records written to the gain controller to adjust its amplitude control state. Pre-calibration compensation values ​​are control records written to the digital pre-calibration unit to adjust its power compression-related compensation state. All these correction values ​​are generated from the deviation attribution result, the current control value in the hardware control register, and the corresponding deviation state, and are entered into the write queue as correction records to be written. Each correction record to be written includes the controlled object identifier, the source of the current control value, the source of the deviation state, the writing order, the write confirmation status, and the anomaly feedback path.

[0103] S501: Obtain the deviation assignment result, the current control value of the hardware control register, the sampling frequency offset, the phase difference, the amplitude difference, and the power compression status. Based on the deviation assignment result, determine the corresponding controlled object, convert the corresponding deviation amount into the register control increment, and generate a correction record to be written.

[0104] The controlled object is determined by the deviation attribution result. When the deviation attribution result points to the frequency synthesizer, the sampling frequency offset status and the current control value of the frequency synthesizer are read to generate a frequency tuning correction record. When the deviation attribution result points to the phase shifter, the phase difference value, the phase difference in the same direction status, and the current control value of the phase shifter are read to generate a phase control correction record. When the deviation attribution result points to the gain controller, the amplitude difference direction, the amplitude deviation status of the low amplitude dwell segment and the high amplitude dwell segment, and the current control value of the gain controller are read to generate a gain control correction record. When the deviation attribution result points to the digital pre-compensation unit, the power compression status, the amplitude and phase correlation status under high power status, and the current control value of the digital pre-compensation unit are read to generate a pre-compensation compensation record.

[0105] like Figure 5 As shown, register control increment is an intermediate record that converts deviation states into control changes that can be received by hardware registers. This conversion is based on the device calibration configuration table, the controllable control boundaries of the controlled object, and the current control value. The conversion rules are stored in the form of lookup table rules and control direction rules, and are not disclosed as formulas or data examples. If the current control value of the corresponding controlled object is missing, no write correction record is generated for that controlled object, and the missing state is fed back to the calibration task record. If the source segment of the deviation state is marked as insufficient effective range, reference abnormality, power detection abnormality, or time delay that cannot be confirmed, the corresponding correction record enters a blocking state. After the write correction record is generated, it enters the write sequence arrangement for use in subsequent register write stages.

[0106] S502: Based on the correction record to be written, frequency tuning correction value, phase control correction value, gain control correction value and pre-correction compensation value are generated respectively. According to the writing order of frequency synthesizer, phase shifter, gain controller and digital pre-correction unit, each correction value is written to the corresponding hardware control register.

[0107] The writing sequence prioritizes the frequency synthesizer, ensuring the frequency tuning state enters a confirmed state before phase control correction. After the frequency tuning correction value is written, the write confirmation status returned from the hardware control bus is read and written to the calibration task record. If the frequency write is not confirmed, subsequent phase shifter, gain controller, and digital pre-calibration unit writes are not executed to avoid writing phase, gain, or pre-calibration compensation records before the frequency state is stable. After frequency write confirmation, the phase shifter writes the phase control correction value and records the phase shifter write confirmation status. After phase shifter write confirmation, the gain controller writes the gain control correction value and records the gain controller write confirmation status. After gain controller write confirmation, the digital pre-calibration unit writes the pre-calibration compensation value and records the pre-calibration write confirmation status.

[0108] When writing to each hardware control register, the write record carries the task identifier, controlled object identifier, write source, control status before writing, and confirmation status after writing. If a controlled object returns a write rejection, bus transmission failure, or register status unconfirmed, the write record for the current controlled object is marked as incomplete, and subsequent controlled object writes are stopped. The incomplete status is also fed back to the calibration task record for use as the startup phase status when the next calibration task is started. If all writes are confirmed as complete, the calibration task record saves the current segment reference table, effective sampling range, deviation attribution result, and register write confirmation status. Subsequent calibration tasks can determine whether to inherit the current control value or regenerate calibration task parameters after reading the previous valid status.

[0109] Furthermore, this invention also discloses a radio frequency signal correction system for 5G communication equipment implemented in conjunction with related methods. This system includes a calibration signal generation module, a coupling readback acquisition module, a delay correction module, a deviation attribution analysis module, and a correction writing module. The calibration signal generation module performs the functions of generating the stationary calibration radio frequency signal and saving the segment reference table in S1, and its output is the stationary calibration radio frequency signal and the segment reference table. The coupling readback acquisition module performs the functions of acquiring the coupling readback signal, determining the readback parameters, and filtering validity in S2. Its inputs come from the coupler, the downconversion channel, the power detection interface, and the hardware control bus, and its outputs are the sampling amplitude, sampling phase, sampling frequency offset, coupling power reading, the current control value of the hardware control register, and the valid readback sampling sequence. The delay correction module performs the functions of finding the sampling amplitude transition position, determining the propagation delay, correcting the segment boundary time, and selecting the valid sampling interval in S3. Its inputs are the segment reference table and the valid readback sampling sequence, and its outputs are the corrected segment boundary time and the valid sampling interval for each stationary segment. The deviation attribution analysis module performs the segment representative value determination, difference status determination, phase difference in-direction status determination, phase difference accumulation status determination, and deviation attribution result generation functions in S4. Its output is the deviation attribution result pointing to the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit. The correction write module performs the correction record generation, write sequence control, and register write confirmation functions in S5. Its inputs are the deviation attribution result, current control value, and deviation status. Its output is the correction value written to each hardware control register and the corresponding confirmation status.

[0110] The calibration signal generation module does not handle coupled readback acquisition or register writing; the coupled readback acquisition module does not generate deviation attribution results; the delay correction module does not change the target amplitude, target phase, target frequency, or target power; the deviation attribution analysis module does not directly write to the hardware control register; and the correction writing module does not re-determine the segment representative value. Data is transmitted between modules via a segment reference table, valid readback sampling sequence, valid sampling interval, deviation attribution results, and correction records to be written. All data transmission carries task and status identifiers. Acquisition anomalies, delay anomalies, insufficient valid intervals, reference anomalies, register read anomalies, and unconfirmed write statuses are all written to the calibration task record, and the corresponding correction writing is blocked or delayed according to the anomaly flow described in the aforementioned method. The system of this invention carries and executes the aforementioned methods within the same embodiment, without forming a second technical link independent of the aforementioned methods.

[0111] The present invention adopts the above technical solution and has the following beneficial effects compared with the prior art:

[0112] (1) This invention constructs a sequential dwell calibration RF signal comprising no-load, phase hold, amplitude step, frequency dwell, and power dwell, and pre-stores the boundary time, target amplitude, target phase, target frequency, and target power of each segment, providing a unified physical reference for the time delay alignment and multi-dimensional deviation separation of the subsequent readback signal. The propagation delay is inferred by using the sampling amplitude transition position between the no-load segment and the phase hold segment, and all boundary times in the segment reference table are shifted in the same direction to correct the time, so that the effective sampling interval of each dwell segment is precisely aligned with the actual readback signal in time, eliminating the interference of link propagation delay on segment boundary positioning, thereby ensuring the time consistency of amplitude, phase, frequency, and power measurements.

[0113] (2) This invention calculates the amplitude difference, phase difference, sampling frequency offset, and power compression state separately within the effective sampling interval. Based on the direction of the amplitude difference between the low-amplitude dwell segment and the high-amplitude dwell segment, the power compression state under high power conditions, the same-direction state of the phase difference across segments, and the cumulative state, it distinguishes multiple link error sources that were originally mixed in a single readback observation, thus achieving accurate deviation positioning of four types of hardware controlled objects: frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit. This invention avoids the repeated trial-and-error adjustments caused by the confusion of deviation sources in traditional methods, and significantly shortens the calibration convergence time.

[0114] (3) This invention generates frequency tuning correction values, phase control correction values, gain control correction values, and pre-calibration compensation values ​​according to the deviation attribution results, and writes them sequentially into the corresponding hardware control registers, forming a complete RF calibration link from signal generation, coupling readback, delay correction, deviation separation to register closed-loop writing. This invention effectively improves the amplitude and phase consistency, frequency stability, and power linearity of the 5G communication equipment transmit link, reduces nonlinear compression distortion under high-power operating conditions, and improves the overall efficiency and reliability of RF calibration.

[0115] Obviously, the described embodiments are only a portion, not all, of the embodiments of this application. Without conflict, the embodiments and features described and illustrated herein can be combined with each other. The components of the embodiments of this application generally described and illustrated in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

Claims

1. A radio frequency signal correction method for 5G communication equipment, applied to the radio frequency transmission link of the 5G communication equipment, the radio frequency transmission link comprising, in sequence, a digital-to-analog converter module, an up-conversion module, a gain controller, a phase shifter, a frequency synthesizer, a power amplifier, and a coupler located at the output end, characterized in that, The method includes the following steps: Based on the calibration task, a dwell calibration RF signal consisting of an idle segment, a phase hold segment, an amplitude step segment, a frequency dwell segment, and a power dwell segment is generated and input into the digital-to-analog converter module; at the same time, a segment reference table is established based on the calibration task. The segment reference table records the boundary time, target amplitude, target phase, target frequency, target power, and deviation judgment threshold determined by the target data for each segment. The resident calibration RF signal is output through the RF transmission link, and then the coupler located at the output end extracts the coupled RF signal. The coupled RF signal is then frequency-shifted and sampled and held according to the local oscillator reference signal by the down-conversion channel to generate the coupled readback signal. Synchronously read the sampling amplitude, sampling phase, sampling frequency offset, and coupling power readings of the coupled readback signal, as well as the current control values ​​of the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit; In the coupled readback signal, locate the sampling amplitude transition position between the unloaded segment and the phase-holding segment, calculate the time difference between the sampling amplitude transition position and the starting boundary time of the phase-holding segment in the segment reference table as the propagation delay; based on the propagation delay, perform same-direction translation correction on all segment boundary times in the segment reference table, and cut out the effective sampling interval of each dwelling segment between the corrected boundary times. Based on the effective sampling interval of each dwell segment, the amplitude difference between the sampling amplitude and the target amplitude, the phase difference between the sampling phase and the target phase, the sampling frequency offset between the sampling frequency and the target frequency, and the power compression state between the sampling power and the target power are calculated for each dwell segment. The deviation attribution result is determined based on the direction of the amplitude difference between the low-amplitude dwell segment and the high-amplitude dwell segment, the power compression state under high power conditions, the same-direction state of the phase difference across segments, and the cumulative state of the phase difference. The deviation attribution result is used to select a controlled object from the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit. Based on the deviation attribution results, the frequency tuning correction value, phase control correction value, gain control correction value, and pre-correction compensation value are written into the hardware control registers of the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit, respectively, to adjust the RF parameters of the corresponding hardware.

2. The radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The implementation of generating resident calibration RF signals and establishing a segment reference table includes: Obtain calibration task parameters, determine the no-load duration, phase hold duration, amplitude step duration, frequency dwell duration, and power dwell duration based on the calibration task parameters, and establish a segment time series and generate segment boundary times in the order of no-load segment, phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment. Based on the time series of segments, target amplitude, target phase, target frequency and target power are written into each segment, and deviation judgment thresholds are determined according to the changes in target amplitude, target frequency and target power between adjacent segments to generate a segment reference table.

3. The radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The implementation of determining the deviation judgment threshold from the target data includes: Obtain the target amplitude, target phase, target frequency, and target power for each segment, and determine the allowable amplitude deviation range, the allowable phase deviation range, the allowable frequency deviation range, and the allowable power compression range corresponding to the target amplitude, the target phase, the target frequency, and the target power, respectively. Establish the correspondence between each segment and the deviation judgment threshold based on the allowable amplitude deviation range, allowable phase deviation range, allowable frequency deviation range, and allowable power compression range, and write the correspondence into the segment reference table.

4. The radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The implementation of generating the coupled readback signal includes: The coupled RF signal output from the coupler is input into the downconversion channel, and the coupled RF signal is frequency-shifted and sampled and held according to the local oscillator reference signal to generate a coupled readback signal; The coupled readback signal is subjected to amplitude envelope extraction, phase expansion processing and frequency offset estimation, and the power detection interface and hardware control bus are read simultaneously to determine the sampling amplitude, sampling phase, sampling frequency offset, coupled power reading and the current control value of the hardware control register.

5. A radio frequency signal correction method for 5G communication equipment according to claim 4, characterized in that, The method also includes validity screening of the coupled readback signal, as detailed below: Based on the gain state of the downconversion channel and the quantization range of the analog-to-digital converter in the downconversion channel, determine the upper clipping threshold and the lower flooding threshold; Each sampling point in the sampling sequence of the coupled readback signal is compared with the upper pruning threshold and the lower flooding threshold. Sampling points whose sampling signal values ​​are greater than the upper pruning threshold or less than the lower flooding threshold are marked as invalid. Sampling points whose number of consecutive valid sampling points reaches the minimum statistical number of the dwell segment are retained as valid readback sampling sequences.

6. The radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The implementation of locating the sampling amplitude transition position and calculating the propagation delay includes: Based on the target amplitude change direction from the idle segment to the phase-holding segment, the sampling moment in the sampling amplitude sequence of the coupled readback signal where the amplitude continuously increases and reaches the amplitude transition confirmation threshold is found, and this is taken as the sampling amplitude transition position. The propagation delay is obtained by subtracting the sampling amplitude transition position from the starting boundary time of the phase-preserving segment in the segment reference table.

7. The radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The calculation of amplitude difference, phase difference, sampling frequency offset, and power compression state for each dwell segment includes: Obtain the effective sampling interval of each dwell segment and the target amplitude, target phase, target frequency and target power in the segment reference table; Within each valid sampling interval, sampling points adjacent to the boundary are removed, and stable statistics are performed on the remaining sampling points to obtain representative values ​​of segment amplitude, segment phase, segment frequency offset, and segment power. The segment amplitude representative value, segment phase representative value, segment frequency offset representative value, and segment power representative value are compared with the corresponding target data to generate amplitude difference, phase difference, sampling frequency offset, and power compression status.

8. A radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The process of determining the phase difference in the same direction state and the phase difference accumulation state includes: The sampling phase within the effective sampling interval of the phase hold segment, amplitude step segment, frequency dwell segment, and power dwell segment is obtained, and the phase difference of the sampling phase of each segment is calculated according to the target phase in the segment reference table to generate the segment phase difference of each dwell segment. Compare the phase difference direction of adjacent dwelling segments. When the number of segments with the same direction reaches the same direction determination threshold, the phase difference is determined to be in the same direction. Accumulate the change in the phase difference of segments according to the execution order of dwelling segments. When the accumulated change reaches the accumulated determination threshold, the phase difference is determined to be in the accumulated state.

9. A radio frequency signal correction method for 5G communication equipment according to claim 1, characterized in that, The generation and writing of frequency tuning correction values, phase control correction values, gain control correction values, and pre-compensation values ​​include: Obtain the deviation attribution result, the current control value of the hardware control register, the sampling frequency offset, the phase difference, the amplitude difference, and the power compression status. Based on the deviation attribution result, determine the corresponding controlled object and convert the corresponding deviation amount into the register control increment to generate a correction record to be written. Based on the correction record to be written, frequency tuning correction values, phase control correction values, gain control correction values, and pre-correction compensation values ​​are generated respectively; The correction values ​​are written to the corresponding hardware control registers in the order of writing the frequency synthesizer, phase shifter, gain controller, and digital pre-correction unit.

10. A radio frequency signal correction system for 5G communication devices, employing the radio frequency signal correction method for 5G communication devices as described in any one of claims 1 to 9, characterized in that the system... include: The calibration signal generation module is used to generate a dwell calibration RF signal consisting of an idle segment, a phase hold segment, an amplitude step segment, a frequency dwell segment, and a power dwell segment in sequence according to the calibration task, and input it into the digital-to-analog converter module; at the same time, it establishes a segment reference table according to the calibration task, which records the boundary time, target amplitude, target phase, target frequency, target power, and deviation judgment threshold determined by the target data for each segment; The coupling readback acquisition module is used to acquire the coupled readback signal formed by the coupler after the resident calibration RF signal is output through the transmit link and then through the down-conversion channel, and to determine the sampling amplitude, sampling phase, sampling frequency offset, coupling power reading and the current control value of the hardware control register. The delay correction module is used to calculate the propagation delay based on the sampling amplitude transition position between the idle segment and the phase-preserving segment, and to extract the effective sampling interval of each dwelling segment based on the boundary times of each segment in the propagation delay correction segment reference table. The deviation attribution analysis module is used to calculate the amplitude difference, phase difference, sampling frequency offset and power compression state based on the effective sampling interval, and to determine the deviation attribution results of the frequency synthesizer, phase shifter, gain controller and digital pre-correction unit according to the amplitude difference direction between the low amplitude dwell segment and the high amplitude dwell segment, the power compression state under the high power state, the phase difference in the same direction state and the phase difference accumulation state. The correction writing module is used to generate frequency tuning correction values, phase control correction values, gain control correction values ​​and pre-correction compensation values ​​according to the deviation assignment results, and write them sequentially into the hardware control registers of the frequency synthesizer, phase shifter, gain controller and digital pre-correction unit.

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