A mailbox-based inter-core synchronization method and system

Abstract

The application discloses an inter-core synchronization method and system based on a mailbox routing message mechanism, which first configures a trigger mode, a message routing relationship and synchronization configuration parameters, establishes a message-driven synchronization relationship between execution modules, maps the execution modules to target mailboxes, then configures a UID, a reference count value and a synchronization trigger condition of the target mailbox according to the message-driven synchronization relationship, receives a synchronization message, obtains the UID of the synchronization message, matches the UID of the synchronization message with the configured UID, if the UIDs are consistent, a counter is added according to a preset rule, otherwise, the message is discarded and the waiting is continued, and when the counter satisfies a preset synchronization trigger condition, a synchronization trigger signal is generated to trigger the target execution module to execute a subsequent synchronization operation. The method uniformly abstracts and models the inter-core synchronization from the software method level, reduces the dependence on shared storage and software polling, and can improve the determinacy, execution efficiency and semantic expression capability of the inter-core synchronization in a heterogeneous computing system.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to an inter-core synchronization method and system based on a mailbox routing message mechanism. Background Technology

[0002] As the scale of artificial intelligence algorithm models continues to expand, in order to improve computing power density and energy efficiency, neural network processor (NPU) chips are gradually adopting multi-core parallel, modular, and heterogeneous architectures. Such architectures typically include control processing cores, computation execution modules, and auxiliary modules related to synchronization and scheduling. These modules need to frequently coordinate and cooperate in tasks such as task scheduling, execution dependencies, and data transfer.

[0003] In multi-core processing systems, inter-core synchronization is a crucial foundation for ensuring the correct execution of parallel tasks. Its role is to coordinate the execution timing of different processing units and ensure that subsequent operations are triggered only after specific conditions are met. Different processor architectures implement inter-core synchronization in significantly different ways. For example, general-purpose CPUs typically rely on shared memory, atomic operations, and memory barriers for synchronization, while GPUs primarily provide synchronization mechanisms within computing thread groups, and cross-computing unit synchronization often relies on software scheduling or host control. Compared to CPUs and GPUs, NPUs emphasize efficient execution for specific computing models. Their hardware design typically downplays complex consistency protocols and general synchronization instructions, instead using event, message, or signal triggering methods to achieve inter-module collaboration. Therefore, how to achieve a flexible, efficient, and scalable inter-core synchronization mechanism without significantly increasing hardware complexity and power consumption is a key technical challenge in current NPU architecture design.

[0004] In existing multi-core processor, AI accelerator, and NPU architectures, the main technical solutions for synchronization and collaboration between cores or modules include the following different levels and focuses: synchronization solutions based on shared memory and atomic operations, synchronization solutions based on message passing or event notification, hardware-assisted synchronization mechanisms, synchronization control solutions based on software or runtime interfaces, and hardware collaboration solutions based on message routing and Mailboxes.

[0005] In traditional multi-core CPUs and some general-purpose processor architectures, inter-core synchronization typically relies on shared memory space, implemented through mechanisms such as atomic read / write operations, spinlocks, semaphores, and memory barriers. Different processing cores coordinate their execution order by accessing shared state variables, thereby achieving functions such as mutual exclusion, conditional waiting, or barrier synchronization. Patents US12260268B2 and US10360079B2 both achieve inter-core synchronization control through atomic operations or shared variables. This type of solution is based on cache coherency protocols and a unified memory view, possessing advantages such as a mature programming model and strong versatility. It has certain applicability in scenarios with a small number of cores or low parallelism. However, as the number of processing cores increases or the scale of parallel tasks expands, frequent atomic operations and coherence maintenance will significantly increase memory access overhead and bus contention, leading to increased synchronization latency and a decline in overall system performance. Furthermore, this type of solution is primarily designed for general-purpose processors and is difficult to efficiently adapt to the fine-grained collaboration requirements between heterogeneous execution units such as NPUs.

[0006] In multi-core systems and dedicated accelerators using Network-on-Chip (NoC) interconnects, message- or event-based communication and synchronization mechanisms are gradually being introduced to reduce shared memory access pressure. These solutions typically use hardware or firmware modules such as mailboxes, message queues, or event flags to transmit status information or completion notifications between different cores or functional modules. The synchronization logic follows a "send-receive" or "notification-response" pattern. For example, patent application US20150339173A1 uses message passing and hardware triggering mechanisms to achieve synchronization control between processing units. While these solutions reduce shared memory contention to some extent, their synchronization semantics are usually limited to simple "event arrival" or "status completion" notifications, making it difficult to directly express complex synchronization relationships such as multi-condition dependencies, multi-count triggers, or phased convergence. In cases of complex task dependencies or a large number of concurrent sources, additional software logic is often required for combination and judgment, increasing software complexity and introducing additional latency.

[0007] To address the limited synchronization efficiency in massively parallel processing systems, some research and engineering practices have introduced dedicated synchronization structures at the hardware level, such as hardware barriers, hardware counters, synchronization trees, or centralized synchronization control modules, to accelerate local or global synchronization between multiple processing units. For example, patents US11061742B2 and US11803380B2 implement barrier synchronization and counting control between multiple threads or cores through hardware. These solutions are typically designed around specific parallel models or computing paradigms and can significantly reduce synchronization latency in specific application scenarios, but they are complex to implement and have relatively limited configuration flexibility and versatility. Once the system architecture or collaboration mode changes, it often requires redesigning or adjusting the hardware logic, making it difficult to meet the diverse and continuously evolving application requirements.

[0008] In the software stack or runtime system of some AI accelerators, synchronization logic is inserted by the software at appropriate times through synchronization APIs, scheduling instructions, or runtime control interfaces to coordinate the execution order of different cores or modules. For example, patent US11803380B2 also involves implementing synchronization control between threads or processing units through software interfaces in conjunction with hardware mechanisms. This type of solution usually relies on the main control core or operating system for unified management, and is characterized by flexible implementation and ease of integration. However, the synchronization process involves a high degree of software involvement, and the synchronization control logic is usually concentrated in the main control core or runtime system. In high-parallelism or high-real-time scenarios, software scheduling and synchronization judgment can easily become system bottlenecks, not only increasing synchronization latency but also potentially affecting overall scheduling efficiency and system responsiveness.

[0009] In next-generation NPUs and heterogeneous SoC architectures, a synchronization method combining message routing units and mailbox structures is gradually being introduced. Message distribution and reception are completed through dedicated message routing interfaces or configuration interfaces, and synchronization notification is achieved on the target side through counting, triggering, and interrupt mechanisms. For example, patent application US20150339173A1 achieves synchronous collaboration between multiple processing units through message routing and hardware triggering mechanisms. This type of solution already possesses multi-source message aggregation, counting triggering, and multi-level routing capabilities at the hardware level, providing basic support for inter-core synchronization. However, in existing implementations, these capabilities are more dispersed in the form of low-level mechanisms, lacking unified software abstraction and method-level organization. Different modules have different triggering conditions, counting rules, and clearing methods for mailboxes, often requiring software adaptation for specific modules, making it difficult to form a reusable and configurable inter-core synchronization model. Furthermore, for synchronization anomalies or situations where triggering conditions are not met for a long time, existing solutions typically only provide local clearing methods, lacking a system-wide consistent anomaly handling and resource release strategy. Summary of the Invention

[0010] To address some or all of the problems in existing technologies, and in order to balance synchronization flexibility, execution determinism, and exception handling capabilities, the first aspect of this invention provides an inter-core synchronization method based on a mailbox routing message mechanism. By uniformly configuring message routing relationships, mailbox counting rules, and synchronization triggering conditions, a unified message-driven synchronization relationship is established at the software layer, achieving unified abstraction and modeling control of the underlying mailbox and message routing mechanism. The inter-core synchronization method includes: Configure trigger mode, message routing relationship, and synchronization configuration parameters to establish message-driven synchronization relationship between execution modules and map execution modules to target mailboxes (MailBoxes). Configure the target mailbox's UID, reference count value, and synchronization trigger conditions according to the message-driven synchronization relationship; Receive a synchronization message and obtain the UID of the synchronization message; The UID of the synchronization message is matched with the configured UID. If they match, the counter is incremented according to the preset rules. Otherwise, the message is discarded and the process continues to wait. Determine whether the counter meets the preset synchronization trigger condition. When the synchronization trigger condition is met, generate a synchronization trigger signal.

[0011] Furthermore, the inter-core synchronization method further includes: Based on the AGSYNC synchronization control mechanism, multi-source synchronization events are managed in a unified manner.

[0012] Furthermore, based on the AGSYNC synchronization control mechanism, unified management of multi-source synchronization events includes: Configure the synchronization control parameters of AGSYNC, wherein the synchronization control parameters include trigger mode and synchronization direction; After receiving the synchronization trigger signal, AGSYNC determines whether the synchronization conditions are met. If so, it matches, counts, and controls the sequence of the trigger events according to the preset configuration. A synchronization event is generated when the number of triggers reaches a threshold or when the sequence condition is met. The synchronization event is forwarded to the target module or target email address via MailRoute.

[0013] Furthermore, the inter-core synchronization method further includes: When the number of triggers does not reach the threshold, the startup command of the execution module remains suspended.

[0014] Furthermore, the inter-core synchronization method further includes: If the synchronization triggering condition is not met within the preset time, the corresponding waiting instruction will be actively discarded and the descriptor resource will be released.

[0015] Furthermore, by configuring the clear register, the corresponding wait instructions are actively discarded and the descriptor resources are released.

[0016] Furthermore, the inter-core synchronization method further includes: The status and error type of the mailbox's internal counters can be queried using the status and error registers.

[0017] Based on the inter-core synchronization method described above, a second aspect of the present invention provides an inter-core synchronization system based on a mailbox routing message mechanism, comprising: The configuration module is used to configure the trigger mode and message routing relationships; The message routing module, which is communicatively connected to the configuration module, is used to route and distribute synchronization messages to the target execution module according to configuration instructions; The mailbox module, which is communicatively connected to the message routing module, includes a counter and a UID matching unit, wherein the counter is used to accumulate the number of received synchronization trigger signals, and the UID matching unit is used to verify the unique identifier of the synchronization message; Furthermore, the inter-core synchronization system also includes: The AGSYNC synchronization control module, connected to the mailbox module, is used to receive trigger signals from the mailbox module and to uniformly schedule multi-source synchronization events.

[0018] This invention discloses an inter-core synchronization method and system based on a mailbox routing message mechanism. Without altering existing hardware capabilities such as message routing and mailboxes, it provides unified abstraction and modeling control of inter-core synchronization at the software level, reducing reliance on shared storage and software polling, and lowering system memory access overhead and synchronization latency. The inter-core synchronization method supports multi-source counting, multiple triggering conditions, and phased synchronization, significantly enhancing the inter-core synchronization mechanism's ability to express complex dependencies. Furthermore, through a unified exception handling and resource release process, it improves the system's stability and controllability under abnormal or high-concurrency scenarios. Because the synchronization method is decoupled from specific hardware modules and routing layers, it possesses good scalability and reusability, making it applicable to heterogeneous computing systems of different sizes and forms. Attached Figure Description

[0019] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0020] Figure 1 This diagram illustrates a flowchart of an inter-core synchronization method based on a mailbox routing message mechanism according to an embodiment of the present invention. Figure 2 This diagram illustrates the timing of an inter-core synchronization method based on a mailbox routing message mechanism according to an embodiment of the present invention. Figure 3 This diagram illustrates a flowchart of an inter-core synchronization method based on a mailbox routing message mechanism, according to yet another embodiment of the present invention. Figure 4 This diagram illustrates a flow chart of a synchronization control and resource recovery method under abnormal or boundary scenarios according to an embodiment of the present invention. Figure 5 This diagram illustrates the structure of an inter-core synchronization system based on a mailbox routing message mechanism, according to an embodiment of the present invention. Detailed Implementation

[0021] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0022] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0023] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0024] In multi-core NPU architectures, existing message- or interrupt-based collaboration mechanisms are primarily used for status notifications. Their synchronization semantics are relatively simple, lacking a unified, configurable inter-core synchronization model, making it difficult to support complex synchronization scenarios such as multi-trigger counting, condition accumulation, and barrier-based synchronization. Furthermore, existing synchronization methods heavily rely on software or the main control core, requiring frequent software intervention or polling in high-parallel execution scenarios, easily introducing unpredictable synchronization delays and impacting overall execution efficiency and real-time performance. In addition, existing mechanisms lack robust exception handling and resource reclamation capabilities when synchronization conditions are not met, trigger anomalies, or execution is blocked, easily leading to long instruction wait times, unreleased descriptors, or continuous occupation of hardware resources. In summary, there is currently a lack of a universal inter-core synchronization method that can adapt to different modules, trigger modes, and synchronization requirements without significantly increasing hardware complexity, making it difficult to achieve consistent synchronization control in heterogeneous, multi-level interconnected systems. To address the aforementioned issues, this invention proposes an inter-core synchronization method based on the MailRoute message mechanism. This method configures message routing relationships, Mailbox counting rules, and triggering strategies through a hardware-software collaborative approach, achieving conditional synchronization control between multiple modules at the hardware level. This balances synchronization flexibility, execution determinism, and exception handling capabilities. Specifically, the system synchronization mechanism uses MailRoute as a unified message forwarding foundation. By collaboratively configuring message routing paths, Mailbox counting rules, and triggering conditions, synchronization messages from different execution modules can be converged and conditionally judged on the hardware side. Building upon this, the software abstracts and combines these hardware capabilities to construct a unified message-driven inter-core synchronization model. This enables multiple execution modules to achieve many-to-many, countable, and conditionally triggered synchronization collaboration without frequent software intervention or polling, thereby alleviating the problems of limited synchronization semantics and high software dependence in existing technologies.

[0025] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0026] Figure 1 The diagram illustrates a flowchart of an inter-core synchronization method based on a mailbox routing message mechanism according to an embodiment of the present invention. Figure 2 This diagram illustrates a timing sequence of an inter-core synchronization method based on a mailbox routing message mechanism, according to an embodiment of the present invention. Figure 1 As shown, an inter-core synchronization method based on a mailbox routing message mechanism is used to implement conditional synchronization control between multiple execution modules, reduce the dependence on software polling and the resulting uncertain synchronization delay, thereby solving the problems of simple synchronization semantics and high software dependency. The inter-core synchronization method includes: First, in step 101, parameter configuration. The trigger mode and message routing relationship are configured to map the execution module to the target mailbox (MailBox). Simultaneously, before using the MailBox, the UID and reference count value are configured in the target mailbox. The software establishes a synchronization configuration relationship between the execution module, message routing, and the target mailbox through the above configuration, enabling synchronized messages to be routed, matched, counted, and triggered according to preset synchronization rules, thereby forming a unified message-driven synchronization model. In one embodiment of the invention, the system operates in a message trigger mode based on the MailRoute interface by configuring the trigger mode register. In another embodiment of the invention, the unique identifier UID and reference count value REF are configured through the register. Next, in step 102, synchronization messages are received. Different execution modules, such as MCU, TE, TEC, and TES, send synchronization messages through the MailRoute interface. The MailRoute module forwards the messages to the corresponding target MailBoxes according to the pre-configured message routing relationships, achieving flexible message distribution from multiple sources to multiple destinations. Figure 2 As shown; Next, in step 103, it is determined whether the UID matches. After receiving the synchronization message, MailBox obtains the UID of the synchronization message and matches it with the configured UID. If they match, proceed to step 104 to count the messages; otherwise, discard the message and continue waiting to receive synchronization messages to avoid interference from irrelevant messages on the synchronization conditions. In step 104, message counting. When a UID matches, the counter (Collector) inside the MailBox increments according to a preset rule to count the synchronization messages; Next, in step 105, it is determined whether the triggering condition is met. If the triggering condition is met, proceed to step 106 to trigger synchronously. In one embodiment of the present invention, MailBox determines the relationship between the Collector's count value and REF based on the configured triggering mode. When the Collector's count value is greater than zero or reaches a preset reference value, proceed to step 106 to trigger synchronously; otherwise, continue to wait and receive a synchronization message. In step 106, synchronization is triggered. When the triggering conditions are met, a synchronization trigger signal is automatically generated to notify the target core or module to continue performing subsequent operations, thereby completing conditional synchronization control at the hardware level.

[0027] This achieves conditional synchronization. Through the collaborative design of message routing, UID matching, and counting triggers, a simplified software-side configuration for conditional synchronization is implemented. This reduces software complexity while improving the determinism and execution efficiency of synchronization between multiple execution modules in the AI ​​chip, and provides a unified model foundation for many-to-many, countable, and conditionally triggered synchronization collaboration. Specifically, the software encapsulates message routing relationships, UIDs, counting rules, and trigger conditions into a unified synchronization configuration object, completing the configuration through a unified interface. This allows different execution modules to establish synchronization relationships in a consistent manner, eliminating the need to develop separate synchronization logic for specific Mailboxes or message routing hardware.

[0028] Figure 3 This diagram illustrates a flowchart of an inter-core synchronization method based on a mailbox routing message mechanism, according to another embodiment of the present invention. This embodiment is applied to centralized control scenarios. It achieves inter-core synchronization through configuration participation by the main control core and combined with the AGSYNC synchronization control mechanism, thereby realizing unified synchronization control of multiple execution modules across cores, clusters, and dies, and reducing the dependence on software polling and uncertain synchronization delays in complex systems. Figure 3 As shown, an inter-core synchronization method based on a mailbox routing message mechanism includes: First, in step 301, parameter configuration. Configure the synchronization control parameters of AGSYNC, including the trigger mode and synchronization direction. In one embodiment of the invention, the main control core centrally configures synchronization-related parameters, including the MailBox's counting rules, trigger conditions, and AGSYNC's synchronization control parameters. On the message transmission path, the MailRoute mechanism enables message forwarding between different execution modules, such as MCU, TE, TEC, and TES, allowing synchronization messages to be routed and distributed between cores, within a CLUSTER, and across DIE scenarios. Simultaneously, by configuring the trigger mode and synchronization direction of AGSYNC, it can uniformly manage and schedule multi-source synchronization events after receiving trigger signals from MailRoute or MailBox. Next, in step 302, trigger signals are received. Trigger signals from various execution modules are received via the AGSYNC module for aggregation processing. Next, in step 303, it is determined whether the synchronization condition is met. The Producer unit within the AGSYNC module determines whether the trigger input meets the synchronization condition based on the configured Mailbox conditions. If it does, proceed to step 304 to count the trigger count; otherwise, continue receiving and waiting for the trigger signal. In step 304, the number of triggers is counted. According to the configuration in the Entry management unit within the AGSYNC module, the triggered events are matched, counted, and their sequence controlled. Next, in step 305, it is determined whether the trigger count or sequence condition is met. If the trigger count or sequence condition is met, proceed to step 306 to generate a synchronization event; In step 306, a synchronization event is generated. A synchronization event is generated after the trigger count or sequence condition is met. Next, in step 307, the synchronization event is forwarded. The Consumer unit within the AGSYNC module, according to its configuration, forwards the synchronization event to the target module or target MailBox via MailRoute, achieving many-to-many synchronization signal distribution.

[0029] The above methods enable multi-trigger counting, sequential dependency control, and multi-level synchronization, allowing execution modules to remain in a waiting state until they receive a synchronization signal that meets the conditions. This achieves unified control of execution dependencies at the hardware level. After the synchronization trigger signal is generated, the target-side processing core, such as the MCU, waits for and receives synchronization events using synchronization instructions like WAIT_SYNC. Upon receiving the corresponding synchronization signal, it triggers the subsequent execution process. After synchronization is complete, the internal count state is cleared, decremented, or reset using MailBox or AGSYNC update strategies, allowing synchronization resources to enter the next usage cycle. Simultaneously, under AGSYNC control, a unified synchronization completion flag or broadcast signal can be generated after multiple modules have synchronized, notifying relevant modules that the synchronization phase has ended.

[0030] Through the synergistic effect of centralized master configuration, MailRoute message forwarding, and the AGSYNC multi-trigger aggregation mechanism, unified synchronization control for multi-module and multi-level systems is achieved. While reducing the involvement of software polling, it improves the determinism of the synchronization process and system-level scheduling capabilities, and supports scalable synchronization collaboration in CORE, CLUSTER, and cross-DIE scenarios.

[0031] In one embodiment of the present invention, a synchronization control and resource reclamation method for abnormal or boundary scenarios is provided to address the problem of unmet trigger conditions or execution blockage. Through trigger count control, exception clearing and state visualization mechanisms, the robustness and maintainability of inter-core synchronization in complex scenarios are improved.

[0032] Figure 4 This diagram illustrates a flow chart of a synchronization control and resource recovery method for abnormal or boundary scenarios according to an embodiment of the present invention. Figure 4 As shown, a synchronization control and resource reclamation method for abnormal or boundary scenarios includes: First, in step 401, a startup command is received. The execution module receives the startup command; Next, in step 402, it is determined whether the trigger count meets the requirement. Based on the trigger count parameter carried in the startup instruction, the corresponding number of synchronous trigger signals are waited for. If the trigger count meets the requirement, step 403 is entered to wake up the instruction; otherwise, the instruction remains suspended, does not occupy execution resources, and step 404 is entered to determine whether a timeout has occurred. In step 403, a wake-up command is issued. When the required number of triggers is met, the wake-up command is issued and the subsequent process continues. In step 404, it is determined whether a timeout has occurred. If the number of triggers has not met the requirement, it is further determined whether the preset time has been reached. If the preset time has not been reached, the process continues to wait; otherwise, it proceeds to step 405 for timeout processing.

[0033] In step 405, timeout handling. If the synchronization trigger condition is not met within the preset time period, the system actively discards the corresponding waiting instruction and releases the descriptor resource by configuring the clear register, thus avoiding long-term resource occupation due to synchronization anomalies; Finally, in step 406, status query and reporting are performed. The status and error type of the MailBox's internal Collector are queried through the status and error registers and reported, thereby achieving observability of the synchronization process and providing hardware support for system debugging and exception handling.

[0034] Based on the inter-core synchronization method described above Figure 5 This diagram illustrates the structure of an inter-core synchronization system based on a mailbox routing message mechanism, according to an embodiment of the present invention. Figure 5 As shown, an inter-core synchronization system based on a mailbox routing message mechanism includes a configuration module 501. Message routing module 502, Email module 503.

[0035] The configuration module 501 is used to configure parameters, including trigger mode, message routing relationship, counting rules, AGSYNC synchronization control parameters, AGSYNC trigger mode and synchronization direction, etc.

[0036] The message routing module 502 is communicatively connected to the configuration module 501 and is used to route and distribute synchronization messages to the target execution module according to configuration instructions.

[0037] The mailbox module 503 is communicatively connected to the message routing module 502. It includes a counter and a UID matching unit, wherein the counter is used to accumulate the number of received synchronization trigger signals, and the UID matching unit is used to verify the unique identifier of the synchronization message.

[0038] As previously described, in one embodiment of the present invention, the inter-core synchronization system further includes an AGSYNC synchronization control module 504. The AGSYNC synchronization control module 504 is connected to the mailbox module 503 and is used to receive trigger signals from the mailbox module 503 and to uniformly schedule multi-source synchronization events. As previously described, the AGSYNC synchronization control module 504 includes a Producer unit, an Entry management unit, and a Consumer unit. The Producer unit is used to determine whether the trigger input meets the synchronization conditions. The Entry management unit stores parameters such as the number of triggers. The Consumer unit is used to forward synchronization events via MailRoute.

[0039] As described above, the inter-core synchronization method and system, without changing the existing message routing and Mailbox hardware capabilities, provide a unified abstraction and control of inter-core synchronization at the software level.

[0040] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for inter-core synchronization based on a mailbox routing message mechanism, characterized in that, include: Configure the trigger mode so that the system works in message trigger mode based on the mailbox routing interface, and configure the message routing relationship. Configure the UID and reference count value in the target mailbox to establish the synchronization configuration relationship between the execution module, message routing and target mailbox, so that the synchronization message can be routed, matched, counted and triggered according to the preset synchronization rules. Upon receiving a synchronization message from the execution module, the mailbox routing interface forwards the synchronization message to the target mailbox according to the message routing relationship, and the target mailbox obtains the UID of the synchronization message; The UID of the synchronization message is matched with the configured UID. If they match, the counter is incremented according to the preset rules. Otherwise, the message is discarded and the process continues to wait. Determine whether the counter meets the preset synchronization trigger condition. When the synchronization trigger condition is met, generate a synchronization trigger signal to trigger the target execution module to perform subsequent synchronization operations.

2. The inter-core synchronization method as described in claim 1, characterized in that, Also includes: Based on the aggregation synchronization control mechanism, the synchronization trigger signals of different execution modules are aggregated and processed.

3. The inter-core synchronization method as described in claim 2, characterized in that, Based on the aggregation synchronization control mechanism, the aggregation processing of synchronization trigger signals from different execution modules includes: Configure the synchronization control parameters for aggregated synchronization, wherein the synchronization control parameters include trigger mode and synchronization direction; After receiving the synchronization trigger signal, Aggregate Synchronization determines whether the synchronization conditions are met. If so, it matches, counts, and controls the sequence of the trigger events according to the preset configuration. A synchronization event is generated when the number of triggers reaches a threshold or when the sequence condition is met. The synchronization event is forwarded to the target module or target email address via email routing.

4. The inter-core synchronization method as described in claim 1, characterized in that, Also includes: The status and error type of the counter can be queried through the status and error register.

5. A core synchronization system based on a mailbox routing message mechanism, characterized in that, For performing the inter-core synchronization method as described in any one of claims 1 to 4, wherein the inter-core synchronization system comprises: The configuration module is configured to configure the trigger mode, which enables the system to work in the message trigger mode based on the mailbox routing interface and configures the message routing relationship. The UID and reference count value are configured in the target mailbox to establish the synchronization configuration relationship between the execution module, message routing and target mailbox, so that the synchronization message can be routed, matched, counted and triggered according to the preset synchronization rules. The message routing module is communicatively connected to the configuration module and is configured to route and distribute synchronization messages to the target execution module according to configuration instructions; The mailbox module, communicatively connected to the message routing module, includes a counter and a UID matching unit, wherein the counter is configured to accumulate synchronization messages that match the configured UID according to a preset rule, and the UID matching unit is configured to verify the unique identifier of the synchronization message.

6. The inter-core synchronization system as described in claim 5, characterized in that, Also includes: An aggregation synchronization control module is connected to the mailbox module and is configured to aggregate synchronization trigger signals from different execution modules to generate synchronization events.

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