A device and method for implementing SDH virtual concatenation dynamic packet analysis based on FPGA
Patent Information
- Application Number
- CN202610828289.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-09
- Publication Date
- 2026-08-18
AI Technical Summary
[0004]1、由于各成员路径可能经过不同路由，导致到达时间不同，因此接收端需要大容量缓冲来实现复杂的对齐，从而增加了芯片成本和延迟
[0025] 1. The apparatus and method for implementing SDH virtual concatenation dynamic packet resolution based on FPGA of the present invention dynamically manages the virtual concatenation packets inside the FPGA. Both alignment and resolution are constructed according to the minimum number of members. Under the condition that the usage resources do not change much, the minimum processing module is reasonably spliced by dynamic configuration to improve the utilization efficiency of the circuit.
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Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, specifically to an apparatus and method for implementing SDH virtual concatenation dynamic packet parsing based on FPGA. Background Technology
[0002] Virtual concatenation is a key technological innovation in SDH (Synchronous Digital Hierarchy) / SONET (Synchronous Optical Network) networks, used to resolve the contradiction between the rigid channel bandwidth of traditional SDH networks and the burstiness and diversity of data services. Simply put, it logically bundles multiple independent virtual containers (VCs) together to form a virtual high-capacity pipeline, thereby greatly improving bandwidth utilization and network flexibility.
[0003] However, existing virtual concatenation tasks have the following problems:
[0004] 1. Since each member path may take different routes, resulting in different arrival times, the receiving end needs a large-capacity buffer to achieve complex alignment, which increases chip cost and latency.
[0005] 2. The buffer under the alignment mechanism needs to meet the maximum number of virtual concatenation members that each virtual concatenation group can accommodate. However, the number of members in the actual communication network is random, which causes the buffer occupied by the alignment mechanism to be wasted. The hardware can only parse a fixed number of virtual concatenation groups and cannot achieve dynamic allocation.
[0006] 3. In existing communication networks, the number of virtual concatenated group members fluctuates between 1 and N. Typically, the FPGA processing flow involves establishing circuits supporting N virtual concatenations. In this circuit, alignment between the N members is first achieved, followed by data conversion and then data parsing and output. While this approach can handle fewer than N members, it can only process one at a time. When multiple small virtual concatenated groups are input, the number of groups must be increased for processing, resulting in resource waste. Furthermore, the processing capacity of an FPGA has an upper limit, making it easy to reach the maximum number of virtual concatenated processing groups. Summary of the Invention
[0007] The purpose of this invention is to provide a device for implementing SDH virtual concatenation dynamic packet parsing based on FPGA. This method increases the number of smaller virtual concatenation groups that can be processed, improves the input processing capability, is compatible with more input groups, and can ensure normal data output, thus effectively improving processing efficiency.
[0008] To achieve the above objectives, the present invention provides a technical solution:
[0009] An apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA, comprising: a dynamic configuration unit, a dynamic alignment unit, and a dynamic resolution unit;
[0010] The dynamic configuration unit is used to configure write enable, read enable and read address to the dynamic alignment unit, and to configure member information of virtual concatenation member groups to the dynamic resolution unit;
[0011] The dynamic alignment unit includes multiple alignment modules. Each alignment module is used to receive virtual concatenated data, configure write address and write data based on the virtual concatenated data parsing result, process data alignment with the minimum number of members in the virtual concatenation, and output multi-path aligned data.
[0012] The dynamic parsing unit includes multiple adaptive data conversion modules, multiple data parsing modules, and a data aggregation module. Each adaptive data conversion module is connected to an alignment module and a data parsing module in a one-to-one correspondence. The adaptive data conversion module receives alignment data output from the corresponding alignment module and performs bit-width conversion on the time axis based on the number of members in the virtual concatenated member group. The data parsing module receives the converted data and determines whether the converted dataset is valid according to the data structure requirements corresponding to the data type. If valid, it outputs the parsed data according to the data structure requirements. The data aggregation module aggregates the parsed data output from each data parsing module.
[0013] Furthermore, the dynamic configuration unit includes: an initialization module, an address allocation module, and a bit-width conversion configuration module. The initialization module is used to format and clear the information in the address allocation module and the bit-width conversion configuration module. The address allocation module is used to allocate write enable for each alignment module within the dynamic alignment unit and select the smallest address within the virtual concatenated data member group to obtain a unified read enable and read address. The bit-width conversion configuration module is used to send virtual concatenated member information to the data conversion module in the dynamic parsing unit after receiving the virtual concatenated service, thereby realizing the conversion of high-bit-width data to low-bit-width data.
[0014] Furthermore, the address allocation module is used to sequentially allocate write enable to each alignment module based on the specific circumstances of the virtual concatenation service and the virtual concatenation data member group number.
[0015] Furthermore, when the data is a GFP signal, the corresponding data structure requirements are: the frame structure of the GFP signal includes a 4-byte core overhead area, a variable-length payload area, and an optional parity field;
[0016] If the data meets the requirements of the data structure, it is considered valid, and the parsed data is output according to the data structure requirements. The parsed data is the data of the variable length payload area. If it is considered invalid, it is not output.
[0017] Furthermore, the data aggregation module aggregates the data parsed by all data parsing modules into a specific data stream based on the Round Robin polling scheduling algorithm.
[0018] Furthermore, the alignment module configures the write address and write data based on the virtual concatenation data parsing result, including: obtaining the frame number and row / column address to which the data belongs based on the virtual concatenation member data parsing result, wherein the frame number and row / column address are concatenated to form the write address, and the data corresponding to the write address is the write data.
[0019] Furthermore, the adaptive data conversion module performs bit-width conversion on the time axis based on the number of members in the virtual concatenated member group, first outputting the low-byte data sequentially, and then transmitting the high-byte data.
[0020] Furthermore, the alignment module is implemented using URAM memory in the FPGA.
[0021] Furthermore, each of the adaptive data conversion modules is configured with a corresponding number of valid members, which represents the number of valid virtual concatenated members in the conversion clock cycle output by the adaptive data conversion module.
[0022] The present invention also provides a technical solution:
[0023] A method for implementing SDH virtual concatenation dynamic packet parsing based on FPGA, wherein the method utilizes the aforementioned device to parse received virtual concatenation data.
[0024] Compared with the prior art, the beneficial effects of the present invention are:
[0025] 1. The apparatus and method for implementing SDH virtual concatenation dynamic packet resolution based on FPGA of the present invention dynamically manages the virtual concatenation packets inside the FPGA. Both alignment and resolution are constructed according to the minimum number of members. Under the condition that the usage resources do not change much, the minimum processing module is reasonably spliced by dynamic configuration to improve the utilization efficiency of the circuit.
[0026] 2. The apparatus and method for dynamic group parsing of SDH virtual concatenation based on FPGA of the present invention can increase the number of groups that can be processed for smaller virtual concatenation groups and improve the input processing capability when realizing adaptive parsing of aligned data between different members of different virtual concatenations.
[0027] 3. The apparatus and method for SDH virtual concatenation dynamic packet parsing based on FPGA of the present invention provides output aggregation function. Under the original output bandwidth, it can accommodate more input groups while ensuring normal data output, effectively improving processing efficiency. In actual field operations, it can process data more freely without requiring hardware expansion for adaptation, reducing the increased costs associated with hardware replacement.
[0028] 4. The apparatus and method for implementing SDH virtual concatenation dynamic packet resolution based on FPGA of the present invention utilizes the smallest alignment module and resolution module instantiated inside the FPGA, and achieves real-time construction of large-granular alignment and resolution by using small-granular alignment and resolution through dynamic configuration, sharing resources, and can increase the number of small-granular groups to be resolved.
[0029] 5. The apparatus and method for implementing SDH virtual concatenation dynamic packet parsing based on FPGA of the present invention utilizes the roundrobin algorithm to realize the dynamic parsing of data into the original output bandwidth, thereby improving the utilization rate of the output bandwidth without the need to change the hardware for adaptation.
[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0031] Figure 1 This is a structural diagram of the device for implementing SDH virtual concatenation dynamic packet parsing based on FPGA according to the present invention;
[0032] Figure 2 This is a structural diagram of the dynamic configuration unit of the present invention;
[0033] Figure 3 This is a functional schematic diagram of the dynamic alignment unit of the present invention;
[0034] Figure 4 This is a structural diagram of the dynamic alignment unit of the present invention;
[0035] Figure 5 This is a structural diagram of the dynamic analysis unit of the present invention. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0038] Reference Figures 1-4 As shown in the figure, this disclosure provides an apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA, including: a dynamic configuration unit 100, a dynamic alignment unit 200 and a dynamic resolution unit 300.
[0039] Specifically, after the data is received, the dynamic configuration unit 100 configures write enable, read enable, and read address to the dynamic alignment unit 200, and configures the member information of the virtual concatenation member group to the dynamic resolution unit 300. The dynamic alignment unit 200 first aligns the member data within the virtual concatenation group, and then the dynamic resolution unit 300 parses and aggregates the data for output.
[0040] like Figure 2 As shown, the dynamic configuration unit 100 includes: an initialization module 110, an address allocation module 120, and a bit width conversion configuration module 130.
[0041] After the FPGA is loaded and started, logic initialization is performed first. The initialization module 110 is used to format and clear the information in the address allocation module 120 and the bit width conversion configuration module 130. That is, the initialization module 110 clears the information in the address allocation module 120 and the bit width conversion configuration module 130.
[0042] When a virtual concatenation service is received, the address allocation module 120 allocates write enable to each alignment module 210 within the dynamic alignment unit 200 in a stack manner. Specifically, the address allocation module 120 allocates write enable to each alignment module 210 sequentially based on the specific details of the virtual concatenation service and the virtual concatenation data member group number.
[0043] Address allocation module 120 selects the smallest address within the virtual concatenated data member group to obtain a unified read enable and read address.
[0044] After receiving the virtual concatenation service, the bit-width conversion configuration module 130 sends the virtual concatenation member information to the data conversion module 310 in the dynamic parsing unit 300 to realize the conversion of high bit-width data to low bit-width data.
[0045] like Figure 3 and Figure 4As shown, the dynamic alignment unit 200 includes multiple alignment modules 210. In this invention, each alignment module 210 is implemented using URAM memory within the FPGA chip. Block URAM is a unique resource within the FPGA called Ultra RAM, characterized by high bit width, single-byte enable, and large cache size.
[0046] Each alignment module 210 can handle data alignment with the minimum number of members within a virtual concatenation. The write address and write data are configured based on the parsing results of the input virtual concatenation data, while write enable, read enable, and read address are configured by the dynamic configuration unit 100. Each alignment module 210 receives virtual concatenation data, configures the write address and write data based on the virtual concatenation data parsing results, handles data alignment with the minimum number of members within the virtual concatenation, and outputs multi-path aligned data.
[0047] Specifically, the alignment module 210 configures the write address and write data based on the virtual concatenation data parsing results, including: the alignment module 210 configures the write address and write data based on the virtual concatenation member data parsing results to obtain the frame number and row / column address to which the data belongs. The frame number and row / column address are concatenated to form the write address, and the data corresponding to this write address is the write data.
[0048] In this invention, the alignment module 210 is implemented through a URAM memory in the FPGA.
[0049] like Figure 5 As shown, the dynamic parsing unit 300 includes multiple adaptive data conversion modules 310, multiple data parsing modules 320, and a data aggregation module 330. The number of adaptive data conversion modules 310 and data parsing modules 320 is the same as the number of alignment modules 210. Each adaptive data conversion module 310 is connected to one of the alignment modules 210 and the data parsing modules 320 respectively. The adaptive data conversion module 310 receives aligned data output from the corresponding alignment module 210 and performs bit-width conversion on the time axis according to the number of members in the virtual concatenated member group.
[0050] In this invention, the adaptive data conversion module 310 performs bit-width conversion on the time axis according to the number of members in the virtual concatenated member group configured by the dynamic configuration unit 100, and outputs it to the data parsing unit according to specific bytes. Specifically, the low-byte data is output first, and then the high-byte data is transmitted.
[0051] Each adaptive data conversion module 310 is configured with a corresponding number of valid members, which represents the number of valid virtual concatenated members in the conversion clock cycle output by the adaptive data conversion module 310.
[0052] The data parsing module 320 receives the converted data and determines whether the converted dataset is valid according to the data structure requirements corresponding to the data type. If it is valid, it outputs the parsed data according to the data structure requirements.
[0053] Specifically, when the data is a GFP signal, the corresponding data structure requirements are: the frame structure of the GFP signal includes a 4-byte core overhead area, a variable-length payload area, and an optional parity field. If the data meets the data structure requirements, it is considered valid, and the data parsing module 320 outputs the parsed data according to the data structure requirements. The parsed data is the data in the variable-length payload area. If it is determined to be invalid, it is not output.
[0054] The data aggregation module 330 aggregates the parsed data output by each data parsing module 320.
[0055] In this invention, the data aggregation module 330 aggregates the data parsed by all data parsing modules 320 into a specific data stream based on the Round Robin polling scheduling algorithm, thereby ensuring the reasonable utilization of output bandwidth while simultaneously solving the problem of an increasing number of input data streams.
[0056] This invention also proposes a method for implementing SDH virtual concatenation dynamic packet parsing based on FPGA. This method utilizes the FPGA-based device for implementing SDH virtual concatenation dynamic packet parsing provided in the above embodiments to parse the received virtual concatenation data.
[0057] This invention utilizes the smallest alignment module 210 and parsing module 320 instantiated within the FPGA. Through dynamic configuration, it enables the real-time construction of large-granular alignment and parsing using small-granular alignment and parsing, sharing resources and increasing the number of small-granular groups for parsing. Furthermore, it employs the round robin algorithm to dynamically merge the parsed data into the original output bandwidth, improving the utilization rate of the output bandwidth without requiring hardware modifications for adaptation.
[0058] The following description uses the virtual concatenation of a low-order virtual container VC12 in SDH as an example to illustrate the apparatus and method for implementing dynamic packet parsing of SDH virtual concatenation based on FPGA.
[0059] For virtual concatenation of low-order virtual containers (VC12) in SDH, the number of virtual concatenation group members fluctuates between 1 and 63 in actual communication networks. Typically, the FPGA processing flow involves establishing a virtual concatenation processing circuit supporting 63 members. In this circuit, alignment between the 63 members is first achieved, followed by data conversion and data parsing output. While this approach is compatible with fewer than 63 members, it can only process one at a time. When multiple small-member virtual concatenation groups are input, the number of groups must be increased for processing, resulting in some resource waste. Furthermore, the processing capacity supported by FPGAs has an upper limit, making it easy to reach the maximum number of virtual concatenation processing groups.
[0060] To solve the above problems, the present invention provides an apparatus and method for implementing SDH virtual concatenation dynamic grouping resolution based on FPGA. An alignment module 210 and a data parsing module 320 are established inside the FPGA with the minimum number of members (1), and are placed in the dynamic alignment unit 200 and the dynamic parsing unit 300, respectively. The dynamic configuration unit 100 dynamically adjusts and calls the modules based on the number of virtual concatenation members, and cooperates with the data conversion module 310 and the data aggregation module 330 to realize data output, so as to solve the above problems.
[0061] Specifically, the dynamic alignment unit 200 consists of several alignment modules 210. For example, to resolve a set of virtual concatenations, it includes 63 alignment modules 210. The alignment modules 210 are implemented by the URAM within the FPGA chip and include write enable, write address, write data, read enable, read address, and read data. Based on the parsing results of the virtual concatenation member data, the VC12 frame number and row / column address to which the data belongs can be obtained. The frame number and row / column address are concatenated to form the write address, and the data corresponding to this address is the write data. The write enable, read enable, and read address are configured by the dynamic configuration unit 100, and the read data is passed to the subsequent dynamic parsing unit 300.
[0062] The dynamic parsing unit 300 includes an adaptive data conversion module 310 (the same number as the alignment module 210), a data parsing module 320 (the same number as the alignment module 210), and a data aggregation module 330. For example, to solve a set of virtual concatenations, it includes 63 data conversion modules 310, data parsing modules 320, and data aggregation modules 330.
[0063] The adaptive data conversion module 310 will align the data. A group of low-order virtual concatenation aligned data is up to 63 bytes and contains multiple valid flags (the same as the number of virtual concatenation groups processed). The data will be connected to the adaptive data conversion module 310 respectively: 1 byte connected to the adaptive data conversion module 310 (1 Bytes), 1-2 bytes connected to the adaptive data conversion module 310 (2 Bytes), ... 1-63 bytes connected to the adaptive data conversion module 310 (63 Bytes).
[0064] Then, bit-width conversion is performed on the timeline, outputting the low-byte data first and then transmitting the high-byte data. For example, if the aligned data is 63 bytes, it will be output sequentially from the low byte, requiring 63 clock cycles; if the aligned data is only 1 byte, it will require 1 clock cycle. Through the above operations, the high-bit-width data is converted to the low-bit-width data, and finally converted into single-byte data.
[0065] The dynamic configuration unit 100 configures the number of valid members for each adaptive data conversion module 310. For example, if bytes 4-5 are a group of virtual concatenated members, then 2 is configured on the adaptive data conversion module 310 (5 Bytes), which means that bytes 4-5 of the conversion clock cycles 1-5 output by the adaptive data conversion module 310 (5 Bytes) are marked with valid flags. If 0 is configured on the adaptive data conversion module 310 (4 Bytes), then there are no valid flags in the conversion clock cycles 1-4 output by the adaptive data conversion module 310 (4 Bytes).
[0066] The data parsing module 320 first determines the validity of the data based on the locking structure of the specific data. If the data is valid, it outputs the parsed data according to the data structure requirements; otherwise, it does not output any data. Finally, the data aggregation module 330 aggregates all the data parsed by the data parsing module 320 into a specific data stream using the Round Robin algorithm.
[0067] In the description of this invention, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0068] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0069] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A device for implementing SDH virtual concatenation dynamic packet resolution based on FPGA, characterized in that, include: Dynamic configuration unit, dynamic alignment unit, and dynamic resolution unit; The dynamic configuration unit is used to configure write enable, read enable and read address to the dynamic alignment unit, and to configure member information of virtual concatenation member groups to the dynamic resolution unit; The dynamic alignment unit includes multiple alignment modules. Each alignment module is used to receive virtual concatenated data, configure write address and write data based on the virtual concatenated data parsing result, process data alignment with the minimum number of members in the virtual concatenation, and output multi-path aligned data. The dynamic parsing unit includes multiple adaptive data transformation modules, multiple data parsing modules, and a data aggregation module, wherein the adaptive data transformation modules are connected to the alignment module and the data parsing module in a one-to-one correspondence. The adaptive data conversion module receives the alignment data output from the corresponding alignment module and performs bit width conversion on the time axis according to the number of members in the virtual concatenated member group; The data parsing module receives the converted data, determines whether the converted dataset is valid according to the data structure requirements corresponding to the data type, and outputs the parsed data according to the data structure requirements if it is valid. The data aggregation module aggregates the parsed data output by each data parsing module.
2. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The dynamic configuration unit includes: an initialization module, an address allocation module, and a bit-width conversion configuration module, wherein... The initialization module is used to format and clear the information in the address allocation module and the bit width conversion configuration module; The address allocation module is used to allocate the write enable of each alignment module in the dynamic alignment unit, and select the smallest address in the virtual concatenated data member group to obtain a unified read enable and read address. The bit-width conversion configuration module is used to send virtual concatenation member information to the data conversion module in the dynamic parsing unit after receiving the virtual concatenation service, so as to realize the conversion of high bit-width data to low bit-width data.
3. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The address allocation module is used to sequentially allocate write enable to each alignment module based on the specific circumstances of the virtual concatenation service and the virtual concatenation data member group number.
4. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, When the data is a GFP signal, the corresponding data structure requirements are: the frame structure of the GFP signal includes a 4-byte core overhead area, a variable-length payload area, and an optional parity field; If the data meets the data structure requirements, it is deemed valid. The data parsing module outputs the parsed data according to the data structure requirements. The parsed data is the data of the variable-length payload area. If it is deemed invalid, it is not output.
5. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The data aggregation module aggregates the data parsed by all data parsing modules into a specific data stream based on the Round Robin polling scheduling algorithm.
6. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The alignment module configures the write address and write data based on the virtual concatenation data parsing result, including: obtaining the frame number and row / column address to which the data belongs based on the virtual concatenation member data parsing result, wherein the frame number and row / column address are concatenated to form the write address, and the data corresponding to the write address is the write data.
7. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The adaptive data conversion module performs bit-width conversion on the time axis based on the number of members in the virtual concatenated member group, first outputting the low-byte data and then transmitting the high-byte data.
8. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, The alignment module is implemented using URAM memory in the FPGA.
9. The apparatus for implementing SDH virtual concatenation dynamic packet resolution based on FPGA according to claim 1, characterized in that, Each of the adaptive data conversion modules is configured with a corresponding number of valid members, which represents the number of valid virtual concatenated members in the conversion clock cycle output by the adaptive data conversion module.
10. A method for implementing SDH virtual concatenation dynamic packet resolution based on FPGA, characterized in that, The method utilizes the apparatus described in any one of claims 1-9 to parse the received virtual concatenation data.