An inter-chip communication control method and device, electronic equipment and storage medium

Abstract

The application discloses a kind of inter-chip communication control method, device, electronic equipment and storage medium, to solve the problem of unstable communication between chips in vehicle domain controller, the method comprises: obtaining the first state of state machine running on the first chip, first state is data communication channel establishment state, data communication state, data communication channel release state or fault handling state;Based on the first state, corresponding processing is executed, specifically including: if it is determined that the first state is data communication channel establishment state or data communication channel release state, then process the channel control message sent by the second chip or power management module based on the first message routing table;If it is determined that the first state is data communication state, then process the service message sent by the second chip based on the second message routing table;When it is determined that the state switching condition is satisfied, the state of state machine is switched.

Description

Technical Field

[0001] This application relates to the field of vehicle control technology, and in particular to a chip-to-chip communication control method, device, electronic device, and storage medium. Background Technology

[0002] As vehicle electronic and electrical architecture evolves from distributed to domain-centralized, a single domain controller typically integrates multiple chips such as MCU (Microcontroller Unit) and high-performance SoC (System on a Chip). The MCU is responsible for high real-time and high-reliability vehicle control, such as CAN (Controller Area Network) communication and power management, while the SoC is responsible for complex information processing, such as in-vehicle entertainment and instrument display. These two types of chips exchange data through IPC (Inter-Process Communication) to achieve functional collaboration.

[0003] In related technologies, IPC schemes between different chips in vehicle domain controllers are typically based on hardware links such as shared memory, SPI (Serial Peripheral Interface), and UART (Universal Asynchronous Receiver Transmitter), and data transmission and reception are achieved by constructing simple protocols. However, existing solutions usually only focus on two coarse states: connection and disconnection of the data communication link. This leads to a situation in the automotive environment where, when connection anomalies occur due to power state switching (such as sleep or wake-up), the system cannot accurately perceive the specific state of the current communication, and it is difficult to automatically and reliably restore to the normal communication state, resulting in unstable inter-chip communication.

[0004] Therefore, improving the communication stability between chips in a vehicle domain controller is one of the technical problems that urgently needs to be solved in the existing technology. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and storage medium for inter-chip communication control, which improves the communication stability between chips in a vehicle domain controller.

[0006] In a first aspect, embodiments of this application provide a chip-to-chip communication control method, applied to a first chip in a vehicle domain controller. The vehicle domain controller further includes a second chip and a power management module, wherein the first chip and the second chip are chips of different types. The method can be executed by the first chip. The method includes: acquiring a first state of a state machine running on the first chip, wherein the first state represents the current communication state between the first chip and the second chip, and the first state is a data communication channel establishment state, a data communication state, a data communication channel release state, or a fault handling state; performing corresponding processing based on the first state, specifically including: if it is determined that the first state is a data communication channel establishment state or a data communication channel release state, then processing the channel control message sent by the second chip or the power management module based on a first message routing table; if it is determined that the first state is a data communication state, then processing the service message sent by the second chip based on a second message routing table; and switching the state of the state machine when it is determined that the state switching condition is met.

[0007] In this application, the communication process between the first and second chips in the vehicle domain controller is set into four communication states through a state machine: data communication channel establishment state, data communication state, data communication channel release state, and fault handling state. Based on the first state of the acquired state machine, i.e., the current communication state between the first and second chips, corresponding processing is performed. This achieves fine-grained communication state management throughout the entire lifecycle of the data communication link: "establishment-maintenance-release-abnormal recovery." These four states cover all scenarios from data communication link establishment, normal operation, release to abnormal handling. Differentiated processing is performed for different communication states, making the communication behavior between chips in the vehicle domain controller predictable and traceable, improving the stability and reliability of communication between different chips. Furthermore, by defining clear state switching conditions, the state machine state is switched when the switching conditions are met. This makes the transition logic of the data communication state between chips controllable, avoiding random jumps in communication state and ensuring that communication is in a valid state. In this application, when the data communication channel is established or released, the channel control message from the second chip or power management module can be processed by querying the first message routing table. When the data communication channel is successfully established and operating normally, the service message from the second chip can be processed by querying the second message routing table. Thus, the physical and logical separation of the channel control message and the service message is achieved through the dual-path message routing mechanism, ensuring the real-time performance and determinism of the critical process.

[0008] In one optional implementation, the channel control message sent by the second chip or power management module is processed based on the first message routing table, specifically including: querying the first processing function corresponding to the channel control message based on the first message routing table; and processing the channel control message based on the first processing function.

[0009] In the above implementation, the correspondence between channel control messages and processing functions is maintained through the first message routing table. In the data communication channel establishment state or data communication channel release state, the channel control messages from the second chip or power management module can be processed by querying the first message routing table, while service messages are not processed. In this way, when the data communication link is not established or is being released, service messages will not be misprocessed or critical control signaling will not be blocked, thus ensuring the functional safety of the system.

[0010] In one optional implementation, the service messages sent by the second chip are processed based on the second message routing table, specifically including: querying the second processing function corresponding to the service message based on the second message routing table; and processing the service message based on the second processing function.

[0011] In the above implementation, the correspondence between business messages and processing functions is maintained through a second message routing table. During data communication, business messages from the second chip can be processed by querying the second message routing table, without processing control messages. This avoids system anomalies or wasted computing resources caused by processing business data in invalid or erroneous states. Furthermore, the second message routing table is independent of the first message routing table, achieving isolation between communication control data and business data at the routing layer, improving data processing efficiency, and ensuring system functional security.

[0012] In one alternative implementation, the corresponding processing based on the first state further includes: if the first state is determined to be a fault handling state, performing a software reset operation, the software reset operation including at least one of the following operations: clearing the timeout counter, clearing the communication sequence number, and clearing the data in the data buffer.

[0013] In the above implementation, when the data communication is in an abnormal state, a complete reset operation is performed at the software state level, which avoids the problem of not being able to clear the erroneous software state that may be caused by restarting the hardware or simply retransmitting the data. In addition, the software reset takes less time, has less computational overhead, and does not affect the normal operation of other unrelated modules, thus improving the efficiency of communication fault recovery.

[0014] In one optional implementation, determining that the state transition condition is met specifically includes: when the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip is successful, then it is determined that the state transition condition is met; and switching the state of the state machine specifically includes: switching the state of the state machine to the data communication state.

[0015] The above implementation method clarifies the switching conditions from the data communication channel establishment state to the data communication state, ensuring that the data communication stage will only be entered after a successful handshake with the second chip. If the handshake fails, the data communication stage cannot be entered, thus avoiding the risk of transmitting business data when the data transmission link is not successfully established.

[0016] In one optional implementation, determining that the state switching condition is met specifically includes: when the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip has timed out, or when the first state is the data communication state, if it is determined that the heartbeat has timed out based on the heartbeat message between the second chip, then it is determined that the state switching condition is met; and switching the state of the state machine specifically includes: switching the state of the state machine to the fault handling state.

[0017] The above implementation achieves communication anomaly detection throughout the entire operation cycle by monitoring whether the handshake timeout occurs during the data communication channel establishment phase and whether the heartbeat timeout occurs during the data communication phase. The handshake timeout or heartbeat timeout is used as the switching condition for switching to the fault handling state, rather than simply retrying to send the handshake message or resend the message, thus improving the efficiency of communication anomaly detection and handling.

[0018] In one optional implementation, determining that the state transition condition is met specifically includes: if the first state is determined to be the fault handling state, then after the software reset operation is completed, determining that the state transition condition is met; and switching the state of the state machine specifically includes: switching the state of the state machine to the data communication channel establishment state.

[0019] In the above implementation, when the software reset operation is completed in the fault handling state, it can automatically switch to the data communication channel establishment state and re-establish the communication link, realizing the automatic recovery process from fault handling back to data communication link establishment.

[0020] In one optional implementation, determining that the state transition condition is met specifically includes: determining that the state transition condition is met when a release request is received from the power management module; and switching the state of the state machine specifically includes: switching the state of the state machine to the data communication channel release state.

[0021] In the above implementation, the power management module sends a release request as a switching condition for switching to the data communication channel release state, ensuring that the data communication link between the vehicle and the second chip is safely released before the vehicle enters sleep mode, thus avoiding data loss caused by abnormal power failure.

[0022] In one optional implementation, the method further includes: receiving a communication status query request sent by the first module; obtaining the second state of the state machine; and returning the second state to the first module through a set application programming interface.

[0023] In the above implementation, the communication status of the first chip is provided to the vehicle subsystem, such as the power management module and the functional safety monitoring module, through the provided standardized API (Application Programming Interface), so that other modules can make collaborative decisions based on the actual operation of the communication link.

[0024] Secondly, embodiments of this application provide an inter-chip communication control device, applied to a first chip in a vehicle domain controller. The vehicle domain controller further includes a second chip and a power management module. The first chip and the second chip are of different types. The device can be executed by the first chip. The device includes: The first state acquisition module is used to acquire the first state of the state machine running on the first chip. The first state represents the current communication state between the first chip and the second chip. The first state is a data communication channel establishment state, a data communication state, a data communication channel release state, or a fault handling state. The processing module is used to perform corresponding processing based on the first state; The processing module is specifically configured to, if it is determined that the first state is the data communication channel establishment state or the data communication channel release state, process the channel control message sent by the second chip or the power management module based on the first message routing table; and if it is determined that the first state is the data communication state, process the service message sent by the second chip based on the second message routing table. The state switching module is used to switch the state of the state machine when it is determined that the state switching conditions are met.

[0025] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the inter-chip communication control method described in this application.

[0026] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps in the inter-chip communication control method described in this application.

[0027] The beneficial effects of the second to fourth aspects mentioned above can be referenced to the beneficial effects of the first aspect and any of its implementation methods. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram illustrating an application scenario of an inter-chip communication control method provided in an embodiment of this application. Figure 2 This is a schematic diagram of the structure of a vehicle domain controller provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a first chip provided in an embodiment of this application; Figure 4 A flowchart illustrating the inter-chip communication control method provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the processing flow of channel control messages when the first state is a data communication channel establishment state or a data communication channel release state, as provided in an embodiment of this application. Figure 6 This is a schematic diagram illustrating the processing flow of service messages when the first state is a data communication state, as provided in an embodiment of this application. Figure 7 A schematic diagram illustrating the switching process of the four-stage communication states of the state machine provided in this application embodiment; Figure 8 A schematic diagram of the message routing process based on the communication state of a state machine provided in an embodiment of this application; Figure 9 This is a schematic diagram of the fault handling and recovery process when the state machine is in the fault handling state, as provided in an embodiment of this application. Figure 10 This is a schematic diagram of the structure of the IPC service layer of the MCU provided in the embodiments of this application; Figure 11 This is a schematic diagram of the structure of the inter-chip communication control device provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0030] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0031] In the embodiments of this application, "when," "if," and "if" all refer to the device taking corresponding actions under certain objective circumstances, not a time limit, nor do they require the device to perform a judgment action, nor do they imply any other limitations. Unless otherwise specified, "if" and "if" are interchangeable, and "when" and "in the case of" are interchangeable. "When" and "if" / "if" are interchangeable. " can be used to mean "multiply".

[0032] The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, the first sequence and the second sequence refer to two different sequences, and do not indicate that the content, priority, or importance of these two sequences are different. Words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0033] Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a list of units is not necessarily limited to those units, but may include other units not expressly listed or inherent to those processes, methods, products, or apparatuses. The methods and apparatuses provided in the embodiments of this application are based on the same or similar technical concepts. Since the principles by which the methods and apparatuses solve the problems are similar, implementations of the apparatus and methods can be referred to mutually, and repeated details will not be elaborated further.

[0034] To facilitate understanding of the technical solutions provided in the embodiments of this application, the relevant technical features involved in the embodiments of this application will be explained below.

[0035] It should be noted that these explanations are intended to make the embodiments of this application easier to understand, and should not be regarded as a limitation on the scope of protection claimed in this application.

[0036] As vehicle electronic and electrical architecture evolves from distributed to domain-centralized, a single domain controller typically integrates multiple chips such as MCU and high-performance SoC. The MCU is responsible for high real-time and high-reliability vehicle control, such as CAN communication and power management, while the SoC is responsible for complex information processing, such as in-vehicle entertainment and instrument display. These two types of chips exchange data through IPC to achieve functional collaboration.

[0037] In related technologies, IPC schemes between different chips in vehicle domain controllers are typically based on hardware links such as shared memory, SPI, and UART, and data transmission and reception are achieved through the construction of simple protocols. However, existing solutions usually only focus on two coarse states: connection and disconnection of the data communication link. This leads to a situation in the vehicle environment where, when connection anomalies occur due to power state switching (such as sleep and wake-up), the system cannot accurately perceive the specific state of the current communication, and it is difficult to automatically and reliably restore to the normal communication state, resulting in unstable inter-chip communication. Moreover, due to the lack of clear state division, channel control messages (such as link handshake, heartbeat maintenance, channel release, etc.) and application service messages (such as vehicle speed information, diagnostic commands, multimedia control messages, etc.) are often mixed and processed in the same communication phase. When the data communication link has not been established or is in an abnormal state, application data may be incorrectly processed or critical control signaling may be blocked, affecting system functional safety. In addition, after a communication timeout, simple retransmission or hardware restart is usually used, which cannot effectively clean up the erroneous software state, which may lead to "zombie" connections or repeated handshake failures, lacking a mechanism for thorough reset and orderly recovery at the software state level. Meanwhile, other vehicle subsystems such as power management and functional safety monitoring cannot know the internal status information of the IPC module, making it impossible for the entire vehicle system to make collaborative decisions based on the actual operating status of the communication link.

[0038] Therefore, this application provides a technical solution to control communication between chips in a vehicle domain controller, thereby improving the stability of communication between chips in the vehicle domain controller. This technical solution can be applied to any scenario involving communication control between chips, including but not limited to the aforementioned communication control between different chips in a vehicle domain controller.

[0039] like Figure 1 The diagram shown is an application scenario diagram of an inter-chip communication control method provided in an embodiment of this application. It is a structural diagram of a vehicle domain controller 10. The vehicle domain controller 10 may include a first chip 101 and a second chip 102. The vehicle domain controller 10 can be any domain controller in a vehicle, such as a body domain controller, a cockpit domain controller, etc. The first chip 101 and the second chip 102 are different types of chips. The first chip 101 can be an MCU, and the second chip 102 can be a SoC. The first chip 101 and the second chip 102 communicate with each other through IPC.

[0040] like Figure 2 The diagram shown is another structural schematic of the vehicle domain controller 10. The vehicle domain controller 10 may also include a power management module 103, which can be used to supply power to the first chip 101 and the second chip 102.

[0041] like Figure 3 The diagram shows the structure of the first chip 101 provided in this application example. It may include an application layer 1011, an IPC service layer 1012, an IPC protocol layer 1013, and a hardware abstraction layer 1014. The inter-chip communication control method provided in this application can be specifically executed by the IPC service layer 1012. The application layer 1011 supports applications such as CAN communication, fault diagnosis, instrumentation, and power management. For different application service data sent by the second chip 102, corresponding application callback functions can be used for processing. The IPC service layer 1012 is used to perform four-stage state machine management. The IPC protocol layer 1013 is used to assemble or unpack the interactive data with the second chip 102, perform CRC (Cyclic Redundancy Check), and manage the ring buffer. The hardware abstraction layer 1014 is used to implement hardware driving using SPI controllers, GPIO (General-Purpose Input / Output) interfaces, etc., to achieve high-speed data interaction with external devices (such as sensors, memory, display driver chips, etc.).

[0042] based on Figures 1-3 The application scenarios shown below will be explained with reference to the appendix. Figures 4-10The exemplary embodiments of this application are described in more detail below. It should be noted that the above application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementation methods of this application are not limited in any way. On the contrary, the implementation methods of this application can be applied to any applicable scenario.

[0043] like Figure 4 The diagram shown illustrates the implementation flow of the inter-chip communication control method provided in this application embodiment. This inter-chip communication control method can be applied to... Figure 1 or Figure 2 The method, which can be executed by the first chip in the vehicle domain controller, may specifically include the following steps: S21. The first chip acquires the first state of the state machine running on the first chip. The first state represents the current communication state between the first chip and the second chip. The first state is the data communication channel establishment state, data communication state, data communication channel release state, or fault handling state.

[0044] In practice, the first chip defines and maintains a four-stage communication state machine, which may include the following states: data communication channel establishment state, data communication state, data communication channel release state, and fault handling state.

[0045] The data communication channel establishment state is used for handshake negotiation with the second chip, exchanging initialization information such as the communication protocol version used by both chips to establish a data communication channel, i.e., a physical and logical communication link. In the data communication channel establishment state, the interactive data between the first and second chips during the handshake process constitutes the channel control messages during the data communication channel establishment process. In this state, the first chip can monitor whether the handshake with the second chip has timed out. Initially, if the first chip powers on, the state machine is set to the data communication channel establishment state.

[0046] After the data communication channel is successfully established, the state machine switches to the data communication state, entering the data communication phase. In the data communication state, the first chip can interact with the second chip for business data. The business data may include, but is not limited to, the business data of the following applications: CAN applications, fault diagnosis applications, instrument applications, etc., which are not limited in this embodiment. In the data communication state, the first chip can also monitor whether the heartbeat timeout occurs between it and the second chip, so as to perform periodic heartbeat maintenance.

[0047] The channel release status is used to confirm the release with the second chip when the vehicle domain controller system needs to disconnect (such as before hibernation) in order to disconnect the communication link.

[0048] If the handshake between the first chip and the second chip times out during the establishment of the data communication channel, or if the heartbeat times out during the data communication state, the state machine switches to the fault handling state, which is used to perform communication anomaly recovery operations.

[0049] In this step, the main task of the IPC service layer of the first chip (such as TASK_IPC) can be scheduled to execute the state scheduling function Ipc_ServiceStatusMainFunction() according to a set period to read the current main state of the state machine represented by the global variable g_ipcInfo.stageStatus, which can be recorded as the first state of the state machine, that is, the communication status information between the first chip and the second chip. The set period can be set according to requirements, such as 10ms, but this embodiment does not limit this. The global variable g_ipcInfo.stageStatus is used to record the current communication status between the first chip and the second chip, where "g_" represents a global variable prefix, "ipcInfo" represents an IPC information structure, and "stageStatus" is a member of the structure "ipcInfo" used to indicate which communication stage is currently in.

[0050] S22. Perform the corresponding processing based on the first state.

[0051] In specific implementation, if the first state is determined to be a data communication channel establishment state or a data communication channel release state, then the channel control message sent by the second chip or power management module is processed based on the first message routing table; if the first state is determined to be a data communication state, then the service message sent by the second chip is processed based on the second message routing table.

[0052] In one implementation, when the first state is either the data communication channel establishment state or the data communication channel release state, it can be done as follows: Figure 5 The process shown involves processing channel control messages, including the following steps: S31. Query the first processing function corresponding to the channel control message based on the first message routing table.

[0053] In specific implementation, the first chip stores a first message routing table. This table stores the correspondence between communication control message identifiers and processing functions (which can be called channel management callback functions), with each type of communication control message corresponding to a unique identifier. For example, the first message routing table includes the correspondence between handshake request message identifiers and handshake request processing functions, release request messages and release request processing functions, and release response messages and release response processing functions. The handshake request message is a communication control message during the establishment of the data communication channel, and the release response message is a communication control message during the release of the data communication channel. The channel control messages sent by the power management module may include release request messages sent by the power management module.

[0054] In this step, if the first chip determines that the first state of the current state machine is either a data communication channel establishment state or a data communication channel release state, for channel control messages sent by the second chip or the power management module during the data communication channel establishment or release process, it can query the first message routing table based on the identifier of the channel control message to obtain the first processing function corresponding to the identifier of the channel control message. In these two stages, if the first chip receives a service message from the second chip, it will discard it directly without processing any service message.

[0055] S32. Process the channel control message based on the first processing function.

[0056] In practice, after the first chip finds the first processing function corresponding to the identifier of the channel control message, it calls the first processing function to process the channel control message.

[0057] In this embodiment, the correspondence between channel control messages and processing functions is maintained through a first message routing table. In the data communication channel establishment state or data communication channel release state, channel control messages from the second chip or power management module can be processed by querying the first message routing table, while service messages are not processed. In this way, when the data communication link is not established or is being released, service messages will not be misprocessed or critical control signaling will not be blocked, thus ensuring the system's functional safety.

[0058] In one implementation, when the first state is a data communication state, it can be done as follows: Figure 6 The process shown involves processing business messages, including the following steps: S41. Query the second processing function corresponding to the business message based on the second message routing table.

[0059] In practical implementation, the first chip also stores a second message routing table. This table stores the correspondence between service message identifiers and processing functions (also known as application processing functions), with each type of service message corresponding to a unique identifier. For example, the second message routing table includes the correspondence between the identifier of a vehicle body CAN message and its processing function, and the correspondence between the identifier of a diagnostic command message and its processing function. When a new service module is added, the new mapping relationship is added to the second message routing table. When the handshake process needs to be modified, adjustments are made within the data communication channel establishment state, making the system easy to expand and maintain.

[0060] In this step, if the first chip determines that the first state is a data communication state, for the service message sent by the second chip, it can query the second message routing table based on the identifier of the service message to obtain the second processing function corresponding to the identifier of the service message. During the data communication phase, if the first chip receives a channel control message from the second chip, it can discard it directly without processing any service message. During the data communication phase, the heartbeat messages between the first and second chips can be processed by the IPC service layer.

[0061] S42. Process the business message based on the second processing function.

[0062] In practice, after the first chip finds the second processing function corresponding to the identifier of the service message, it distributes the service message to the corresponding service module so that the service module can call the second processing function to process the service message. For example, if the service message is a CAN message, the CAN message is distributed to the CAN module; if the service message is a diagnostic message, the diagnostic message is distributed to the fault diagnosis module; and if the service message is an instrument control command, the instrument control command is sent to the instrument module.

[0063] In this embodiment, a second message routing table maintains the correspondence between service messages and processing functions. In data communication mode, i.e., when the data communication channel is successfully established and operating normally, service messages from the second chip can be processed by querying the second message routing table, without processing control messages. This avoids system anomalies or wasted computing resources caused by processing service data in invalid or erroneous states. Furthermore, the second message routing table is independent of the first message routing table, achieving isolation between communication control data and service data at the routing level, improving data processing efficiency, and ensuring system functional security. The dual-path separation processing mechanism for channel control messages and service messages avoids interference from service data to control signaling when the communication link is unstable, ensuring the real-time performance of critical control processes such as handshake, heartbeat, and release, and improving system security.

[0064] In one implementation, when the first state is a fault handling state, the following processing can be performed: if the first chip determines that the first state is a fault handling state, it performs a software reset operation, which includes at least one of the following operations: clearing the timeout counter, clearing the communication sequence number, and clearing the data in the data buffer.

[0065] The counters can include heartbeat counters, handshake counters, etc. The heartbeat counter is used to count heartbeat messages during communication between the first chip and the second chip, and the handshake counter is used to count handshake messages between the first chip and the second chip during the establishment of the data communication channel. The communication sequence number is the sequence number for sending and receiving data between the first chip and the second chip. Each message corresponds to a unique communication sequence number to avoid message retransmission.

[0066] In this embodiment, when the data communication is in an abnormal state, a complete reset operation is performed at the software state level, which avoids the problem of not being able to clear the erroneous software state that may be caused by restarting the hardware or simply retransmitting the data. Moreover, the software reset takes less time, has less computational overhead, and does not affect the normal operation of other unrelated modules, thus improving the efficiency of communication fault recovery.

[0067] S23. When it is determined that the state transition condition is met, the state of the state machine is switched.

[0068] In practice, when the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip is successful, then the state switching condition is met, and the state machine is switched to the data communication state.

[0069] Specifically, if the first state of the current state machine is the data communication channel establishment state, and the first chip and the second chip successfully handshake, then the state switching condition is met. The first chip switches the state machine to the data communication state, thereby enabling the communication state to enter the data communication stage.

[0070] In this embodiment, the switching conditions from the data communication channel establishment state to the data communication state are clearly defined, ensuring that the data communication stage will only be entered after a successful handshake with the second chip, and the data communication stage will not be entered if the handshake fails, thus avoiding the risk of transmitting business data when the data transmission link is not successfully established.

[0071] When the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip has timed out, or when the first state is the data communication state, if it is determined that the heartbeat has timed out based on the heartbeat message between the second chip, then the state switching condition is met. At this time, the state machine is switched to the fault handling state.

[0072] In specific implementation, if the first state of the current state machine is the data communication channel establishment state, and the handshake between the first chip and the second chip times out, then the state switching condition is determined to be met. The first chip switches the state machine to the fault handling state, thereby causing the communication state to enter the fault handling stage. Alternatively, if the first state of the current state machine is the data communication state, and the heartbeat between the first chip and the second chip times out, then the state switching condition is determined to be met. The first chip switches the state machine to the fault handling state, thereby causing the communication state to enter the fault handling stage.

[0073] In this embodiment, by monitoring whether the handshake timed out during the data communication channel establishment phase and whether the heartbeat timed out during the data communication phase, communication anomaly detection for the entire operating cycle is achieved. Handshake timeout or heartbeat timeout is used as the switching condition for switching to the fault handling state, rather than simply retrying to send the handshake message or resend the message, thereby improving the efficiency of communication anomaly detection and handling.

[0074] If the first state is determined to be the fault handling state, then after the software reset operation is completed, if the state switching conditions are met, the state machine will be switched to the data communication channel establishment state.

[0075] In practice, if the first state of the current state machine is the fault handling state, after the software reset operation is completed, it is determined that the state switching condition is met. The first chip switches the state machine to the data communication channel establishment state, forcibly resets the state machine back to the communication link establishment state, and triggers a new handshake process.

[0076] In this embodiment of the application, when the software reset operation is completed in the fault handling state, the system can automatically switch to the data communication channel establishment state and re-establish the communication link, thereby realizing the automatic recovery process from fault handling back to data communication link establishment.

[0077] In one implementation, the first chip is configured with an application programming interface (API) that allows other modules (referred to as the first module) to query the state of the first chip's state machine. The first module can be, but is not limited to, a power management module, a functional safety monitoring module, etc. The first chip can also proactively send the current state of its state machine to other modules through the API.

[0078] For example, after the first chip completes the software reset operation, it can also actively send a control command to the power management module to control the power management module to trigger a hardware reset operation on the first chip and the second chip, forming a composite recovery mechanism of software state cleaning and hardware link reconstruction, thereby improving the efficiency of anomaly handling.

[0079] In one implementation, when a release request is received from the power management module, it is determined that the state switching condition is met. At this time, the state machine is switched to the data communication channel release state.

[0080] In practice, before the vehicle enters sleep mode, the power management module can send a release request to the first chip through the setting application interface of the first chip. The release request is used to request the first chip to release the data communication channel with the second chip. When the first chip receives the release request sent by the power management module, it determines that the state switching condition is met and switches the state machine to the data communication channel release state, thereby entering the data communication channel release stage.

[0081] In this embodiment, the power management module sends a release request as a switching condition for switching to the data communication channel release state, ensuring that the data communication link between the vehicle and the second chip is safely released before the vehicle enters sleep mode, thus avoiding data loss caused by abnormal power outages.

[0082] In one implementation, the first chip can also receive a communication status query request sent by the first module, obtain the second state of the state machine, and return the second state to the first module through a set application programming interface.

[0083] In practical implementation, the first module can send a communication status query request through the configuration application interface set by the first chip. The first chip obtains the current second state of the state machine and returns the second state to the first module through the configuration application interface. For example, when the first module is a power management module, the power management module can query the current main state of the state machine in real time through the configuration application interface provided by the first chip. Based on the current communication status returned by the first chip, the power management module can make intelligent decisions. For example, when it is determined that the current communication status has entered the data communication channel release state or the fault handling state, it can control the relevant power domains (first chip and second chip) to enter the sleep state. Or, when the status cannot enter the data communication state for a long time, it can report a system-level fault, thereby achieving support for system collaboration.

[0084] In the above implementation, the communication status of the first chip is provided to the vehicle subsystem, such as the power management module and the functional safety monitoring module, through a standardized status query interface, so that other modules can make collaborative decisions based on the actual operation of the communication link and achieve system-level collaboration.

[0085] In this embodiment, a four-stage state machine model is used to clearly define the communication lifecycle between vehicle domain controller chips as four core states: "data communication channel establishment, data communication, data communication channel release, and fault handling." This state machine model fully covers the entire process of vehicular communication from link negotiation, service transmission, disconnection to anomaly recovery, providing a clear and reliable state framework for inter-process communication management in complex vehicular environments. A dual-path message routing mechanism achieves physical and logical separation of channel control messages and service data, ensuring the real-time and deterministic nature of critical processes. When a fault such as release timeout or heartbeat timeout occurs and the system enters the fault handling state, instead of a simple hardware reset or message retransmission, a targeted software state reset is performed, restoring the system to a clean initial state before automatically re-initiating the handshake process. This eliminates the erroneous state at its source and achieves complete recovery. Furthermore, by providing communication status query interfaces to modules such as power management, thermal management, and fault diagnosis, the entire vehicle system can make collaborative decisions based on the real health status of the IPC link (such as whether it has been successfully established or safely released), such as intelligent sleep management, thereby realizing information linkage between modules and system-level functional optimization.

[0086] The following describes the overall transition process of the four-stage communication states of a state machine, such as... Figure 7 As shown, this is a schematic diagram of the communication state transition process in the four stages of a state machine, which may include the following steps: S51, the first chip sets the state of the state machine to the data communication channel establishment state.

[0087] In practice, after the first chip is powered on, its IPC service layer is initialized, the state machine is set to the data communication channel establishment state, and the channel establishment processing function (that is, the first processing function corresponding to the channel control message) is called. This function sends and receives three-way handshake messages with the second chip.

[0088] S52. The first chip determines whether the handshake with the second chip is successful. If yes, proceed to step S53; otherwise, proceed to step S54.

[0089] S53. The first chip switches the state machine to the data communication state, executes step S56, and executes step S57 after receiving the release request sent by the power management module.

[0090] In practice, after the first chip and the second chip successfully handshake, the IPC service layer switches the state machine to the data communication state.

[0091] S54. The first chip determines whether the handshake between it and the second chip has timed out. If so, proceed to step S55; otherwise, proceed to step S51.

[0092] In practice, if the IPC service layer determines that the handshake with the second chip has timed out, it will execute step S55.

[0093] S55. The first chip switches the state machine to the fault handling state, and after the software state reset is completed, switches the state machine to the data communication channel establishment state, and re-executes step S51.

[0094] In practice, if it is determined that the handshake with the second chip has timed out, or the heartbeat with the second chip has timed out, the IPC service layer will switch the state machine to the fault handling state, perform a software reset operation, and after the software reset is completed, switch the state machine to the data communication channel establishment state, and re-execute step S51 to try to re-establish the data communication channel. At the same time, it can also notify the power management module to record the fault or perform a hardware reset on the first chip and the second chip.

[0095] S56. The first chip determines whether the heartbeat between it and the second chip has timed out. If so, step S55 is executed; otherwise, the state machine is maintained in the data communication state.

[0096] In practice, upon entering the data communication state, the IPC service layer calls the data communication processing function (i.e., the second processing function corresponding to the service data) to process the service messages from the second chip. Simultaneously, the IPC service layer processes heartbeat messages, keeping the data communication link active. If the heartbeat with the second chip times out, step S55 is executed.

[0097] S57, the first chip switches the state machine to the data communication channel release state.

[0098] In practice, the IPC service layer processes the data communication channel release signal sent by the power management module. After the data communication channel is released, the first chip can enter a low-power mode (such as sleep mode). When the first chip is powered on again, step S51 is executed again.

[0099] The following describes the message routing process based on the communication state of a state machine, such as... Figure 8 As shown, the following steps may be included:

[0100] S61. The first chip determines whether the state machine is in a data communication state. If so, it executes step S62; otherwise, it executes step S63.

[0101] S62. When the first chip receives a service message from the second chip, it queries the second message routing table to determine the second processing function corresponding to the service message, and distributes the service message to the corresponding service module so that the service module can call the second processing function to process the service message.

[0102] S63. When the first chip receives a communication control message from the second chip or the power management module, it queries the first message routing table to determine the first processing function corresponding to the communication control message, and processes the channel control message based on the first processing function.

[0103] S64. The first chip receives the processing result returned after processing.

[0104] The following describes the fault handling and recovery process when the state machine is in the fault handling state, such as... Figure 9 As shown, the following steps may be included: S71, The first chip determines that the handshake with the second chip has timed out or the heartbeat has timed out.

[0105] S72, the first chip switches the state machine to the fault handling state.

[0106] S73, the first chip performs a software reset operation.

[0107] S74. After the software reset operation is completed, the first chip switches the state machine to the data communication channel establishment state.

[0108] S75, the first chip automatically triggers the handshake process with the second chip.

[0109] Optionally, step S76 may also be performed.

[0110] The software reset operation of the S76, first chip notification power management module and other collaborative modules is complete.

[0111] For example, the structure diagram of the MCU's IPC service layer is as follows: Figure 10 As shown, the IPC service layer 1012 may include: a state machine management module 1012-1, a message routing module 1012-2, a state processing module 1012-3, and an interface module 1012-4.

[0112] The state machine management module 1012-1 defines and maintains a global variable eIpcStageStatus of enumeration type. This global variable is used to represent the main communication state. It provides interfaces such as Ipc_ServiceSetStageStatus() and Ipc_ServiceSetStageStatus() for other modules to read and write the state. Among them, the Ipc_ServiceSetStageStatus() interface is provided by the IPC module, which can call this interface to write the state of the state machine. The Ipc_ServiceSetStageStatus() interface is provided by modules such as the power management module and the functional safety monitoring module, which can call the Ipc_ServiceSetStageStatus() interface to read (query) the state of the state machine.

[0113] The main loop task of IPC service layer 1012 periodically calls the status scheduling function Ipc_ServiceStatusMainFunciton(). For example, the status scheduling function Ipc_ServiceStatusMainFunciton() can be set as follows: void Ipc_ServiceStatusMainFunciton(void) { switch(Ipc_ServiceGetStageStatus()) { case IPC_STAGE_SETUP_CHANNEL: / Call the channel establishment processing function / break; case IPC_STAGE_COMMUNICATION: / Call the data communication processing function / break; case IPC_STAGE_RELEASE_CHANNEL: / Call the channel release handler function / break; case IPC_STAGE_ERROR: / Call the fault handling function / break; } }

[0114] In the state scheduling function described above, when the state machine switches states, a switch-case statement (multi-branch selection statement) can be used to jump to the corresponding state handling function.

[0115] The message routing module 1012-2 contains two routing table data structures: a first message routing table (g_ipcRxManagerMessageTab) and a second message routing table (g_rxMessageTab). The first message routing table is used for channel control messages, and the second message routing table is used for service messages. The first message routing table is an array of structures, and each element can contain: a channel control message identifier and a pointer to a channel management callback function. Different types of channel control messages correspond to different channel management callback functions, for example: {MSG_DOWNLINK_REQUEST_SETUP_CHANNEL, Ipc_RxSetupChannelRequestHandle}, where MSG_DOWNLINK_REQUEST_SETUP_CHANNEL represents the downlink channel establishment request message identifier (i.e., the identifier of the channel establishment request message sent by the SoC to the MCU), and Ipc_RxSetupChannelRequestHandle represents the channel management callback function corresponding to the channel establishment request message. The structure of the second message routing table is similar to that of the first message routing table. Each element can contain: an application service message identifier and an application processing function. Different types of application service messages correspond to different application processing functions. For example: {MSG_DOWN_CLASS_ID_CAN, Ipc_AppRxCanProcess}, where MSG_DOWN_CLASS_ID_CAN represents the downlink body CAN message identifier, and Ipc_AppRxCanProcess represents the application processing function corresponding to the body CAN message. The message routing module 1012-2 determines which routing table to use for message distribution and processing based on the message type from the SoC.

[0116] The state processing module 1012-3 includes sub-functions: channel establishment processing function, data communication processing function, channel release processing function, and fault processing function. Each sub-function corresponds to a main state.

[0117] When the state machine is in the data communication channel establishment state, the state processing module 1012-3 calls the channel establishment processing function Ipc_ServiceRxManagerMessageHandle() to read data (i.e., channel control messages, such as handshake messages) from the message buffer, and executes the callback function corresponding to the handshake message by querying the first message routing table. For example, after the MCU receives the handshake request from the SoC, it replies to the SoC with the version information of the communication protocol used.

[0118] When the state machine is in the data communication state, the state processing module 1012-3 calls the data communication processing function to execute the corresponding application's business message. The data communication processing function includes Ipc_ServiceRxAppMessageHandle() and Ipc_ServiceTxAppMessageHandle(). Ipc_ServiceRxAppMessageHandle() is used to read the application's business data from the cache and distribute the application's business data to the corresponding business module, such as the CAN module and the fault diagnosis module, by querying the second message routing table. Ipc_ServiceTxAppMessageHandle() is used to check and send the business data to be sent submitted by the business module.

[0119] When the state machine is in the channel release state, the state processing module 1012-3 calls the channel release processing function Ipc_ServiceReleaseHandle() to disconnect the data communication link (e.g., before the vehicle enters sleep mode). In this state, the state processing module 1012-3 can send a release request message to the peer (SoC) and continuously receive release response messages (such as release completion messages) returned by the peer through Ipc_ServiceRxManagerMessageHandle(). It then dispatches the release response message to the corresponding release callback function (such as the Ipc_RxReleaseChannelCompleteHandle() function) by querying the first message routing table, thereby providing a release completion flag to other modules (such as the PM module) and switching the state to the data channel establishment state (IPC_STAGE_SETUP_CHANNEL), waiting for a handshake request.

[0120] When the state machine is in the fault handling state, the state handling module 1012-3 calls the fault handling function Ipc_ServiceInitHandle(), which is an initialization function. This initialization function does not involve hardware and is used to reset all software state variables, such as the timeout counter and error count in the g_ipcInfo structure, and reset the state machine to the data communication channel establishment state (IPC_STAGE_SETUP_CHANNEL), thereby providing a clean software context for re-handshaking with the SoC.

[0121] Interface module 1012-4 provides application interfaces such as the handshake status reading function Ipc_ServiceGetHandshakeStatus(). The power management module can periodically query the handshake status between the MCU and the SoC through this interface. If the handshake status remains in the "error" or "establishing" state for a long time, the power management module can determine that there is a failure in the inter-process communication between the MCU and the SoC, thereby triggering a system-level collaborative processing flow.

[0122] In one implementation, the first chip can also be a SoC, in which case the second chip is an MCU. The first chip and the second chip are different types of chips, and this application does not limit this.

[0123] The foregoing primarily describes the inter-chip communication control method provided in this application from the perspective of the first chip. It is understood that, to achieve the above functions, the first chip includes the corresponding hardware structure and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0124] Based on the same technical concept, embodiments of this application provide an inter-chip communication control device, which includes a module / unit / means for executing the method executed by the first chip in the above method embodiments. This module / unit / means can be implemented in software, or in hardware, or implemented by hardware executing corresponding software.

[0125] For example, see Figure 11 This device can be applied to Figure 1 or Figure 2 The first chip in the vehicle domain controller, the vehicle domain controller also includes a second chip and a power management module, the first chip and the second chip are of different types; the device can be executed by the first chip, and the device may include: The first state acquisition module 81 is used to acquire the first state of the state machine running on the first chip. The first state represents the current communication state between the first chip and the second chip. The first state is a data communication channel establishment state, a data communication state, a data communication channel release state, or a fault handling state. Processing module 82 is used to perform corresponding processing based on the first state. The processing module 82 is specifically configured to, if it is determined that the first state is the data communication channel establishment state or the data communication channel release state, process the channel control message sent by the second chip or the power management module based on the first message routing table; and if it is determined that the first state is the data communication state, process the service message sent by the second chip based on the second message routing table. The state switching module 83 is used to switch the state of the state machine when it is determined that the state switching conditions are met.

[0126] In one optional implementation, the processing module 82 is specifically used to query the first processing function corresponding to the channel control message based on the first message routing table; and to process the channel control message based on the first processing function.

[0127] In one optional implementation, the processing module 82 is specifically used to query the second processing function corresponding to the business message based on the second message routing table; and to process the business message based on the second processing function.

[0128] In an optional implementation, the processing module 82 is further configured to perform a software reset operation if the first state is determined to be a fault handling state. The software reset operation includes at least one of the following operations: clearing the timeout counter, clearing the communication sequence number, and clearing the data in the data buffer.

[0129] In one optional implementation, the state switching module 83 is specifically used to determine that the state switching condition is met when the first state is the data communication channel establishment state and it is determined that the handshake with the second chip is successful; and to switch the state of the state machine to the data communication state.

[0130] In one optional implementation, the state switching module 83 is specifically used to determine that the state switching condition is met when the first state is the data communication channel establishment state and it is determined that the handshake with the second chip has timed out, or when the first state is the data communication state and it is determined that the heartbeat has timed out based on the heartbeat message between the first state and the second chip; and to switch the state of the state machine to the fault handling state.

[0131] In one optional implementation, the state switching module 83 is specifically used to determine that the state switching conditions are met after the software reset operation is completed if the first state is determined to be a fault handling state; and to switch the state of the state machine to the data communication channel establishment state.

[0132] In one optional implementation, the state switching module 83 is specifically used to determine that the state switching conditions are met when a release request is received from the power management module; and to switch the state of the state machine to the data communication channel release state.

[0133] In one alternative implementation, the apparatus further includes: The receiving module is used to receive communication status query requests sent by the first module; The second state acquisition module is used to acquire the second state of the state machine; The return module is used to return the second state to the first module by setting the application programming interface.

[0134] It should be understood that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0135] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0136] Based on the same technical concept, see [link / reference] Figure 12 This application also provides an electronic device 900, including: at least one processor 901; and a communication interface 903 communicatively connected to the at least one processor 901; the at least one processor 901 executes instructions stored in a memory 902, causing the electronic device 900 to execute the method steps performed by the electronic device in the above method embodiment through the communication interface 903.

[0137] Optionally, the memory 902 is located outside the electronic device 900.

[0138] Optionally, the electronic device 900 includes a memory 902 connected to the at least one processor 901, and the memory 902 contains instructions executable by the at least one processor 901. (See attached image) Figure 12 The dashed line indicates that the memory 902 is optional for the electronic device 900.

[0139] The at least one processor 901 and the memory 902 can be coupled through an interface circuit or integrated together, which is not limited here.

[0140] This application embodiment does not limit the specific connection medium between at least one processor 901, memory 902, and communication interface 903. This application embodiment... Figure 12 At least one processor 901, memory 902, and communication interface 903 are connected via a bus 904, and the bus is in Figure 12 The connections between other components are shown in bold and are for illustrative purposes only, not as limiting information. This bus section can be an address bus, data bus, control bus, etc. For ease of illustration, Figure 12 It is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0141] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor, implemented by reading software code stored in memory.

[0142] For example, the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0143] It should be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which acts as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct RAM (DR RAM).

[0144] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0145] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0146] Based on the above embodiments and the same concept, this application also provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the method performed by the electronic device in the above embodiments.

[0147] Based on the above embodiments and the same concept, this application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer causes the computer to perform the method performed by the electronic device in the above embodiments.

[0148] Those skilled in the art will understand that the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above methods can be implemented, in whole or in part, in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. Semiconductor media can be solid-state drives (SSDs).

[0149] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0150] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0152] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A communication control method between chips, characterized by, A first chip is applied in a vehicle domain controller, the vehicle domain controller further includes a second chip and a power management module, the first chip and the second chip are chips of different types; the method includes: Obtain the first state of the state machine running on the first chip. The first state represents the current communication state between the first chip and the second chip. The first state is a data communication channel establishment state, a data communication state, a data communication channel release state, or a fault handling state. Based on the first state, corresponding processing is performed, specifically including: if the first state is determined to be the data communication channel establishment state or the data communication channel release state, then the channel control message sent by the second chip or the power management module is processed based on the first message routing table; if the first state is determined to be the data communication state, then the service message sent by the second chip is processed based on the second message routing table. When the state transition condition is determined to be met, the state of the state machine is switched.

2. The method as described in claim 1, characterized in that, The channel control messages sent by the second chip or the power management module are processed based on the first message routing table, specifically including: Based on the first message routing table, query the first processing function corresponding to the channel control message; The channel control message is processed based on the first processing function.

3. The method as described in claim 1, characterized in that, The service messages sent by the second chip are processed based on the second message routing table, specifically including: Based on the second message routing table, query the second processing function corresponding to the business message; The business message is processed based on the second processing function.

4. The method as described in claim 1, characterized in that, Based on the first state, the corresponding processing is performed, which also includes: If the first state is determined to be a fault handling state, a software reset operation is performed. The software reset operation includes at least one of the following operations: clearing the timeout counter, clearing the communication sequence number, and clearing the data in the data buffer.

5. The method as described in claim 1, characterized in that, The conditions for state transition are determined to be met, specifically including: When the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip is successful, then it is determined that the state transition condition is met; and Switching the states of the state machine specifically includes: Switch the state of the state machine to the data communication state.

6. The method as described in claim 1, characterized in that, The conditions for state transition are determined to be met, specifically including: When the first state is the data communication channel establishment state, if it is determined that the handshake with the second chip has timed out, or when the first state is the data communication state, if it is determined that the heartbeat has timed out based on the heartbeat message between the second chip, then it is determined that the state switching condition is met; and Switching the states of the state machine specifically includes: Switch the state of the state machine to the fault handling state.

7. The method as described in claim 4, characterized in that, The conditions for state transition are determined to be met, specifically including: If the first state is determined to be a fault handling state, then after the software reset operation is completed, it is determined that the state transition conditions are met; and Switching the states of the state machine specifically includes: Switch the state of the state machine to the state of establishing the data communication channel.

8. The method as described in claim 1, characterized in that, The conditions for state transition are determined to be met, specifically including: When a release request is received from the power management module, it is determined that the state transition conditions are met; and Switching the states of the state machine specifically includes: Switch the state of the state machine to the data communication channel release state.

9. The method as described in claim 1, characterized in that, Also includes: Receive the communication status query request sent by the first module; Obtain the second state of the state machine; The second state is returned to the first module by setting the application programming interface.

10. A chip-to-chip communication control device, characterized in that, A first chip is used in a vehicle domain controller, the vehicle domain controller further includes a second chip and a power management module, the first chip and the second chip are chips of different types; the device includes: The first state acquisition module is used to acquire the first state of the state machine running on the first chip. The first state represents the current communication state between the first chip and the second chip. The first state is a data communication channel establishment state, a data communication state, a data communication channel release state, or a fault handling state. The processing module is used to perform corresponding processing based on the first state; The processing module is specifically configured to, if it is determined that the first state is the data communication channel establishment state or the data communication channel release state, process the channel control message sent by the second chip or the power management module based on the first message routing table; and if it is determined that the first state is the data communication state, process the service message sent by the second chip based on the second message routing table. The state switching module is used to switch the state of the state machine when it is determined that the state switching conditions are met.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the inter-chip communication control method as described in any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the inter-chip communication control method as described in any one of claims 1 to 9.

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