Image sensor and method of operating the same

Abstract

An image sensor and an operating method thereof are provided. The image sensor includes a pixel including a photodiode that accumulates an electric charge based on light, a first transfer transistor connected between the photodiode and a first floating diffusion node and operated based on a first transfer signal, a second transfer transistor connected between the photodiode and a second floating diffusion node and operated based on a second transfer signal, a dual conversion transistor connected between the first floating diffusion node and the second floating diffusion node and operated based on a dual conversion signal, a reset transistor connected between a first power terminal and the second floating diffusion node and operated based on a reset signal, a drive transistor connected between a second power terminal and a first node and operated based on a first floating diffusion node voltage, and a selection transistor connected between the first node and a column line and operated based on a selection signal.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate to image sensors and methods of operating thereof. Background Technology

[0002] An image sensor converts light received by a photodiode into an electrical signal. For example, an image sensor converts a light signal corresponding to light reflected from an external object into an electrical signal, thereby obtaining image data of the external object. Electronic devices that include an image sensor can display an image on a display panel using the obtained image data.

[0003] Meanwhile, in order to achieve high dynamic range (HDR), the image sensor can acquire image data by performing readout operations via dual conversion gain mode. Summary of the Invention

[0004] The exemplary embodiments of this disclosure propose a scheme to improve the performance of image sensors that support dual-conversion gain modes.

[0005] Embodiments of this disclosure provide an image sensor including pixels that support a dual conversion gain mode.

[0006] According to one aspect of this disclosure, an image sensor is provided, including a pixel, wherein the pixel includes: a photodiode configured to accumulate charge based on an optical signal; a first transfer transistor connected between the photodiode and a first floating diffusion node, the first transfer transistor being configured to operate based on a first transfer signal; a second transfer transistor connected between the photodiode and a second floating diffusion node, the second transfer transistor being configured to operate based on a second transfer signal; a dual-conversion transistor connected between the first floating diffusion node and the second floating diffusion node, the dual-conversion transistor being configured to operate based on a dual-conversion signal; a reset transistor connected between a first power supply terminal and the second floating diffusion node, the reset transistor being configured to operate based on a reset signal; a drive transistor connected between a second power supply terminal and a first node, the drive transistor being configured to operate based on a voltage of the first floating diffusion node; and a selection transistor connected between the first node and a column line, the selection transistor being configured to operate based on a selection signal.

[0007] According to another aspect of this disclosure, an image sensor is provided, including a pixel comprising: a first transfer transistor, a second transfer transistor, and a photodiode, the photodiode being configured to accumulate charge based on an optical signal, wherein, based on the pixel operating in a high conversion gain mode: the first transfer transistor is configured to transfer a portion of the charge accumulated in the photodiode to a first floating diffusion node, and the second transfer transistor is configured to transfer at least a portion of the remaining charge accumulated in the photodiode to a second floating diffusion node, and wherein a first readout operation is performed corresponding to the portion of charge transferred to the first floating diffusion node; and wherein the pixel is configured to enter a low conversion gain mode after the first readout operation.

[0008] According to another aspect of this disclosure, an image sensor is provided, comprising: a pixel array including a plurality of pixels; a timing controller configured to generate a control signal; and a row decoder configured to generate at least one of a first transfer signal, a second transfer signal, a dual-conversion signal, a reset signal, and a selection signal based on the control signal to drive the pixel array. Each of the plurality of pixels may include: a photodiode configured to accumulate charge based on an optical signal; a first transfer transistor connected between the photodiode and a first floating diffusion node, the first transfer transistor being configured to operate based on the first transfer signal; a second transfer transistor connected between the photodiode and a second floating diffusion node, the second transfer transistor being configured to operate based on a second transfer signal; a dual-conversion transistor connected between the first floating diffusion node and the second floating diffusion node, the dual-conversion transistor being configured to operate based on a dual-conversion signal; a reset transistor connected between a first power supply terminal and the second floating diffusion node, the reset transistor being configured to operate based on a reset signal; a drive transistor connected between a second power supply terminal and a first node, the drive transistor being configured to operate based on a voltage of the first floating diffusion node; and a selection transistor connected between the first node and a column line, the selection transistor being configured to operate based on a selection signal. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating an image processing system according to an embodiment of the present disclosure.

[0011] Figure 2A and 2B This is a block diagram illustrating an image sensor according to an embodiment of the present disclosure.

[0012] Figure 3 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure.

[0013] Figure 4 This is a timing diagram illustrating an example of the operation of an image sensor according to an embodiment of the present disclosure.

[0014] Figure 5 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure.

[0015] Figure 6 This is a timing diagram illustrating an example of the operation of an image sensor according to an embodiment of the present disclosure.

[0016] Figures 7A to 7E This is a diagram that conceptually describes the operation of pixels according to embodiments of the present disclosure.

[0017] Figure 8A and Figure 8B This is a diagram that conceptually describes the operation of pixels according to embodiments of the present disclosure.

[0018] Figure 9 This is a flowchart illustrating an example of the operation of an image sensor according to an embodiment of the present disclosure.

[0019] Figure 10 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure.

[0020] Figure 11 It is a block diagram of an electronic device that includes multiple camera modules.

[0021] Figure 12 It is shown in detail Figure 11 A block diagram of the camera module. Detailed Implementation

[0022] In the following, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can readily implement the disclosure.

[0023] The components described with reference to the terminology used in the detailed description or claims and the functional blocks shown in the drawings can be implemented in software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. For example, hardware can include, but is not limited to, electrical circuits, electronic circuits, electrical components, processors, memory, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, passive components, or combinations thereof.

[0024] Figure 1 This is a block diagram illustrating an image processing system according to an embodiment of the present disclosure. Reference Figure 1The image processing system 10 may include a lens 12, an image sensor 14, an image signal processor (ISP) front-end block 16, and an image signal processor 18. However, this disclosure is not limited thereto, and therefore, according to embodiments, the image processing system 10 may include one or more additional elements. The image processing system 10 may be implemented as part of various electronic devices such as smartphones, digital cameras, laptops, and desktop computers.

[0025] Light can be reflected by the object to be photographed, scenery, etc., and lens 12 can receive the reflected light. Image sensor 14 can generate an electrical signal based on the light (or optical signal) received through lens 12. For example, image sensor 14 can be implemented as a complementary metal-oxide-semiconductor (CMOS) image sensor, etc. For example, image sensor 14 can be a multi-pixel image sensor with a dual-pixel structure or a tetracell structure.

[0026] Image sensor 14 may include a pixel array. The pixel array may include pixels that convert light into electrical signals. For example, pixels can generate pixel signals (e.g., electrical signals) by converting light. The ratio at which light is converted into electrical signals (e.g., voltage) can be defined as the conversion gain. For example, the pixel array can generate pixel signals in a low conversion gain mode (hereinafter referred to as "LCG mode") and a high conversion gain mode (hereinafter referred to as "HCG mode") using a dual conversion gain (DCG) with varying conversion gain.

[0027] According to an embodiment, the image sensor 14 may include an analog-to-digital conversion circuit (hereinafter referred to as "ADC circuit") for performing correlated double sampling (CDS) on the pixel signals. Reference Figure 2A and Figure 2B The configuration of image sensor 14 is described in more detail.

[0028] According to an embodiment, the ISP front-end block 16 can perform preprocessing on the electrical signal output from the image sensor 14 to suit the processing of the image signal processor 18. For example, the ISP front-end block 16 can perform preprocessing on the electrical signal output from the image sensor 14 and input the preprocessed electrical signal to the image signal processor 18.

[0029] According to an embodiment, the image signal processor 18 can generate image data associated with the captured object, landscape, etc., by appropriately processing the electrical signals processed by the ISP front-end block 16. For this purpose, the image signal processor 18 can perform various processes, such as color correction, automatic white balance, gamma correction, color saturation correction, bad pixel correction, and tone correction.

[0030] Although Figure 1The image processing system 10 is shown as including a lens 12 and an image sensor 14, but this is an example and the scope of this disclosure is not limited thereto. For example, the image processing system 10 may include multiple lenses, multiple image sensors, and multiple ISP front-end blocks. In this case, the multiple lenses may have different fields of view from each other. Furthermore, each of the multiple image sensors may have different functions, different performance, and / or different characteristics, and may include pixel arrays with different configurations.

[0031] Figure 2A and 2B This is a block diagram illustrating an image sensor according to an embodiment of the present disclosure. Reference Figure 1 and Figure 2A The image sensor 100 may include a pixel array 110, a line decoder 120, a ramp generator 130, an ADC circuit 140, a buffer circuit 150, and a timing controller 160.

[0032] Pixel array 110 may include multiple pixel PIXs and may be in the form of a matrix including multiple pixel rows and multiple pixel columns. In other words, each of the multiple pixel PIXs may be arranged along both row and column directions. Pixel PIXs located in the same column may be connected to the same column line CL. Pixel PIXs located in the same row may be connected to the same reset line.

[0033] Each of the plurality of pixel PIXs in pixel array 110 may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photodiode, phototransistor, photogate, pinned photodiode, etc. Each of the plurality of pixel PIXs can detect light using the photoelectric conversion element and convert the optical signal corresponding to the detected light into an electrical signal (e.g., a pixel signal). For example, each of the plurality of pixel PIXs may output a pixel signal based on the intensity or amount of light received from the outside. In this case, the pixel signal may be an analog signal corresponding to the intensity or amount of light received from the outside.

[0034] Although Figure 2A The pixel array 110 is shown as comprising four rows and four columns (i.e., 4 × 4) of pixel PIX, but this is an example and the scope of this disclosure is not limited thereto, and the number of multiple pixel PIX may be less or more than the number described above, and the arrangement structure may differ from that described above.

[0035] As described above, the pixel PIX according to embodiments of this disclosure can support dual conversion gain mode. Therefore, the pixel PIX can operate in HCG mode or LCG mode.

[0036] Multiple pixel PIXs can generate pixel signals based on various signals received from the row decoder 120 and output the generated pixel signals through multiple column lines CL. These various signals can include (but are not limited to) control signals such as the transfer signal VTS, the reset signal VRST, the double conversion signal VDC, or the selection signal VSEL. For example, each of the multiple pixel PIXs can output an HCG pixel signal in HCG mode and an LCG pixel signal in LCG mode.

[0037] The line decoder 120 can select and drive the rows of the pixel array 110. For example, the line decoder 120 can decode the address and / or control signals generated by the timing controller 160 to generate control signals (e.g., transfer signal VTS, reset signal VRST, dual conversion signal VDC, select signal VSEL, etc.) for selecting and driving the rows of the pixel array 110.

[0038] Ramp generator 130 can generate a ramp signal RAMP. Ramp generator 130 can operate under the control of timing controller 160. For example, ramp generator 130 can operate in response to control signals (such as ramp enable signals, mode signals, etc.). In the example case where the ramp enable signal is activated, ramp generator 130 can generate the ramp signal RAMP based on a reference value. For example, when the ramp enable signal is activated, ramp generator 130 can generate the ramp signal RAMP based on a reference value. The reference value can be a predetermined value. For example, the predetermined value can include, but is not limited to, a start level, an end level, a ramp, etc. That is, the ramp signal RAMP can be a signal that increases or decreases according to a predetermined ramp during a specific time period. The ramp signal RAMP can be provided to ADC circuit 140.

[0039] The ADC circuit 140 can receive pixel signals from multiple pixels of the pixel array 110 via column lines CL, and can receive ramp signals RAMP from the ramp generator 130. The ADC circuit 140 can perform analog-to-digital conversion on the pixel signals. For example, the ADC circuit 140 converts the pixel signals (which are analog signals) output from the pixel array 110 into digital signals. The ADC circuit 140 may include multiple ADCs. For example, each of the multiple ADCs may operate based on correlated double sampling (CDS) technology, which obtains the reset level and signal level of the pixel signal received from the corresponding pixel and extracts the difference as the effective signal component.

[0040] For example, each of a plurality of ADCs may include a comparator and a counter. The comparator can compare the pixel signal output by the corresponding pixel PIX through the column line CL with the ramp signal RAMP and output the comparison result. The counter can count the pulses of the signal output by the corresponding comparator that have been subjected to correlated double sampling (CDS) and output the counted pulses as a digital signal.

[0041] For example, the ADC circuit 140 can perform analog-to-digital conversion by comparing the HCG reset level and HCG signal level for the HCG pixel signal and the LCG reset level and LCG signal level for the LCG pixel signal output by each of the multiple pixel PIXs with the ramp signal RAMP level.

[0042] The buffer circuit 150 can store the digital signal output from the ADC circuit 140. The buffer circuit 150 can detect and amplify the stored digital signal. The buffer circuit 150 can also output the amplified digital signal as image data. For example, the buffer circuit 150 can transmit image data to the ISP front-end block 16 (such as...). Figure 1 (As shown).

[0043] As described above, each of the plurality of pixel PIXs included in the pixel array 110 of the image sensor 100 may include a photoelectric conversion element and supports a dual conversion gain mode. The image sensor 100 according to embodiments of this disclosure can perform readout operations in both HCG and LCG modes. For example, each of the plurality of pixel PIXs may include two or more floating diffusion nodes.

[0044] For example, each of the multiple pixel PIXs may include a first floating diffusion node and a second floating diffusion node. For example, in HCG mode, the first and second floating diffusion nodes may not be electrically connected. For example, in LCG mode, the first and second floating diffusion nodes may be electrically connected. In this case, in LCG mode, the first and second floating diffusion nodes are electrically connected, allowing the generation of extended floating diffusion nodes.

[0045] The photoelectric conversion element can accumulate charge based on the optical signal. A pixel can transfer a portion of the charge accumulated in the photoelectric conversion element to a first floating diffusion node. Furthermore, a pixel can transfer the remaining charge accumulated in the photoelectric conversion element to a second floating diffusion node.

[0046] The image sensor 100 can perform a first readout operation (or HCG readout operation) on the first floating diffusion node in HCG mode, and a second readout operation (or LCG readout operation) on the extended floating diffusion node in LCG mode. Here, before the image sensor 100 performs the first and second readout operations, the image sensor 100 can perform operations to transfer the partial charge and the remaining charge to the first and second floating diffusion nodes, respectively. (Refer to the following...) Figures 5 to 8B The pixel configuration and operation of the image sensor 100 are described in detail.

[0047] refer to Figure 1 and Figure 2B The image sensor 100 may include a pixel array 110, a line decoder 120, a ramp generator 130, a buffer circuit 150, and a timing controller 160. Figure 2A The image sensors are 100 different. Figure 2B The image sensor 100 may not include a separate ADC circuit 140, and each of the multiple pixel PIXs may include an internal ADC. That is, Figure 2B The image sensor 100 may be an image sensor 100 including a pixel array 110 implemented based on a pixel-level ADC structure. In the following text, those configured to... Figure 2A The image sensors have the same configuration and operate in the same way. Figure 2B Redundant description of the configuration of the image sensor 100.

[0048] Each of the multiple pixel PIXs may include an internal ADC. Each of the multiple pixel PIXs may generate a pixel signal based on a light signal detected by a photoelectric conversion element. The generated pixel signal may be converted into a digital signal by the internal ADC. For example, when the pixel signal is in Figure 2A When the image sensor 100 outputs the pixel signal to the ADC circuit 140 via the column line CL, the pixel signal can... Figure 2B The image sensor 100 outputs digital signals previously converted by an internal ADC within the pixel via column lines CL.

[0049] For example, each of the multiple pixel PIXs may also include local memory. The digital signal converted by the internal ADC can be stored in the local memory. The image sensor 100 can transmit the digital signal stored in the local memory included in each of the multiple pixel PIXs to the buffer circuit 150 via the column line CL.

[0050] The ramp generator 130 can provide a ramp signal RAMP to the pixel array 110 under the control of the timing controller 160. For example, the ramp generator 130 can transmit the ramp signal RAMP to each of the plurality of pixel PIXs in the pixel array 110. The internal ADC of each of the plurality of pixel PIXs can convert the pixel signal into a digital signal based on the ramp signal RAMP received from the ramp generator 130.

[0051] Figure 3 This is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure. Reference Figure 3 A pixel PIX may include a photodiode PD, a transfer transistor TG, a dual conversion gain transistor DCG, a reset transistor RG, a drive transistor DG, a select transistor SEL, an internal ADC, and local memory.

[0052] The transfer transistor TG can be connected between the photodiode PD and the first floating diffusion node FD1, and can include a gate electrode for receiving the transfer signal VTS.

[0053] The dual-conversion gain transistor DCG can be connected between the first floating diffusion node FD1 and the second floating diffusion node FD2, and can include a gate electrode that receives the dual-conversion signal VDC.

[0054] The reset transistor RG can be connected between the first power supply terminal and the second floating diffusion node FD2, and can include a gate electrode that receives the reset signal VRST. Here, the first power supply terminal can receive a first power supply voltage VDD1.

[0055] The driving transistor DG can be connected between the second power supply terminal and the first node N1, and can include a gate electrode connected to the first floating diffusion node FD1. Here, the second power supply terminal can receive the second power supply voltage VDD2.

[0056] The select transistor SEL can be connected between the first node N1 and the internal ADC, and can include a gate electrode that receives the select signal VSEL.

[0057] A photodiode (PD) can accumulate charge based on an externally incident light signal. For example, a PD can generate a charge corresponding to the intensity of light incident on it from the outside, and accumulate the generated charge.

[0058] The transfer transistor TG can operate based on the transfer signal VTS, the dual conversion gain transistor DCG can operate based on the dual conversion signal VDC, the reset transistor RG can operate based on the reset signal VRST, the drive transistor DG can operate based on the voltage of the first floating diffusion node FD1, and the select transistor SEL can operate based on the select signal VSEL.

[0059] In the example where the dual-conversion-gain transistor DCG is off, the first floating diffusion node FD1 and the second floating diffusion node FD2 may not be electrically connected. In the example where the dual-conversion-gain transistor DCG is on, the first floating diffusion node FD1 and the second floating diffusion node FD2 may be electrically connected. In this disclosure, the first floating diffusion node FD1 and the second floating diffusion node FD2, which are electrically connected when the dual-conversion-gain transistor DCG is on, are referred to as extended floating diffusion nodes. Extended floating diffusion nodes may also be referred to as expanded floating diffusion nodes.

[0060] In the example scenario where the dual conversion gain transistor DCG is off, the pixel PIX can operate in HCG mode. In the example scenario where the dual conversion gain transistor DCG is on, the pixel PIX can operate in LCG mode. For example, the pixel PIX can operate in HCG mode and then in LCG mode.

[0061] According to an embodiment, the pixel PIX can transfer a portion of the charge accumulated in the photodiode PD to the first floating diffusion node FD1 in HCG mode, and can perform a first readout operation on the portion of charge transferred to the first floating diffusion node FD1.

[0062] According to an embodiment, the pixel PIX can transfer the remaining charge accumulated in the photodiode PD to an extended floating diffusion node in LCG mode, and can perform a second readout operation on the remaining charge transferred to the extended floating diffusion node. For example, after performing a first readout operation, the pixel PIX can transfer the remaining charge accumulated in the photodiode PD to an extended floating diffusion node in LCG mode, and can perform a second readout operation on the remaining charge transferred to the extended floating diffusion node.

[0063] exist Figure 3 In the diagram, although the pixel PIX is shown as being implemented based on a pixel-level ADC structure, such as including Figure 2B The image sensor 100 contains a pixel array 110 with multiple pixels, but this is just an example, and the scope of this disclosure is not limited thereto. For example, a pixel PIX can be implemented as including multiple pixels in the pixel array 110. Figure 2A Multiple pixels in the pixel array 110 of the image sensor 100.

[0064] Figure 4 This is a timing diagram illustrating an example of the operation of an image sensor according to embodiments of the present disclosure. Reference Figure 3 and Figure 4The following example illustrates the levels of the time-dependent reset signal VRST, double-conversion signal VDC, transfer signal VTS, selection signal VSEL, and ramp signal RAMP. Figure 4 In the timing diagram, the horizontal axis represents time 'T', and the vertical axis represents voltage level 'V'.

[0065] During the time period between the zero time point T00 and the fifth time point T05, the image sensor 100 can operate in HCG mode, and during the time period after the fifth time point T05, the image sensor 100 can operate in LCG mode. The image sensor 100 can sample the HCG pixel signal during the time period between the zero time point T00 and the fourth time point T04, and can perform a first readout operation during the time period between the fourth time point T04 and the fifth time point T05. During the time period between the fifth time point T05 and the ninth time point T09, the image sensor 100 can sample the LCG pixel signal, and during the time period after the ninth time point T09, the image sensor 100 can perform a second readout operation.

[0066] During the period between the second time point T02 and the third time point T03, the transfer signal VTS can be at a logic high level. During the period between the second time point T02 and the third time point T03, the transfer transistor TG can be turned on, and the transfer transistor TG can transfer part of the charge accumulated in the photodiode PD to the first floating diffusion node FD1.

[0067] During the period between the fourth time point T04 and the fifth time point T05, the image sensor 100 can perform a first readout operation corresponding to the portion of charge transferred to the first floating diffusion node FD1.

[0068] During the period between time point T06 and time point T07, both the transfer signal VTS and the double-conversion signal VDC can be at a logic high level. During the period between time point T06 and time point T07, both the transfer transistor TG and the double-conversion gain transistor DCG can be turned on, and the transfer transistor TG can transfer the remaining charge accumulated in the photodiode PD to the extended floating diffusion node.

[0069] During the period following the ninth time point T09, the image sensor 100 may perform a second readout operation corresponding to the remaining charge transferred to the extended floating diffusion node.

[0070] According to an embodiment, the time period during which the image sensor 100 performs sampling can be shorter than the time period during which the image sensor 100 performs readout operations. For example, the time spent by the image sensor 100 sampling pixel signals during the period between the zero time point T00 and the fourth time point T04, and during the period between the fifth time point T05 and the ninth time point T09, can be shorter than the time spent by the image sensor 100 performing readout operations on pixel signals during the period between the fourth time point T04 and the fifth time point T05, and during the period after the ninth time point T09.

[0071] According to embodiments of this disclosure, in the image sensor 100, a long time period (e.g., the time period between the third time point T03 and the sixth time point T06) may exist between the second time point T02 and the third time point T03, and between the sixth time point T06 and the seventh time point T07. That is, there may be an exposure integration time (EIT) difference between the time period between the second time point T02 and the third time point T03 and the time period between the sixth time point T06 and the seventh time point T07.

[0072] For example, from the time the image sensor 100 transfers a portion of the charge corresponding to the HCG pixel signal from the photodiode PD to the first floating diffusion node FD1 until the image sensor 100 transfers the remaining charge corresponding to the LCG pixel signal from the photodiode PD to the extended floating diffusion node (e.g., during the period between the third time point T03 and the sixth time point T06), the photodiode PD can receive more light from the outside. Therefore, the photodiode PD can additionally accumulate charge corresponding to the light received during the period between the third time point T03 and the sixth time point T06.

[0073] Therefore, the residual charge transferred from the photodiode (PD) to the extended floating diffusion node during the period between the sixth time point T06 and the seventh time point T07 may include additional charge accumulated in the photodiode (PD) during the period between the third time point T03 and the sixth time point T06. In this case, the additional accumulated charge included in the residual charge generates noise in the image data. For example, the image data may contain a ghost image component due to the additional accumulated charge included in the residual charge.

[0074] exist Figure 4In this design, the time period during which the image sensor 100 samples the HCG pixel signal may include the HCG reset time period HCG-RST and the HCG signal time period HCG-SIG. Similarly, the time period during which the image sensor 100 samples the LCG pixel signal may include the LCG signal time period LCG-SIG and the LCG reset time period LCG-RST. For example, the time periods during which the HCG pixel signal is sampled may be configured sequentially as the HCG reset time period HCG-RST and the HCG signal time period HCG-SIG. In other words, the image sensor 100 can perform RSSR (Reset-Signal-Signal-Reset) sampling.

[0075] However, Figure 4 The sequence of HCG reset period HCG-RST, HCG signal period HCG-SIG, LCG signal period LCG-SIG, and LCG reset period LCG-RST shown is an example, and the scope of this disclosure is not limited thereto. For example, the image sensor 100 may be configured to perform RSRS (reset-signal-reset-signal) sampling, RRSS (reset-reset-signal-signal) sampling, etc.

[0076] Figure 5 This is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure. Reference Figure 2A , Figure 2B and Figure 5 A pixel (PIX) may include a photodiode (PD), a first transfer transistor (TG1), a second transfer transistor (TG2), a dual-conversion gain transistor (DCG), a reset transistor (RG), a drive transistor (DG), a select transistor (SEL), an internal ADC, and local memory. Figure 3 Compared to the pixel PIX, Figure 5 The pixel PIX may also include a second transfer transistor TG2. Figure 3 The transfer transistor TG of the pixel PIX can correspond to Figure 5 The first transfer transistor TG1 of the pixel PIX.

[0077] The second transfer transistor TG2 can be connected between the photodiode PD and the second floating diffusion node FD2, and can include a gate electrode for receiving the second transfer signal VTS2. The second transfer transistor TG2 can operate based on the second transfer signal VTS2. The first transfer transistor TG1, the dual-conversion gain transistor DCG, the reset transistor RG, the drive transistor DG, and the select transistor SEL are configured as described above. Figure 3 The descriptions are identical, therefore redundant descriptions are omitted.

[0078] According to an embodiment, in Figure 5In pixel PIX (such as in Figure 3 In the pixel PIX, when the dual conversion gain transistor DCG is off, the first floating diffusion node FD1 and the second floating diffusion node FD2 can be decoupled from each other, and when the dual conversion diode DC is on, the first floating diffusion node FD1 and the second floating diffusion node FD2 can be electrically connected to become an extended floating diffusion node.

[0079] Furthermore, in the example case where the dual conversion gain transistor DCG is off, the pixel PIX can operate in HCG mode. In the example case where the dual conversion gain transistor DCG is on, the pixel PIX can operate in LCG mode. For example, the pixel PIX can operate in HCG mode and then in LCG mode.

[0080] The first transfer transistor TG1 can transfer a portion of the charge accumulated in the photodiode PD to the first floating diffusion node FD1, and the second transfer transistor TG2 can transfer the remaining charge, excluding the portion transferred to the first floating diffusion node FD1, to the second floating diffusion node FD2.

[0081] The first floating diffusion node FD1 may have a first capacitor, and the second floating diffusion node FD2 may have a second capacitor. The first capacitor may be due to a parasitic capacitor in the first floating diffusion node FD1, and the second capacitor may be due to a parasitic capacitor in the second floating diffusion node FD2. However, the scope of this disclosure is not limited thereto, and separate physical MIM (metal-insulator-metal) capacitors or DRAM capacitors may be connected to the floating diffusion nodes FD1 and FD2.

[0082] During the time when the first transfer transistor TG1 is turned on by the first transfer signal VTS1 received from the line decoder 120, the charge supplied from the photodiode PD can accumulate in the first floating diffusion node FD1. Furthermore, during the time when the second transfer transistor TG2 is turned on by the second transfer signal VTS2 received from the line decoder 120, the charge supplied from the photodiode PD can accumulate in the second floating diffusion node FD2. Therefore, a voltage potential corresponding to the charge accumulated in the first floating diffusion node FD1 and the second floating diffusion node FD2 can be formed.

[0083] In cases of high light intensity, the capacitance of the first floating diffusion node FD1 may be insufficient to contain all the charge accumulated in the photodiode PD. For example, when the light intensity is higher than a reference value, it can be considered strong. In this case, since the first floating diffusion node FD1 is prone to saturation, it may not be able to properly generate image data for the image to be captured. Therefore, to prevent saturation, a second floating diffusion node FD2 can be used. That is, the remaining charge accumulated in the photodiode PD, besides the portion corresponding to the capacitance of the first floating diffusion node FD1, can be accumulated in the second floating diffusion node FD2.

[0084] In another example case of high light intensity, the sum of the capacitances of the first floating diffusion node FD1 and the second floating diffusion node FD2 may be insufficient to contain all the charge accumulated in the photodiode PD. Accordingly, a portion (or at least a portion) of the remaining charge, excluding the portion corresponding to the capacitance of the first floating diffusion node FD1, may accumulate in the second floating diffusion node FD2. Hereinafter, the sum of the capacitances of the first floating diffusion node FD1 and the second floating diffusion node FD2 will be described as sufficient to contain all the charge accumulated in the photodiode PD, but the scope of this disclosure is not limited thereto.

[0085] In the example case of low light intensity, the capacitance of the first floating diffusion node FD1 is sufficient to accommodate all the charge accumulated in the photodiode PD. For example, when the light intensity is below a reference value, it can be considered weak. Accordingly, all the charge accumulated in the photodiode PD can accumulate in the first floating diffusion node FD1, and no charge can accumulate in the second floating diffusion node FD2.

[0086] According to an embodiment, in HCG mode, the pixel PIX can transfer a portion of the charge accumulated in the photodiode PD to a first floating diffusion node FD1, and can transfer the remaining charge accumulated in the photodiode PD to a second floating diffusion node FD2. A first readout operation can be performed on the portion of charge transferred to the first floating diffusion node FD1. According to an embodiment, in LCG mode, the pixel PIX can perform a second readout operation on the portion of charge and the remaining charge shared with the extended floating diffusion node. For example, after performing the first readout operation, the pixel PIX can perform a second readout operation on the portion of charge and the remaining charge shared with the extended floating diffusion node in LCG mode.

[0087] According to an embodiment, before performing the first readout operation in HCG mode, the pixel PIX can sequentially perform operations to accumulate charge through the first transfer transistor TG1 and the second transfer transistor TG2 in the first floating diffusion node FD1 and the second floating diffusion node FD2, respectively. Afterwards, the pixel PIX can perform the first readout operation on a portion of the charge transferred to the first floating diffusion node FD1 in HCG mode.

[0088] Next, according to an embodiment of this disclosure, the pixel PIX enters LCG mode, and the dual-conversion gain transistor DCG can be turned on by the dual-conversion signal VDC received from the line decoder 120. In this case, as described above, the first floating diffusion node FD1 and the second floating diffusion node FD2 can be electrically connected to form an extended floating diffusion node. Accordingly, a portion of the charge accumulated in the first floating diffusion node FD1 and the remaining charge accumulated in the second floating diffusion node FD2 can be shared together in the extended floating diffusion node.

[0089] Finally, according to embodiments of the present disclosure, a pixel PIX can perform a second readout operation on the charge shared with the extended floating diffusion node.

[0090] The reset transistor RG can be turned on by the reset signal VRST received from the line decoder 120 to provide a reset voltage (e.g., a first power supply voltage VDD1) to the first floating diffusion node FD1 or the extended floating diffusion node. As a result, the charge accumulated in the first floating diffusion node FD1 or the extended floating diffusion node moves to the first power supply terminal, and the voltage of the first floating diffusion node FD1 or the extended floating diffusion node can be reset.

[0091] The driving transistor DG can amplify the potential changes of the first floating diffusion node FD1 or the extended floating diffusion node, and can generate a corresponding voltage level (e.g., pixel signal level). For example, when the gate electrode is connected to the first floating diffusion node FD1 or the extended floating diffusion node and a terminal is connected to the second power supply terminal, the driving transistor DG can be driven as a source follower amplifier.

[0092] The select transistor SEL can be driven by the select signal VSEL received from the line decoder 120 to transmit the pixel signal generated by the drive transistor DG to the internal ADC.

[0093] The internal ADC can convert the pixel signal, which is an analog signal, into a digital signal based on the pixel signal received by the selection transistor SEL and the ramp signal RAMP received from the ramp generator 130.

[0094] The local memory can receive and store digital signals corresponding to pixel signals from the internal ADC. In the example case where the pixel performs a first readout operation or a second readout operation, the local memory can output the stored digital signals via the column line CL.

[0095] exist Figure 5 In the diagram, the pixel PIX is shown as being implemented based on a pixel-level ADC structure, such as including Figure 2B The image sensor 100 contains multiple pixels in its pixel array 110, but this is an example, and the scope of this disclosure is not limited thereto. For example, a pixel PIX can be implemented as including multiple pixels in the image sensor 100's pixel array 110. Figure 2A Multiple pixels in the pixel array 110 of the image sensor 100.

[0096] Figure 6 This is a timing diagram illustrating an example of the operation of an image sensor according to embodiments of the present disclosure. Reference Figure 5 and Figure 6 The diagram exemplarily illustrates the levels of the time-dependent reset signal VRST, double-conversion signal VDC, first transfer signal VTS1, second transfer signal VTS2, selection signal VSEL, and ramp signal RAMP. Figure 6 In the timing diagram, the horizontal axis represents time 'T', and the vertical axis represents voltage level 'V'.

[0097] During the period between the tenth time point T10 and the sixteenth time point T16, the image sensor 100 can operate in HCG mode, and during the period after the sixteenth time point T16, the image sensor 100 can operate in LCG mode. The image sensor 100 can sample the HCG pixel signal during the period between the tenth time point T10 and the fifteenth time point T15, and can perform a first readout operation during the period between the fifteenth time point T15 and the sixteenth time point T16. During the period between the sixteenth time point T16 and the eighteenth time point T18, the image sensor 100 can sample the LCG pixel signal, and during the period after the eighteenth time point T18, the image sensor 100 can perform a second readout operation.

[0098] For example, during the time period between the tenth time point T10 and the eleventh time point T11, the image sensor 100 can sample the HCG reset level of the HCG pixel signal, and during the time period between the eleventh time point T11 and the fifteenth time point T15, the image sensor 100 can sample the HCG signal level. Additionally, during the time period between the sixteenth time point T16 and the seventeenth time point T17, the image sensor 100 can sample the LCG signal level for the LCG pixel signal, and during the time period between the seventeenth time point T17 and the eighteenth time point T18, the image sensor 100 can sample the LCG reset level.

[0099] During the HCG-Reset period HCG-RST (or the period between the tenth time point T10 and the eleventh time point T11), the voltages of the first floating diffusion node FD1 and the second floating diffusion node FD2 can both be reset. The HCG reset level can be converted into a digital signal by the internal ADC and stored in the local memory.

[0100] During the HCG-signal period HCG-SIG (or the period between the eleventh time point T11 and the fifteenth time point T15), the charge transferred from the photodiode PD can be accumulated in the first floating diffusion node FD1 and the second floating diffusion node FD2, respectively.

[0101] During the period between the twelfth time point T12 and the thirteenth time point T13, the first transfer signal VTS1 can be at a logic high level. During the period between the twelfth time point T12 and the thirteenth time point T13, the first transfer transistor TG1 can be turned on, and the first transfer transistor TG1 can transfer part of the charge accumulated in the photodiode PD to the first floating diffusion node FD1.

[0102] During the period between time point thirteen (T13) and time point fourteen (T14), the second transfer signal VTS2 can be at a logic high level, and both the first transfer signal VTS1 and the double-conversion signal VDC can be at a logic low level. During the period between time point thirteen (T13) and time point fourteen (T14), the second transfer transistor TG2 can be turned on, and the second transfer transistor TG2 can transfer the remaining charge accumulated in the photodiode PD to the second floating diffusion node FD2.

[0103] In this case, the time period during which the image sensor 100 performs the first readout operation may not be included in the time periods between the twelfth time point T12 and the thirteenth time point T13, or between the thirteenth time point T13 and the fourteenth time point T14. That is, the exposure integration time (EIT) may be the same between the time periods between the twelfth time point T12 and the thirteenth time point T13, and between the thirteenth time point T13 and the fourteenth time point T14.

[0104] According to embodiments of this disclosure, before performing the first readout operation in HCG mode, the image sensor 100 may perform operations to transfer a portion of the charge corresponding to the HCG pixel signal from the photodiode PD to the first floating diffusion node FD1 and to transfer the remaining charge corresponding to the LCG pixel signal from the photodiode PD to the second floating diffusion node FD2.

[0105] In this situation, from the time the image sensor 100 transfers a portion of the charge corresponding to the HCG pixel signal from the photodiode PD to the first floating diffusion node FD1 until the image sensor 100 transfers the remaining charge corresponding to the LCG pixel signal from the photodiode PD to the second floating diffusion node FD2, the photodiode PD may not receive more light from the outside.

[0106] Therefore, according to the embodiments, Figure 5 and Figure 6 The image sensor 100 shown can be solved by referring to the above reference. Figure 3 and Figure 4 To improve image quality, the problem of noise generated in the image data is addressed. For example, Figure 5 The image sensor 100 shown has a configuration for removing ghosting image components from image data.

[0107] During the HCG signal period HCG-SIG (or the period between the eleventh time point T11 and the fifteenth time point T15), the HCG signal level can be converted into a digital signal by the internal ADC and stored in the local memory.

[0108] During the HCG readout period HCG-RO (or the period between the fifteenth time point T15 and the sixteenth time point T16), the image sensor 100 can perform a first readout operation on a portion of the charge accumulated in the first floating diffusion node FD1. For example, the image sensor 100 can read out digital signals corresponding to the HCG reset level and HCG signal level stored in local memory via column line CL.

[0109] During the LCG-signal period LCG-SIG (or the period between time points T16 and T17), the dual-conversion gain transistor DCG can be turned on as the dual-conversion signal VDC goes high. As described above, the first floating diffusion node FD1 and the second floating diffusion node FD2 can be electrically connected to form an extended floating diffusion node, and a portion of the charge accumulated in the first floating diffusion node FD1 and the remaining charge accumulated in the second floating diffusion node FD2 can be shared by the extended floating diffusion node. The LCG signal level can be converted into a digital signal by an ADC and stored in local memory.

[0110] During the LCG-Reset period LCG-RST (or the period between time point T17 and time point T18), the voltage of the extended floating diffusion node can be reset. The LCG reset level can be converted into a digital signal by the internal ADC and stored in local memory.

[0111] During the LCG readout period LCG-RO (or the period after the eighteenth time point T18), the image sensor 100 can perform a second readout operation on the charge shared with the extended floating diffusion node. For example, the image sensor 100 can read out digital signals corresponding to the LCG signal level and LCG reset level stored in local memory via column line CL.

[0112] and Figure 4 Similarly, in Figure 6 In this process, the time period during which the image sensor 100 samples the HCG pixel signal may include the HCG-reset time period HCG-RST and the HCG signal time period HCG-SIG. Similarly, the time period during which the image sensor 100 samples the LCG pixel signal may include the LCG signal time period LCG-SIG and the LCG reset time period LCG-RST. For example, the time periods for sampling the HCG pixel signal may be configured sequentially as the HCG reset time period HCG-RST and the HCG signal time period HCG-SIG. In other words, the image sensor 100 can perform RSSR (Reset-Sig-Sig-Reset) sampling.

[0113] However, Figure 6 The sequence of HCG reset period HCG-RST, HCG signal period HCG-SIG, LCG signal period LCG-SIG, and LCG reset period LCG-RST shown is an example, and the scope of this disclosure is not limited thereto. For example, the image sensor 100 may be configured to perform RSRS sampling, RRSS sampling, etc.

[0114] Figures 7A to 7E This is a diagram conceptually illustrating the operation of pixels according to embodiments of the present disclosure. Reference Figure 5 , Figure 6 and Figures 7A to 7E This illustrates the charge flow (or potential level) between the photodiode PD, the first floating diffusion node FD1, and the second floating diffusion node FD2 according to the operating flow of the image sensor 100. Although in Figures 7A to 7E The figure is not shown for simplicity, but the dual conversion gain transistor DCG between the first floating diffusion node FD1 and the first floating diffusion node FD1 can be turned off.

[0115] Figure 7A It can correspond to Figure 6 The state during the HCG reset period HCG-RST (or the period before the twelfth time point T12). For example, Figure 7A The initial charge states of the photodiode PD, the first floating diffusion node FD1, and the second floating diffusion node FD2 can be shown. Both the first transfer transistor TG1 and the second transfer transistor TG2 can be turned off. The charge generated by the photodiode PD based on the optical signal can accumulate in the photodiode PD.

[0116] Figure 7B It can correspond to Figure 6 The state at time point T12. The first transfer transistor TG1 can be turned on, and the second transfer transistor TG2 can be turned off. Part of the charge accumulated in the photodiode PD can be accumulated in the first floating diffusion node FD1.

[0117] Figure 7C and Figure 7D It can correspond to Figure 6 The state at time point T13. After the first transfer transistor TG1, which has already been turned on, is turned off (or simultaneously), the second transfer transistor TG2 can be turned on. Of the charge accumulated in the photodiode PD, the remaining charge, excluding the portion transferred to the first floating diffusion node FD1, can be accumulated in the second floating diffusion node FD2.

[0118] Figure 7E It can correspond to Figure 6 The state during the HCG readout period HCG-RO (or the period between time point fourteen T14 and time point sixteen T16). Both the first transfer transistor TG1 and the second transfer transistor TG2 can be turned off. This partial charge and the remaining charge can accumulate in the first floating diffusion node FD1 and the second floating diffusion node FD2, respectively. The image sensor 100 can perform a first readout operation on the partial charge accumulated in the first floating diffusion node FD1.

[0119] Figure 8A and Figure 8B This is a diagram conceptually illustrating the operation of pixels according to embodiments of the present disclosure. Reference Figure 5 , Figure 6 , Figures 7A to 7E as well as Figure 8A and Figure 8B The diagram illustrates the charge flow (or potential level) between the photodiode PD, the first floating diffusion node FD1, and the second floating diffusion node FD2 according to the operating flow of the image sensor 100. Although for simplicity... Figure 8A and 8B The second transfer transistor TG2 between the second floating diffusion node FD2 and the photodiode PD can be turned off, although it is not shown in the attached diagram.

[0120] Figure 8A The state can correspond to Figure 7E The state is such that both the first transfer transistor TG1 and the dual conversion gain transistor DCG can be turned off.

[0121] Figure 8B It can correspond to Figure 6 The state during the LCG signal period LCG-SIG (or the period between time point T16 and time point T17). The first transfer transistor TG1 can be turned off, and the dual conversion gain transistor DCG can be turned on. The capacitance of the extended floating diffusion node can be extended to the sum of the capacitances of the first floating diffusion node FD1 and the second floating diffusion node FD2. This partial charge and the remaining charge can both be shared by the extended floating diffusion node.

[0122] On the other hand, as described above, the capacitance of the extended floating diffusion node in this disclosure has been assumed to be sufficient to accommodate all the charge accumulated in the photodiode PD, but the scope of this disclosure is not limited thereto. For example, the capacitance of the extended floating diffusion node may be insufficient to accommodate all the charge accumulated in the photodiode PD. In this case, a portion (or at least a portion) of the remaining charge in the photodiode PD, excluding the portion corresponding to the capacitance of the first floating diffusion node FD1, may accumulate in the second floating diffusion node FD2.

[0123] Figure 9 This is a flowchart illustrating an example of the operation of an image sensor according to an embodiment of the present disclosure. Reference Figure 2A , Figure 2B , Figure 5 , Figure 6 , Figures 7A to 7E , Figure 8A , Figure 8B and Figure 9In operation S110, the image sensor 100 can enter HCG mode. For example, each of the multiple pixels of the image sensor 100 can also enter HCG mode. For example, the dual conversion gain transistor DCG of the pixel PIX can be turned off.

[0124] In operation S120, the image sensor 100 can transfer a portion of the charge accumulated in the photodiode PD from the photodiode PD to the first floating diffusion node FD1. For example, the first transfer transistor TG1 of each of the plurality of pixels included in the image sensor 100 can transfer a portion of the charge accumulated in the photodiode PD from the photodiode PD to the first floating diffusion node FD1 based on the first transfer signal VTS1.

[0125] In operation S130, the image sensor 100 can transfer residual charge from the photodiode PD to the second floating diffusion node FD2. For example, based on the second transfer signal VTS2, the second transfer transistor TG2 of each of the plurality of pixels included in the image sensor 100 can transfer the residual charge accumulated in the photodiode PD, excluding the portion of charge transferred to the first floating diffusion node FD1, from the photodiode PD to the second floating diffusion node FD2.

[0126] In operation S140, the image sensor 100 can perform an HCG readout operation corresponding to a portion of the charge transferred to the first floating diffusion node FD1. For example, each of the plurality of pixels included in the image sensor 100 can perform a first readout operation for the HCG pixel signal.

[0127] In operation S150, the image sensor 100 can enter LCG mode. For example, each of the plurality of pixels included in the image sensor 100 can enter LCG mode. For example, the dual conversion gain transistor DCG of the pixel PIX can be turned on.

[0128] In operation S160, the image sensor 100 may perform an LCG readout operation corresponding to the charge shared with the extended floating diffusion node. For example, each of the plurality of pixels included in the image sensor 100 may perform a second readout operation on the LCG pixel signal.

[0129] Figure 10 This is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure. Reference Figure 2A , Figure 2B , Figure 5 and Figure 10The pixel PIX may include a large photodiode LPD, a first transfer transistor TG1, a second transfer transistor TG2, a first dual conversion gain transistor DCG1, a reset transistor RG, a first drive transistor DG1, a first selection transistor SEL1, a small photodiode SPD, a third transfer transistor TG3, a second dual conversion gain transistor DCG2, a second drive transistor DG2, and a second selection transistor SEL2. Figure 10 Pixel PIX and Figure 5 Compared to the pixel PIX, it may also include a small photodiode SPD, a third transfer transistor TG3, a second dual conversion gain transistor DCG2, a second drive transistor DG2, and a second selection transistor SEL2. Figure 5 The photodiode PD, dual-conversion gain transistor DCG, drive transistor DG, and select transistor SEL of the pixel PIX can respectively correspond to Figure 10 The pixel PIX has a large photodiode LPD, a first dual conversion gain transistor DCG1, a first drive transistor DG1, and a first selection transistor SEL1.

[0130] The third transfer transistor TG3 can be connected between the small photodiode SPD and the third floating diffusion node FD3, and can include a gate electrode that receives the third transfer signal VTS3.

[0131] The second dual-conversion gain transistor DCG2 may be connected between the second floating diffusion node FD2 and the third floating diffusion node FD3, and may include a gate electrode for receiving the second dual-conversion signal VDC2. In the example case where the second dual-conversion signal VDC2 is at a logic high level, the second dual-conversion gain transistor DCG2 may be turned on, and the second floating diffusion node FD2 and the third floating diffusion node FD3 may be electrically connected.

[0132] The second driving transistor DG2 can be connected between the third power supply terminal and the second node N2, and can include a gate electrode connected to the third floating diffusion node FD3. Here, the third power supply terminal can receive the second power supply voltage VDD2.

[0133] The second selection transistor SEL2 can be connected between the second node N2 and the column line CL, and can include a gate electrode that receives the second selection signal VSEL2.

[0134] Similar to large photodiodes (LPDs), small photodiodes (SPDs) can accumulate charge based on externally incident light signals. For example, a small SPD can generate a charge corresponding to the intensity of externally incident light and accumulate the generated charge.

[0135] The third transfer transistor TG3 can operate based on the third transfer signal VTS3, the second dual-conversion gain transistor DCG2 can operate based on the second dual-conversion signal VDC2, the second drive transistor DG2 can operate in response to the voltage of the third floating diffusion node FD3, and the second selection transistor SEL2 can operate based on the second selection signal VSEL2. The first transfer transistor TG1, the second transfer transistor TG2, the first dual-conversion gain transistor DCG1, the reset transistor RG, the first drive transistor DG1, and the first selection transistor SEL1 are configured as described above. Figure 3 and Figure 5 The descriptions are identical, therefore redundant descriptions are omitted.

[0136] According to an embodiment, Figure 10 A pixel PIX can be a pixel PIX with a split photodiode (split PD) structure that includes multiple photodiodes LPD and SPD. For example, a pixel PIX can include a large photodiode LPD with a large light-receiving area and a small photodiode SPD with a small light-receiving area.

[0137] For example, a large photodiode (LPD) can handle pixel signals with low illumination, while a small photodiode (SPD) can handle pixel signals with high illumination. For instance, a pixel PIX can convert low illumination signals with a relatively high conversion gain using a large LPD, and convert high illumination signals with a relatively low conversion gain using a small SPD.

[0138] According to an embodiment, a pixel PIX having a split photodiode structure, such as Figure 10 The pixel PIX shown can also perform the same operation as the reference above. Figures 5 to 9 The functions and operations of the described pixel PIX are the same. For example, the large photodiode LPD, first transfer transistor TG1, second transfer transistor TG2, first dual-conversion gain transistor DCG1, reset transistor RG, first drive transistor DG1, and first selection transistor SEL1 of the pixel PIX can operate identically to the photodiode PD, first transfer transistor TG1, second transfer transistor TG2, dual-conversion gain transistor DCG, reset transistor RG, drive transistor DG, and selection transistor SEL of the pixel PIX according to embodiments of this disclosure. Therefore, [details omitted]. Figure 10 The redundant description of the operation of the pixel PIX shown.

[0139] exist Figure 10 In the diagram, the pixel PIX is illustrated as being implemented as including Figure 2AThe image sensor 100 contains multiple pixels in its pixel array 110, but this is an example, and the scope of this disclosure is not limited thereto. For example, a pixel PIX can be implemented based on a pixel-level ADC structure, such as... Figure 2B The image sensor 100 includes multiple pixels in its pixel array 110.

[0140] According to embodiments of this disclosure, a method for operating an image sensor is provided. The method includes accumulating charge on a photodiode of the image sensor based on an optical signal, entering a high conversion gain mode, transferring a portion of the accumulated charge to a first floating diffusion node, transferring at least a portion of the remaining charge of the accumulated charge to a second floating diffusion node, performing a first readout operation corresponding to the portion of charge transferred to the first floating diffusion node, and entering a low conversion gain mode.

[0141] For example, when a pixel is operating in a high conversion gain mode, the method includes transferring a portion of the accumulated charge to a first floating diffusion node, transferring at least a portion of the remaining charge of the accumulated charge to a second floating diffusion node, performing a first readout operation corresponding to the portion of charge transferred to the first floating diffusion node, and entering a low conversion gain mode.

[0142] An image sensor may include pixels, each pixel comprising: a photodiode, a first transfer transistor, a second transfer transistor, a dual-conversion transistor, a reset transistor, a drive transistor, and a selection transistor. The first transfer transistor may be connected between the photodiode and a first floating diffusion node, and is configured to operate based on a first transfer signal. The second transfer transistor may be connected between the photodiode and a second floating diffusion node, and is configured to operate based on a second transfer signal. The dual-conversion transistor may be connected between the first and second floating diffusion nodes, and is configured to operate based on a dual-conversion signal. The reset transistor may be connected between a first power supply terminal and a second floating diffusion node, and is configured to operate based on a reset signal. The drive transistor may be connected between a second power supply terminal and a first node, and is configured to operate based on the voltage of the first floating diffusion node. The selection transistor may be connected between the first node and a column line, and is configured to operate based on a selection signal.

[0143] Entering high conversion gain mode can include turning off the dual-conversion transistor.

[0144] Transferring this portion of the charge may include turning on the first transfer transistor and turning off the first transfer transistor after transferring the portion of the charge to the first floating diffusion node.

[0145] Transferring at least a portion of the remaining charge may include: turning on the second transfer transistor and turning off the second transfer transistor after transferring at least a portion of the remaining charge to the second floating diffusion node.

[0146] Entering low conversion gain mode can include turning on a dual-conversion transistor.

[0147] The method may also include electrically connecting the first floating diffusion node and the second floating diffusion node to generate an extended floating diffusion node.

[0148] The method may further include sharing at least a portion of the charge transferred to the first floating diffusion node and the remaining charge transferred to the second floating diffusion node with the extended floating diffusion node.

[0149] The method may also include performing a second readout operation corresponding to the charge shared to the extended floating diffusion node.

[0150] Figure 11 It is a block diagram of an electronic device that includes multiple camera modules. Figure 12 It is shown in detail Figure 11 A block diagram of the camera module.

[0151] refer to Figure 11 The electronic device 1000 may include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0152] The camera module group 1100 may include multiple camera modules 1100a, 1100b and 1100c. Figure 11 An electronic device comprising three camera modules 1100a, 1100b, and 1100c is shown, but this disclosure is not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. Furthermore, in some embodiments, the camera module group 1100 may be modified to include "n" camera modules (n being a natural number of 4 or greater).

[0153] In one embodiment, Figure 2A or Figure 2B The image sensor 100 may be included in the camera module group 1100. However, this disclosure is not limited thereto.

[0154] Below, we will refer to Figure 12 The following description provides a more comprehensive and detailed description of the configuration of camera module 1100b, but the same description applies to the other camera modules 1100a and 1100c.

[0155] refer to Figure 12The camera module 1100b may include a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device 1150.

[0156] The prism 1105 may include a reflective plane 1107 of light-reflecting material and may change the path of light “L” incident from the outside.

[0157] In some embodiments, prism 1105 can change the path of light "L" incident along the first direction (X) to a second direction (Y) perpendicular to the first direction (X). Furthermore, prism 1105 can change the path of light "L" incident along the first direction (X) to a second direction (Y) perpendicular to the first direction (X-axis) by rotating the reflective plane 1107 of the light-reflecting material about the central axis 1106 in direction "A" or by rotating the central axis 1106 in direction "B". In this case, OPFE 1110 can move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0158] In some embodiments, such as Figure 12 As shown, the maximum rotation angle of prism 1105 in direction "A" can be equal to or less than 15 degrees in the positive A direction and greater than 15 degrees in the negative A direction, but this disclosure is not limited thereto.

[0159] In some embodiments, the prism 1105 may move within about 20 degrees, between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees in the positive B direction or the negative B direction; here, the prism 1105 may move at the same angle in the positive B direction or the negative B direction, or may move at a similar angle within about 1 degree.

[0160] In some embodiments, the prism 1105 can move the reflective plane 1107 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the direction in which the central axis 1106 extends.

[0161] OPFE 1110 may include optical lenses, for example, the optical lenses comprising "m" groups (m being a natural number). Here, the "m" lenses can be moved in a second direction (Y) to change the optical zoom ratio of camera module 1100b. In the example case where the default optical zoom ratio of camera module 1100b is "Z", the optical zoom ratio of camera module 1100b can be changed to 3Z, 5Z, or 5Z or greater by moving the "m" optical lenses included in OPFE 1110.

[0162] Actuator 1130 can move OPFE 1110 or optical lens (hereinafter referred to as "optical lens") to a specific position. For example, actuator 1130 can adjust the position of optical lens so that image sensor 1142 is placed at the focal length of optical lens for accurate sensing.

[0163] Image sensing device 1140 may include image sensor 1142, control logic 1144, and memory 1146. Image sensor 1142 can sense an image of a target using light "L" provided through an optical lens. Control logic 1144 can control the overall operation of camera module 1100b. For example, control logic 1144 can control the operation of camera module 1100b based on control signals provided through control signal line CSLb.

[0164] Memory 1146 may store information required for the operation of camera module 1100b, such as calibration data 1147. Calibration data 1147 may include information required by camera module 1100b to generate image data using externally supplied light "L". Calibration data 1147 may include, for example, information about the aforementioned degree of rotation, information about the focal length, information about the optical axis, etc. In the case where camera module 1100b is implemented as a multi-state camera where the focal length varies depending on the position of the optical lens, calibration data 1147 may include the focal length value for each position (or state) of the optical lens and information about autofocus.

[0165] Storage device 1150 can store image data sensed by image sensor 1142. Storage device 1150 can be disposed outside image sensing device 1140 and can be implemented in the form of a stack of storage device 1150 and sensor chip constituting image sensing device 1140. In some embodiments, storage device 1150 can be implemented with electrically erasable programmable read-only memory (EEPROM), but this disclosure is not limited thereto.

[0166] Let's refer to each other. Figure 11 and Figure 12 In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Thus, depending on the operation of the actuator 1130 therein, the same calibration data 1147 or different calibration data 1147 may be included in the plurality of camera modules 1100a, 1100b, and 1100c.

[0167] In some embodiments, one of the plurality of camera modules 1100a, 1100b and 1100c (e.g. 1100b) may be a camera module with a folded lens shape including the aforementioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g. 1100a and 1100c) may be camera modules with a vertical shape excluding the aforementioned prism 1105 and OPFE 1110; however, this disclosure is not limited thereto.

[0168] In some embodiments, one of the plurality of camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be a depth camera of a vertical shape, for example, that extracts depth information using infrared (IR). In this case, the application processor 1200 may combine image data provided from the depth camera with image data provided from any other camera module (e.g., 1100a or 1100b) and may generate a three-dimensional (3D) depth image.

[0169] In some embodiments, at least two camera modules (e.g., 1100a and 1100b) of the plurality of camera modules 1100a, 1100b and 1100c may have different fields of view. In this case, at least two camera modules (e.g., 1100a and 1100b) of the plurality of camera modules 1100a, 1100b and 1100c may include different optical lenses, but this disclosure is not limited thereto.

[0170] Furthermore, in some embodiments, the fields of view of the multiple camera modules 1100a, 1100b, and 1100c may be different. In this case, the multiple camera modules 1100a, 1100b, and 1100c may include different optical lenses, but are not limited thereto.

[0171] In some embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may be configured to be physically separate from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c may not use the sensing area of ​​a single image sensor 1142, but rather the plurality of camera modules 1100a, 1100b, and 1100c may each include an independent image sensor 1142.

[0172] return Figure 11 The application processor 1200 may include an image processing device 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 may be implemented separately from the multiple camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the multiple camera modules 1100a, 1100b, and 1100c may be implemented using separate semiconductor chips.

[0173] The image processing apparatus 1210 may include a plurality of sub-image processors 1212a, 1212b and 1212c, an image generator 1214 and a camera module controller 1216.

[0174] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b and 1212c, the number of which corresponds to the number of the plurality of camera modules 1100a, 1100b and 1100c.

[0175] Image data generated from camera modules 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c via separate image signal lines ISLa, ISLb, and ISLc, respectively. For example, image data generated from camera module 1100a can be provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b can be provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c can be provided to sub-image processor 1212c via image signal line ISLc. This image data transmission can be performed, for example, using a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but this disclosure is not limited thereto.

[0176] In some embodiments, a sub-image processor can be provided to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c can be implemented integratedly rather than separately, as shown below. Figure 11 As shown; in this case, one of the multiple image data provided from camera module 1100a and camera module 1100c can be selected by a selection element (e.g., a multiplexer), and the selected image data can be provided to the integrated sub-image processor.

[0177] Image data provided to sub-image processors 1212a, 1212b, and 1212c can be provided to image generator 1214. Image generator 1214 can generate an output image based on image generation information (generation information) or a mode signal by using the image data provided from sub-image processors 1212a, 1212b, and 1212c.

[0178] In detail, the image generator 1214 can generate an output image by merging at least a portion of image data generated from camera modules 1100a, 1100b, and 1100c, which have different fields of view, based on image generation information (generation information) or a mode signal. Furthermore, the image generator 1214 can generate an output image by selecting one of the image data generated from camera modules 1100a, 1100b, and 1100c, which have different fields of view, based on image generation information (generation information) or a mode signal.

[0179] In some embodiments, image generation information (generation information) may include a zoom signal or zoom factor. Furthermore, in some embodiments, the mode signal may be, for example, a signal based on a mode selected by the user.

[0180] When the image generation information (generation information) is a zoom signal (or zoom factor) and camera modules 1100a, 1100b, and 1100c have different fields of view, the image generator 1214 can perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 can merge image data output from camera module 1100a and image data output from camera module 1100c, and can generate an output image by using the merged image signal and image data output from camera module 1100b that was not used in the merging operation. When the zoom signal is a second signal different from the first signal, without an image data merging operation, the image generator 1214 can select one of the image data output from camera modules 1100a, 1100b, and 1100c respectively, and can output the selected image data as the output image. However, this disclosure is not limited thereto, and the way image data is processed can be modified without limitation if needed.

[0181] In some embodiments, the image generator 1214 can generate merged image data with increased dynamic range by receiving multiple image data with different exposure times from at least one of multiple sub-image processors 1212a, 1212b and 1212c and performing high dynamic range (HDR) processing on the multiple image data.

[0182] The camera module controller 1216 can provide control signals to camera modules 1100a, 1100b, and 1100c respectively. The control signals generated from the camera module controller 1216 can be provided to the corresponding camera modules 1100a, 1100b, and 1100c respectively through separate control signal lines CSLa, CSLb, and CSLc.

[0183] Based on image generation information (generation information) including zoom signals or mode signals, one of the multiple camera modules 1100a, 1100b, and 1100c can be designated as the master camera (e.g., 1100b), and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. This designation information can be included in control signals, and the control signals including the designation information can be provided to the respective camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0184] The camera module can be configured to operate as a master or slave device based on the zoom factor or operating mode signal. For example, when the field of view of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b can operate as the master device, and camera module 1100a can operate as the slave device. Conversely, when the zoom factor indicates a high zoom ratio, camera module 1100a can operate as the master device, and camera module 1100b can operate as the slave device.

[0185] In some implementations, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when camera module 1100b is used as the main camera and camera modules 1100a and 1100c are used as slave cameras, the camera module controller 1216 may send a synchronization enable signal to camera module 1100b. Camera module 1100b, provided with the synchronization enable signal, may generate a synchronization signal based on the provided synchronization enable signal and may provide the generated synchronization signal to camera modules 1100a and 1100c via the synchronization signal line SSL. Camera modules 1100b, 1100a, and 1100c may synchronize with the synchronization signal to send image data to the application processor 1200.

[0186] In some embodiments, control signals provided from camera module controller 1216 to each of camera modules 1100a, 1100b, and 1100c may include mode information based on mode signals. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode relating to sensing speed.

[0187] In the first operating mode, multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a first speed (e.g., generate image signals at a first frame rate), encode the image signals at a second speed (e.g., encode image signals at a second frame rate higher than the first frame rate), and send the encoded image signals to the application processor 1200. In this case, the second speed can be 30 times or less than the first speed.

[0188] Application processor 1200 can store the received image signal (i.e., the encoded image signal) in the memory 1230 provided therein or in an external memory 1400 located outside of application processor 1200. Then, application processor 1200 can read the encoded image signal from memory 1230 or external memory 1400 and decode it, and can display image data generated based on the decoded image signal. For example, one of the sub-image processors 1212a, 1212b, and 1212c of image processing device 1210 can perform decoding and can also perform image processing on the decoded image signal.

[0189] In the second operating mode, multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a third speed (e.g., a third frame rate image signal lower than the first frame rate) and send the image signals to the application processor 1200. The image signals provided to the application processor 1200 can be unencoded signals. The application processor 1200 can perform image processing on the received image signals, or it can store the image signals in memory 1230 or external memory 1400.

[0190] PMIC 1300 can supply power, for example, power supply voltage, to multiple camera modules 1100a, 1100b, and 1100c respectively. For example, under the control of application processor 1200, PMIC 1300 can supply first power to camera module 1100a via power signal line PSLa, supply second power to camera module 1100b via power signal line PSLb, and supply third power to camera module 1100c via power signal line PSLc.

[0191] According to an embodiment, based on a power control signal PCON from an application processor 1200, the PMIC 1300 can generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c, and can adjust the power level. The power control signal PCON can include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode can include a low-power mode. In this case, the power control signal PCON can include information about the camera module operating in low-power mode and setting the power level. The power levels supplied to the plurality of camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Furthermore, the power levels can be changed dynamically.

[0192] The above description describes detailed embodiments for carrying out this disclosure. Embodiments with simple or easily modified designs, as well as the above-described embodiments, can be included in this disclosure. Furthermore, techniques that can be easily modified and implemented using the above-described embodiments can be included in this disclosure. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, and should be defined not only by the appended claims but also by claims equivalent to those of this disclosure.

Claims

1. An image sensor, comprising: Pixels, wherein the pixels include: A photodiode is configured to accumulate charge based on a light signal; A first transfer transistor is connected between the photodiode and the first floating diffusion node, and the first transfer transistor is configured to operate based on a first transfer signal; A second transfer transistor is connected between the photodiode and the second floating diffusion node, and the second transfer transistor is configured to operate based on a second transfer signal; A dual-conversion transistor is connected between the first floating diffusion node and the second floating diffusion node, and the dual-conversion transistor is configured to operate based on a dual-conversion signal; A reset transistor is connected between a first power supply terminal and a second floating diffusion node, and the reset transistor is configured to operate based on a reset signal. A driving transistor, connected between a second power supply terminal and a first node, is configured to operate based on the voltage of the first floating diffuse node; and A selection transistor is connected between the first node and the column line, and the selection transistor is configured to operate based on a selection signal.

2. The image sensor of claim 1, wherein, Based on the shutdown of the dual-conversion transistor, the pixel is configured to operate in a high conversion gain mode. Wherein, based on the dual-conversion transistor being turned on, the pixel is configured to operate in a low conversion gain mode, and The pixel is configured to operate in the low conversion gain mode after operating in the high conversion gain mode.

3. The image sensor of claim 2, wherein, During the period when the pixel operates in the high conversion gain mode: The first transfer transistor is turned on from the off state and then turned off again; as well as After the first transfer transistor turns off again, the second transfer transistor turns on from the off state, and then turns off again.

4. The image sensor of claim 3, wherein, During the period when the first transfer transistor is turned on, the first transfer transistor is configured to transfer a portion of the charge accumulated in the photodiode to the first floating diffusion node, and Wherein, after the first transfer transistor is turned off again, during the period when the second transfer transistor is turned on, the second transfer transistor is configured to transfer at least a portion of the remaining charge accumulated in the photodiode to the second floating diffusion node.

5. The image sensor of claim 4, wherein, After the second transfer transistor is turned off again, the image sensor is configured to perform a first readout operation corresponding to the portion of charge transferred to the first floating diffusion node.

6. The image sensor of claim 5, wherein, After the first readout operation is performed, the pixel is configured to operate in the low conversion gain mode, and the dual conversion transistor is configured to turn on from the off state.

7. The image sensor of claim 6, wherein, During the period when the dual-conversion transistor is turned on, the dual-conversion transistor is configured to electrically connect the first floating diffusion node and the second floating diffusion node to generate an extended floating diffusion node.

8. The image sensor of claim 7, wherein, The dual-conversion transistor is configured to share at least a portion of the charge transferred to the first floating diffusion node and the remaining charge transferred to the second floating diffusion node with the extended floating diffusion node.

9. The image sensor of claim 8, wherein, The image sensor is configured to perform a second readout operation corresponding to the charge shared to the extended floating diffusion node.

10. An image sensor, comprising: Pixels, including: First transfer transistor, The second transfer transistor, and Photodiodes are configured to accumulate charge based on optical signals. Specifically, this is based on the pixel operating in high conversion gain mode: The first transfer transistor is configured to transfer a portion of the charge accumulated in the photodiode to a first floating diffusion node, and The second transfer transistor is configured to transfer at least a portion of the remaining charge accumulated in the photodiode to the second floating diffusion node, and Wherein, the first readout operation corresponds to the partial charge transferred to the first floating diffusion node being performed; and The pixel is configured to enter a low conversion gain mode after the first readout operation.

11. The image sensor according to claim 10, wherein, The pixel also includes a dual-conversion transistor, a reset transistor, a drive transistor, and a selection transistor; The first transfer transistor is connected between the photodiode and the first floating diffusion node, and the first transfer transistor is configured to operate based on a first transfer signal. The second transfer transistor is connected between the photodiode and the second floating diffusion node, and the second transfer transistor is configured to operate based on a second transfer signal; The dual-conversion transistor is connected between the first floating diffusion node and the second floating diffusion node, and the dual-conversion transistor is configured to operate based on a dual-conversion signal. The reset transistor is connected between the first power supply terminal and the second floating diffusion node, and the reset transistor is configured to operate based on a reset signal. The driving transistor is connected between the second power supply terminal and the first node, and is configured to operate based on the voltage of the first floating diffusion node; and The selection transistor is connected between the first node and the column line, and the selection transistor is configured to operate based on a selection signal.

12. The image sensor according to claim 11, wherein, Entering the high conversion gain mode includes turning off the dual conversion transistor.

13. The image sensor according to claim 11, wherein, The transfer of the partial charge includes: Turn on the first transfer transistor; and After the portion of the charge is transferred to the first floating diffusion node, the first transfer transistor is turned off.

14. The image sensor according to claim 11, wherein, Transferring at least a portion of the remaining charge includes: Turn on the second transfer transistor; and After at least a portion of the remaining charge has been transferred to the second floating diffusion node, the second transfer transistor is turned off.

15. The image sensor according to claim 11, wherein, Entering the low conversion gain mode includes turning on the dual conversion transistor.

16. The image sensor according to claim 15, wherein, The first floating diffusion node and the second floating diffusion node are electrically connected to generate an extended floating diffusion node.

17. The image sensor according to claim 16, wherein: The pixel is also configured to share at least a portion of the charge transferred to the first floating diffusion node and the remaining charge transferred to the second floating diffusion node with the extended floating diffusion node.

18. The image sensor according to claim 17, wherein, The pixel is also configured to perform a second readout operation corresponding to the charge shared to the extended floating diffusion node.

19. An image sensor, comprising: A pixel array, comprising multiple pixels; The timing controller is configured to generate control signals; as well as The line decoder is configured to generate at least one of a first transfer signal, a second transfer signal, a dual conversion signal, a reset signal, and a selection signal based on the control signal to drive the pixel array. Each of the plurality of pixels includes: A photodiode is configured to accumulate charge based on a light signal; A first transfer transistor is connected between the photodiode and the first floating diffusion node, and the first transfer transistor is configured to operate based on a first transfer signal; A second transfer transistor is connected between the photodiode and the second floating diffusion node, and the second transfer transistor is configured to operate based on a second transfer signal; A dual-conversion transistor is connected between the first floating diffusion node and the second floating diffusion node, and the dual-conversion transistor is configured to operate based on a dual-conversion signal; A reset transistor is connected between a first power supply terminal and a second floating diffusion node, and the reset transistor is configured to operate based on a reset signal; A driving transistor, connected between a second power supply terminal and a first node, is configured to operate based on the voltage of the first floating diffuse node; and A selection transistor is connected between the first node and the column line, and the selection transistor is configured to operate based on a selection signal.

20. The image sensor according to claim 19, wherein, After transferring a portion of the charge accumulated in the photodiode to the first floating diffusion node and before performing a first readout operation corresponding to the portion of charge transferred to the first floating diffusion node, the image sensor is configured to transfer at least a portion of the remaining charge accumulated in the photodiode to the second floating diffusion node.

Images