A data transmission method and system for aerospace TT&C

Abstract

The application relates to the technical field of digital communication, and discloses a data transmission method and system for aviation measurement and control, which comprises the following steps: dividing measurement and control parameters into basic and extended bit sequences, calculating a payload budget based on a physical channel state; when the total number of full-quantity bits is over the limit, removing the extended sequence, extracting a truncated control vector to splice a global sequence; generating an implicit check sequence by using the control vector, performing forward error correction coding and interleaving, adding a synchronization word and transmitting; extracting a received payload, performing reverse heuristic checking by using a local hypothesis vector in a parallel pipeline, and locking a matching pipeline to reconstruct a protocol. The system comprises a sending end device and a receiving end device which execute the above method. The application realizes dynamic truncation and implicit check parallel blind solution, eliminates explicit signaling dependence, avoids link congestion and whole-frame analysis failure risk, and guarantees the continuity and reliability of aviation measurement and control data transmission.

Description

Technical Field

[0001] This invention relates to the field of digital communication technology, specifically to a data transmission method and system for aviation telemetry and control. Background Technology

[0002] Airborne telemetry, tracking, and command (TT&C) is a fundamental air-to-ground communication link that ensures aircraft can perform their missions. It primarily relies on radio waves to achieve two-way synchronization of information between the spacecraft and the ground control center. The operational process encompasses telemetry downlink and remote control uplink. Its data transmission links need to continuously transmit parameters such as flight attitude and equipment status, and must overcome channel disturbances caused by high-speed movement and complex electromagnetic interference to maintain the stable delivery of underlying operational data.

[0003] Existing telemetry and control data transmission schemes are generally based on static frame structures and explicit signaling mechanisms. The transmitting end typically packages various parameters periodically according to a fixed protocol template and appends a plaintext control header at the beginning of the data packet. This control header is responsible for indicating the effective length of the current payload and the format status such as the error correction coding mode. The receiving end usually needs to extract and successfully parse the plaintext indication field before it can determine the deinterleaving and decoding rules for subsequent service payloads.

[0004] In practical aviation applications, telemetry, tracking, and command (TT&C) channels are often affected by Doppler shift and multipath fading, and the available physical capacity is prone to dynamic shrinkage. Traditional fixed-format protocols cannot flexibly reduce low-priority extended data according to channel capacity, easily leading to link congestion and high-priority data delays. Meanwhile, explicit signaling using plaintext to indicate transmission status occupies additional effective bandwidth, and under harsh electromagnetic conditions, if a sudden bit error damages the plaintext control header, the receiver will be unable to obtain the correct demodulation and decoding rules, directly causing the entire frame's payload to fail to be parsed, making it difficult to guarantee continuous and reliable TT&C interaction.

[0005] Therefore, this invention proposes a data transmission method and system for aviation telemetry and control to overcome the shortcomings of existing technologies. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a data transmission method and system for aviation telemetry and control, which solves the problems of link congestion caused by channel capacity shrinkage in existing fixed transmission formats, and the failure to parse the entire frame data due to damage to explicit plaintext signaling.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] The first aspect of this invention provides a data transmission method for aviation telemetry and control, comprising the following steps:

[0009] The measurement and control parameters are divided into basic bit sequences and extended bit sequences, and multiple truncation feature configuration files are mapped to truncation control vectors respectively;

[0010] Calculate the total bit budget of the payload and the total number of bits for full transmission based on the physical layer channel state;

[0011] When the total number of bits in the full transmission is greater than the total bit budget of the payload, the extended bit sequence is removed, the target truncation feature configuration file is matched and the corresponding target truncation control vector is extracted, and the global basic sequence and the global extended sequence are spliced ​​together to generate the global basic sequence and the global extended sequence.

[0012] An implicit verification sequence is generated using the target truncated control vector and the global basic sequence, and forward error correction coding is performed to assemble the uninterleaved payload block;

[0013] The interleaving matrix is ​​generated using the target truncation control vector to interleave and scramble the uninterleaved payload block, and a physical synchronization feature word is added before transmission.

[0014] Extract the received payload sequence from the link layer, and perform reverse deinterleaving and reverse verification tests using a preset local hypothesis control vector in multiple parallel hardware pipelines. Select the successfully matched parallel hardware pipeline to complete the reconstruction of the aviation telemetry and control data protocol.

[0015] Preferably, the step of dividing the measurement and control parameters into a basic bit sequence and an extended bit sequence, and mapping multiple truncated feature configuration files to truncated control vectors respectively includes:

[0016] The measurement and control parameters are defined as data tuples containing an identifier, a priority, the basic bit sequence, and the extended bit sequence; wherein, the basic bit sequence and the extended bit sequence are obtained by statically stripping the original acquired values ​​corresponding to the measurement and control parameters by performing bitwise truncation instructions.

[0017] Each of the aforementioned truncation feature configuration files specifies a set of fixed truncation combination modes for the measurement and control parameters;

[0018] The index number of the truncation feature configuration file is input into the gate-level static addressing mapping logic array, and a preset binary pseudo-random sequence is output as the truncation control vector.

[0019] Preferably, the step of calculating the total bit budget of the payload and the total number of bits for full transmission based on the physical layer channel state includes:

[0020] The physical layer signal-to-noise ratio and Doppler frequency shift are extracted as the physical layer channel state input hardware state machine mapping function, and the maximum number of bits is output through a two-dimensional lookup table as the total bit budget of the effective payload.

[0021] The total number of bits in the full transmission is obtained by summing the lengths of the basic bit sequence and the extended bit sequence of all the measurement and control parameters.

[0022] Preferably, the steps of discarding the extended bit sequence when the total number of bits in the full transmission is greater than the total bit budget of the payload, matching the target truncation feature configuration file and extracting the corresponding target truncation control vector, and concatenating them to generate the global base sequence and the global extended sequence include:

[0023] The measurement and control parameters are arranged in ascending order according to the preset measurement and control priority, and the lowest priority extended bit sequence is marked and removed one by one, and the dynamic remaining length variable is reduced accordingly.

[0024] When the dynamic remaining length variable is not greater than the total bit budget of the effective payload, the elimination stops, and a temporary truncation decision set is obtained.

[0025] Find a fixed truncation combination mode that covers the temporary truncation decision set, the total data length after truncation does not exceed the total bit budget of the effective payload, the payload occupancy length does not exceed the link layer payload extraction length corresponding to the current physical layer capacity level, and the amount of data discarded is the least, and use the corresponding truncation feature configuration file as the target truncation feature configuration file to extract the target truncation control vector;

[0026] The retained basic bit sequence and the extended bit sequence are concatenated to form the global basic sequence and the global extended sequence, respectively.

[0027] Preferably, the step of concatenating the retained basic bit sequence and the extended bit sequence into the global basic sequence and the global extended sequence respectively includes:

[0028] According to the indication rules of the target truncation feature configuration file, the basic bit sequence in the measurement and control parameters is shifted into the first group of shift register chains and packaged into the global basic sequence;

[0029] The retained extended bit sequence is shifted into the second set of shift register chains and packaged into the global extended sequence.

[0030] Preferably, the step of generating an implicit verification sequence using the target truncated control vector and the global base sequence, and performing forward error correction coding to assemble the uninterleaved payload block includes:

[0031] The target truncation control vector is input into a linear feedback shift register to perform polynomial operations, generating a target scrambling sequence;

[0032] The target scrambling sequence is added modulo 2 to the global basic sequence, and the remainder segment is obtained by cyclic redundancy check shift division as the implicit check sequence.

[0033] Forward error correction coding is performed on the basic parity combination sequence composed of the global basic sequence and the implicit parity sequence at the first error correction code rate to generate a protected basic codeword sequence;

[0034] Perform forward error correction coding on the global extended sequence according to the second error correction code rate to generate a protected extended codeword sequence;

[0035] The protected base codeword sequence, the protected extended codeword sequence, and the preset padding bits are assembled into the uninterleaved payload block.

[0036] Preferably, the step of generating an interleaving matrix using the target truncation control vector to interleave and scramble the uninterleaved payload block, attaching physical synchronization feature words, and transmitting includes:

[0037] Write the uninterleaved load block into a two-dimensional block interleaved memory;

[0038] The pseudo-random address generation logic is activated using the target truncation control vector to generate a read address mapping table as the interleaving matrix.

[0039] Data is extracted from the two-dimensional block interleaving memory according to the non-linear jump address of the interleaving matrix and rearranged into an interleaved bit stream;

[0040] A high autocorrelation bit pattern is spliced ​​at the beginning of the interleaved bit stream as the physical synchronization feature word to form a physical transmission frame and transmit it.

[0041] Preferably, the step of extracting the link layer received payload sequence includes:

[0042] The Hamming distance between the sliding window data and the physical synchronization feature word is calculated using a hardware correlator. If the distance is not greater than a preset tolerance threshold, the position is locked and the physical frame start boundary is marked. A data segment of the length corresponding to the current physical layer capacity level is extracted and used as the link layer received payload sequence.

[0043] Preferably, the step of performing reverse deinterleaving and reverse verification tests using preset local hypothesis control vectors in multiple parallel hardware pipelines, and selecting the successfully matched parallel hardware pipeline to complete the reconstruction of the aviation telemetry and control data protocol includes:

[0044] Each of the parallel hardware pipelines generates a reverse deinterleaving address sequence according to the allocated local hypothesis control vector, and performs reverse rearrangement of the link layer received payload sequence according to the reverse deinterleaving address sequence;

[0045] Forward error correction decoding is performed on the reverse rearranged link layer received payload sequence to obtain candidate basic check combination sequence and candidate extended sequence;

[0046] The reverse deinterleaved base sequence and the received check sequence are stripped from the candidate basic check combination sequence;

[0047] The inverse deinterleaving base sequence is XORed with the local hypothesis scrambling sequence generated by the local hypothesis control vector to generate an inverse XOR result polynomial, and a cyclic redundancy check shift division is performed on the inverse XOR result polynomial to obtain a trial check remainder.

[0048] By comparing the trial verification remainder with the received verification sequence, and using the field offset address table embedded in the truncation feature configuration file corresponding to the parallel hardware pipeline with the same comparison result, the global extended sequence is extracted from the candidate extended sequence to complete the reconstruction of the aviation telemetry and control data protocol.

[0049] This invention provides a data transmission method and system for aviation telemetry and control. It has the following beneficial effects:

[0050] 1. This invention divides the measurement and control parameters into a basic bit sequence and an extended bit sequence, and calculates the total bit budget of the effective payload in conjunction with the current physical layer channel state. When the full transmission demand exceeds the current carrying capacity, priority-driven dynamic truncation is performed. This reduces the risk of link congestion caused by fixed frame structures in bandwidth-limited or fluctuating environments, allows aviation equipment to prioritize the reliable transmission of core measurement and control basic data, and improves the adaptive capability of the underlying measurement and control transmission.

[0051] 2. This invention generates a scrambling code by using a truncated control vector-driven register, calculates an implicit parity sequence by operating the scrambling code with a global basic sequence, and performs differential code rate forward error correction coding on the basic parity combination sequence and the global extended sequence. This allows the truncation state to be bound to the basic data integrity verification process without adding a plaintext truncation mode signaling field, reducing protocol header overhead in aviation communications, enhancing the recovery capability of core telemetry and control data in interference environments, and improving the transmission efficiency of underlying data.

[0052] 3. This invention deploys multiple parallel hardware pipelines at the receiving end, independently performing reverse deinterleaving and verification probing using local hypothetical control vectors. Based on parallel comparison results, matching items are locked and the protocol is reconstructed. This mechanism eliminates the dependence on explicit configuration instructions, enabling the aviation receiving terminal to quickly restore synchronization after a link interruption, avoiding packet loss in telemetry and control caused by state parsing errors, and ensuring continuous transmission of service data. Attached Figure Description

[0053] Figure 1This is a data transmission system architecture diagram for aviation telemetry and control according to the present invention;

[0054] Figure 2 This is a flowchart of the data transmission method for aviation telemetry and control according to the present invention;

[0055] Figure 3 The parameter initialization mapping flowchart of this invention;

[0056] Figure 4 This is a flowchart of the physical layer budget calculation process of the present invention;

[0057] Figure 5 This is a flowchart of the truncation, matching, separation, and recombination process of the present invention;

[0058] Figure 6 This is a flowchart of the encoding, verification, interleaving, and transmission process of the present invention;

[0059] Figure 7 This is a flowchart of the parallel verification and parsing process at the receiving end of the present invention.

[0060] Among them, 100 is the transmitting device; 101 is the configuration initialization module; 102 is the budget calculation module; 103 is the truncation matching module; 104 is the encoding verification module; 105 is the interleaving transmission module; 200 is the receiving device; 201 is the synchronization extraction module; and 202 is the parallel verification parsing module. Detailed Implementation

[0061] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] See attached document Figure 1 This invention provides a data transmission system for aviation telemetry and control. This data transmission system is deployed in a highly dynamic aviation telemetry and control communication network environment, and achieves low-level physical bitstream interaction through a radio electromagnetic frequency channel between an airborne telemetry and control computer and a ground-based telemetry and control baseband processing terminal. The system includes a transmitting end device 100 deployed at the front of the aircraft and a receiving end device 200 deployed at the ground base station.

[0063] The transmitting device 100 includes a configuration initialization module 101, a budget calculation module 102, a truncation matching module 103, an encoding verification module 104, and an interleaved transmission module 105. The receiving device 200 includes a synchronization extraction module 201 and a parallel verification parsing module 202.

[0064] The transmitting device 100 acquires the raw telemetry data streams from each sensor node in real time via its internal airborne bus. The configuration initialization module 101 preloads the measurement and control parameter set and a limited number of truncation feature configuration files, providing parameter division basis and truncation state constraints for subsequent data link layer framing actions, and statically maps each truncation feature configuration file to a unique corresponding truncation control vector.

[0065] The budget calculation module 102 interacts directly with the physical layer demodulation unit to extract the physical layer signal-to-noise ratio and physical layer Doppler frequency shift of the telemetry and control channel at the current moment in real time, and determines the total bit budget of the effective payload for the current transmission period accordingly.

[0066] According to the measurement and control priority rules, the truncation matching module 103 performs field-level pruning on the extended bit sequence in the full data to be transmitted; when the total bit budget of the effective payload is exceeded, the secondary extended bit sequence is removed, and the spliced ​​global basic sequence and global extended sequence are output, and the target truncation control vector used to indicate the current truncation state is extracted synchronously.

[0067] The encoding and verification module 104 takes over the separated data sequence and converts the target truncation control vector into a target scrambling sequence through hardware shift register logic. It then performs a bitwise XOR operation with the global base sequence to generate an implicit verification sequence bound to the current truncation state. Subsequently, it calls the hardware forward error correction encoding logic to apply differential code rate error correction protection to the data part composed of the global base sequence and the implicit verification sequence, as well as the global extended sequence, and splices them together to generate an uninterleaved payload block.

[0068] The interleaved transmission module 105 receives the uninterleaved payload block, directly injects the target truncation control vector into the address generator of the data link layer two-dimensional block interleaving memory, and performs dynamic shuffling and permutation on the payload bit stream by changing the read address order of the data link layer two-dimensional block interleaving memory. Then, a fixed physical synchronization feature word is added to the front end of the interleaved bit stream to form a complete physical transmission frame, and finally, it is fed into the airborne antenna through digital-to-analog conversion and radio frequency circuit to be transmitted to the telemetry and control channel.

[0069] After adding Doppler frequency shift and fading noise to the spatial wireless channel, the physical transmission frame is transmitted to the receiving device 200. The hardware correlator inside the synchronization extraction module 201 performs continuous sliding cross-correlation operation on the digital baseband received bit stream, locks the position of the physical synchronization feature word in the header, marks the physical frame start boundary accordingly, and extracts the link layer received payload sequence of the corresponding length to the current physical layer capacity level.

[0070] The parallel verification and parsing module 202 pre-instantiates multiple independent parallel hardware pipelines within the field-programmable gate array. It utilizes all legal local hypothesis control vectors stored locally to simultaneously perform reverse memory address addressing restoration (reverse deinterleaving) and scrambling code XOR verification tests on the received payload sequence at the link layer. Based on the matching results output by the hardware verification circuits of each pipeline, it selects the correct data branch and completes the reverse parsing and reconstruction of the underlying physical bit stream to the upper-layer aviation telemetry and control data protocol.

[0071] See attached document Figure 2 This invention provides a data transmission method for aviation telemetry and control. This data transmission method for aviation telemetry and control is executed between a transmitting device 100 and a receiving device 200, and includes the following steps:

[0072] S1, initialize the measurement and control parameter set and truncation feature configuration file, and map the truncation feature configuration file to the truncation control vector.

[0073] The configuration initialization module 101 pre-configures the measurement and control parameter set, defining each measurement and control parameter in the set as a data tuple containing a parameter identifier, measurement and control priority, basic bit sequence, and extended bit sequence; at the same time, the configuration initialization module 101 pre-defines multiple truncation feature configuration files, mapping each of the multiple truncation feature configuration files to a unique truncation control vector;

[0074] S2 calculates the total bit budget of the payload based on the physical layer channel state and calculates the total number of bits for full transmission.

[0075] The budget calculation module 102 acquires the physical layer signal-to-noise ratio and physical layer Doppler frequency shift in real time, calculates the total effective bit budget of the current physical transmission frame based on the physical layer signal-to-noise ratio and physical layer Doppler frequency shift, and calculates the total number of full transmission bits required to transmit all measurement and control parameters.

[0076] S3 compares the total number of bits transmitted in full with the total bit budget of the payload to match the target truncation control vector, separating the global base sequence and the global extended sequence.

[0077] When the total number of bits in the full transmission is greater than the total bit budget of the effective payload, the truncation matching module 103 removes the extended bit sequences corresponding to the measurement and control parameters in order of measurement and control priority from low to high, until the total data length after truncation is less than or equal to the total bit budget of the effective payload. Among multiple truncation feature configuration files, a target truncation feature configuration file that meets the constraint of the total bit budget of the effective payload is matched. A target truncation control vector corresponding to the target truncation feature configuration file is extracted. All the remaining basic bit sequences are concatenated into a global basic sequence, and all the remaining extended bit sequences are concatenated into a global extended sequence.

[0078] S4 uses the target truncation control vector and the global basic sequence to generate an implicit check sequence, which is then encoded to generate an uninterleaved load block.

[0079] The encoding and verification module 104 generates a target scrambling sequence using the target truncation control vector, performs an XOR operation between the target scrambling sequence and the global basic sequence to generate an implicit verification sequence, performs forward error correction coding on the global basic sequence and the implicit verification sequence according to the first error correction code rate to generate a protected basic codeword sequence, performs forward error correction coding on the global extended sequence according to the second error correction code rate to generate a protected extended codeword sequence, and concatenates the protected basic codeword sequence and the protected extended codeword sequence to assemble an uninterleaved payload block.

[0080] S5 utilizes the target truncation control vector to interleave uninterleaved payload blocks, adds physical synchronization feature words, and transmits them to the telemetry and control channel.

[0081] The interleaving transmission module 105 uses the target truncation control vector as the initialization vector of the data link layer block interleaver to generate an interleaving matrix. It then uses the interleaving matrix to perform two-dimensional bit permutation on the uninterleaved payload block to generate an interleaved bit stream. After adding a physical synchronization feature word to the front end of the interleaved bit stream, it performs baseband modulation and transmits it to the telemetry and control channel.

[0082] S6, lock the physical synchronization feature word in the received signal to extract the payload, and use the assumed control vector to verify, parse and reconstruct the data in parallel.

[0083] The synchronization extraction module 201 receives and demodulates the digital baseband signal to obtain the received bitstream. It uses a hardware correlator to search for the physical synchronization feature words contained in the received bitstream to lock the physical frame start boundary and extract the link layer received payload sequence. The parallel verification and parsing module 202 instantiates multiple parallel hardware pipelines corresponding to multiple truncation feature configuration files on the receiving device 200. Each parallel hardware pipeline uses a preset local hypothesis control vector to perform reverse deinterleaving on the link layer received payload sequence, separating the reverse deinterleaving base sequence and the received verification sequence. It performs an XOR operation with the local hypothesis scrambling code sequence corresponding to the local hypothesis control vector and the reverse deinterleaving base sequence and performs a reverse verification test. The parallel hardware pipeline whose reverse verification test result is equal to the received verification sequence is selected to confirm that the global base sequence transmission is error-free. The global extended sequence is extracted according to the target truncation feature configuration file corresponding to the equal parallel hardware pipeline to complete the reconstruction of the aviation telemetry and control data protocol.

[0084] To further clarify the implementation of each technical aspect of the present invention, the following will provide a detailed description of the implementation of each functional module involved above and its internal processing flow.

[0085] See attached document Figure 3In this embodiment, the specific implementation of step S1 includes the following sub-steps:

[0086] S101, acquire the raw telemetry data stream and define the measurement and control parameters as data tuples containing bit-level partitioning.

[0087] The transmitting device 100 acquires raw telemetry data streams from each sensor node in real time via its internal airborne bus. For example, each sensor node includes an aircraft wing strain gauge, an engine temperature sensor, and an inertial navigation unit.

[0088] The configuration initialization module 101 preloads a fixed set of measurement and control parameters and uses this set as the parameter source for subsequent data link layer framing actions. The configuration initialization module 101 pre-configures the set of measurement and control parameters, defining each measurement and control parameter in the set as a data tuple containing a parameter identifier, measurement and control priority, basic bit sequence, and extended bit sequence.

[0089] In this step, the telemetry, tracking, and command (TT&C) parameter set is the complete set of all sensor parameter objects permitted for transmission within the current aviation TT&C mission cycle. The parameter identifier is a logical addressing code used to uniquely identify the source of a sensor channel within the communication network.

[0090] Telemetry, tracking, and command (TT&C) priority is a digital weighting level pre-assigned based on the importance of parameters to the aircraft's safety control and attitude calculation. The lower the digital weighting level, the lower the importance of the service, and the more likely it is to be discarded or transmitted with reduced precision; the higher the digital weighting level, the higher the importance of the service, and the more likely it should be reserved.

[0091] For each acquired value in the raw telemetry data stream, the configuration initialization module 101 performs a static separation operation between the basic bit sequence and the extended bit sequence using bitwise truncation instructions. The basic bit sequence is the set of most significant bits necessary to maintain the profile of the basic physical parameters; the extended bit sequence is the set of least significant bits that provides high precision.

[0092] As a feasible implementation method, assume that the original binary acquired value corresponding to a certain measurement and control parameter is Its total data bit width is Bit, represented in binary as ,in The most significant bit, The least significant bit. The total data width is typically... The value is determined based on the inherent properties of the sensor hardware datasheet; for example, a common value is 16 or 32. The configuration initialization module 101 configures the system according to the preset cutoff point. Acquire raw binary values The process is to split the data using the following formula:

[0093] ;

[0094] ;

[0095] In the formula, The data segment corresponding to the basic bit sequence has a length of [length missing]. Bits are used to ensure that even if only the data fragments corresponding to the basic bit sequence arrive at the receiving device 200 under poor channel conditions, the basic state dimensions of the measurement and control parameters can be recovered. The data segment corresponding to the extended bit sequence has a length of Bits are used to provide finer decimal or low-precision data when the channel environment is good; and These are all loop variable indices for the summation operator.

[0096] Cutoff point The range of values ​​is Its specific value depends on the minimum tolerance accuracy required by the measurement and control parameters under static configuration. For example, for a certain type of high-precision temperature sensor, its total data bit width... When the value is 16, if only the basic profile at the degree level needs to be maintained, then the truncation point is... It can be configured to 8, thereby dividing the lower 8 bits of the fractional part into the extended part.

[0097] Through the aforementioned mathematical decomposition mechanism, it is possible to decompose a single collected value without altering the original physical dimensions. The data is deconstructed into two independent data segments: the high-order bits and the low-order bits. Accordingly, the data tuple output by the configuration initialization module 101 includes parameter identifiers, measurement and control priorities, basic bit sequences, and extended bit sequences, serving as the basic computational unit for subsequent matching and truncation operations.

[0098] S102, solidify a limited number of truncation combination patterns to define multiple truncation feature profiles.

[0099] The configuration initialization module 101 predefines multiple truncation feature configuration files and stores a limited number of these files in its internal read-only memory. Essentially, each truncation feature configuration file is a predefined set of fixed truncation combinations, used to determine which extended bit sequences of all the aforementioned measurement and control parameters are removed and which are retained when facing a specific channel capacity bottleneck.

[0100] In complex and variable channel environments, to avoid the problem of an excessive number of states in the subsequent parallel verification and parsing phase of the receiving device 200, the transmitting device 100 abandons the unconstrained dynamic calculation bit width truncation mode. Preferably, the number of multiple truncation feature configuration files is set to a fixed value, such as 4, 8 or 16, and hard-coded in the initialization configuration memory of the transmitting device 100 and the receiving device 200.

[0101] Each truncation feature configuration profile specifies a fixed truncation combination mode for a set of measurement and control parameters. For example, the first configuration profile indicates that the extended bit sequence of all measurement and control parameters should be retained, the second configuration profile indicates that only the extended bit sequence of the temperature parameter should be discarded, and so on.

[0102] Specifically, to ensure the integrity of the algorithm logic under extremely harsh channel conditions, multiple truncation feature configuration files are forcibly configured to include a bottom-level configuration file that retains only the basic bit sequence, and the total length of the basic bit sequence corresponding to this bottom-level configuration file does not exceed the minimum effective payload bit budget allowed by the system. By fixing a limited number of truncation feature configuration files, the arbitrary unordered truncation combination of measurement and control parameters is restricted, thereby limiting the state exhaustive space of the parallel verification and parsing phase.

[0103] For example, if the finite number is set to 8, the receiving device 200 only needs to statically allocate 8 sets of parallel operation branches within the field-programmable gate array. Each set of parallel operation branches is pre-set with a fixed local hypothesis control vector and its corresponding deinterleaving rule and scrambling generation rule. When a frame of data is received, the 8 branches simultaneously perform reverse deinterleaving, decoding, and verification operations, and finally output only the data result of a single branch that has successfully matched the verification. By compressing an infinite number of truncated permutations and combinations into a fixed number of preset matching relationships, the parallel verification and parsing complexity of the receiving device 200 can be reduced.

[0104] S103 maps the truncation feature configuration file to the corresponding truncation control vector through a static logic array.

[0105] The configuration initialization module 101 statically maps each of the multiple truncation feature configuration files to a unique truncation control vector. In specific implementation, the configuration initialization module 101 internally deploys a gate-level static addressing mapping logic array, using the inherent index number of the truncation feature configuration file as the addressing input of the gate-level static addressing mapping logic array.

[0106] Within each physical address space of the gate-level static addressing mapping logic array, independent and unrelated binary pseudo-random sequences are pre-programmed. The length of the binary pseudo-random sequences is, for example, 16 bits, 32 bits, or 64 bits. When the configuration initialization module 101 is initialized and started, a one-to-one correspondence is established between the truncation feature configuration file and the binary pseudo-random sequence. The binary pseudo-random sequence is output and named the truncation control vector. The truncation control vector serves as a unique code representing the current specific truncation combination mode and will also directly act as the initial input variable for the scrambling generation logic and the interleaving array in subsequent data transmission links. Through the above data tuple segmentation, finite configuration file definition, and physical mapping operations, the business logic boundary setting from the upper-level measurement and control parameters to the lower-level control vector is completed.

[0107] See attached document Figure 4 In this embodiment, step S2 is specifically implemented by including the following sub-steps:

[0108] S201, extract the fading state index of the telemetry and control channel and quantify it as an input variable.

[0109] The budget calculation module 102 acquires the physical layer signal-to-noise ratio (SNR) and physical layer Doppler shift in real time. In this embodiment, the budget calculation module 102 directly interacts with the physical layer demodulation unit (PSU). The PSU is located within the transmitting device 100 and is used to receive link probe signals or status feedback signals transmitted back from the ground telemetry and control station. It performs carrier synchronization, demodulation, and status measurement on the link probe signals or status feedback signals. During signal tracking, the PSU outputs the PNR and PSU Doppler shift of the current telemetry and control communication channel in its internal status register. The budget calculation module 102 reads this status register through a dedicated data acquisition bus.

[0110] The physical layer signal-to-noise ratio (SNR) is determined by the ratio of the effective signal power to the background noise power in the currently received signal, and is used to characterize the additive noise intensity of the channel. Since the aircraft is in a state of high-speed relative motion, the radio frequency carrier frequency will shift. The value output by the physical layer phase-locked loop after locking the carrier frequency deviation is defined as the physical layer Doppler shift, which is used to characterize the phase change rate of fast fading in the channel.

[0111] The physical layer demodulation unit continuously tracks the signal and writes the updated physical layer signal-to-noise ratio and physical layer Doppler frequency shift to a specific memory address. The budget calculation module 102 reads the specific memory address according to a fixed frame period to complete the real-time acquisition of status indicators.

[0112] S202, perform state machine mapping based on state indicators to output channel carrying capacity.

[0113] The budget calculation module 102 calculates the total bit budget of the payload for the current physical transmission frame based on the physical layer signal-to-noise ratio and the physical layer Doppler shift. The total bit budget of the payload refers to the minimum bit error rate constraint required to maintain uninterrupted data link communication, for example, a bit error rate not exceeding 1 × 10⁻⁶. -5 At that time, the upper limit of the net service data length before encoding that the underlying physical channel can provide to carry the basic bit sequence and the extended bit sequence within the current communication frame period.

[0114] To avoid introducing floating-point operations in high-speed communication scenarios and causing processing delays, the budget calculation module 102 takes the physical layer signal-to-noise ratio and physical layer Doppler shift as input variables and sends them to the hardware state machine mapping function. It outputs the maximum number of binary bits that the current physical channel can carry through the lookup table logic, and defines the maximum number of binary bits as the total bit budget of the effective payload.

[0115] As a preferred approach, the budget calculation module 102 has a built-in two-dimensional lookup table. The specific construction process of the two-dimensional lookup table is as follows: through offline channel simulation verification, the highest modulation order and coding rate that the underlying communication link can support under different combinations of physical layer signal-to-noise ratio and physical layer Doppler frequency shift are pre-calibrated, and then the maximum usable data capacity within a fixed frame period is derived.

[0116] For example, the effective dynamic range of the physical layer signal-to-noise ratio is divided into multiple consecutive signal-to-noise ratio intervals according to a specific step size and mapped to row indices, such as row index 0 corresponding to 0 to 5dB and row index 1 corresponding to 5 to 10dB; at the same time, the dynamic range of the physical layer Doppler frequency shift is divided into multiple consecutive frequency shift intervals and mapped to column indices, such as column index 0 corresponding to 0 to 500Hz.

[0117] For each cross-mapping node of row and column indices, the highest capacity bit value that satisfies the minimum bit error rate threshold constraint under that fading interval combination is calculated, such as 1024 bits, 2048 bits, or 4096 bits, and this highest capacity bit value is written into the two-dimensional lookup table as the preset output value of the cross-mapping node. In actual operation, when the physical layer state input from the lookup table falls into the interval of row index 1 and column index 0, the budget calculation module 102 directly outputs the preset maximum available data capacity from the cross-mapping node.

[0118] In actual table lookup operations, the physical layer signal-to-noise ratio (SNR) input to the hardware state machine mapping function is divided into intervals to generate row index addresses, and the physical layer Doppler shift is divided into intervals to generate column index addresses. The interval division threshold is set according to engineering requirements; for example, the physical layer SNR can be divided into 1dB intervals, and the physical layer Doppler shift can be divided into 100Hz intervals. The fixed value extracted by addressing the row and column index addresses is the maximum number of binary bits (i.e., the total bit budget of the effective payload described below). The mathematical expression corresponding to the above logic is as follows:

[0119] ;

[0120] In the formula, This represents the total bit budget for the payload; Indicates the input physical layer signal-to-noise ratio; This indicates the physical layer Doppler frequency shift of the input; This represents a preset hardware state machine mapping function, whose mapping relationship is determined by a pre-entered two-dimensional lookup table, used to discretize continuous physical variables into specific bit capacity limits.

[0121] S203, accumulate the data length within the measurement and control parameter set to calculate the full business requirements.

[0122] The budget calculation module 102 calculates the total number of bits required for full transmission of all measurement and control parameters. The total number of bits for full transmission refers to the total length of binary data required to completely transmit the data tuples of all measurement and control parameters in the current measurement and control parameter set without triggering the bit width trimming mechanism.

[0123] The budget calculation module 102 reads the length information contained in the data tuple of the measurement and control parameters established by the configuration initialization module 101, and performs a summation operation on the fixed length of the basic bit sequence and the fixed length of the extended bit sequence contained in the data tuple. The specific calculation formula is as follows:

[0124] ;

[0125] In the formula, Indicates the total number of bits transmitted in the full data transfer. This represents the total number of activated measurement and control parameters in the current measurement and control parameter set, and is a positive integer. For the step index of the summation process; Indicates the first The fixed length of the basic bit sequence in the data tuple corresponding to each measurement and control parameter; Indicates the first The fixed length of the extended bit sequence in the data tuple corresponding to each measurement and control parameter.

[0126] By executing the above sub-steps, the budget calculation module 102 obtains the total payload bit budget representing the physical layer's supply capacity, and the total number of full transmission bits representing the service layer's transmission requirements, providing a quantitative numerical comparison benchmark for subsequent stages to determine whether to initiate bit-width pruning.

[0127] See attached document Figure 5 In this embodiment, step S3 specifically includes the following sub-steps:

[0128] S301 forms a temporary truncation decision set based on the total number of bits transmitted in full, and executes the extended bit truncation logic step by step in ascending order of measurement and control priority when needed.

[0129] The truncation matching module 103 performs field-level pruning of the extended bit sequence in the full data to be transmitted according to the measurement and control priority rules. In this embodiment, the truncation matching module 103 compares the total number of bits of the full transmission calculated in the preceding steps with the total bit budget of the effective payload, and makes a preliminary judgment on whether it is necessary to start extended bit pruning.

[0130] To ensure the completeness of the algorithm logic, the truncation matching module 103 first uses the extended bit sequence corresponding to all measurement and control parameters as the initial elimination state, and sets the elimination set corresponding to the initial elimination state to an empty set.

[0131] If the total number of bits transmitted in full is less than or equal to the total bit budget of the payload, the truncation matching module 103 will use the empty set as the temporary truncation decision set.

[0132] If the total number of bits transmitted in full exceeds the total bit budget of the effective payload, it means that the underlying physical channel cannot carry all the original measurement and control data, and the truncation matching module 103 will trigger the data truncation and precision reduction processing flow.

[0133] After triggering the data truncation and precision reduction process, the truncation matching module 103 sequentially removes the extended bit sequence corresponding to the measurement and control parameters in order of measurement and control priority from low to high until the total data length after truncation is less than or equal to the total bit budget of the effective payload.

[0134] As a specific implementation, the truncation matching module 103 reads all activated measurement and control parameters in the current measurement and control parameter set and sorts them in ascending order according to the preset digital weight level of measurement and control priority. In this sorting, the lower the value of the digital weight level, the lower the business importance of the corresponding measurement and control parameter, and the higher the priority of its extended bit sequence being removed.

[0135] The truncation matching module 103 sets a dynamic remaining length variable and assigns its initial value to the total number of bits transmitted in full. Based on the ascending order, the truncation matching module 103 starts with the measurement and control parameters with the lowest service importance, marks and removes the extended bit sequences contained in the measurement and control parameters one by one, and subtracts the fixed length of the marked and removed extended bit sequences from the dynamic remaining length variable.

[0136] After each removal mark and subtraction operation, the truncation matching module 103 compares the updated dynamic remaining length variable with the total payload bit budget. If the dynamic remaining length variable is still greater than the total payload bit budget, the same extended bit sequence removal operation is performed on the next measurement and control parameter in ascending order; if the dynamic remaining length variable is less than or equal to the total payload bit budget, the removal loop is stopped immediately. The judgment logic followed by the above-mentioned step-by-step stripping action can be expressed by the following iterative formula:

[0137] ;

[0138] In the formula, This indicates that the truncation matching module 103 is in the... The dynamic remaining length variable calculated after each elimination cycle; Indicates the total number of bits transmitted in the full data transfer. This indicates the total number of measurement and control parameters whose extended bit sequences have been marked and removed. This is the processing index sorted in ascending order according to measurement and control priority; This indicates that the sorting order in ascending order is the first... The data element corresponding to each measurement and control parameter has a fixed length of extended bit sequence. When the inequality is satisfied... Time (of which) (For the total bit budget of the payload), the truncation matching module 103 locks the current elimination state and terminates the loop iteration to obtain a temporary truncation decision set.

[0139] S302, Match the target truncation feature configuration file with the calculated truncation decision state and extract the target truncation control vector.

[0140] The truncation matching module 103 matches a target truncation feature configuration file that satisfies the total payload bit budget constraint from multiple truncation feature configuration files. To confine the temporary truncation decision set within a pre-defined finite state space, the truncation matching module 103 performs a pattern comparison between the locked elimination state and the multiple predefined truncation feature configuration files; wherein, the locked elimination state is used to indicate which extended bit sequences of measurement and control parameters are retained and which extended bit sequences of measurement and control parameters are eliminated.

[0141] The truncation matching module 103 traverses multiple truncation feature configuration files, searching for a set of extended bit sequences to be removed that completely covers the temporary truncation decision set, where the total truncated data length corresponding to the truncation feature configuration file does not exceed the total effective payload bit budget, and the payload occupancy length pre-recorded in the truncation feature configuration file does not exceed the number of link layer payload bits allowed by the current fixed frame format. Simultaneously, compared to other truncation feature configuration files that meet the constraints, the fixed truncation combination mode with the least amount of discarded data is identified as the target truncation feature configuration file. The payload occupancy length represents the number of link layer payload bits occupied by the corresponding truncation feature configuration file under the current fixed frame format, and the payload occupancy length is pre-recorded in the corresponding truncation feature configuration file.

[0142] Subsequently, the truncation matching module 103 extracts the target truncation control vector corresponding to the target truncation feature configuration file based on the static mapping relationship between the truncation feature configuration file and the truncation control vector.

[0143] Through this matching action, the truncation state of the current physical transmission frame is constrained to one of the limited number of pre-fixed combination patterns in the configuration initialization module 101, thereby avoiding the generation of a huge dynamic decoding search space at the receiving end.

[0144] S303 reassembles the retained data bit segments to generate a global base sequence and a global extended sequence.

[0145] When the total bit budget of the effective payload is exceeded, the truncation matching module 103 removes minor extended bit sequences and outputs the spliced ​​global base sequence and global extended sequence. Specifically, the truncation matching module 103 performs physical extraction and spatial reconstruction on the data tuples of all measurement and control parameters in the target truncation feature configuration file according to the indication rules for retaining and removing extended bit sequences. The indication rules are used to mark whether the extended bit sequence of each measurement and control parameter is in a retained or removed state.

[0146] The truncation matching module 103 concatenates all the retained basic bit sequences into a global basic sequence, and concatenates all the retained extended bit sequences into a global extended sequence.

[0147] The global base sequence is a concatenated continuous bit stream composed of the most significant bits of all telemetry and control parameters allowed to be transmitted in the current transmission frame, used to carry the basic physical parameter profile of the device under test. The global extended sequence is a concatenated continuous bit stream composed of the least significant bits of telemetry and control parameters that are allowed to be retained as indicated by the target truncation feature configuration file, used to provide additional high-precision digital resolution information within the margin of channel capacity.

[0148] At the hardware implementation level, the truncation matching module 103 has two independent shift register chains built in. For each measurement and control parameter in the current measurement and control parameter set, the truncation matching module 103 shifts the basic bit sequence in the data tuple corresponding to the measurement and control parameter into the first shift register chain according to the parameter arrangement order in the measurement and control parameter set at a fixed clock cycle;

[0149] After completing the above operations, check the target truncation feature configuration file. If the extended bit sequence of the measurement and control parameters is indicated to be reserved by the target truncation feature configuration file, then move the extended bit sequence into the second set of shift register chains.

[0150] If the target truncation feature configuration file indicates rejection, the extended bit sequence indicated for rejection is directly intercepted and discarded without any shift or write operation. After all measurement and control parameters have been traversed, the continuous data stream latched in the first set of shift register chains is encapsulated and packaged for output as the global basic sequence, and the continuous data stream latched in the second set of shift register chains is encapsulated and packaged for output as the global extended sequence.

[0151] By executing the above separation and splicing logic, the original sensor continuous bit-width structure is divided into basic data stream and extended data stream according to importance, providing isolated data streams for subsequent implementation of differentiated error correction protection.

[0152] See attached document Figure 6 In this embodiment, the specific implementation of step S4 includes the following sub-steps:

[0153] S401 uses the target truncation control vector to drive the linear feedback shift register to generate the target scrambling sequence and performs an XOR operation.

[0154] The encoding verification module 104 generates a target scrambling sequence using the target truncated control vector. In this embodiment, the encoding verification module 104 internally deploys a linear feedback shift register, and uses the extracted target truncated control vector as the seed input of the linear feedback shift register. When the length of the target truncated control vector is consistent with the register order of the linear feedback shift register, the target truncated control vector is directly used as the initial fill vector of the linear feedback shift register. When the two lengths are inconsistent, the target truncated control vector is converted into an initial fill vector consistent with the register order according to the truncation, padding, or compression mapping rules consistent between the transmitting end device 100 and the receiving end device 200.

[0155] The linear feedback shift register performs polynomial shift and feedback tap operations driven by the operating clock, outputting a continuous bit stream with pseudo-random characteristics. The generator polynomial used for the feedback tap operation is pre-programmed in the underlying hardware, ensuring the deterministic generation of the target scrambling sequence. For example, if the generator polynomial pre-programmed in the underlying hardware is... This corresponds to constructing a 3-level shift register chain containing 3 register units.

[0156] At each clock cycle, the data within the 3-stage shift register chain is shifted one bit towards the output. Simultaneously, the binary values ​​output from the 2nd and 3rd stage registers are extracted and subjected to a modulo-2 XOR operation. The result of this XOR operation is then used as feedback data to fill the input of the 1st stage register unit. As the clock pulse continues to trigger, the pseudo-random bit stream continuously output from the end of the shift register chain serves as the target scrambling sequence in this embodiment. This target scrambling sequence is used to mask the original characteristics of the data, and its internal binary arrangement order is uniquely determined by the target truncation control vector or the initial padding vector converted from the target truncation control vector.

[0157] Subsequently, based on the generated target scrambling sequence, the encoding verification module 104 performs an XOR operation between the target scrambling sequence and the global base sequence. Specifically, the encoding verification module 104 extracts a segment of the target scrambling sequence with a length equal to that of the global base sequence. Through underlying hardware logic gates, it performs a bitwise modulo-2 addition operation between the extracted target scrambling sequence and the global base sequence to generate an XOR result polynomial. The corresponding mathematical relationship is expressed as:

[0158] ;

[0159] In the formula, This represents the polynomial generated by the XOR operation. These are the basis variables for polynomial algebra operations; Represents the binary polynomial corresponding to the global basic sequence; This represents the binary polynomial corresponding to the target scrambling sequence; This represents the bitwise XOR operator. Therefore, the truncation state represented by the target truncation control vector is introduced into the XOR result polynomial.

[0160] S402, an implicit check sequence is generated based on the shift division mechanism of the XOR result polynomial.

[0161] After performing the XOR operation, the encoding verification module 104 calculates and generates an implicit verification sequence. Specifically, the encoding verification module 104 inputs the XOR result polynomial into the cyclic redundancy check generator polynomial and calculates the verification remainder using a shift division mechanism. The mathematical principle of the shift division calculation is to add a set number of zero bits to the end of the XOR result polynomial and then divide it by a preset generator polynomial to obtain the remainder. The specific logic is as follows:

[0162] ;

[0163] In the formula, This represents the highest order of the cyclic redundancy check generator polynomial. It is a positive integer and is usually set to 16 or 32 depending on the system's error detection requirements. This represents the quotient polynomial generated during a division operation. This represents the underlying preset cyclic redundancy check generator polynomial, such as the generator polynomial corresponding to CRC-16-CCITT or CRC-32. This represents the check remainder polynomial obtained after the shift division operation.

[0164] After completing the shift division operation, the encoding verification module 104 extracts the verification remainder polynomial. The corresponding binary bit field, and the check remainder polynomial The corresponding binary bit field is directly defined as an implicit check sequence.

[0165] The implicit check sequence carries both data integrity features for the global base sequence and information about the specific truncation feature configuration file used in the current communication frame. Using this implicit binding mechanism, the receiver can determine the truncation feature configuration file used by the transmitter through blind check matching of candidate control vectors without additional truncation mode signaling overhead.

[0166] S403 allocates error correction code rates based on unequal error protection strategies and splices together uninterrupted payload blocks.

[0167] The encoding and verification module 104 calls the internal hardware forward error correction encoding logic to perform forward error correction encoding on the basic verification combination sequence, which is composed of the global basic sequence and the implicit verification sequence in the order of global basic sequence first and implicit verification sequence last, to generate a protected basic codeword sequence.

[0168] The first error correction code rate is set to a coding ratio with a high redundancy ratio, such as 1 / 3, to improve the recovery probability of the global basic sequence under adverse channel conditions. The protected basic codeword sequence is the output after forward error correction and includes the global basic sequence, the implicit parity sequence, and an anti-interference data stream with associated parity bits.

[0169] At the same time, the encoding verification module 104 performs forward error correction coding on the global extended sequence according to the second error correction code rate to generate a protected extended codeword sequence; when the target truncation feature configuration file indicates that all extended bit sequences have been removed, the global extended sequence is an empty sequence, the encoding verification module 104 skips the forward error correction coding step corresponding to the second error correction code rate, and sets the protected extended codeword sequence to an empty sequence.

[0170] The second error correction code rate is set to a coding ratio with a redundancy ratio lower than that of the first error correction code rate, for example, a second error correction code rate of 2 / 3, used to reduce bandwidth overhead while ensuring the basic error correction capability of the extended data. The protected extended codeword sequence is a data stream that contains global extended sequence content and possesses the strength of conventional error correction protection.

[0171] By setting a redundancy ratio difference between the first and second error correction code rates, an unequal error protection structure oriented towards the global base sequence and the global extended sequence can be formed. For the specific algorithmic operations of forward error correction coding, such as the implementation mechanism for generating parity bits based on low-density parity-check codes or Turbo codes, those skilled in the art can refer to existing communication standards for configuration. The specific encoding process is well-known in the field and will not be elaborated upon here.

[0172] After completing the above encoding operations, the encoding verification module 104 concatenates the protected basic codeword sequence and the protected extended codeword sequence to assemble an uninterleaved payload block. When the length of the concatenated uninterleaved payload block is less than the link layer payload extraction length corresponding to the current physical transmission frame, the encoding verification module 104 fills the end of the uninterleaved payload block with preset padding bits. The preset padding bits are, for example, an all-zero bit sequence or an alternating 0101 bit sequence, and the position of the preset padding bits is used as the fixed field boundary information jointly determined by the corresponding truncation feature configuration file and the current physical layer capacity level. When the receiving device 200 reconstructs the protocol, it discards the preset padding bits according to the successfully matched truncation feature configuration file and the current physical layer capacity level.

[0173] In the specific assembly process, the encoding and verification module 104 writes the two independent data output streams sequentially into adjacent memory addresses of the sending buffer according to the predefined frame format, forming a unified linear data structure.

[0174] For example, the encoding verification module 104 starts from the starting base address of the transmission buffer and writes the protected basic codeword sequence bit by bit into the continuously increasing memory space. After the last bit of the protected basic codeword sequence is written, the protected extended codeword sequence is seamlessly appended to the tail space of the transmission buffer at the next physical adjacent address after the previous memory address, according to the same address increment logic.

[0175] An uninterleaved payload block refers to a frame data entity that has not yet undergone physical layer bit interleaving and scrambling, and has completed all service layer bit width clipping, implicit check calculations, and forward error correction coding logic. At this point, the coding and verification module 104 has completed data encapsulation before physical waveform modulation.

[0176] See attached document Figure 6 In this embodiment, the specific implementation of step S5 includes the following sub-steps:

[0177] S501 writes the uninterleaved payload blocks into the data link layer dual-port memory in a fixed timing sequence.

[0178] The interleaved transmit module 105 receives the previously assembled uninterleaved payload block and writes the uninterleaved payload block into its internal buffer memory.

[0179] In this embodiment, the interleaved transmission module 105 internally deploys a data link layer two-dimensional block interleaving memory, which adopts a dual-port random access memory hardware structure. The interleaved transmission module 105, through the independent write port of the dual-port random access memory, writes the consecutive bits contained in the uninterleaved payload block into the consecutive address space of the data link layer two-dimensional block interleaving memory bit by bit, according to a fixed working timing sequence of row address increment and column address increment.

[0180] During this write phase, the physical arrangement order of data in the data link layer two-dimensional block interleaving memory is consistent with the logical generation order of the uninterleaved payload block itself. The interleaving transmission module 105 continues to perform write operations until the effective bits and necessary preset fill ratio contained in the uninterleaved payload block fill the set memory depth.

[0181] S502 uses the target truncation control vector to drive the address generator to dynamically generate the interleaving matrix.

[0182] The interleaving transmission module 105 uses the target truncation control vector as the initialization vector for the data link layer block interleaver to generate the interleaving matrix. After completing the sequential data writing, in order to give the transmission frame the ability to resist burst continuous interference in the channel, the interleaving transmission module 105 directly injects the extracted target truncation control vector into the address generator of the data link layer two-dimensional block interleaving memory.

[0183] The address generator integrates pseudo-random address generation logic. In one specific implementation, the interleaving transmission module 105 uses the target truncation control vector as the initialization vector to activate the pseudo-random address generation logic, drives the underlying logic gates to calculate and generate a set of read address mapping tables with nonlinear jump properties, and directly uses the read address mapping table as the interleaving matrix.

[0184] For example, the pseudo-random address generation logic adopts a linear feedback shift structure. After loading the target truncated control vector or the address generated by converting the target truncated control vector according to the same seed as the transmitting device 100 and the receiving device 200 into the pseudo-random address generation logic, it outputs a binary sequence with pseudo-random characteristics under each shift clock trigger. The pseudo-random address generation logic drives the non-repeating address selection logic according to the binary sequence to generate an address arrangement sequence that covers all valid addresses of the two-dimensional block interleaved memory of the data link layer and is non-repeating, and converts the address arrangement sequence into the corresponding row address and column address.

[0185] When the candidate address obtained by the modulo operation is already occupied, the first unoccupied address is searched in the address increment direction as the output address for this time, thereby continuously generating the coordinate data that constitute the read address mapping table.

[0186] An interleaving matrix is ​​a two-dimensional coordinate index array used to guide read operations from the underlying memory. It internally records the shuffled sequence of physical memory read coordinates. The interleaving matrix is ​​a one-to-one mapping matrix, ensuring that each valid memory address in the data link layer two-dimensional block interleaved memory is accessed once and only once during a single interleaved read. When address conflicts exist in the candidate address sequence generated by the truncation control vector, the address generator searches for the first unoccupied address in the address incrementing direction as the corresponding output address, until a read address mapping table covering all valid addresses in the data link layer two-dimensional block interleaved memory without overlap is generated.

[0187] Since the generation of the interleaving matrix depends solely on the target truncation control vector used as the initialization benchmark, it achieves a deep binding association between the physical interleaving and shuffling mode and the truncation state of the front-end business data without introducing additional signaling overhead.

[0188] S503 performs two-dimensional bit permutation based on the interleaving matrix to output the interleaved bit stream.

[0189] The interleaving transmission module 105 uses an interleaving matrix to perform two-dimensional bit permutation on the uninterleaved payload blocks to generate an interleaved bit stream. Specifically, the interleaving transmission module 105 extracts data bits one by one from the memory array through the read port of the dual-port random access memory, according to the non-linear jump address order indicated by the interleaving matrix, i.e., the read address mapping table, so that the original continuous order of the uninterleaved payload blocks is rearranged. The rearranged data set is the interleaved bit stream.

[0190] The interleaved bitstream refers to a discrete bit sequence that disrupts the original parametric syntax association and continuous error correction check block structure. When the interleaved bitstream encounters a sudden deep fading in the physical channel, the originally continuous bit errors are dispersed into random bit errors after deinterleaving at the receiver, thus falling within the effective correction range of the forward error correction algorithm. The mathematical mapping of the above two-dimensional permutation readout relationship can be expressed as:

[0191] ;

[0192] In the formula, This represents the first bit in the generated interleaved bitstream. One output bit; The index for reading the clock sequence is a positive integer ranging from 1 to the total number of valid bits written to the data link layer two-dimensional block interleaving memory; A physical data array representing a two-dimensional block interleaving memory for the data link layer that stores uninterleaved payload blocks and their necessary padding bits; and These represent the outputs of the interleaving matrix operation, corresponding to the first... The physical row address and physical column address of the next read action are controlled by the pseudo-random sequence logic initialized by the target truncation control vector.

[0193] S504, with the addition of physical synchronization feature words, assembles the transmission frame and performs radio frequency transmission.

[0194] The interleaving transmission module 105 adds a fixed physical synchronization feature word to the front end of the interleaved bit stream after it is broken up to form a complete physical transmission frame. The complete physical transmission frame does not contain fields used to indicate truncation feature configuration files or truncation control vectors in plaintext.

[0195] To ensure that the remote receiving device can accurately capture the start boundary of the data frame in the continuous radio frequency waveform, the interleaving transmission module 105 hard-concatenates a known bit pattern with high autocorrelation characteristics (such as a Barker code sequence or an m-sequence of length 32 bits or 64 bits) at the start memory location of the interleaved bit stream, defining the known bit pattern as the physical synchronization feature word. The linear data structure after concatenation constitutes the complete physical transmission frame to be transmitted.

[0196] After completing the frame encapsulation in the digital domain, the interleaved transmission module 105 performs baseband modulation on the complete physical transmission frame and transmits it to the telemetry, tracking, and command (TT&C) channel. Specifically, the interleaved transmission module 105 performs phase or amplitude mapping on the complete physical transmission frame in the form of a symbol stream to complete baseband modulation. Then, it performs digital-to-analog conversion on the modulated digital signal, and performs up-conversion and power amplification on the converted analog signal before finally feeding it into the airborne antenna for transmission to the TT&C channel.

[0197] Regarding the specific constellation mapping rules for baseband modulation, the sampling and quantization logic for digital-to-analog conversion, and the physical hardware implementation of up-conversion and power amplification, those skilled in the art can refer to the well-known digital communication transmitter architecture for implementation. The specific waveform conversion and signal transmission hardware module construction are all well-known technologies in this field and will not be elaborated here.

[0198] See attached document Figure 7 In this embodiment, step S6 specifically includes the following sub-steps:

[0199] S601, locks the absolute physical boundary and extracts the link layer received payload sequence.

[0200] The receiving device 200 receives the physical transmission frame sent by the transmitting end through a spatial wireless channel. After adding a physical synchronization feature word to the front end of the interleaved bit stream, the transmitting end performs baseband modulation on the complete physical transmission frame and transmits it to the telemetry and control channel via up-conversion on the radio frequency link. The spatial wireless channel adds Doppler frequency shift and fading noise before transmitting the physical transmission frame to the receiving device 200.

[0201] In the specific physical implementation, the radio frequency antenna and front-end circuit of the receiving device 200 capture spatial electromagnetic waves and perform down-conversion and analog-to-digital conversion processing on the intercepted analog high-frequency electromagnetic waves to shift their frequency to the digital baseband processing range, thereby generating a digital baseband signal. Subsequently, the synchronization extraction module 201 receives and demodulates the digital baseband signal to obtain the received bit stream.

[0202] In order to accurately anchor data boundaries without setting a plaintext truncation mode indication field, the synchronization extraction module 201 uses a hardware correlator to search for physical synchronization feature words contained in the received bit stream, lock the physical frame start boundary, and extract the link layer received payload sequence.

[0203] During the search for the physical synchronization feature word by the hardware correlator, the hardware correlator uses the length of the physical synchronization feature word as the sliding window length and slides with a search step size of 1 bit or a fixed step size, calculating the Hamming distance matching degree between the data within the sliding window and the target reference code, i.e., the aforementioned physical synchronization feature word. When the calculated Hamming distance is less than or equal to a preset tolerance threshold, for example, the system can set the tolerance threshold to 0 or 1 bit, the hardware correlator locks the location of the physical synchronization feature word.

[0204] Using the location of the locked physical synchronization feature word, the synchronization extraction module 201 marks the physical frame start boundary and extracts the data segment corresponding to the preset physical frame length or the current physical layer capacity level as the link layer received payload sequence. The current physical layer capacity level is determined by the receiving device 200 based on the local physical layer state estimation result, fixed frame length configuration, or a link capacity level table consistent with the sending device 100. The link layer received payload sequence is the unordered data bit segment containing payload interleaving information that is extracted by the receiving end after stripping the physical boundary header.

[0205] S602 deploys a parallel hardware pipeline to perform reverse deinterleaving and stripping of checksums.

[0206] To parse the link layer received payload sequence after interleaving driven by an unknown truncation configuration, the parallel verification parsing module 202 pre-instantiates multiple independent parallel hardware pipelines inside the field-programmable gate array.

[0207] In practical deployment, the parallel verification and parsing module 202 instantiates multiple parallel hardware pipelines on the receiving device 200, corresponding to the number of truncation feature profiles. Each parallel hardware pipeline is assigned a valid local hypothesis control vector, which corresponds to a truncation feature profile state that may be adopted by the sending end.

[0208] When the data link layer receives the payload sequence, each parallel hardware pipeline performs reverse deinterleaving and rearrangement of the data link layer received payload sequence using a preset local hypothesis control vector. During reverse deinterleaving, each parallel hardware pipeline generates a local hypothesis interleaving matrix based on the corresponding local hypothesis control vector, and uses the coordinate mapping relationship of the local hypothesis interleaving matrix to perform address reverse rearrangement of the data link layer received payload sequence.

[0209] After address reversal, the disordered interleaved bit stream is restored into candidate uninterleaved payload blocks. Each candidate uninterleaved payload block consists of a logically continuous protected base codeword sequence, a protected extended codeword sequence, and necessary pre-set padding bits.

[0210] Subsequently, the forward error correction decoding logic within each parallel hardware pipeline determines the candidate boundaries of the protected basic codeword sequence and the protected extended codeword sequence based on the truncation feature configuration file associated with the corresponding local hypothetical control vector, and performs decoding operations on the protected basic codeword sequence and the protected extended codeword sequence using a forward error correction decoding algorithm matched with the transmitter to correct channel errors.

[0211] After decoding, each parallel hardware pipeline obtains a candidate basic check combination sequence and a candidate extended sequence. Based on the length constraint information in the truncation feature configuration file associated with the corresponding local hypothesis control vector, the reverse deinterleaving basic sequence and the receive check sequence are extracted from the candidate basic check combination sequence. The reverse deinterleaving basic sequence corresponds to the core contour data protected at the transmitting end, and the receive check sequence corresponds to the implicit check sequence calculated by the transmitting end.

[0212] S603 performs hardware XOR tests and parallel verification under a simultaneous clock sequence.

[0213] Since the receiver cannot directly know which pipeline uses parameters that match the actual state of the transmitter before decoding, the parallel verification and parsing module 202 uses all the legal local hypothesis control vectors stored locally to perform reverse memory address addressing restoration (i.e., the aforementioned reverse deinterleaving) and scrambling code XOR verification test on the link layer received payload sequence.

[0214] Driven by a unified global system clock tick, multiple parallel hardware pipelines synchronously execute verification calculations. Each pipeline hardware performs an XOR operation on the local hypothesis scrambling code sequence corresponding to the local hypothesis control vector and the inverse deinterleaved base sequence, and then performs a reverse verification test. The specific inverse XOR calculation relationship is represented as follows:

[0215] ;

[0216] In the formula, This represents the inverse XOR result polynomial generated in each pipeline at the receiving end; These are the basis variables for polynomial algebra operations; This represents the binary polynomial corresponding to the inverse deinterleaved basic sequence that has been decoded and recovered; This represents the binary polynomial corresponding to the local hypothesis scrambling sequence of the current pipeline. This indicates the bitwise XOR operator implemented by the underlying logic array.

[0217] After generating the inverse XOR result polynomial, each parallel hardware pipeline inputs it into the cyclic redundancy check shift logic and divides it by a fixed generator polynomial to calculate the corresponding trial check remainder. Subsequently, the parallel verification parsing module 202 compares the trial check remainders of each pipeline with the received check sequence in parallel.

[0218] Based on the matching results output by the hardware verification circuits of each pipeline, the parallel verification parsing module 202 selects the parallel hardware pipeline whose reverse verification test result, i.e., the trial verification remainder, is equal to the received verification sequence. Since the cyclic redundancy check sequence has sufficient length redundancy, for example, set to 32 bits, the probability of verification collisions caused by different truncation configurations is compressed to a negligible level, thereby ensuring the uniqueness of the matching result in a probabilistic sense.

[0219] When two or more parallel hardware pipelines match successfully at the same time, the parallel verification and parsing module 202 marks the current frame as an abnormal frame and discards it, or starts the preset second-level consistency verification rules. The second-level consistency verification rules include comparing whether the forward error correction decoding checksum of each matching pipeline is zero and whether the length of the base sequence, the length of the received check sequence, and the length of the extended sequence after decoding meet the length constraints predefined in the corresponding truncation feature configuration file.

[0220] Once a parallel hardware pipeline is successfully matched, it can be confirmed that the local hypothetical control vector corresponding to the successfully matched parallel hardware pipeline is the target truncation control vector actually used by the transmitter. This confirms that the reverse deinterleaving base sequence stripped from the parallel hardware pipeline is the global base sequence, and that the transmission of the global base sequence is error-free.

[0221] S604 completes the underlying data reconstruction and closes the loop for aviation telemetry and control services.

[0222] After locating the uniquely matching parallel hardware pipeline, the receiving device 200 begins to perform high-level semantic protocol restoration. Based on the target truncation feature configuration file corresponding to the equal parallel hardware pipeline, it determines the global extension sequence from the candidate extension sequences decoded by the parallel hardware pipeline, thus completing the reconstruction of the aviation telemetry and control data protocol.

[0223] During the specific protocol reconstruction execution, the receiving device 200 queries the truncation rules and field offset address table embedded in the target truncation feature configuration file corresponding to the equal parallel hardware pipeline. The truncation rules are used to indicate whether the extended bit sequence of each measurement and control parameter under the corresponding truncation feature configuration file is retained or removed. The field offset address table is used to record the starting position and length of the basic bit sequence and the retained extended bit sequence of each measurement and control parameter under the corresponding truncation feature configuration file in the candidate basic check combination sequence and candidate extended sequence after decoding, and to record the starting position and length of the padding bits in the candidate uninterleaved payload block.

[0224] According to the bit width and arrangement order of different parameters defined in the field offset address table, the receiving device 200 splits the candidate extended sequence after successful parallel hardware pipeline decoding a second time and extracts the global extended sequence that is indicated to be retained by the target truncated feature configuration file.

[0225] Simultaneously, the receiving device 200 restores the globally basic sequence and globally extended sequence output by the successfully matched parallel hardware pipeline into their respective independent data parameters according to the protocol specifications. Based on the parameter identifiers associated with each data tuple in the locally pre-configured measurement and control parameter set consistent with that of the transmitting device 100, the receiving device 200 maps the restored data parameters to the corresponding sensor channels. After data parameter type conversion and quantization, the receiving device 200 restores the binary bit segments to sensor parameters with clear physical quantization scales, such as specific temperature values ​​in degrees Celsius, pressure values ​​in Pascals, and navigation latitude and longitude coordinates, thereby completing the reverse parsing and reconstruction from the underlying physical bit stream to the upper-level aviation measurement and control data protocol.

[0226] When the sensor parameters reconstructed through reverse analysis are submitted to the ground station application layer or ground telemetry and control data processing computer via the underlying data bus, it marks the final completion of a highly reliable transmission loop in the air-to-ground two-way link for aviation telemetry and control.

[0227] To further illustrate the implementation process and technical effects of this invention, the following description is provided in conjunction with specific application scenarios and experimental data. The specific numerical values, scenario parameters, and comparative experiments described below are only used to explain the implementation principle of this invention and do not limit the scope of protection of this invention.

[0228] In practical application, the transmitting device 100 and the receiving device 200 operate in a highly dynamic aviation telemetry and control communication network environment. The configuration initialization module 101 acquires the raw telemetry data streams from each sensor node and pre-configures the telemetry and control parameter set. In this embodiment, the total number of currently activated telemetry and control parameters is set to 30, including 10 wing strain gauge parameters, 10 engine temperature sensor parameters, and 10 inertial navigation unit parameters.

[0229] The configuration initialization module 101 defines each measurement and control parameter in the measurement and control parameter set as a data tuple containing a parameter identifier, measurement and control priority, a basic bit sequence, and an extended bit sequence. The total data bit width of the original binary acquired value of each measurement and control parameter is set to 16 bits, and the truncation point is configured to 8. After performing a static stripping operation via bitwise truncation instructions, each measurement and control parameter is split into a fixed-length 8-bit basic bit sequence and a fixed-length 8-bit extended bit sequence.

[0230] Based on the importance of each parameter in the current telemetry and control mission to attitude calculation and flight control closed loop, the configuration initialization module 101 assigns a digital weight level to each telemetry and control parameter according to the priority of the telemetry and control: the digital weight level of 10 wing strain gauge parameters is set to 1; the digital weight level of 10 engine temperature sensor parameters is set to 2; and the digital weight level of 10 inertial navigation unit parameters is set to 3.

[0231] The configuration initialization module 101 predefines four truncation feature configuration files and statically maps them to a unique corresponding truncation control vector through a gate-level static addressing mapping logic array:

[0232] First configuration file: Indicates that the extended bit sequence of all measurement and control parameters be retained;

[0233] Second configuration file: Indicates that only the extended bit sequence corresponding to the measurement and control parameters with a digital weight level of 1 will be removed;

[0234] The third configuration file indicates the removal of the extended bit sequences corresponding to the measurement and control parameters with digital weight level 1 and digital weight level 2;

[0235] Fourth configuration file: Indicates the removal of the extended bit sequence of all measurement and control parameters.

[0236] The budget calculation module 102 acquires the physical layer signal-to-noise ratio (PNR) of the telemetry and control channel in real time (set to an input value of 4dB at the current moment) and the physical layer Doppler shift (set to an input value of 300Hz at the current moment). The budget calculation module 102 sends these input variables to the hardware state machine mapping function and outputs the corresponding maximum number of binary bits based on a pre-entered two-dimensional lookup table. The total effective payload bit budget obtained from the lookup table is set to 320 bits, and the link layer payload extraction length corresponding to the current physical layer capacity level is 1000 bits.

[0237] Simultaneously, the budget calculation module 102 calculates the total number of bits for full transmission: 30 measurement and control parameters, each measurement and control parameter's data tuple contains an 8-bit basic bit sequence and an 8-bit extended bit sequence, and the total number of bits for full transmission is 30 × (8 + 8) = 480 bits.

[0238] The truncation matching module 103 begins performing comparison and pattern matching operations. At this time, the total number of bits for full transmission is 480 bits. This is greater than the total payload bit budget of 320 bits, thus triggering truncation matching. The truncation matching module 103 performs pattern matching based on the payload occupancy length pre-recorded in each truncation feature configuration file. The first configuration file indicates that the extended bit sequence of all measurement and control parameters should be retained, and its corresponding payload occupancy length is 1176 bits, which exceeds the 1000-bit link layer payload extraction length corresponding to the current physical layer capacity setting. Therefore, the first configuration file does not meet the current capacity constraint.

[0239] Since the payload length of 1176 bits corresponding to the first configuration level is greater than the link layer payload extraction length of 1000 bits corresponding to the current physical layer capacity level, the truncation matching module 103 performs a rejection operation in ascending order of measurement and control priority. First, it rejects the extended bit sequence corresponding to the 10 wing strain gauge parameters with a digital weight level of 1, which corresponds to the second configuration level. At this time, the length of the rejected extended bit sequence is 10 × 8 = 80 bits, and the payload length of the second configuration level is 1056 bits, which is still greater than the link layer payload extraction length of 1000 bits corresponding to the current physical layer capacity level. Therefore, the second configuration level still does not meet the current capacity constraint.

[0240] The truncation matching module 103 continues to remove the extended bit sequences corresponding to the 10 engine temperature sensor parameters with a digital weight level of 2, corresponding to the third configuration. At this point, only the extended bit sequences of the inertial navigation unit parameters with a digital weight level of 3 are retained. The length of the extended bit sequences removed again is 10 × 8 = 80 bits, and the cumulative length of the removed extended bit sequences is 160 bits. The total data length after truncation is 480 - 160 = 320 bits, which is equal to the total effective payload bit budget of 320 bits. The payload occupancy length corresponding to the third configuration is 936 bits, which is less than the 1000-bit link layer payload extraction length corresponding to the current physical layer capacity level. Therefore, the third configuration meets the current capacity constraint.

[0241] The total data length of the truncated third configuration profile, 320 bits, is equal to the total bit budget of the effective payload, 320 bits. The payload occupancy length of 936 bits is less than the link layer payload extraction length of 1000 bits corresponding to the current physical layer capacity profile. Therefore, the truncation matching module 103 matches the third configuration profile that satisfies the total bit budget constraint of the effective payload among multiple truncation feature configuration profiles as the target truncation feature configuration profile, extracts a target truncation control vector corresponding to the third configuration profile, and outputs a global basic sequence (240 bits) generated by splicing together 30 basic bit sequences, and a global extended sequence (80 bits) generated by splicing together 10 retained extended bit sequences.

[0242] The encoding verification module 104 generates a target scrambling sequence using the target truncation control vector, and then performs an XOR operation between the target scrambling sequence and the global basic sequence. Based on the XOR result, it calculates and generates an implicit verification sequence with a length of 32 bits. Subsequently, the encoding verification module 104 performs forward error correction coding on the basic verification combination sequence at a first error correction code rate of 1 / 3 to generate a protected basic codeword sequence with a length of 816 bits; and performs forward error correction coding on the global extension sequence at a second error correction code rate of 2 / 3 to generate a protected extension codeword sequence with a length of 120 bits.

[0243] The total length of the protected basic codeword sequence and the protected extended codeword sequence is 936 bits. The encoding verification module 104 fills the end with 64 all-zero bits as preset padding bits and splices them together to form a fixed-length 1000-bit uninterrupted payload block.

[0244] The interleaving transmission module 105 uses the target truncation control vector as the initialization vector to generate an interleaving matrix, performs two-dimensional bit permutation on the uninterleaved payload block to generate an interleaved bit stream, adds physical synchronization feature words, and transmits it to the telemetry and control channel.

[0245] On the receiving device 200 side, the synchronization extraction module 201 locks the physical frame start boundary and extracts 1000 bits of the link layer received payload sequence. The parallel verification and parsing module 202 instantiates four parallel hardware pipelines corresponding to the number of 4 truncation feature configuration files. Each parallel hardware pipeline independently performs reverse deinterleaving arrangement using a preset local hypothesis control vector to obtain candidate uninterleaved payload blocks, and performs forward error correction decoding on the protected basic codeword sequence and protected extended codeword sequence. Then, it separates the reverse deinterleaved basic sequence and the received verification sequence.

[0246] Each parallel hardware pipeline performs an XOR operation on the local hypothesis scrambling sequence corresponding to the local hypothesis control vector and the inverse deinterleaving base sequence, and then performs a reverse verification test. Based on the matching results output by the hardware verification circuits of each pipeline, only the parallel hardware pipeline with the local hypothesis control vector preset to the third configuration file has a reverse verification test result that is completely equal to the received verification sequence.

[0247] The parallel verification and parsing module 202 selects the equal parallel hardware pipeline, confirms that the global basic sequence transmission is correct, and extracts the global extended sequence according to the field offset address table recorded in the target truncation feature configuration file corresponding to the parallel hardware pipeline, thus completing the reverse parsing and reconstruction of the underlying physical bit stream to the upper-level aviation telemetry and control data protocol.

[0248] Experimental verification and effect comparison:

[0249] To verify the actual transmission performance and reliability of the data transmission method used in aviation telemetry and control, a semi-physical simulation platform for digital baseband communication was built and experimental comparisons were performed. Two other existing technologies were selected as benchmarking methods, with the specific settings as follows:

[0250] Traditional fixed-rate method: This method does not perform the stripping and pruning of the base and extension bits of the measurement and control parameters. All measurement and control parameters are transmitted as a single data block using a fixed frame structure and a uniformly set 1 / 2 error correction rate.

[0251] Traditional explicit signaling methods support parameter truncation, but use an independent 8-bit plaintext signaling field, not protected by differentiated bitrates, placed in the data frame header to indicate the truncation mode. The plaintext signaling field and service data are transmitted using the same 2 / 3 error correction bitrate.

[0252] The physical layer Doppler shift of the telemetry, tracking, and command (TT&C) channel is set to a continuous fast fading state. Three fixed conditions are sequentially set for the physical layer signal-to-noise ratio: 10dB (good channel environment), 6dB (normal channel environment), and 2dB (poor channel environment). Under each condition, 10,000 physical transmission frames are continuously transmitted using each of the three methods. Two quantitative indicators are statistically analyzed: the core basic parameter delivery rate (the probability that the receiver correctly reconstructs the basic bit sequence in the TT&C parameters); and the effective data net throughput ratio, which is the normalized ratio of the amount of effective service data successfully recovered and submitted to the application layer by the receiver after removing fixed synchronization overhead, forward error correction redundancy, and padding bits, relative to the theoretically submittable effective service data amount under the current channel conditions.

[0253] The statistical data results are as follows:

[0254] Under a physical layer signal-to-noise ratio of 10dB, the channel carrying capacity is sufficient. The effective net data throughput of the traditional fixed code rate method is 85.2%; the effective net data throughput of the traditional explicit signaling method drops to 82.4% due to the fixed overhead of the plaintext signaling field; the effective net data throughput of the method of this invention is 85.1%. The delivery rate of the core basic parameters of all three methods remains at 99.9%.

[0255] Under a physical layer signal-to-noise ratio of 6dB, the delivery rate of core basic parameters of the traditional fixed code rate method drops to 90.2%; the delivery rate of core basic parameters of the traditional explicit signaling method is 92.1%; the method of the present invention maintains the delivery rate of core basic parameters at 99.8% by applying a first error correction code rate protection to the global basic sequence.

[0256] Under a physical layer signal-to-noise ratio of 2dB, the underlying physical channel enters deep fading, and the total bit budget of the effective payload is drastically reduced. Traditional fixed-rate methods, due to the continuous exceeding of capacity constraints by the underlying physical frames, render the fixed 1 / 2 error correction rate completely ineffective, resulting in a large number of frame verification failures and discarding. This causes the core basic parameter delivery rate to plummet to 41.3%, and the effective data net throughput ratio to drop to 32.1%. Traditional explicit signaling methods, because the plaintext signaling field in the header is only protected with the second error correction rate uniformly with the service data, and does not employ high-redundancy differentiated protection for the basic data, are more prone to bit flipping under poor channel conditions. Once a signaling indication error causes misalignment at the receiver, all subsequent data parsing fails, and the core basic parameter delivery rate is only 68.7%, with the effective data net throughput ratio dropping to 45.2%. In contrast, the core basic parameter delivery rate of the method of this invention remains at a relatively high level of 99.6%, and the effective data net throughput ratio is maintained at 84.5%.

[0257] Experimental data shows that this invention can accurately remove minor extended bit sequences when the total bit budget of the effective payload is exceeded. By combining implicit check sequence generation with parallel verification and parsing logic at the receiving end, it avoids the risk of format misjudgment caused by single-point errors in plaintext truncation mode signaling fields, and ensures reliable reconstruction of core basic parameters of aviation telemetry and control in extremely harsh physical channel environments.

[0258] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A data transmission method for aviation telemetry and control, characterized in that, Includes the following steps: The measurement and control parameters are divided into basic bit sequences and extended bit sequences, and multiple truncation feature configuration files are mapped to truncation control vectors respectively; Calculate the total bit budget of the payload and the total number of bits for full transmission based on the physical layer channel state; When the total number of bits in the full transmission is greater than the total bit budget of the payload, the extended bit sequence is removed, the target truncation feature configuration file is matched and the corresponding target truncation control vector is extracted, and the global basic sequence and the global extended sequence are spliced ​​together to generate the global basic sequence and the global extended sequence. An implicit verification sequence is generated using the target truncated control vector and the global basic sequence, and forward error correction coding is performed to assemble the uninterleaved payload block; The interleaving matrix is ​​generated using the target truncation control vector to interleave and scramble the uninterleaved payload block, and a physical synchronization feature word is added before transmission. Extract the received payload sequence from the link layer, and perform reverse deinterleaving and reverse verification tests using a preset local hypothesis control vector in multiple parallel hardware pipelines. Select the successfully matched parallel hardware pipeline to complete the reconstruction of the aviation telemetry and control data protocol.

2. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The step of dividing the measurement and control parameters into a basic bit sequence and an extended bit sequence, and mapping multiple truncated feature configuration files to truncated control vectors respectively includes: The measurement and control parameters are defined as data tuples containing an identifier, a priority, the basic bit sequence, and the extended bit sequence; wherein, the basic bit sequence and the extended bit sequence are obtained by statically stripping the original acquired values ​​corresponding to the measurement and control parameters by performing bitwise truncation instructions. Each of the aforementioned truncation feature configuration files specifies a set of fixed truncation combination modes for the measurement and control parameters; The index number of the truncation feature configuration file is input into the gate-level static addressing mapping logic array, and a preset binary pseudo-random sequence is output as the truncation control vector.

3. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The steps for calculating the total bit budget of the payload and the total number of bits for full transmission based on the physical layer channel state include: The physical layer signal-to-noise ratio and Doppler frequency shift are extracted as the physical layer channel state input hardware state machine mapping function, and the maximum number of bits is output through a two-dimensional lookup table as the total bit budget of the effective payload. The total number of bits in the full transmission is obtained by summing the lengths of the basic bit sequence and the extended bit sequence of all the measurement and control parameters.

4. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The steps of discarding the extended bit sequence when the total number of bits in the full transmission is greater than the total bit budget of the effective payload, matching the target truncation feature configuration file and extracting the corresponding target truncation control vector, and concatenating them to generate the global basic sequence and the global extended sequence include: The measurement and control parameters are arranged in ascending order according to the preset measurement and control priority, and the lowest priority extended bit sequence is marked and removed one by one, and the dynamic remaining length variable is reduced accordingly. When the dynamic remaining length variable is not greater than the total bit budget of the effective payload, the elimination stops, and a temporary truncation decision set is obtained. Find a fixed truncation combination mode that covers the temporary truncation decision set, the total data length after truncation does not exceed the total bit budget of the effective payload, the payload occupancy length does not exceed the link layer payload extraction length corresponding to the current physical layer capacity level, and the amount of data discarded is the least, and use the corresponding truncation feature configuration file as the target truncation feature configuration file to extract the target truncation control vector; The retained basic bit sequence and the extended bit sequence are concatenated to form the global basic sequence and the global extended sequence, respectively.

5. The data transmission method for aviation telemetry and control according to claim 4, characterized in that, The step of concatenating the retained basic bit sequence and the extended bit sequence into the global basic sequence and the global extended sequence respectively includes: According to the indication rules of the target truncation feature configuration file, the basic bit sequence in the measurement and control parameters is shifted into the first group of shift register chains and packaged into the global basic sequence; The retained extended bit sequence is shifted into the second set of shift register chains and packaged into the global extended sequence.

6. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The step of generating an implicit verification sequence using the target truncated control vector and the global basic sequence, and performing forward error correction coding to assemble the uninterleaved payload block includes: The target truncation control vector is input into a linear feedback shift register to perform polynomial operations, generating a target scrambling sequence; The target scrambling sequence is added modulo 2 to the global basic sequence, and the remainder segment is obtained by cyclic redundancy check shift division as the implicit check sequence. Forward error correction coding is performed on the basic parity combination sequence composed of the global basic sequence and the implicit parity sequence at the first error correction code rate to generate a protected basic codeword sequence; Perform forward error correction coding on the global extended sequence according to the second error correction code rate to generate a protected extended codeword sequence; The protected base codeword sequence, the protected extended codeword sequence, and the preset padding bits are assembled into the uninterleaved payload block.

7. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The steps of generating an interleaving matrix using the target truncation control vector to interleave and scramble the uninterleaved payload block, attaching physical synchronization feature words, and transmitting include: Write the uninterleaved load block into a two-dimensional block interleaved memory; The pseudo-random address generation logic is activated using the target truncation control vector to generate a read address mapping table as the interleaving matrix. Data is extracted from the two-dimensional block interleaving memory according to the non-linear jump address of the interleaving matrix and rearranged into an interleaved bit stream; A high autocorrelation bit pattern is spliced ​​at the beginning of the interleaved bit stream as the physical synchronization feature word to form a physical transmission frame and transmit it.

8. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The step of extracting the link layer received payload sequence includes: The Hamming distance between the sliding window data and the physical synchronization feature word is calculated using a hardware correlator. If the distance is not greater than a preset tolerance threshold, the position is locked and the physical frame start boundary is marked. Extract the data segment of the length corresponding to the current physical layer capacity level and use it as the received payload sequence of the link layer.

9. The data transmission method for aviation telemetry and control according to claim 1, characterized in that, The steps of performing reverse deinterleaving and reverse verification tests using preset local hypothesis control vectors in multiple parallel hardware pipelines, and selecting the successfully matched parallel hardware pipeline to complete the reconstruction of the aviation telemetry and control data protocol include: Each of the parallel hardware pipelines generates a reverse deinterleaving address sequence according to the allocated local hypothesis control vector, and performs reverse rearrangement of the link layer received payload sequence according to the reverse deinterleaving address sequence; Forward error correction decoding is performed on the reverse rearranged link layer received payload sequence to obtain candidate basic check combination sequence and candidate extended sequence; The reverse deinterleaved base sequence and the received check sequence are stripped from the candidate basic check combination sequence; The inverse deinterleaving base sequence is XORed with the local hypothesis scrambling sequence generated by the local hypothesis control vector to generate an inverse XOR result polynomial, and a cyclic redundancy check shift division is performed on the inverse XOR result polynomial to obtain a trial check remainder. By comparing the trial verification remainder with the received verification sequence, and using the field offset address table embedded in the truncation feature configuration file corresponding to the parallel hardware pipeline with the same comparison result, the global extended sequence is extracted from the candidate extended sequence to complete the reconstruction of the aviation telemetry and control data protocol.

10. A data transmission system for aviation telemetry and control, comprising the data transmission method for aviation telemetry and control as described in any one of claims 1 to 9, characterized in that, The system includes: Configure the initialization module to divide the measurement and control parameters into basic bit sequences and extended bit sequences, and map multiple truncation feature configuration files to the truncation control vector respectively; The budget calculation module is configured to calculate the total payload bit budget and the total number of bits for full transmission based on the physical layer channel state. The truncation matching module is configured to remove the extended bit sequence when the total number of bits in the full transmission is greater than the total bit budget of the payload, match the target truncation feature configuration file and extract the corresponding target truncation control vector, and splice them to generate a global basic sequence and a global extended sequence. The encoding verification module is configured to generate an implicit verification sequence using the target truncated control vector and the global basic sequence, and perform forward error correction encoding to assemble the uninterrupted payload block. An interleaved transmission module is configured to use the target truncation control vector to generate an interleaved matrix to interleave and scramble the uninterleaved payload block, attach physical synchronization feature words, and then transmit. The synchronous extraction module and the parallel verification and parsing module are configured to extract the received payload sequence at the link layer. In multiple parallel hardware pipelines, reverse deinterleaving and reverse verification tests are performed using a preset local hypothesis control vector. The selected parallel hardware pipeline that successfully matches the data completes the reconstruction of the aviation telemetry and control data protocol.

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