Display device and electronic device

Abstract

A display device and an electronic device according to the present application include a display panel including a pad area, a plurality of pads disposed in the pad area, aligned in a first direction, and each pad extending in a diagonal direction inclined at a first angle with respect to a second direction crossing the first direction, and an inspection pattern extending in the diagonal direction and corresponding to at least a portion of the plurality of pads.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2025-0020992, filed on February 18, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices and electronic devices, and more specifically, to display devices and electronic devices, each having improved reliability. Background Technology

[0004] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablet computers, include display panels that display images. Various display panels, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, electrowetting display panels, and electrophoretic display panels, are being developed as display panels.

[0005] The display device includes a display area that is activated in response to an electrical signal. The display device can detect input applied from the outside through the display area, and the display device can also display various images to provide information to the user.

[0006] The display device includes a display panel and a circuit board. The display panel can be connected to the motherboard via the circuit board. A driver chip can be mounted on the display panel. The driver chip can be electrically connected to the display panel via pads located in the non-display area of ​​the display panel. Summary of the Invention

[0007] This disclosure provides display devices and electronic devices, each capable of checking whether pads are arranged.

[0008] An embodiment of the present invention provides a display device comprising: a display panel including a pad area; a plurality of pads disposed in the pad area, aligned in a first direction, and each pad extending in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; and an inspection pattern extending in the diagonal direction and corresponding to at least a portion of the plurality of pads.

[0009] In an embodiment of the present invention, the display device includes: a display panel including a pad area; a plurality of pads disposed in the pad area, aligned in a first direction, and each pad extending in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; a sub-pattern electrically connected to at least a portion of the plurality of pads and extending in the diagonal direction corresponding to said at least a portion of the plurality of pads; and an insulating layer disposed on the plurality of pads and the sub-pattern. The plurality of pads may be exposed through openings defined in the insulating layer.

[0010] In an embodiment of the present invention, the electronic device includes: a display panel including a pad area; a plurality of pads disposed in the pad area, aligned in a first direction, and each pad extending in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; an inspection pattern extending in the diagonal direction and corresponding to at least a portion of the plurality of pads; and a printed circuit board including a plurality of connection pads and electrically connected to the display panel via the plurality of connection pads. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings: Figure 1A This is a block diagram of an electronic device according to an embodiment of the present invention; Figures 1B to 1D Each is a perspective view of an electronic device according to an embodiment of the concept of the present invention; Figure 2 This is a perspective view of an electronic device according to an embodiment of the present invention; Figure 3 This is an exploded perspective view of an electronic device according to an embodiment of the present invention; Figure 4A and Figure 4B This is a plan view of a display device according to an embodiment of the present invention; Figure 5 This is a cross-sectional view of a display module according to an embodiment of the present invention; Figure 6 yes Figure 4A An enlarged view of region AA' shown in the image; Figure 7 It is along Figure 6 The sectional view shown is taken by line I-I'. Figure 8 This is a cross-sectional view of a portion of an electronic device according to an embodiment of the present invention. Figure 9This is a view showing a portion of the display panel DPa according to an embodiment of the present invention; and Figure 10 This is a view showing a portion of the display panel DP according to an embodiment of the present invention. Detailed Implementation

[0012] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "attached to" another element, it may be directly disposed on, directly connected to, or directly attached to the other element, or other elements may be disposed between the element and the other element.

[0013] Throughout the text, the same reference numerals denote the same elements. In the accompanying drawings, the thickness, scale, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0014] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. For example, without departing from the scope of the inventive concept, the first element, first component, first region, first layer, or first segment discussed below may be referred to as a second element, second component, second region, second layer, or second segment. Similarly, a second element, second component, second region, second layer, or second segment may be referred to as a first element, first component, first region, first layer, or first segment. In this specification, unless the context clearly indicates otherwise, the singular expressions “a,” “an,” and “the” are intended to also include the plural forms.

[0015] In some respects, the terms "below," "on the lower side," "above," "on the upper side," etc., are used to describe the relationship between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0016] It will also be understood that the terms “comprising,” “including,” “having,” and / or “including,” “containing,” “having,” as used in this specification, designate the presence of stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof.

[0017] Given the measurements discussed and the errors associated with the measurement of a particular quantity, the terms “about” or “approximately” as used herein include the value and include a suitable range of deviations from the particular value as determined by one of ordinary skill in the art. For example, the terms “about” or “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0018] The term "substantially" as used in this document means approximately or actually. The term "substantially equal" means approximately equal or actually equal. The term "substantially identical" means approximately identical or actually identical. The term "substantially perpendicular" means approximately perpendicular or actually perpendicular. The term "substantially parallel" means approximately parallel or actually parallel.

[0019] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized sense unless expressly so defined herein.

[0020] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0021] Figure 1A This is a block diagram of an electronic device according to an embodiment of the present invention. Figures 1B to 1D Each is a perspective view of an electronic device according to an embodiment of the present invention.

[0022] An electronic device ED according to an embodiment of the present invention includes a display device DD (see...) Figure 3 The electronic device ED according to an embodiment of the present invention can be as follows: Figure 2 The mobile phones shown are not limited to these.

[0023] like Figure 1A As shown, the electronic device ED outputs various information through the display module 140 in the operating system. In an example where the processor 110 runs an application stored in the memory 120, the display module 140 provides application information to the user through the display panel 141.

[0024] Processor 110 receives external input via input module 130 or sensor module 161 and runs the application corresponding to the external input. In the example where the user selects the camera icon displayed on display panel 141, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image via display panel 141.

[0025] As another example, when personal information authentication is performed in display module 140, fingerprint sensor 161-1 obtains the input fingerprint information as input data. Processor 110 compares the input data obtained by fingerprint sensor 161-1 with the authentication data stored in memory 120, and runs the application based on the comparison result. Display module 140 can display information based on the logic of the application through display panel 141.

[0026] As another example, when a music stream icon displayed on display module 140 is selected, processor 110 receives user input via input sensor 161-2 and activates the music stream application stored in memory 120. In the example where a music playback command is input to the music stream application, processor 110 activates sound output module 163 and provides the user with sound information corresponding to the music playback command.

[0027] The operation of the electronic device ED has been briefly described above. The components of the electronic device ED will be described in detail below. Among the components of the electronic device ED described later, some components may be integrally formed into one component, and a component may be divided into two or more components.

[0028] refer to Figure 1A The electronic device ED can communicate with the external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to embodiments, the electronic device ED may include a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, a built-in module 160, and an external module 170. According to embodiments, at least one of the aforementioned components may be omitted from the electronic device ED, or one or more other components may be added. According to embodiments, some of the aforementioned components (e.g., sensor module 161, antenna module 162, or audio output module 163) may be integrated into another component (e.g., display module 140).

[0029] The processor 110 can run software to control at least one other component (e.g., hardware or software component) connected to the electronic device ED, and can perform various data processing or calculations. According to an embodiment, as at least part of the data processing or calculation, the processor 110 can store commands or data received from other components (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121, process the commands or data stored in volatile memory 121, and store the resulting data in non-volatile memory 122.

[0030] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include one or more of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural processing unit (NPU) 111-3. Neural processing unit 111-3 may be a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be one or a combination of two or more of the following: deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), and deep Q-networks, but are not limited to the examples above. In addition to the hardware architecture, the artificial intelligence model may additionally or optionally include a software architecture. At least two of the aforementioned processing units and processors can be implemented as an integrated component (e.g., a single chip), or the aforementioned processing units and processors can be implemented as independent components (e.g., multiple chips).

[0031] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include an interface conversion circuit and a timing control circuit. The controller 112-1 receives image signals from the main processor 111 and outputs image data obtained by converting the data format of the image signals to make the image data suitable for the interface specifications with the display module 140. The controller 112-1 may output various control signals that support driving the display module 140.

[0032] The auxiliary processor 112 may also include a data conversion circuit 112-2, a gamma correction circuit 112-3, and a rendering circuit 112-4. The data conversion circuit 112-2 can receive image data from the controller 112-1 and can compensate the image data to display the image at a brightness desired according to the characteristics of the electronic device ED or a user-defined brightness, or it can convert the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 112-3 can convert image data, gamma reference voltage, etc., so that the image displayed on the electronic device ED has the desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller 112-1 and render the image data taking into account the pixel arrangement of the display panel 141 applied to the electronic device ED. At least one of the data conversion circuit 112-2, gamma correction circuit 112-3, and rendering circuit 112-4 can be integrated into another component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver 143, which will be described later.

[0033] The memory 120 may store various data used by at least one component of the electronic device ED (e.g., processor 110 or sensor module 161), as well as input or output data for related commands. The memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0034] The input module 130 can receive commands or data from outside the electronic device ED (e.g., from a user or external electronic device 102) to be used by components of the electronic device ED (e.g., processor 110, sensor module 161, or sound output module 163).

[0035] Input module 130 may include a first input module 131 and a second input module 132. Commands or data are input from the user to the first input module 131, and commands or data are input from an external electronic device 102 to the second input module 132. The first input module 131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol that allows wired or wireless connection to the external electronic device 102. According to embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 132 may include a connector that can be physically connected to the external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0036] Display module 140 provides information to the user visually. Display module 140 may include display panel 141, scan driver 142, and data driver 143. Display module 140 may also include a window, housing, or bracket for protecting display panel 141.

[0037] The display panel 141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and there is no particular limitation on the type of display panel 141. The display panel 141 may be a rigid type or a flexible type that can be rolled or folded. The display module 140 may also include a support member, bracket, heat dissipation component, etc., that supports the display panel 141.

[0038] The scan driver 142 can be mounted as a driver chip on the display panel 141. Alternatively, the scan driver 142 can be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon thin-film transistor (TFT) gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) embedded in the display panel 141. The scan driver 142 receives a control signal from the controller 112-1 and outputs a scan signal to the display panel 141 in response to the control signal.

[0039] The display panel 141 may also include a transmit driver. The transmit driver outputs a transmit control signal to the display panel 141 in response to a control signal received from the controller 112-1. The transmit driver may be separate from the scan driver 142 or integrated into the scan driver 142.

[0040] The data driver 143 receives a control signal from the controller 112-1 and converts the image data into an analog voltage (e.g., a data voltage) in response to the control signal, and then outputs the data voltage to the display panel 141.

[0041] The data driver 143 can be integrated into other components (e.g., controller 112-1). The functions of the interface conversion circuitry and timing control circuitry of controller 112-1 described herein can be integrated into the data driver 143.

[0042] The display module 140 may also include a transmitter driver, a voltage generation circuit, etc. The voltage generation circuit can output various voltages that support driving the display panel 141.

[0043] Power module 150 supplies power to components of electronic device ED. Power module 150 may include a battery charged with electrical voltage. The battery may include a non-rechargeable primary battery, a rechargeable rechargeable battery, or a fuel cell, etc. Power module 150 may include a power management integrated circuit (PMIC). The PMIC provides optimized power to each of the modules described herein and those described later. Power module 150 may include wireless power transmission / reception components electrically connected to the battery. The wireless power transmission / reception components may include multiple antenna radiators in the form of coils.

[0044] The electronic device ED may also include a built-in module 160 and an external module 170. The built-in module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0045] Sensor module 161 can detect input made by the user's body or by the pen of the first input module 131, and can generate an electrical signal or data value corresponding to the input. Sensor module 161 may include at least one of fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3.

[0046] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0047] Input sensor 161-2 can generate data values ​​corresponding to the coordinate information of input made by the user's body or by a pen. Input sensor 161-2 generates capacitance changes caused by the input as data values. Input sensor 161-2 can detect input made by a passive pen, or can transmit data to or receive data from an active pen.

[0048] Input sensor 161-2 can measure biosignals such as blood pressure, water content, or body fat. In an example where a user touches the sensor layer or sensing panel with a part of their body and does not move it for a certain period of time, input sensor 161-2 can detect biosignals based on changes in the electric field caused by the body part and output the information desired by the user to display module 140.

[0049] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information of input made by a pen. The digitizer 161-3 generates electromagnetic changes caused by the input as data values. The digitizer 161-3 can detect input made by a passive pen, or transmit data to or receive data from an active pen.

[0050] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be configured as a sensor layer formed on the display panel 141 by a continuous process. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed above the display panel 141. In another embodiment, one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed below the display panel 141.

[0051] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrated into a single sensing panel using the same process. In an example where at least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel 141 and a window positioned above the display panel 141. According to an embodiment, the sensing panel can be positioned on the window, and the position of the sensing panel is not particularly limited.

[0052] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be built into the display panel 141. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 141.

[0053] In some respects, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device ED. Sensor module 161 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biosensors, temperature sensors, humidity sensors, or illuminance sensors.

[0054] Antenna module 162 may include at least one antenna for transmitting or receiving signals or power to or from an external source. According to an embodiment, communication module 173 may transmit or receive signals from external electronic device 102 via an antenna suitable for a communication method. The antenna pattern of antenna module 162 may be integrated into a component of display module 140 (e.g., display panel 141), input sensors 161-2, etc.

[0055] The sound output module 163 may be a means for outputting sound signals to the external electronic device ED, and may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver for receiving calls only. Depending on the embodiment, the receiver may be integrally formed with or separate from the speaker. The sound output mode of the sound output module 163 may be integrated into the display module 140.

[0056] Camera module 171 can capture still images or moving images. According to embodiments, camera module 171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 171 may also include an infrared camera capable of measuring the presence / absence of a user, the user's position, the user's gaze, etc.

[0057] The light module 172 can provide light. The light module 172 may include a light-emitting diode or a xenon lamp. The light module 172 can operate together with the camera module 171 or operate independently.

[0058] Communication module 173 can establish a wired or wireless communication channel between electronic device ED and external electronic device 102, and support communication through the established communication channel. Communication module 173 may include one or all of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a Local Area Network (LAN) communication module or a power line communication module. Communication module 173 can communicate with external electronic device 102 via a short-range communication network such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a WAN). The various types of communication modules 173 described above can be implemented as a single chip or separately as individual chips.

[0059] Input module 130, sensor module 161, camera module 171, etc. can be used together with processor 110 to control the operation of display module 140.

[0060] The processor 110 outputs commands or data to the display module 140, the sound output module 163, the camera module 171, or the optical module 172 based on input data received from the input module 130. For example, the processor 110 may generate image data in response to input data input via a mouse, active pen, etc., and output the image data to the display module 140, or it may generate command data in response to input data and output the command data to the camera module 171 or the optical module 172. In an example where no input data is received from the input module 130 within a predetermined time period, the processor 110 may switch the operating mode of the electronic device ED to a low-power mode or a sleep mode, thereby reducing the power consumed by the electronic device ED.

[0061] Processor 110 outputs commands or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can compare authentication data input by fingerprint sensor 161-1 with authentication data stored in memory 120, and then run an application based on the comparison result. Processor 110 can run commands or output corresponding image data to display module 140 based on sensing data detected by input sensor 161-2 or digitizer 161-3. In an example where sensor module 161 includes a temperature sensor, processor 110 can receive temperature data for the measured temperature from sensor module 161, and also perform brightness correction, etc., on image data based on the temperature data.

[0062] Processor 110 can receive measurement data from camera module 171 regarding the presence / absence of a user, the user's location, and the user's gaze. Processor 110 can also perform brightness correction and other functions on image data based on the measurement data. For example, processor 110, having determined the presence / absence of a user through input from camera module 171, can output brightness-corrected image data to display module 140 via data conversion circuit 112-2 or gamma correction circuit 112-3.

[0063] Some of the aforementioned components can be connected to each other and exchange signals (e.g., commands or data) via communication methods used between peripheral devices (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) links). Processor 110 can communicate with display module 140 through a designated interface. For example, one of the aforementioned communication methods can be used, and the communication methods are not limited to those described above.

[0064] The electronic device ED according to the various embodiments described herein can be of various types. The electronic device ED may include at least one of, for example, portable communication devices (e.g., smartphones), tablet devices, portable multimedia devices, wearable devices, and home appliances. The electronic device ED according to the embodiments herein is not limited to the devices described above. Figure 1B The AR glasses shown Figure 1C The various types of in-vehicle information devices shown and Figure 1D The smartwatch shown can be implemented as an electronic device ED according to an embodiment of the present invention.

[0065] Figure 2 This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 3 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0066] An electronic device (ED) can be a device activated in response to an electrical signal. An electronic device (ED) can include various implementations. For example, an electronic device (ED) can be applied to electronic devices such as mobile phones, smartwatches, tablet computers, laptop computers, computers, or smart TVs. The display device according to the present invention is not limited to the examples described above, and unless departing from the inventive concept, the display device according to the present invention can be used as another electronic device. In this embodiment, a mobile phone is shown as an example of an electronic device (ED).

[0067] The electronic device ED can display an image IM on a display surface FS parallel to each of the first direction DR1 and the second direction DR2, facing a third direction DR3. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include not only moving images but also still images. Figure 2 In the image, a clock window and icons are shown as examples of IM.

[0068] In this embodiment, the front (or top) and rear (or bottom) surfaces of each component are defined based on the orientation of the displayed image IM. The front and rear surfaces may be opposite each other in a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. The spacing between the front and rear surfaces in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. The term "in a plane" as used herein may refer to the state when viewed in the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions.

[0069] The electronic device (ED) can detect external input applied from the outside. External input can include various types of input provided from outside the electronic device (ED). For example, external input can include not only touch made by a part of the body (such as a user's hand), but also external input applied by approaching or being adjacent to the electronic device (ED) at a distance (e.g., hovering). In some aspects, external input can include various types of input such as force, pressure, temperature, and light.

[0070] An electronic device ED may include a window (WM) and a housing (HU). The window (WM) and housing (HU) may be joined to form the appearance of the electronic device ED.

[0071] The window WM can be divided into a transmission area TA and a frame area BZA. The front surface of the electronic device ED can correspond to the transmission area TA and the frame area BZA of the window WM.

[0072] The transmissive region TA can be the area on which the image IM is displayed. The transmissive region TA can be an optically transparent area. The user can see the image IM through the transmissive region TA.

[0073] In this embodiment, the transmission region TA is shown in a rectangular shape with rounded vertices. However, this is shown as an example, and the transmission region TA can have various shapes and is not limited to any one embodiment.

[0074] Compared to the transmissive region TA, the border region BZA can be a region with relatively low light transmittance. For example, the border region BZA can be set as an area on which a material of a certain color is printed.

[0075] The border region BZA can be a region adjacent to the transmission region TA. The border region BZA can surround the transmission region TA. Therefore, the shape of the transmission region TA can be substantially defined by the border region BZA. However, this is shown as an example, and the border region BZA can be arranged adjacent to one side of the transmission region TA, or it can be omitted.

[0076] refer to Figure 2 and Figure 3 The electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing HU. Figure 3 An electronic device ED is briefly shown, and the electronic device ED may also include a mechanical structure (e.g., a hinge) for controlling the operation (e.g., folding or rolling) of the display device DD.

[0077] The display device DD includes a window WM, a display module DM, a lower component LM, a driver chip DIC, and a printed circuit board PCB. The display module DM may include a display panel DP and an input sensing layer ISL.

[0078] A window (WM) can be installed on the display module (DM). The window protects the display module (DM). The window can include optically transparent materials, such as glass, sapphire, or plastic. Images from the display module (DM) can be displayed to the user through the window.

[0079] Window WMs can have a single-layer or multi-layer structure. For example, a window WM can include multiple plastic films connected to each other or a glass substrate and plastic films connected to each other.

[0080] The display module DM may include a front surface IS comprising an active area AA and a peripheral area NAA. The active area AA may be an area activated in response to an electrical signal. In this embodiment, the active area AA may be an area on which an image IM is displayed, and may also be an area through which external input is detected.

[0081] The transmission region TA may overlap with at least a portion of the effective region AA. Therefore, a user can see the image IM through the transmission region TA or detect external input through the transmission region TA. However, this is shown as an example, and the area on which the image IM is displayed and the area through which external input is detected may be separated from each other within the effective region AA, and is not limited to any one implementation.

[0082] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA can surround the active region AA. The driving circuit, driving lines, etc. used to drive the active region AA can be set in the peripheral region NAA.

[0083] The display panel DP according to embodiments of the present invention can be a liquid crystal display panel or an emitting display panel, but is not particularly limited thereto. For example, the emitting display panel can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc.

[0084] Display panel DP can be flexible. The term "flexible" indicates the property of being able to bend and can include all structures from fully foldable structures to structures that can be partially bent. For example, display panel DP can be a curved display panel or a foldable display panel. However, display panel DP is not limited to this, and display panel DP can also be rigid.

[0085] The input sensing layer (ISL) can be set on the display panel (DP). For example... Figure 3As shown, the input sensing layer ISL can be directly disposed on the display panel DP. That is, the input sensing layer ISL can be disposed on the display panel DP through a continuous process, and the adhesive film may not be disposed between the input sensing layer ISL and the display panel DP. However, embodiments of this disclosure are not limited to this, and the adhesive film may be disposed between the input sensing layer ISL and the display panel DP. The input sensing layer ISL can be manufactured with the display panel DP through a separate process, and then fixed to the top surface of the display panel DP by the adhesive film.

[0086] The Input Sensing Layer (ISL) can detect external inputs applied from the outside. As described herein, the Input Sensing Layer (ISL) can detect external inputs provided on a window (WM).

[0087] The printed circuit board (PCB) can be mounted on one side of the display panel (DP). The PCB may include a connection circuit board (CF) and a main circuit board (MB).

[0088] The connection circuit board CF can connect the display panel DP to the main circuit board MB. The connection circuit board CF can be powered on and connected to the display panel DP from the side adjacent to it. The connection circuit board CF can also be powered on and connected to the main circuit board MB from the other side adjacent to it.

[0089] This embodiment shows a connection circuit board CF connecting the display panel DP to the main circuit board MB. However, embodiments of this disclosure are not limited to this, and multiple connection circuit boards CF can be configured to connect the display panel DP to the main circuit board MB.

[0090] The connecting circuit board (CF) can be a flexible printed circuit board. The connecting circuit board (CF) provides electrical signals to the display panel (DP) for driving the display panel (DP). These electrical signals can be generated from the connecting circuit board (CF) or from the main circuit board (MB).

[0091] The driver chip (DIC) can be mounted on the connecting circuit board (CF). The driver chip (DIC) can be mounted on a flexible printed circuit board and can be configured as a chip-on-film (COF). The driver chip (DIC) can include driving elements for driving the pixels of the display panel (DP). The driver chip (DIC) can include driving circuitry, and the driving circuitry can be configured as an integrated circuit. The driving circuitry can include a controller, data driver, voltage generator, etc.

[0092] The main circuit board (MB) may include a main controller. The main circuit board (MB) may include signal lines (not shown) for transmitting control signals and image signals received from the main controller to the connection circuit board (CF) and the display panel (DP).

[0093] Although not shown, the printed circuit board (PCB) may also include an input circuit board electrically connected to the input sensing layer (ISL). The input circuit board connects the input sensing layer (ISL) to the main circuit board (MB). In this embodiment, the input circuit board may be configured as a flexible circuit film and connect the input sensing layer (ISL) to the main circuit board (MB). The input circuit board provides electrical signals to the input sensing layer (ISL) for driving the ISL. These electrical signals may be generated from the input circuit board or from the main circuit board (MB).

[0094] Each of the connection circuit board CF and the input circuit board can be connected to a main circuit board MB. Alternatively, one of the connection circuit board CF or the input circuit board may not be connected to the main circuit board MB, and this is not limited to any particular implementation.

[0095] The lower component LM can be located below the display panel DP. The lower component LM may include a protective film for the display panel DP, a support component for supporting the display panel DP, a digitizer, etc.

[0096] The electronic module (EM) and power module (PSM) can be located below the display module (DM). The EM and PSM can be electrically connected to each other via separate circuit boards.

[0097] A power supply module (PSM) can provide the power necessary to support the operation of an electronic device (ED). For example, a power supply module (PSM) may include a general-purpose battery module.

[0098] The electronic module (EM) may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, and an external interface module. The EM may include a main circuit board, and the aforementioned modules may be mounted on the main circuit board or electrically connected to the main circuit board via a flexible circuit board. The EM is electrically connected to the power supply module (PSM).

[0099] Although not shown separately, the electronic device ED may also include an electro-optic module. The electro-optic module can be an electronic component for outputting or receiving optical signals. The electro-optic module may include a camera module and / or a proximity sensor. The camera module can capture external images through a portion of the display panel DP.

[0100] Figure 3 The housing HU shown is connected to the display device DD, specifically to the window WM, and houses the other modules mentioned above. The housing HU is shown as a single unit, but is not limited thereto. The housing HU may include multiple parts (e.g., side edge portions and bottom portions) that are connected to each other. The housing HU protects the display module DM housed within its internal space from external impacts and prevents foreign objects or moisture from penetrating the display module DM.

[0101] Figure 4Aand Figure 4B This is a plan view of a display device according to an embodiment of the present invention.

[0102] refer to Figure 4A On a plane, the display area DA and the non-display area NDA can be defined within the display panel DP. The display area DA can be the area on which an image is displayed. The non-display area NDA can be the area on which no image is displayed. The non-display area NDA can be the area adjacent to the display area DA. The non-display area NDA can surround the display area DA, but its shape is not limited to this.

[0103] The display panel DP may include multiple pixels (PX), scan drive circuitry (SDC), multiple signal lines, and multiple pads (PD). The display panel DP may include scan lines (SL), transmit lines (EL), data lines (DL), scan control lines (SCL), initialization voltage lines (VINTL), and voltage lines (VL) as signal lines.

[0104] Each pixel PX includes a display element and a thin-film transistor electrically connected to the display element. The display element may include, for example, an organic light-emitting diode. Pixels PX may be disposed in the display area DA. However, embodiments of this disclosure are not limited thereto, and portions of pixels PX may be disposed in the non-display area NDA.

[0105] Pixels PX can be arranged in a matrix shape along a first direction DR1 and a second direction DR2 that intersect each other perpendicularly. In embodiments of the present invention, pixels PX may include first to third pixels that display red, green, and blue, respectively. In embodiments, pixels PX may also include pixels that display off-white, cyan, and magenta, respectively.

[0106] The scan drive circuit SDC can be arranged adjacent to one side of the non-display area NDA. However, embodiments of this disclosure are not limited thereto, and the scan drive circuit SDC can be disposed within the display area DA. The scan drive circuit SDC can generate multiple scan signals and multiple transmit signals, and sequentially output the generated scan signals and transmit signals to the scan line SL and the transmit line EL, which will be described later. The scan drive circuit SDC can also output another control signal to the drive circuit of the pixel PX.

[0107] Each scan line SL extends from the scan drive circuit SDC along the first direction DR1 and connects to a corresponding pixel among the plurality of pixels PX. Each emitter line EL extends from the scan drive circuit SDC along the first direction DR1 and is arranged parallel to the corresponding scan line in the scan line SL. The scan lines SL and emitter lines EL can be connected to the scan drive circuit SDC.

[0108] Each data line DL can extend along the second direction DR2 and connect to a corresponding pixel among multiple pixels PX. The scan control line SCL can provide control signals to the scan drive circuit SDC.

[0109] The initialization voltage line VINTL can provide initialization voltage to multiple pixels PX. The voltage line VL can be connected to multiple pixels PX and provide voltage to them. The voltage line VL can include multiple lines extending along a first direction DR1 and multiple lines extending along a second direction DR2.

[0110] Some of the scan lines SL, data lines DL, emit lines EL, scan control lines SCL, initialization voltage lines VINTL, and voltage lines VL can be set on the same layer, while others can be set on different layers.

[0111] The pads PD can be located in the non-display area NDA. Specifically, the pads PD can be located in the pad area PA of the non-display area NDA. The pads PD can be arranged parallel to each other in the first direction DR1. In this embodiment, the pads PD are shown and described as arranged in a row along the first direction DR1, but are not limited thereto. For example, the pads PD can be arranged in two or more rows, or in a zigzag shape. The pads PD can be connected to the data line DL, the scan control line SCL, the initialization voltage line VINTL, and the voltage line VL.

[0112] The connection circuit board CF may include a connection base layer CP-F, multiple connection pads CP-A, and multiple substrate connection pads CP-B.

[0113] The connection base layer CP-F can be an insulating layer on which multiple connection pads CP-A and multiple substrate connection pads CP-B are disposed. The connection base layer CP-F may include a flexible film.

[0114] The connection pad CP-A can be arranged along the first direction DR1 on the side of the connection base layer CP-F adjacent to the display panel DP. The connection pad CP-A can be connected to the corresponding pad PD of the display panel DP.

[0115] The pad PD can be arranged on the front surface of the display panel DP, and the connection pad CP-A can be arranged on the rear surface of the connection base layer CP-F. However, the embodiments of this disclosure are not limited thereto. The pad PD can be arranged on the rear surface of the display panel DP, and the connection pad CP-A can be arranged on the front surface of the connection base layer CP-F.

[0116] The substrate connection pad CP-B can be arranged along a first direction DR1 on the side of the connection base layer CP-F adjacent to the main circuit board MB. The substrate connection pad CP-B can be spaced apart from the connection pad CP-A along a second direction DR2. The substrate connection pad CP-B can be arranged on the rear surface of the connection base layer CP-F. However, embodiments of this disclosure are not limited thereto, and the substrate connection pad CP-B can also be arranged on the front surface of the connection base layer CP-F.

[0117] The connection circuit board CF may include multiple lines. Each of these lines can transmit an electrical signal to components connected to one end of the line and the other end, respectively. The multiple lines may include a line electrically connecting the connection pad CP-A to the driver chip DIC and a line electrically connecting the substrate connection pad CP-B to the driver chip DIC. The multiple lines may be disposed on the connection base layer CP-F.

[0118] The main circuit board (MB) may include multiple substrate pads (MP). The main circuit board (MB) may include multiple lines connected to the substrate pads (MP).

[0119] The substrate pad MP can be arranged along the first direction DR1 on the side of the main circuit board MB adjacent to the connecting circuit board CF. The substrate pad MP can be arranged on the front surface of the main circuit board MB. However, embodiments of this disclosure are not limited thereto, and the substrate pad MP can also be arranged on the rear surface of the main circuit board MB.

[0120] Substrate pads MP can be connected to substrate connection pads CP-B on the connection board CF, corresponding to the substrate pads MP. Substrate pads MP can be electrically connected to the main controller and can receive control signals and image signals from the main controller. Substrate pads MP can transmit the received signals to substrate connection pads CP-B.

[0121] According to an embodiment of the present invention, a plurality of pads PD can extend in a direction inclined at a first angle relative to the second direction DR2. Specifically, the plurality of pads PD can extend in a first oblique direction CDR1 or a second oblique direction CDR2. For example, a plurality of pads PD disposed on the left side of the pad region PA can extend in a first oblique direction CDR1 forming an acute angle clockwise relative to the second direction DR2, and a plurality of pads PD disposed on the right side of the pad region PA can extend in a second oblique direction CDR2 forming an acute angle counterclockwise relative to the second direction DR2.

[0122] In some respects, multiple connection pads CP-A, multiple substrate connection pads CP-B, and multiple substrate pads MP may correspond to multiple pads PD respectively, and extend in a direction inclined at a first angle relative to the second direction DR2.

[0123] refer to Figure 4B The connecting circuit board CF can be attached to the pad area PA of the display panel DP. Although not shown, a conductive adhesive film can be disposed between the display panel DP and the connecting circuit board CF. For example, the conductive adhesive film may include anisotropic conductive film (ACF). In some aspects, the connecting circuit board CF can be attached to the main circuit board MB.

[0124] In embodiments of the present invention, during the attachment of the connection circuit board CF to the pad area PA of the display panel DP, multiple pads PD and multiple connection pads CP-A may be misaligned with each other. Therefore, misalignment checks of the multiple pads PD and connection pads CP-A can be performed. This will be described in detail later.

[0125] Figure 4B The pads are shown to be misaligned to better understand the connection between pad PD and connection pad CP-A, as well as the connection between substrate pad MP and substrate connection pad CP-B. However, the pads can be connected to their respective pads to overlap with the corresponding pads.

[0126] When the pad PD and the connection pad CP-A are fully and completely connected to each other, the control signals and image signals received from the drive circuit of the driver chip DIC can be transmitted to the display panel DP without distortion. When the substrate pad MP and the substrate connection pad CP-B are fully and completely connected to each other, the control signals and image signals received from the main controller of the main board MB can be transmitted to the drive circuit of the driver chip DIC without distortion.

[0127] Figure 5 This is a cross-sectional view of a display module according to an embodiment of the present invention. For example, Figure 5 It shows the relationship with Figure 4A The pixel PX in the image corresponds to the cross section of the display module DM.

[0128] refer to Figure 5 The pixel driving circuit PC that drives the light-emitting element (LD) may include multiple pixel driving elements. The pixel driving circuit PC may include multiple S-TFTs and O-TFTs and a capacitor Cst. The multiple S-TFTs and O-TFTs may include silicon S-TFTs and oxide O-TFTs. As an example, Figure 5 The silicon transistor S-TFT and oxide transistor O-TFT are shown. Figure 5 The pixel driving circuit PC described herein is merely one implementation, and the components of the pixel driving circuit PC are not necessarily limited to this. The pixel driving circuit PC may include one type of transistor, namely silicon transistor S-TFT and oxide transistor O-TFT.

[0129] Figure 5 A base layer BL with a single-layer structure is shown. The base layer BL may include a synthetic resin such as polyimide. A synthetic resin layer may be applied to a working substrate (or a carrier substrate) to form the base layer BL. In an example where the display module DM is completed through subsequent processes, the working substrate may be removed.

[0130] A first shielding electrode (or shielding electrode) BML1 may be disposed on the base layer BL. The first shielding electrode BML1 may receive a bias voltage. The first shielding electrode BML1 may receive a first electrical voltage. The first shielding electrode BML1 may prevent the potential from affecting the silicon transistor S-TFT due to polarization. The first shielding electrode BML1 may prevent external light from reaching the silicon transistor S-TFT. In embodiments of the present invention, the first shielding electrode BML1 may be a floating electrode having a shape isolated from another electrode or line. The first shielding electrode BML1 may be arranged to correspond to the silicon transistor S-TFT. The first shielding electrode BML1 may include a metal (e.g., molybdenum).

[0131] A barrier layer (BRL) can be disposed on the base layer (BL) and the first shielding electrode (BML1). The barrier layer (BRL) prevents foreign matter from being introduced from the outside. The barrier layer (BRL) may include at least one inorganic layer. The barrier layer (BRL) may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be disposed in multiples, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0132] A buffer layer BFL can be disposed on the barrier layer BRL. The buffer layer BFL prevents metal atoms or impurities from diffusing from the base layer BL to the first semiconductor pattern SC1 above the buffer layer BFL. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0133] The first semiconductor pattern SC1 can be disposed on the buffer layer BFL. The first semiconductor pattern SC1 can include a silicon semiconductor. For example, the silicon semiconductor can include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 can include low-temperature polycrystalline silicon.

[0134] The first semiconductor pattern SC1 can have different electrical properties depending on whether it is doped. The first semiconductor pattern SC1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an n-type dopant or a p-type dopant. A p-type transistor may include a doped region doped with a p-type dopant, and an n-type transistor may include a doped region doped with an n-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. In this embodiment, the first semiconductor pattern SC1 may be doped with an n-type dopant.

[0135] The conductivity of the first region can be higher than that of the second region, and the first region can be used substantially as an electrode or signal line. The second region can substantially correspond to the channel region (or active region) of the transistor. In other words, a portion of the first semiconductor pattern SC1 can be the channel of the transistor, another portion of the first semiconductor pattern SC1 can be the source or drain of the transistor, and yet another portion of the first semiconductor pattern SC1 can be a connecting electrode or a connecting signal line.

[0136] The source region SE1, channel region AC1 (or active region), and drain region DE1 of a silicon transistor S-TFT can be provided by a first semiconductor pattern SC1. The source region SE1 and drain region DE1 can extend from the channel region AC1 in opposite directions in cross-section.

[0137] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a silicon oxide layer having a single-layer structure. Not only the first insulating layer 10, but also the inorganic layers of the circuit layer DP-CL, which will be described later, may each have a single-layer structure or a multi-layer structure, and may each include at least one of the materials described herein. However, embodiments of this disclosure are not limited thereto.

[0138] The gate (or gate electrode) GT1 of the silicon S-TFT is disposed on the first insulating layer 10. The gate GT1 may be a portion of a metal pattern. The gate GT1 overlaps with the channel region AC1. The gate GT1 may be used as a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst is disposed on the first insulating layer 10. Figure 5 The embodiments shown are different, and the first electrode CE10 and the gate GT1 can have an integral shape.

[0139] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate GT1. In an embodiment of the present invention, the upper electrode overlapping the gate GT1 may be further disposed on the second insulating layer 20. The second electrode CE20 overlapping the first electrode CE10 may be disposed on the second insulating layer 20. In a planar plane, the upper electrode and the second electrode CE20 may have an integral shape.

[0140] The second shielding electrode BML2 is disposed on the second insulating layer 20. The second shielding electrode BML2 can be arranged to correspond to the oxide transistor O-TFT. In an embodiment of the present invention, the second shielding electrode BML2 can be omitted. In an embodiment of the present invention, the first shielding electrode BML1 can extend below the oxide transistor O-TFT and replace the second shielding electrode BML2.

[0141] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include the channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and zinc oxide (ZnO). x Transparent conductive oxides (TCO) of indium oxide (In2O3) or indium oxide (In2O3).

[0142] The metal-oxide-semiconductor (MOS) pattern may include multiple regions SE2, AC2, and DE2, divided according to whether the transparent conductive oxide is reduced. The regions where the transparent conductive oxide is reduced (hereinafter referred to as reduced regions) have higher conductivity than the regions where the transparent conductive oxide is not reduced (hereinafter referred to as non-reduced regions). The reduced regions are essentially used as signal lines or source / drain regions of the transistor. The non-reduced regions essentially correspond to the semiconductor regions (or channel regions) of the transistor. In other words, a portion of the second semiconductor pattern SC2 may be the semiconductor regions of the transistor, another portion of the second semiconductor pattern SC2 may be the source region SE2 / drain region DE2 of the transistor, and yet another portion of the second semiconductor pattern SC2 may be the signal transmission region.

[0143] The fourth insulating layer 40 can be disposed on the third insulating layer 30. For example... Figure 5 As shown, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In an embodiment of the present invention, the fourth insulating layer 40 may be an insulating pattern that overlaps with the gate GT2 of the oxide transistor O-TFT and exposes each of the source region SE2 and drain region DE2 of the oxide transistor O-TFT.

[0144] The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a portion of a metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0145] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first insulating layer 10 to the fifth insulating layer 50 may be an inorganic layer.

[0146] A conductive layer may be disposed on the fifth insulating layer 50. In this inventive concept, the conductive layer may include a first connection pattern CNP1 and a second connection pattern CNP2. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed using the same process and therefore have the same material and the same stacking structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 passing through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationships between the first connection pattern CNP1 and the second connection pattern CNP2 and the silicon transistor S-TFT and the oxide transistor O-TFT are not necessarily limited to this.

[0147] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. A third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 through a third pixel contact hole PCH3 passing through the sixth insulating layer 60. A data line DL may be disposed on the sixth insulating layer 60. A seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed using the same process and therefore have the same material and the same stacking structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0148] The first shielding electrode BML1, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT may each comprise molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy, each possessing good heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may comprise aluminum with high conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may each have a three-layer structure (e.g., titanium / aluminum / titanium) in which titanium and aluminum are stacked.

[0149] A light-emitting element (LD) may include an anode (AE) (or a first electrode), a light-emitting layer (EML), and a cathode (CE) (or a second electrode). The anode (AE) of the LD may be disposed on a seventh insulating layer (70). The anode (AE) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode (AE) may include a stacked structure of ITO and Ag sequentially stacked (e.g., ITO / Ag / ITO). The positions of the anode (AE) and the cathode (CE) may be interchanged.

[0150] A pixel-defining layer (PDL) may be disposed on a seventh insulating layer 70. The PDL may be an organic layer. The PDL may have light-absorbing properties, and for example, it may be black. The PDL may include a black component (black colorant). The black component may include a black dye or black pigment. The black component may include carbon black, a metal such as chromium, or its oxide. The PDL may correspond to a light-blocking pattern having light-blocking properties.

[0151] The pixel defining layer (PDL) can cover a portion of the anode (AE). For example, an opening portion (PDL-OP) exposing the anode (AE) can be defined within the pixel defining layer (PDL). The light-emitting region (LA) can be defined to correspond to the opening portion (PDL-OP). In embodiments of the present invention, a hole control layer can be disposed between the anode (AE) and the light-emitting layer (EML). The hole control layer may include a hole transport layer and a hole injection layer. An electron control layer can be disposed between the light-emitting layer (EML) and the cathode (CE). The electron control layer may include an electron transport layer and an electron injection layer.

[0152] The encapsulation layer TFE can cover the light-emitting element (LD). The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, embodiments of this disclosure are not limited thereto, and the encapsulation layer TFE may also include multiple inorganic and organic layers.

[0153] The first encapsulation insulating layer IL1 can be an inorganic layer. The first encapsulation insulating layer IL1 prevents external moisture or oxygen from penetrating into the light-emitting element (LD). For example, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or compounds in combination thereof. The first encapsulation insulating layer IL1 can be formed by a chemical vapor deposition process.

[0154] The second encapsulation insulating layer IL2 can be an organic layer. The second encapsulation insulating layer IL2 can be disposed on the first encapsulation insulating layer IL1 to contact the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 can provide a flat surface on the first encapsulation insulating layer IL1. Unevennesses formed on the top surface of the first encapsulation insulating layer IL1, particles present on the first encapsulation insulating layer IL1, etc., can be covered by the second encapsulation insulating layer IL2, thereby preventing the surface condition of the top surface of the first encapsulation insulating layer IL1 from affecting the components disposed on the second encapsulation insulating layer IL2. In some aspects, the second encapsulation insulating layer IL2 can alleviate stress between layers in contact with each other. The second encapsulation insulating layer IL2 can be formed by a solution process such as spin coating, slot coating, or inkjet printing.

[0155] A third encapsulation insulating layer IL3 is disposed on and covers the second encapsulation insulating layer IL2. Compared to the case where the third encapsulation insulating layer IL3 is disposed on the first encapsulation insulating layer IL1, the third encapsulation insulating layer IL3 can be stably disposed on a relatively flat surface. The third encapsulation insulating layer IL3 can encapsulate moisture and the like emitted from the second encapsulation insulating layer IL2 and prevent moisture and the like from being introduced to the outside.

[0156] The third encapsulation insulating layer IL3 can be optically transparent. For example, the third encapsulation insulating layer IL3 can have a visible light transmittance of approximately 90% or higher. The third encapsulation insulating layer IL3 can have a relatively higher transmittance than the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 can be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO2). x The first encapsulation insulating layer IL1 or silicon nitride oxide (SiON) may be used. The third encapsulation insulating layer IL3 may be formed by chemical vapor deposition. Each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include multiple layers and is not limited to any one embodiment.

[0157] The input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensing layer ISL may include a first insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 5 The conductive lines of the first conductive layer ICL1 and the second conductive layer ICL2 are briefly shown in the figure.

[0158] The first insulating layer IS-IL1 can be directly disposed on the display panel DP. The first insulating layer IS-IL1 can be an inorganic layer comprising at least one of silicon nitride, silicon oxide nitride, and silicon oxide. Each of the first conductive layer ICL1 and the second conductive layer ICL2 can have a single-layer structure or a multilayer structure in which the layers are stacked on a third-direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 can include conductive lines of electrodes defining a grid shape. The conductive lines of the first conductive layer ICL1 and the second conductive layer ICL2 can be connected to each other through contact holes in the second insulating layer IS-IL2, or they can be unconnected. The connection relationship between the conductive lines of the first conductive layer ICL1 and the second conductive layer ICL2 can be determined according to the type of sensor configured as the input sensing layer ISL.

[0159] The first conductive layer ICL1 and the second conductive layer ICL2, each having a single-layer structure, may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). x Transparent conductive oxides such as indium zinc tin oxide (IZTO) or indium zinc tin oxide (IZTO) can be used. In some aspects, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, and graphene.

[0160] The first conductive layer ICL1 and the second conductive layer ICL2, each having a multilayer structure, may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer. A second insulating layer IS-IL2 may be disposed between the first conductive layer ICL1 and the second conductive layer ICL2. A third insulating layer IS-IL3 may cover the second conductive layer ICL2. In embodiments of the present invention, the third insulating layer IS-IL3 may be omitted. The second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include inorganic or organic layers.

[0161] Figure 6 yes Figure 4A An enlarged view of region AA' shown in the image. Figure 7 It is along Figure 6 The sectional view shown is taken by line I-I'. Figure 8 This is a cross-sectional view of a portion of an electronic device according to an embodiment of the present invention. Figure 8 The diagram shows the connection circuit board CF being bonded to... Figure 3 An example of a cross-section of the electronic device ED on the display panel DP shown. Content identical to that described above will be omitted.

[0162] Let's refer to each other. Figure 6 and Figure 7 Multiple pads (PDs) can be electrically connected to multiple connection lines (CLs) extending in the second direction (DR2). For example, multiple pads (PDs) can be electrically connected to multiple connection lines (CLs) through corresponding third contact holes (CH3s) defined to pass through the third insulating layer (30) and the fourth insulating layer (40). The multiple connection lines (CLs) can be connected to... Figure 4A The data line DL, scan control line SCL, initialization voltage line VINTL, and voltage line VL shown correspond to the signal lines. Multiple pads PD can transmit signals corresponding to pixels PX through multiple connection lines CL.

[0163] Multiple pads (PDs) can be electrically connected to inspection lines (IWLs) extending in the direction opposite to the second direction (DR2). For example, the multiple pads (PDs) can be electrically connected to the inspection lines (IWLs) through corresponding first contact holes (CH1s) defined to pass through the third insulating layer (30) and the fourth insulating layer (40). Multiple inspection lines (IWLs) can be provided to correspond to the multiple pads (PDs). The inspection lines (IWLs) can be disposed on the same layer as multiple connection lines (CLs). The inspection lines (IWLs) and the multiple connection lines (CLs) can be... Figure 5 The second shielding electrode BML2 shown herein comprises the same material. That is, the inspection line IWL and the multiple connecting lines CL can be formed using the same process as the second shielding electrode BML2.

[0164] The inspection line (IWL) can transmit inspection signals to multiple pads (PDs). These inspection signals check whether the multiple pads (PDs) are electrically connected to multiple connection lines (CLs), and can also check for short circuits between the multiple pads (PDs) and the multiple connection lines (CLs).

[0165] Multiple subpatterns (SPs) can be disposed between multiple pads (PDs) and inspection lines (IWLs). Multiple subpatterns (SPs) can be referred to as rework patterns. Multiple subpatterns (SPs) can comprise the same material as the multiple pads (PDs). Multiple subpatterns (SPs) can be electrically connected to the inspection lines (IWLs). For example, multiple subpatterns (SPs) can be electrically connected to the inspection lines (IWLs) through corresponding second contact holes (CH2s) defined to pass through the third insulating layer (30) and the fourth insulating layer (40). Multiple subpatterns (SPs) can be disposed on the same layer as the multiple pads (PDs). Multiple subpatterns (SPs) and multiple pads (PDs) can be... Figure 5 The first connection pattern CNP1 and the second connection pattern CNP2 shown herein are made of the same material. That is, the multiple sub-patterns SP and the multiple pads PD can be formed with the first connection pattern CNP1 and the second connection pattern CNP2 respectively through the same process.

[0166] According to an embodiment of the present invention, a plurality of sub-patterns SP can extend along a first diagonal direction CDR1 to correspond to a plurality of pads PD. That is, each of the plurality of sub-patterns SP can extend in the same direction as a corresponding pad PD among the plurality of pads PD. In an example where the plurality of sub-patterns SP extends along a second direction DR2, the plurality of pads PD may be affected by noise generated from the plurality of sub-patterns SP. However, since the plurality of sub-patterns SP extends along the first diagonal direction CDR1 to correspond to the plurality of pads PD according to an embodiment of the present invention, the noise transmitted from the plurality of sub-patterns SP to the plurality of pads PD can be reduced.

[0167] Let's refer to each other. Figure 7 and Figure 8 Multiple pads PD can be exposed to the outside through corresponding openings OP defined in the sixth insulating layer 60. The connection circuit board CF may include a connection base layer CP-F and multiple connection pads CP-A. The multiple connection pads CP-A may be disposed on the rear surface of the connection base layer CP-F.

[0168] Multiple connection pads CP-A can be electrically connected to multiple pads PD exposed to the outside through the opening portion OP. Specifically, the multiple connection pads CP-A can be electrically connected to the multiple pads PD through a conductive adhesive layer CAL. The conductive adhesive layer CAL can include an adhesive resin RS and conductive particles CP dispersed in the adhesive resin RS. In an embodiment, the conductive adhesive layer CAL can be an anisotropic conductive adhesive.

[0169] The adhesive resin RS can be filled between the conductive particles CP and will connect the circuit board CF (see...). Figure 3 Connect to the display panel DP (see...) Figure 3 The adhesive resin RS may include polymeric materials. For example, the adhesive resin RS may include at least one of acrylic polymers, silicone polymers, urethane polymers, and imide polymers. The adhesive resin RS may be a portion formed by thermosetting or photosetting a base resin such as an acrylic resin, silicone resin, urethane resin, or imide resin.

[0170] The conductive particles CP can be metal particles, alloy particles containing multiple metals, etc. For example, the conductive particles CP can be metal particles or metal alloy particles including at least one of silver, copper, bismuth, zinc, indium, tin, nickel, cobalt, chromium, and iron. Optionally, each conductive particle CP may have a core portion including a polymer resin, etc., and a coating surrounding the core portion including a conductive material.

[0171] Conductive particles CP can be disposed in the adhesive resin RS between corresponding pads PD and multiple connecting pads CP-A. The conductive particles CP can be anisotropic, allowing for connection to the circuit board CF (see...). Figure 3 During the bonding process, current can flow in the pressing direction when pressed. Therefore, the pad PD can be electrically connected to the connecting pad CP-A via the conductive particles CP.

[0172] Refer again Figure 6 The pad region PA according to an embodiment of the present invention (see Figure 4A The inspection area IA may be included. In a plane, the inspection area IA may be defined at the outermost portion of the pad area PA, specifically on each of the opposite sides of the pad area PA in the first direction DR1. The inspection area IA may be connected via a connection circuit board CF (see [link to circuit board]). Figure 4A In the process of inspecting the connection circuit board CF (see) Figure 4A Multiple connection pads CP-A (see) Figure 4A Alignment between the pad and the PD is used to ensure reliable bonding in the area.

[0173] An inspection pattern IP can be disposed in the inspection area IA. The inspection pattern IP may include portions having the same shape as each of the pads PD. Specifically, the inspection pattern IP may be aligned in a first direction DR1 and extend in a first diagonal direction CDR1. The inspection pattern IP may be disposed on the same layer as the pads PD and may comprise the same material as the pads PD. In a display device DD (see embodiment of the present invention) Figure 3 In this process, the inspection pattern IP, extending in the same direction as the pad PD, can be defined within the inspection area IA. Thus, the inspection pattern IP supports the inspection of whether the pad PD is positioned and whether, after the bonding process, the pad PD is aligned with the connecting pad CP-A extending in the first oblique direction CDR1, which is in the same direction as the pad PD. Therefore, the process reliability of the display device DD can be improved.

[0174] According to an embodiment of the present invention, the inspection pattern IP may include a first inspection pattern IP1 and a second inspection pattern IP2 spaced apart from each other in a first diagonal direction CDR1. Each of the first inspection pattern IP1 and the second inspection pattern IP2 may be provided in multiples. The first inspection pattern IP1 and the second inspection pattern IP2 may have the same shape.

[0175] Multiple sub-patterns SP can include a first sub-pattern SP1 and a second sub-pattern SP2. The first sub-pattern SP1 can be set within the inspection area IA. The first sub-pattern SP1 and the second sub-pattern SP2 can be spaced apart from each other in the first direction DR1. Multiple first sub-patterns SP1 can be set. Multiple second sub-patterns SP2 can be set. For example... Figure 6 As shown, the first inspection pattern IP1 can be set between two first sub-patterns SP1.

[0176] The inspection line IWL may include a first inspection line IWL1 and a second inspection line IWL2. The first inspection line IWL1 may be disposed in the inspection area IA. According to an embodiment of the present invention, the first inspection line IWL1 may extend in a first diagonal direction CDR1. That is, the first inspection line IWL1 extending in the first diagonal direction CDR1 in the inspection area IA can be used to check whether the pad PD is arranged.

[0177] The first inspection line IWL1 and the second inspection line IWL2 can be spaced apart from each other in the first direction DR1. Each of the first inspection line IWL1 and the second inspection line IWL2 can be configured in multiple ways. For example... Figure 6 As shown, the second inspection pattern IP2 can be disposed between the two first inspection lines IWL1. Unlike the first inspection lines IWL1, the second inspection line IWL2 can extend in the second direction DR2.

[0178] Figure 9 This is a view showing a portion of the display panel DPa according to an embodiment of the present invention.

[0179] refer to Figure 9 According to embodiments of the present invention, the pad PDA may further include a dummy pad DPD. The dummy pad DPD may be disposed among multiple pad PDAs. The dummy pad DPD may be substantially unconnected. Figure 4A The signal lines shown are (e.g., data line DL, scan control line SCL, initialization voltage line VINTL, and voltage line VL). In other words, the dummy pad DPD is a pad formed using the same process as the pad PDA, and is configured for uniform arrangement of the pad PDA, and can be a floating electrode.

[0180] According to embodiments of the present invention, the sub-pattern SP (e.g., the second sub-pattern SP2) corresponding to the dummy pad DPD may not be limited. Similarly, the second inspection line IWL2a corresponding to the dummy pad DPD may not be limited. The second inspection line IWL2a may include the (2-1) inspection line IWL2-1 and the (2-2) inspection line IWL2-2 spaced apart from each other in the first direction DR1.

[0181] Figure 10 This is a view showing a portion of the display panel DP according to an embodiment of the present invention.

[0182] refer to Figure 10 According to an embodiment of the present invention, the pad PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The first pad PD1 and the second pad PD2 may be spaced apart from each other in a first direction DR1 relative to the third pad PD3. The first pad PD1 may extend in a first diagonal direction CDR1, the second pad PD2 may extend in a second diagonal direction CDR2, and the third pad PD3 may extend in a second direction DR2.

[0183] The direction in which the first pad PD1 extends (i.e., the first diagonal direction CDR1) is clockwise relative to the second direction DR2 at a first angle. The direction in which the second pad PD2 extends (i.e., the second diagonal direction CDR2) is counterclockwise relative to the second direction DR2 at a first angle. The first angle may gradually decrease as the first pad PD1 and the second pad PD2 get closer to the third pad PD3.

[0184] On the plane, inspection areas IA1 and IA2 can be defined within the pad area PA (see...). Figure 4A The outermost portion of the pad region IA1 is specifically defined on the opposite side of the pad region PA in the first direction DR1. The inspection regions IA1 and IA2 may include a first inspection region IA1 located on the left side of the pad region PA in the first direction DR1 and a second inspection region IA2 located on the right side of the pad region PA in the first direction DR1.

[0185] The inspection pattern IPa may include a first inspection pattern IP1, a second inspection pattern IP2, a third inspection pattern IP3, and a fourth inspection pattern IP4. The first inspection pattern IP1 and the second inspection pattern IP2 may be set in a first inspection area IA1, and the third inspection pattern IP3 and the fourth inspection pattern IP4 may be set in a second inspection area IA2.

[0186] Multiple sub-patterns SP1 may include a first sub-pattern SP1, a second sub-pattern SP2, and a third sub-pattern SP3. The first sub-pattern SP1 may be located in a first inspection area IA1, and the second sub-pattern SP2 may be located in a second inspection area IA2. The third sub-pattern SP3 may be located between the first sub-pattern SP1 and the second sub-pattern SP2.

[0187] The inspection line IWLa may include a first inspection line IWL1, a second inspection line IWL2, and a third inspection line IWL3. The first inspection line IWL1 may be located in a first inspection area IA1, and the second inspection line IWL2 may be located in a second inspection area IA2. The third inspection line IWL3 may be located between the first inspection line IWL1 and the second inspection line IWL2.

[0188] According to embodiments of the present invention, an inspection pattern extending in the same direction as the pads can be defined within an inspection area, thereby providing a means for inspecting whether pads are arranged and whether the pads and connection pads are aligned with each other after the bonding process. Therefore, a reliable display device can be provided.

[0189] The embodiments of the present invention have been described above with reference to the present invention concept. However, those skilled in the art or those with ordinary skills will understand that various modifications and changes can be made to the present invention concept, as long as such modifications and changes do not depart from the spirit and technical scope of the present invention concept set forth in the claims to be described.

[0190] Therefore, the technical scope of the present invention is not limited to what is stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: Display panel, including pad area; Multiple pads are disposed in the pad area, aligned in a first direction, and each of the pads extends in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; as well as The pattern is examined to extend in the diagonal direction and correspond to at least a portion of the plurality of pads.

2. The display device according to claim 1, wherein, The pad area includes an inspection area located at the outermost portion of the pad area in the first direction, and The inspection pattern is set in the inspection area.

3. The display device according to claim 2 further includes multiple inspection lines electrically connected to the plurality of pads.

4. The display device according to claim 3, wherein, The first of the plurality of inspection lines is located in the inspection area and extends in the diagonal direction.

5. The display device according to claim 3, wherein, The second inspection line of the plurality of inspection lines is not located in the inspection area and extends in the second direction.

6. The display device according to claim 3, wherein, The multiple inspection lines are located on different layers relative to the multiple pads.

7. The display device according to claim 1, further comprising a plurality of sub-patterns, the plurality of sub-patterns being electrically connected to at least a portion of the plurality of pads, extending in the oblique direction and corresponding to at least a portion of the plurality of pads. in, The plurality of pads and the plurality of sub-patterns are disposed on the same layer.

8. The display device of claim 7, further comprising inspection lines electrically connecting the plurality of pads and the plurality of subpatterns to each other.

9. The display device according to claim 8, wherein, The connecting lines are positioned on different layers relative to each of the plurality of pads and the plurality of sub-patterns. The inspection line is electrically connected to the plurality of pads through the first contact hole. The inspection line is electrically connected to the plurality of sub-patterns through a second contact hole, and The connecting line is electrically connected to the plurality of pads through a third contact hole.

10. The display device according to claim 7, further comprising an insulating layer disposed on the plurality of pads and the plurality of sub-patterns, in, The plurality of pads are exposed through openings defined in the insulating layer.

11. The display device according to claim 1, wherein, The first angle gradually decreases toward the center of the pad area.

12. A display device, comprising: Display panel, including pad area; Multiple pads are disposed in the pad area, aligned in a first direction, and each of the pads extends in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; Multiple sub-patterns, electrically connected to at least a portion of the multiple pads, extending in the diagonal direction and corresponding to the at least a portion of the multiple pads; as well as An insulating layer is disposed on the plurality of pads and the plurality of sub-patterns; The plurality of pads are exposed through openings defined in the insulating layer.

13. The display device according to claim 12, wherein, The plurality of pads and the plurality of sub-patterns are disposed on the same layer, and The display device also includes inspection lines that electrically connect the plurality of pads and the plurality of sub-patterns to each other.

14. The display device according to claim 13, wherein, The connecting lines are positioned on different layers relative to each of the plurality of pads and the plurality of sub-patterns. The inspection line is electrically connected to the plurality of pads through a first contact hole, and The inspection line is electrically connected to the plurality of sub-patterns through a second contact hole, and The connecting line is electrically connected to the plurality of pads through a third contact hole.

15. The display device of claim 12, further comprising an inspection pattern extending in the diagonal direction and corresponding to at least a portion of the plurality of pads.

16. The display device according to claim 15, wherein, The pad area includes an inspection area located at the outermost portion of the pad area in the first direction, and The inspection pattern is set in the inspection area.

17. Electronic devices, including: Display panel, including pad area; Multiple pads are disposed in the pad area, aligned in a first direction, and each of the pads extends in a diagonal direction inclined at a first angle relative to a second direction intersecting the first direction; The pattern is examined to show that it extends in the diagonal direction and corresponds to at least a portion of the plurality of pads; as well as The printed circuit board includes multiple connection pads and is electrically connected to the display panel via the multiple connection pads.

18. The electronic device according to claim 17, wherein, The plurality of connection pads are aligned in the first direction and correspond to the plurality of pads and extend in the diagonal direction.

19. The electronic device of claim 17, further comprising a conductive adhesive layer electrically connecting the plurality of connection pads to each other.

20. The electronic device according to claim 17, wherein, The printed circuit board includes: The main circuit board includes a plurality of substrate pads arranged along the first direction; A connecting circuit board, powered on one side and connected to the display panel, and powered on the other side and connected to the main circuit board; and The driver chip is mounted on the connection circuit board.

Images