A printed wiring board manufacturing method for precisely controlling the overall shift angle of a pattern

Abstract

The application discloses a printed wiring board manufacturing method for precisely controlling the overall shift angle of a pattern, comprising the following steps: obtaining the weaving parameters of a glass cloth in a copper-clad plate; determining a shift angle for making the impedance line and the glass fiber bundle not continuously and long-distance overlapped according to the weaving parameters; and rotating the line layer pattern of the printed wiring board as a whole by the shift angle, so that the overlapping length of the impedance line and the glass fiber bundle is less than 30% of the width of a single fiber bundle. By rotating the line layer pattern as a whole by an optimized angle of 3-10 degrees, the application effectively avoids the long-distance parallel overlap of the impedance line and the glass fiber bundle, significantly reduces the impedance fluctuation caused by the periodic fluctuation of the dielectric constant, and reduces the impedance fluctuation amplitude by more than 60% compared with the traditional 0 / 90 degree design, and the yield of the impedance tolerance of ±5% is improved by 15-20 percentage points. The application does not change the existing material system and main process flow, has low implementation cost, and is particularly suitable for the printed wiring board with high-precision impedance requirements, such as high-speed signal transmission above 25 Gbps, AI servers and communication backplanes.

Description

Technical Field

[0001] This invention relates to the field of high-precision impedance printed circuit board technology, and in particular to a method for manufacturing printed circuit boards that precisely controls the overall offset angle of the pattern. Background Technology

[0002] In today's electronics industry, high-end industries such as communications, servers, and AI have increasingly higher requirements for signal transmission rates, and correspondingly, the requirements for transmission loss and stability are becoming more and more stringent. Therefore, controlling impedance in the printed circuit board process is becoming increasingly difficult.

[0003] 1. Common designs in the printed circuit board industry: a. Designed as a vertically arranged graphic, with impedance lines as vertical straight lines (e.g.) Figure 1 ); b. Designed as a horizontal graphic, with impedance lines as horizontal straight lines (e.g.) Figure 2 ); 2. The copper-clad laminate required for printed circuit boards is made of epoxy resin + fiberglass cloth + copper foil laminated together (e.g. Figure 3 The glass cloth is arranged in a straight line, both horizontally and vertically.

[0004] 3. When designed as Figure 1 and Figure 2 impedance lines and Figure 3 When fiber bundles overlap, large fluctuations will occur in high-precision impedance products.

[0005] In the design and manufacturing of high-precision impedance printed circuit boards, the inventors discovered and systematically analyzed a key root cause of impedance fluctuations for the first time: traditional impedance line designs all employ 0-degree or 90-degree routing methods (i.e., vertical or horizontal straight lines) that are completely parallel to the warp or weft of the copper-clad laminate's fiberglass cloth. Since the copper-clad laminate is composed of epoxy resin, fiberglass cloth, and copper foil, its internal fiberglass bundles have a regular warp and weft woven structure, causing the dielectric constant of the board to exhibit periodic fluctuations at the microscale. When the impedance line direction is completely parallel to the fiberglass bundle direction, the routing path is highly likely to completely overlap with a single fiberglass bundle over long distances or fall entirely within the resin window, resulting in extreme differences in the effective dielectric constant of that line, which in turn manifests as severe fluctuations in the impedance curve during time-domain reflectometry testing. This problem is particularly prominent in scenarios requiring high-speed signal transmission of 25Gbps or higher, such as communications, servers, and AI, where fluctuation amplitudes often exceed ±7% or even ±10%, severely impacting signal integrity and product yield. Summary of the Invention

[0006] The purpose of this invention is to provide a method for manufacturing printed circuit boards that precisely controls the overall offset angle of the pattern.

[0007] To address this, the present invention adopts the following technical solution: A method for manufacturing a printed circuit board with precise control over the overall offset angle of a pattern includes the following steps: (1) Obtain the weaving parameters of the fiberglass cloth in the copper clad laminate; (2) Determine the offset angle that prevents the impedance wires from overlapping the glass fiber bundles over a continuous long distance based on the braiding parameters; (3) Rotate the circuit layer pattern of the printed circuit board as a whole by the offset angle so that the overlap length between the impedance line and the glass fiber bundle is less than 30% of the width of a single fiber bundle.

[0008] Step (1) includes obtaining the warp and weft weaving density, fiber bundle spacing and dielectric constant fluctuation period of the fiberglass cloth in the copper clad laminate.

[0009] Preferably, the offset angle ranges from 3 degrees to 10 degrees.

[0010] Furthermore, it also includes: performing impedance compensation design on the offset pattern, and adjusting the line width, line spacing or reference layer distance to ensure that the impedance consistency of the entire board meets the design requirements.

[0011] Furthermore, the impedance compensation design uses electromagnetic simulation software for refitting. The compensation principle is: the impedance deviation caused by the change in the equivalent dielectric constant after rotation is restored to the target value by fine-tuning the linewidth (within ±5%) or the reference layer dielectric thickness (within ±10%).

[0012] Preferably, the printed circuit board is a high-precision impedance circuit board used for high-speed signal transmission of 25Gbps or higher, AI servers, or communication backplanes.

[0013] Furthermore, the overall rotation of the pattern is performed only on the signal layer containing high-speed impedance lines, while the ground plane layer and power layer rotate synchronously or maintain interlayer offset consistency through alignment marks.

[0014] A printed circuit board designed and manufactured using the method described above.

[0015] Furthermore, the printed circuit board circuit layer pattern is rotated by 3 to 10 degrees relative to the board edge or reference direction, and the overlap length between the impedance line and the glass fiber bundle is less than 30% of the width of a single fiber bundle.

[0016] Addressing the aforementioned industry pain points, the inventors of this application have broken with traditional design inertia and, for the first time in China, proposed and verified a method for precisely controlling the overall offset angle of a graphic. Unlike the conventional understanding of "random wiring" or "tilting based solely on experience," this invention explicitly points out for the first time that, considering the specific weaving parameters of the fiberglass cloth, manufacturing tolerances, and high-precision impedance compensation requirements, there exists an optimal offset angle range (3 to 10 degrees). Within this range, not only can long-distance overlap between impedance lines and fiberglass bundles be effectively avoided, but existing drilling, alignment, and etching processes can also be maximized for compatibility, solving the technical problems of large impedance fluctuations and low yield rates from the design source. This method fills a technological gap in this specific field in China.

[0017] In summary, the technical solution of this invention has the following beneficial effects: 1. Significantly improved impedance stability: Within the offset range of 3 to 10 degrees, the impedance fluctuation amplitude is reduced by about 60% compared to the traditional 0-degree / 90-degree design, and by more than 30% compared to random angle or non-optimized angle design; 2. Significantly improved yield: Within ±7% impedance tolerance, the overall yield (including after client mounting) improves by approximately 10%; within ±5% impedance tolerance, the overall yield improves by 15%–20%. 3. Strong process compatibility: This method does not change the existing material system and main process flow, but only requires adjustments in the design stage, resulting in low implementation cost and easy promotion; 4. Wide range of applications: This method is especially suitable for products with high-precision impedance requirements, such as high-speed signal transmission above 25Gbps, AI servers, and communication backplanes. Attached Figure Description

[0018] Figure 1 A schematic diagram showing a printed circuit board designed with a vertical layout and impedance lines as vertical straight lines; Figure 2 A schematic diagram showing a horizontally arranged graphic for a printed circuit board, with impedance lines as horizontal straight lines; Figure 3 A schematic diagram of the structure of the copper-clad laminate required for printed circuit boards; Figure 4 This is the design drawing after rotating Example 1. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, but this does not constitute a limitation on the scope of protection of the present invention.

[0020] This invention provides a method for manufacturing printed circuit boards that precisely controls the overall offset angle of patterns, comprising the following steps: Step 1: Determine the weaving parameters of the copper clad laminate fiberglass cloth - obtain the warp and weft weaving density, fiber bundle spacing and dielectric constant fluctuation period of the fiberglass cloth in the copper clad laminate to be used.

[0021] Step Two: Calculate the Offset Angle Range—Based on the parameters obtained in Step One, calculate the minimum offset angle required to ensure that the impedance line does not overlap with the fiber bundle at any position. Combine this with manufacturing process parameters (such as drilling and milling positioning accuracy and graphic alignment tolerances) to determine the practically feasible offset angle range. Theoretical and experimental verification shows that this angle range is 3 to 10 degrees.

[0022] Step 3: Overall graphic offset design – In the printed circuit board design file, rotate the graphic of the circuit layer containing the impedance lines by the angle determined in Step 2, so that all impedance lines are laid out in that angular direction, ensuring that the impedance lines do not overlap with the glass fiber bundles or only overlap by a very small length throughout the entire board.

[0023] Step 4: Matching impedance compensation design - For local impedance changes caused by changes in trace direction after offset, compensation is made by adjusting the trace width, trace spacing or reference layer distance to ensure the impedance consistency of the entire board.

[0024] Step 5: Graphic Alignment and Production Control – During the production process, the offset graphic is aligned with the drilling and shape to ensure that the offset angle remains consistent throughout each production process.

[0025] Example 1 (Ordinary High-Speed) (1) Copper Clad Laminate Parameters The selected product is an IT-170GRA type copper clad laminate from a certain manufacturer. The fiberglass cloth model is 1080. The warp weave density is 57 strands / cm, the weft weave density is 44 strands / cm, the warp fiber bundle spacing is about 175μm, the weft spacing is about 227μm, and the dielectric constant fluctuation period is consistent with the weave period.

[0026] (2) Calculation of offset angle Based on the fiberglass bundle spacing and pattern alignment tolerance (drilling and milling positioning accuracy ±50μm, pattern alignment tolerance ±25μm), the minimum effective offset angle is calculated; in actual production, it can be obtained through simplified empirical calculation, (warp weaving density + weft weaving density) / 20, that is, in this embodiment, (57+44) / 20≈5 degrees.

[0027] (3) Rotation of the entire graphic In InCAMPro design software, select all high-speed signal layers (L1, L3, L6, L8) and rotate the entire board by 5° (counterclockwise) with the center as the reference. After rotation, the angle between the impedance lines and the fiber optic warp direction is 5°. Simulation verification shows that the overlap length between the impedance lines and the fiber optic bundles across the entire board is less than 20% of the width of a single fiber bundle. Figure 4As shown.

[0028] (4) Impedance compensation design Original design: 100μm line width, 120μm line spacing, 75μm reference layer distance, target impedance 50Ω. After rotation, the change in trace direction caused a change in the local equivalent dielectric constant. By adjusting the line width to 102μm, maintaining the line spacing at 120μm, and adjusting the reference layer distance to 73μm, the impedance was restored to 50Ω±2Ω.

[0029] (5) Production alignment In the drilling, outer layer patterning, solder masking, and contour milling processes, the rotated pattern is used as the reference, and the same rotation angle offset compensation (5°) is set to ensure the stacking alignment accuracy.

[0030] (6) Impedance test results The six differential lines on the finished board were tested using a TDR (Time Domain Reflectometer) (frequency 10 GHz): • Traditional 0° design: Impedance fluctuation range 46.2Ω~53.8Ω (fluctuation 7.6Ω) • This invention features a 5° design: impedance fluctuation range of 48.9Ω~51.3Ω (fluctuation of 2.4Ω). The fluctuation range was reduced by 68%, and the yield rate that meets the ±5% impedance tolerance (47.5Ω~52.5Ω) increased from 72% to 94%.

[0031] Example 2 (Communication Backplane) (1) Copper Clad Laminate Parameters The selected material is a Shengyi S1000-2M copper clad laminate with fiberglass cloth model 2116. The warp weave density is 43 strands / cm, the weft weave density is 32 strands / cm, the warp fiber bundle spacing is about 233μm, the weft spacing is about 313μm, and the dielectric constant fluctuates significantly.

[0032] (2) Calculation of offset angle To avoid impedance resonance caused by a large weaving cycle, and considering manufacturing tolerances (drilling and milling ±40μm, pattern alignment ±20μm), the theoretical minimum angle is calculated. In actual production, it can be obtained through simplified empirical calculation: (warp weaving density + weft weaving density) / 20, which is (43+32) / 20 = 3.75 degrees in this embodiment.

[0033] (3) Rotation of the entire graphic The inner impedance wire layers (L2, L5) and outer layers (L1, L6) were rotated as a whole by 3.75° in a clockwise direction. After rotation, the overlap length distribution between the impedance wires and the glass fiber bundles was more uniform.

[0034] (4) Impedance compensation design The original design had a linewidth of 85μm (outer layer) / 80μm (inner layer) and a line spacing of 110μm. After rotation, the outer layer linewidth was adjusted to 86.5μm, the inner layer linewidth remained unchanged, and the reference layer distance was slightly adjusted accordingly to compensate for local capacitance changes caused by the angle.

[0035] (5) Production alignment In the LDI (Laser Direct Imaging) exposure process, a 3.75° rotation compensation is set, and the drill bit file is rotated in the same way to ensure that the hole position matches the graphic.

[0036] (6) Impedance test results Testing 12 25Gbps signal lines: • Traditional 0° design: Impedance fluctuation ±4.2Ω (fluctuation 8.4Ω) • This invention features a 3.75° design: impedance fluctuation ±1.5Ω (fluctuation 3.0Ω). The fluctuation range was reduced by 64%. With an impedance tolerance of ±5% (47.5Ω~52.5Ω), the yield rate increased from 68% to 89%; with a tolerance of ±7%, the yield rate increased from 85% to 97%.

[0037] Example 3 (AI Server) (1) Copper Clad Laminate Parameters The Taiguang EM-891K(2) high-speed copper clad laminate was selected, with fiberglass cloth model 3313, warp weaving density: 67 strands / cm, weft weaving density: 57 strands / cm, fiber bundle spacing is small (about 149μm in the warp and about 175μm in the weft), and dielectric constant fluctuation period is short.

[0038] (2) Calculation of offset angle Due to the high weaving density, theoretically a small angle can be avoided. However, in order to further reduce residual fluctuations and adapt to the alignment tolerance of ±35μm, the actual production can be obtained through a simplified empirical calculation: (warp weaving density + weft weaving density) / 20. The calculation takes 6.2° as the engineering implementation angle.

[0039] (3) Rotation of the entire graphic All signal layers of the 16-layer board were rotated by 6.2°, and rotation compensation marks were added to the panel to facilitate subsequent AOI (Automated Optical Inspection) and electrical testing.

[0040] (4) Impedance compensation design The original design was a 50Ω microstrip line (120μm linewidth, 100μm dielectric thickness). After rotation, impedance simulation software (PolarSI9000) was used to refit the line, adjusting the linewidth to 123μm, maintaining the line spacing at 150μm, and adjusting the reference layer distance to 97μm, ensuring an impedance of 50Ω ± 1.5Ω.

[0041] (5) Production alignment A CCD (charge-coupled device) alignment system is used to automatically identify the rotated alignment target before each layer is exposed, ensuring the consistency of the interlayer offset angle.

[0042] (6) Impedance testing and reliability verification A full-board TDR scan was performed on the 40 PCIe 5.0 (32Gbps) signal lines on the AI ​​server motherboard (510mm × 460mm): Traditional 0° design: Impedance fluctuation ±5.6Ω (fluctuation 11.2Ω), 23% of points are non-compliant. • This invention features a 6.2° design: impedance fluctuation ±1.8Ω (fluctuation 3.6Ω), with a defect rate of only 3%. Impedance fluctuations were reduced by 68%.

[0043] After thermal cycling tests (-40℃~125℃, 500 cycles), the impedance drift is less than ±1Ω, which is far superior to ±3Ω of traditional designs.

[0044] (7) Yield statistics Under ±5% impedance tolerance (47.5Ω~52.5Ω), the overall board yield (including post-mount functional testing) increased from 62% in the traditional design to 82%, an improvement of 20%.

[0045] The three embodiments described above employed offset angles of 5°, 3.75°, and 6.2°, respectively, covering different fiberglass cloth weaving densities (1080, 2116, and 3313) and different application scenarios (ordinary high-speed, communication backplane, and AI server). All embodiments were implemented following the steps of "parameter acquisition → angle calculation → graphic rotation → impedance compensation → alignment production." The final TDR test results all showed that the impedance fluctuation amplitude was reduced by more than 60% compared to the traditional 0° design, and the ±5% tolerance yield was improved by 15-20 percentage points, fully demonstrating the feasibility and universality of the invention.

[0046] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for manufacturing a printed circuit board with precise control over the overall offset angle of a pattern, characterized in that, Includes the following steps: (1) Obtain the weaving parameters of the fiberglass cloth in the copper clad laminate; (2) Determine the offset angle that prevents the impedance wires from overlapping the glass fiber bundles over a continuous long distance based on the braiding parameters; (3) Rotate the circuit layer pattern of the printed circuit board as a whole by the offset angle so that the overlap length between the impedance line and the glass fiber bundle is less than 30% of the width of a single fiber bundle.

2. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 1, characterized in that: Step (1) includes obtaining the warp and weft weaving density, fiber bundle spacing and dielectric constant fluctuation period of the fiberglass cloth in the copper clad laminate.

3. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 1, characterized in that: The offset angle range is 3 to 10 degrees.

4. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 1, characterized in that: Also includes: Impedance compensation design is performed on the offset pattern. By adjusting the line width, line spacing, or reference layer distance, the impedance consistency of the entire board meets the design requirements.

5. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 4, characterized in that: The impedance compensation design uses electromagnetic simulation software for refitting. The compensation principle is: the impedance deviation caused by the change in the equivalent dielectric constant after rotation is restored to the target value by fine-tuning the linewidth or the thickness of the reference layer dielectric.

6. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 1, characterized in that: The printed circuit board is a high-precision impedance circuit board used for high-speed signal transmission of 25Gbps or higher, AI servers, or communication backplanes.

7. The printed circuit board manufacturing method for precisely controlling the overall offset angle of a pattern according to claim 1, characterized in that: The overall rotation of the graphic is performed only on the signal layer containing high-speed impedance lines. The ground plane layer and the power layer rotate synchronously or maintain interlayer offset consistency through alignment marks.

8. A printed circuit board, characterized in that, Designed and manufactured using the method described in any one of claims 1 to 7.

9. The printed circuit board according to claim 8, characterized in that: Its circuit layer pattern is rotated by 3 to 10 degrees relative to the reference direction, and the overlap length between the impedance line and the glass fiber bundle is less than 30% of the width of a single fiber bundle.

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