High current embedded thick copper fine line substrate and processing method thereof

Abstract

The application discloses a high-current embedded thick copper fine line substrate and a processing method thereof. The method comprises the following steps: manufacturing an intermediate plate A provided with a line substrate pattern on both sides; setting a composite insulating layer composed of at least two layers of different types of film layers on both sides of the intermediate plate A, and obtaining an intermediate plate B after hot pressing, compression and sectional curing; processing a profiled groove matching with the shape of the line substrate pattern on the composite insulating layer, and completely exposing the line substrate pattern; cleaning and activating the profiled groove and the line substrate pattern, and performing a bottom-up electroplating copper growth operation in the profiled groove until the profiled groove is filled with the electroplated copper layer, and a line pattern sketch is obtained; and grinding off the part of the line pattern sketch protruding outside the profiled groove, and obtaining a line pattern with a copper thickness of greater than or equal to 200 microns and a line spacing of 20-30 microns. The processing method is simple and easy to implement, the obtained line pattern can bear large current and high-density interconnection, and the technical requirement of a power management integrated circuit is met.

Description

Technical Field

[0001] This invention relates to the field of power management integrated circuit technology, and in particular to a high current-carrying embedded thick copper fine circuit substrate and its processing method. Background Technology

[0002] Power management integrated circuits (PMICs) are core chips in modern electronic devices such as smartphones, tablets, and wearable devices, responsible for all power-related management, distribution, conversion, and monitoring functions. With the surge in demand for high-voltage, high-current applications in fields such as artificial intelligence (AI) data centers and new energy vehicles, PMIC chips are rapidly evolving towards higher power density and higher integration. To meet the demands of high-current transmission and high-density packaging, the substrate supporting the PMIC chip requires the following technical parameters: a copper thickness of at least 200 μm for the circuit substrate pattern, and a fine line spacing of 20–30 μm.

[0003] However, there are significant shortcomings in using traditional circuit fabrication processes to process the aforementioned ultra-thick copper, micro-pitch circuits, such as: ① When using the subtractive etching method to fabricate circuits, the entire board needs to be electroplated to a copper thickness of over 200μm before chemical etching is used to form the circuits. However, due to the excessive copper thickness, the side etching effect is severe during etching, making it impossible to precisely control the line spacing of 20-30μm; moreover, the etching time is long, resulting in low production efficiency.

[0004] ② When fabricating circuits using the additive method, the copper layer needs to be selectively thickened by electroplating the dry film pattern. However, since the target copper plating thickness is over 200μm, the required dry film thickness is also very thick. Existing dry film technology cannot easily achieve fine openings of 20-30μm, resulting in insufficient pattern resolution.

[0005] ③ The local copper thickness can be increased by selectively electroplating the surface of the board with the circuit substrate pattern. However, this method is mainly used to compensate for the microscopic height difference caused by etching of the circuit substrate pattern and improve the solderability of the pads; but when the target copper thickness is more than 200μm, this method faces problems such as long electroplating time, dry film inability to support the substrate, and severe side etching of the circuit, so it is impossible to produce a circuit structure with both high current carrying capacity and micro pitch.

[0006] In view of this, the present invention is hereby proposed. Summary of the Invention

[0007] To overcome the above-mentioned defects, the present invention provides a high current-carrying embedded thick copper fine circuit substrate and its processing method. The processing method is simple, reasonable, flexible and easy to implement, and produces embedded circuit patterns with a copper thickness ≥200μm and a line spacing of 20~30μm. It can both carry high current and achieve high-density interconnection, which well meets the technical requirements of power management integrated circuits for packaging substrates.

[0008] The technical solution adopted by this invention to solve its technical problem is: a processing method for a high current-carrying embedded thick copper fine circuit substrate, comprising: An intermediate board A is fabricated with circuit substrate patterns formed on both sides. The copper thickness of the circuit substrate patterns is ≤20μm, the line spacing is 20~30μm, and the two layers of the circuit substrate patterns are electrically connected. A composite insulating layer consisting of at least two different types of film layers is stacked on both sides of the intermediate plate A, where the circuit substrate pattern is provided. After hot pressing, a segmented curing process is performed to obtain the intermediate plate B. In the obtained intermediate plate B, the thickness of the two composite insulating layers is 200-220 μm, and the peel strength between each composite insulating layer and its adjacent circuit substrate pattern, as well as between any two adjacent film layers in each composite insulating layer, reaches 0.8 N / mm or more. Using laser grooving technology, contoured grooves matching the shape of the circuit substrate are respectively processed on the two composite insulation layers to fully expose the circuit substrate pattern; After cleaning and activating the contoured groove and the circuit substrate pattern located therein, a bottom-up electroplating copper growth operation is performed in the contoured groove until the contoured groove is filled with an electroplated copper layer, thus obtaining a circuit pattern prototype composed of the circuit substrate pattern and the electroplated copper layer. The portion of the circuit pattern protruding beyond the contoured groove is ground away to obtain a circuit pattern with a copper thickness ≥200μm and a line spacing of 20~30μm.

[0009] As a further improvement of the present invention, the composite insulating layer is composed of a BF film and a PI film stacked together, and the BF film is located between the PI film and the side of the intermediate plate A on which the circuit substrate pattern is provided.

[0010] As a further improvement of the present invention, the thickness of the PI film is 180-200 μm, and the thickness of the BF film is 20-40 μm; The processing parameters for hot pressing are as follows: vacuum degree ≤ 50 Pa, pressing temperature 80~120℃, pressing pressure 0.3~1.5 MPa, and pressing time 10~30 min; The processing parameters for the above-mentioned segmented curing process are as follows: first, pre-curing at 120℃±5℃ for 20 minutes, then curing at 150℃±5℃ for 20 minutes, and finally curing at 190℃±5℃ for 60 minutes.

[0011] As a further improvement of the present invention, in the obtained intermediate board B, the peel strength between each BF film and its adjacent circuit substrate pattern and PI film reaches more than 0.8 N / mm; and the intermediate board B does not delaminate or produce microcracks after 1000 thermal cycles at -55℃ to 125℃.

[0012] As a further improvement of the present invention, in the obtained intermediate plate B, the thickness uniformity of the two composite insulating layers is controlled within ±5μm, and the surface roughness Ra≤0.3μm.

[0013] As a further improvement of the present invention, the processing conditions of the above-mentioned laser grooving process are as follows: a CO2 laser or a UV laser is used, the laser power is 10-30W, the laser frequency is 20-50KHz, the laser pulse width is 10-30μs, the laser scanning speed is 100-500mm / s, and the number of laser scans is 2-5. The width of the contoured groove is 1.2 to 1.8 times the line width of the circuit base pattern; in addition, based on the horizontal placement of the intermediate plate B, the inclination angle of the sidewall of the contoured groove relative to the horizontal plane is 70° to 90°.

[0014] As a further improvement of the present invention, the contoured groove and the circuit substrate pattern therein are subjected to plasma cleaning and micro-etching activation treatment to remove organic residues and control the surface contact angle of the circuit substrate pattern to be less than 20°. In addition, the processing parameters for the plasma cleaning process are as follows: a mixed gas composed of oxygen and carbon tetrafluoride is used, the radio frequency power is 500-1000W, and the processing time is 5-10min; the micro-etching amount for the micro-etching activation process on the circuit substrate pattern is controlled at 0.5-1.5μm.

[0015] As a further improvement of the present invention, the processing parameters for the above-mentioned electroplating copper growth operation are: current density of 1 to 10 A / dm². 2 The electroplating time is 60 to 210 minutes.

[0016] As a further improvement of the present invention, a non-woven fabric brush wheel and / or a ceramic brush wheel are used to grind the whole board to grind away the part of the circuit pattern protruding outside the contour groove, thereby obtaining the circuit pattern, and at the same time obtaining a semi-finished product with a surface flatness ≤ ±5μm and a surface roughness Ra ≤ 0.2μm. The obtained semi-finished product is subjected to routine operations such as solder resist, surface treatment, molding, finished product testing and inspection, shipment inspection, and packaging and shipping to obtain the high current-carrying embedded thick copper fine circuit board.

[0017] The present invention also provides a high current-carrying embedded thick copper fine circuit board, which is manufactured using the processing method of the high current-carrying embedded thick copper fine circuit board as described in the present invention.

[0018] The beneficial effects of this invention are as follows: Compared with the prior art, this invention has the following advantages: ① Through process innovation, this invention adopts a processing method consisting of "firstly fabricating a circuit substrate pattern with thin copper micro-pitch characteristics, then laminating and pressing, then laser-firing contoured grooves, then performing bottom-up electroplating growth of copper, and then grinding and shaping," to produce embedded circuit patterns with a copper thickness ≥200μm and a line spacing of 20-30μm; it can achieve both high current carrying capacity (≥50A) and high-density interconnection, well meeting the technical requirements of power management integrated circuits for packaging substrates. ② By adopting the preferred bottom-up electroplating growth copper operation method, this invention not only makes the electroplating filling process more controllable, reliable, and of higher quality, but also greatly enhances the bonding force between the electroplated copper layer and other components, effectively preventing circuit peeling problems caused by thermal expansion under high current carrying capacity applications; it also significantly reduces the processing difficulty of the electroplating solution system, improves the mass production yield (up to 95% or more), and expands the application fields, providing technical support for future substrates with higher integration. ③ In the fabrication of intermediate plate B, this invention employs an optimized hot-pressing and segmented curing process. This ensures that the resulting intermediate plate B possesses excellent interlayer bonding strength and a very firm bond. Furthermore, it controls the thickness uniformity of the composite insulating layer to within ±5μm and the surface roughness Ra≤0.3μm, providing a high-precision reference surface for subsequent laser grooving operations. ④ This invention optimizes the contoured groove structure, facilitating subsequent electroplating filling and preventing voids, thus effectively guaranteeing the processing quality of subsequent copper electroplating growth operations. ⑤ The processing method provided by this invention is simple, easy to implement in production, effectively reducing production costs and improving production efficiency. Attached Figure Description

[0019] Figure 1 This is a flowchart of the high current-carrying embedded thick copper fine circuit board processing method described in Embodiment 1 of the present invention; Figure 2 This is a schematic cross-sectional view of the intermediate plate A obtained in Embodiment 1 of the present invention; Figure 3 This is a schematic cross-sectional view of the intermediate plate B obtained in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the cross-sectional structure after the contoured groove is machined on the obtained intermediate plate B in Embodiment 1 of the present invention; Figure 5 This is a partial cross-sectional view of the high current-carrying embedded thick copper fine circuit board obtained in Embodiment 1 of the present invention.

[0020] Referring to the accompanying drawings, the following explanations are provided: 1. Circuit substrate pattern; 2. Composite insulation layer; 20. Contouring groove; 21. BF film; 22. PI film; 3. Electroplated copper layer; 4. Circuit pattern; 5. Insulating intermediate layer; 6. Connecting copper layer. Detailed Implementation

[0021] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Example 1:

[0023] Please see the appendix Figure 1 To be continued Figure 5 As shown, this embodiment 1 provides a method for processing a high current-carrying embedded thick copper fine circuit board, including the following processing steps: S1: Fabricate an intermediate board A, on both opposite sides of the intermediate board A, a circuit substrate pattern 1 is formed, the copper thickness of the two circuit substrate patterns 1 is ≤20μm, the line spacing is 20~30μm, and the two circuit substrate patterns 1 are electrically connected.

[0024] Regarding the intermediate board A, its specific implementation structure and manufacturing method are determined according to product design requirements, and this application does not impose any restrictions. However, in order to clearly and thoroughly explain the processing method of the high current-carrying embedded thick copper fine circuit board provided in this application, this application adopts the following subtractive method to manufacture the intermediate board A, specifically as follows: S11: Provide a double-sided copper-clad laminate, wherein the double-sided copper-clad laminate has an insulating intermediate layer 5 and two thin copper layers respectively fixed on opposite sides of the insulating intermediate layer 5. The insulating intermediate layer 5 may be, but is not limited to, a prepreg, and the thickness of the insulating intermediate layer 5 is preferably controlled to be 60-200 μm, and the thickness of the thin copper layers is preferably controlled to be 12-18 μm.

[0025] S12: The double-sided copper-clad laminate is sequentially subjected to drilling, whole-board copper plating, electroplating, film coating, exposure, development, etching, and film removal to create the circuit substrate pattern 1, which is the intermediate board A; see appendix for details. Figure 2 As shown.

[0026] Furthermore, the aforementioned drilling refers to drilling tool holes (such as alignment holes) and interlayer through holes (such as X-shaped through holes) at preset positions on the double-sided copper-clad laminate using mechanical drilling or laser drilling methods.

[0027] The aforementioned whole-board copper plating and electroplating refer to the deposition of a seed layer (approximately 0.5–1.5 μm thick) on the entire surface of the intermediate board A, the interlayer vias, and the inner walls of the tool holes using a chemical copper plating process. Then, a via-filling electroplating process is used to fully plating copper into the interlayer vias to create a connecting copper layer 6 that links the two thin copper layers, and to thicken the two thin copper layers. Specifically, the thickness of the thickened thin copper layer must still be controlled within 20 μm to lay the foundation for subsequent fabrication of fine circuit patterns.

[0028] The aforementioned coating, exposure, and development process refers to the process of applying a photosensitive dry film onto two thickened thin copper layers using a vacuum laminator, exposing a portion of the photosensitive dry film according to the work instructions and using an LDI exposure machine, and then removing the unexposed areas of the photosensitive dry film using a development machine.

[0029] Understandably, since the thickness of the thin copper layer is relatively thin (≤20μm), a photosensitive dry film with a standard thickness (such as 30-50μm) can be used to create a dry film pattern with a film spacing of 20-30μm, which lays the foundation for the subsequent production of fine circuit patterns with a line spacing of 20-30μm.

[0030] The above-mentioned etching and film removal refer to using an acidic etching solution to etch away the part of the thin copper layer that is exposed outside the photoresist dry film, and then using a film removal solution to remove the photoresist dry film, thus creating a two-layer circuit substrate pattern 1, which is the intermediate board A.

[0031] Based on the above method for manufacturing intermediate board A, the specific implementation structure of intermediate board A in this embodiment is as follows: Please refer to the appendix. Figure 2 As shown, the circuit includes an insulating intermediate layer 5 and two circuit substrate patterns 1 fixedly disposed on opposite sides of the insulating intermediate layer 5. The copper thickness of the two circuit substrate patterns 1 is ≤20μm and the line spacing is 20~30μm. That is, the circuit substrate pattern 1 exhibits the characteristics of "thin copper and micro line spacing", which lays the foundation for the subsequent production of circuit pattern 4 that meets the technical requirements of "ultra-thick copper (copper thickness ≥200μm) and micro line spacing (line spacing is 20~30μm)". The two circuit substrate patterns 1 are also electrically connected through the connecting copper layer 6.

[0032] In addition, after the intermediate board A is manufactured, this embodiment also performs a 100% visual inspection of the circuit substrate pattern 1 to ensure the quality of the pattern processing.

[0033] S2: A composite insulating layer 2, consisting of at least two layers of different types of film, is stacked on both sides of the intermediate board A, where the circuit substrate pattern 1 is provided. Then, hot pressing and segmented curing processes are performed sequentially to obtain the intermediate board B. For details, please refer to the appendix. Figure 3 As shown. In particular, in the obtained intermediate board B, the thickness of the two composite insulating layers 2 is 200-220 μm, which lays the foundation for the subsequent fabrication of the circuit pattern 4 that meets the technical requirements of "ultra-thick copper (copper thickness ≥ 200 μm) and micro-spacing (spacing of 20-30 μm)".

[0034] Furthermore, in this embodiment, the composite insulating layer 2 preferably adopts the following structure: Please refer to the appendix. Figure 3 As shown, the composite insulating layer 2 is composed of a stacked BF film 21 (i.e., a multilayer insulating film) and a PI film 22 (i.e., a polyimide film). The BF film 21 is arranged between the PI film 22 and the side of the intermediate plate A on which the circuit substrate pattern 1 is provided. The thickness of the PI film 22 is preferably controlled to be 180-200 μm, and the thickness of the BF film 21 is preferably controlled to be 20-40 μm.

[0035] Understandably, the PI film 22 possesses an extremely high glass transition temperature (greater than 250°C), a low coefficient of thermal expansion (approximately 10–20 ppm / °C), and excellent high-temperature and chemical resistance, providing stable dimensional support for the intermediate board B and the subsequently obtained substrate product, and matching the thermomechanical behavior of the chip and copper circuitry. The BF film 21 exhibits excellent thermorheological properties, fully filling the micro-gaps / micro-spacings between the circuit substrate patterns 1 during hot pressing, and tightly wrapping the sidewalls of the circuit substrate patterns 1 (the BF film 21 has naturally good adhesion to the copper surface), effectively eliminating voids and improving bonding quality. In other words, by optimizing the structure of the composite insulating layer 2 as described above, while meeting the technical requirements of "ultra-thick copper," the technical requirements of substrate insulation reliability and thermomechanical stability under high frequency and high voltage are also ensured.

[0036] Additional notes: The BF film 21 and the PI film 22 are generally refrigerated (below 5°C). Therefore, before lamination, the BF film 21 and the PI film 22 are thawed for 8 hours at 5°C to 10°C, and then placed in an environment with a temperature of 23°C ± 2°C and a humidity of 50 ± 10% for 4 hours to fully release storage stress and prevent air bubbles from forming during pressing due to moisture absorption or thermal shock. After completing the above pretreatment, the intermediate plate A, the BF film 21, and the PI film 22 are then stacked.

[0037] Furthermore, based on the implementation structure of the composite insulation layer 2, this embodiment optimizes the processing parameters of the hot pressing as follows: ① Vacuum degree ≤ 50 Pa, which can effectively eliminate pores; ② Pressing temperature is 80-120℃, lower than the complete curing temperature of the BF film 21, thereby ensuring that the molten BF colloid flows fully and does not crosslink prematurely; ③ Pressing pressure is 0.3-1.5 MPa, and pressing time is 10-30 min. Further, at the above vacuum degree and pressing temperature, this embodiment first presses at 0.3-0.6 MPa for 2-5 min to promote the full flow and filling of the molten BF colloid; then the pressure is increased to the target pressure to expel excess gas and colloid, achieving complete wetting of the circuit substrate pattern 1 surface by the BF colloid.

[0038] After completing the above hot pressing, to avoid excessive internal stress at the interface between the BF material and PI material due to the difference in their coefficients of thermal expansion, which could lead to delamination or bubbles, this embodiment preferably adopts a segmented curing process to cure the BF material and PI material. Specifically, the process is as follows: first, pre-curing is performed at 120℃±5℃ for 20 minutes (which can be understood as the low-temperature pre-curing stage) to allow the BF colloid to begin cross-linking and release residual pressure from the pressing; then, curing is performed at 150℃±5℃ for 20 minutes (which can be understood as the medium-temperature transition stage) to further cure the BF colloid and allow the PI material layer to gradually adapt to thermal expansion; finally, curing is performed at 190℃±5℃ for 60 minutes (which can be understood as the high-temperature complete curing stage) to allow the BF material to reach a fully cured state and achieve interdiffusion and chemical bonding of the molecular chains at the interface between the BF material and the PI material.

[0039] Through production verification, using the optimized hot-pressing and segmented curing processes described above, the peel strength between each BF film 21 and its adjacent circuit substrate pattern 1 and PI film 22 in the resulting intermediate board B reaches 0.8 N / mm or higher. Furthermore, the resulting intermediate board B exhibits no delamination or microcracks after 1000 thermal cycles at -55℃ to 125℃. Therefore, it can be understood that the resulting intermediate board B possesses excellent interlayer bonding strength and a very strong adhesion.

[0040] In addition, by means of the optimized hot pressing process and segmented curing process, after the intermediate plate B is made, the thickness uniformity of the two composite insulating layers 2 is controlled within ±5μm and the surface roughness Ra≤0.3μm; which can provide a high-precision reference surface for subsequent laser grooving operation.

[0041] Furthermore, to prevent excessive overflow of the BF material during hot pressing and contamination of the target area or uneven thickness, this embodiment also incorporates the following process improvements: ① A release film and a buffer pad are placed between the composite insulation layer 2 and the pressing steel plate. ② The gelation time of the BF material is controlled, such as hot pressing at 120°C for 3-4 minutes, to ensure that it quickly enters a semi-cured state after completely filling the micro-gaps of the circuit substrate pattern 1, thus limiting excessive flow.

[0042] S3: Using laser grooving technology, contoured grooves 20 matching the shape of the circuit substrate pattern 1 are respectively processed on the two composite insulation layers 2 to completely expose the circuit substrate pattern 1; see appendix for details. Figure 4 As shown.

[0043] Furthermore, based on the absorption characteristics of the composite insulating layer 2 material to the laser wavelength, the processing conditions of the above-mentioned laser grooving process are optimized as follows: using a CO2 laser or a UV laser, with a laser power of 10-30W, a laser frequency of 20-50KHz, a laser pulse width of 10-30μs, a laser scanning speed of 100-500mm / s, and 2-5 laser scans.

[0044] Furthermore, to ensure the processing quality of subsequent electroplating copper growth operations, this embodiment also optimizes the structure of the contoured groove 20 as follows: ① The width of the contoured groove 20 is 1.2 to 1.8 times the line width of the circuit substrate pattern 1. For example, when the line width of the circuit substrate pattern 1 is 30 μm, the width of the contoured groove 20 can be 40 to 50 μm. Additionally, there are gaps between both sides of the circuit substrate pattern 1 in the width direction and the inner wall of the contoured groove 20 (see Appendix). Figure 4 As shown), to facilitate subsequent electroplating filling. ② Based on the horizontal placement of the intermediate plate B, the inclination angle of the sidewall of the contoured groove 20 relative to the horizontal plane is 70° to 90°, that is, the sidewall of the contoured groove 20 is relatively steep, which further facilitates subsequent electroplating filling and avoids voids.

[0045] S4: First, plasma cleaning and micro-etching activation treatment are performed on the contoured groove 20 and the circuit substrate pattern 1 located therein to remove organic residues (such as glue residue and residual carbides) and to control the surface contact angle of the circuit substrate pattern 1 to less than 20°, so as to ensure good bonding between the electroplated copper layer 3 and the circuit substrate pattern 1 during subsequent electroplating operations; then, a bottom-up electroplating copper growth operation is performed in the contoured groove 20 until the contoured groove 20 is filled with the electroplated copper layer 3, to obtain a circuit pattern prototype composed of the circuit substrate pattern 1 and the electroplated copper layer 3.

[0046] Furthermore, the optimal processing parameters for the plasma cleaning treatment are as follows: a mixed gas consisting of oxygen and carbon tetrafluoride in a volume ratio of 80:20 is used, the radio frequency power is 500-1000W, and the processing time is 5-10min; in order to achieve efficient removal of organic residues.

[0047] The amount of micro-etching activated by the above-mentioned micro-etching treatment on the circuit substrate pattern 1 is controlled at 0.5 to 1.5 μm, so as to remove the oxide layer, increase the surface roughness (Ra controlled at 0.3 to 0.5 μm), and improve the adhesion between the subsequent electroplated copper layer 3 and the circuit substrate pattern 1.

[0048] Understandably, based on the above-mentioned structural optimization of the contoured groove 20, combined with the above-mentioned cleaning and activation treatment, 100% void-free electroplating filling can be achieved, laying the foundation for ensuring the processing quality of the subsequent circuit pattern.

[0049] Furthermore, unlike traditional processes that combine whole-plate copper plating with through-hole plating, and where the plating current grows simultaneously from the bottom and side walls of the groove towards the center during plating, this embodiment preferably employs a bottom-up copper plating process. That is, the plating current can only be transmitted through the circuit substrate pattern 1 at the bottom of the contoured groove 20 to the interior of the contoured groove 20, forming a unidirectional, bottom-up copper growth process until the entire contoured groove 20 is completely filled, thus obtaining the electroplated copper layer 3.

[0050] Understandably, this embodiment achieves the following benefits by improving the copper electroplating process as described above: ① Since the electroplated copper layer grows only from the bottom of the contoured groove 20, there is no clamping or bridging phenomenon caused by multi-directional growth, making the filling process more controllable, reliable, and of higher quality. That is, the electroplating process provided in this embodiment greatly enhances the bonding force between the electroplated copper layer 3 and other components, effectively preventing line stripping problems caused by thermal expansion under high current-carrying applications. ② Compared with traditional electroplating processes, the electroplating process provided in this embodiment does not require a complex additive system to inhibit copper growth at the top of the tank or promote copper deposition at the bottom of the tank. It only needs to maintain the stability of the conventional electroplating solution, thus reducing the processing difficulty of the electroplating solution system. ③ Compared with traditional electroplating processes where the yield is less than 70% when filling grooves with a depth-to-width ratio greater than 3, the electroplating process provided in this embodiment has a higher tolerance for fluctuations in process parameters, and the mass production yield can reach over 95%. ④ The electroplating operation provided in this embodiment is applicable to filling grooves with a depth-to-width ratio of not less than 5, which is highly versatile and can provide technical support for future substrates with higher integration.

[0051] Additional explanation: The aforementioned clamping phenomenon refers to the situation where, when filling grooves with a high aspect ratio using traditional electroplating processes, the top of the groove closes prematurely, leaving a hole inside. The aforementioned bridging phenomenon refers to the situation where, when filling grooves with a high aspect ratio using traditional electroplating processes, due to the higher current density near the groove opening and the faster copper deposition rate, the top of the groove may "bridge" and close before it is completely filled, resulting in voids or gaps inside the groove.

[0052] Furthermore, to meet product manufacturing requirements, this embodiment optimizes the processing parameters for the electroplating copper growth operation to: a current density of 1–10 A / dm². 2 The electroplating time is 60–210 minutes. As for the electroplating solution, any commonly used electroplating solution in the industry can be used, so it will not be described in detail here.

[0053] Understandably, since this embodiment adopts a bottom-up electroplating mechanism, which ensures the electroplating filling sequence, electroplating can be performed directly using a constant current density, simplifying the electroplating process.

[0054] S5: Use a non-woven fabric brush wheel and / or a ceramic brush wheel to grind the entire board, removing the portion of the circuit pattern protruding beyond the contoured groove 20, to obtain a circuit pattern 4 with a copper thickness ≥200μm and a line spacing of 20~30μm, and simultaneously obtain a semi-finished product with a surface flatness ≤±5μm and a surface roughness Ra≤0.2μm; see appendix for details. Figure 5 As shown.

[0055] Furthermore, during the whole-board grinding, a coarse grinding process is first performed using a #600 to #1200 non-woven fabric brush wheel / or ceramic brush wheel at a removal rate of 5 to 10 μm / min, followed by a fine grinding process using a #2000 to #4000 non-woven fabric brush wheel / or ceramic brush wheel at a removal rate of 1 to 2 μm / min. This ensures that the resulting circuit pattern 4 is highly coplanar with the composite insulating layer 2 (understandably, the resulting circuit pattern 4 exhibits an embedded structure relative to the composite insulating layer 2), thereby ensuring the flatness of subsequent multilayer circuit stacking and the reliability of chip mounting.

[0056] In addition, after completing the whole-board grinding operation, this embodiment also performs deionized water ultrasonic cleaning (to remove grinding debris) and drying treatment (using 60°C hot air or nitrogen to dry).

[0057] In addition, after obtaining the semi-finished product, this embodiment also conducts a 100% visual inspection of the circuit pattern 4 to ensure the quality of the pattern processing.

[0058] S6: The obtained semi-finished product undergoes routine solder resist application (i.e., applying solder resist ink to designated locations on the board surface), surface treatment (i.e., applying a surface treatment layer to designated locations on the circuit pattern 4; the surface treatment layer may be, but is not limited to, electroplated soft gold, electroless nickel-palladium-gold, or electroless nickel-gold layers), molding, finished product testing and inspection, outgoing inspection, packaging and shipping, etc., to obtain the high current-carrying embedded thick copper fine circuit board; see appendix for details. Figure 5 As shown.

[0059] As can be seen from the above, compared with the existing technology, ① this embodiment, through process innovation, adopts a processing method consisting of "firstly fabricating a circuit substrate pattern with thin copper micro-spacing characteristics, then laminating and pressing, then laser-firing contoured grooves, then performing bottom-up electroplating growth of copper, and then grinding and shaping," to produce an embedded circuit pattern 4 with a copper thickness ≥200μm and a line spacing of 20-30μm; it can both carry high current (≥50A) and achieve high-density interconnection, which well meets the technical requirements of power management integrated circuits for packaging substrates. ② This embodiment, by adopting the preferred bottom-up electroplating growth of copper operation method, not only makes the electroplating filling process more controllable, reliable, and of high quality, but also greatly enhances the bonding force between the electroplated copper layer and other components, effectively preventing circuit peeling problems caused by thermal expansion under high current carrying capacity applications; it also significantly reduces the processing difficulty of the electroplating solution system, improves the mass production yield (up to 95% or more), and expands the application field, providing technical support for future substrates with higher integration. ③ In this embodiment, an optimized hot-pressing and segmented curing process is adopted when manufacturing the intermediate plate B. On the one hand, this results in the intermediate plate B having excellent interlayer bonding and a very strong bond. On the other hand, it ensures that the thickness uniformity of the composite insulating layer 2 is controlled within ±5μm and the surface roughness Ra≤0.3μm, providing a high-precision reference surface for subsequent laser grooving operations. ④ This embodiment optimizes the structure of the contoured groove 20, which is beneficial for subsequent electroplating filling and avoids voids, thus ensuring the processing quality of subsequent copper electroplating growth operations. ⑤ The processing method provided in this embodiment is simple, easy to implement in production, effectively reduces production costs, and improves production efficiency.

[0060] Example 2:

[0061] This embodiment 2 provides a high current-carrying embedded thick copper fine circuit board, which is manufactured using the processing method of the high current-carrying embedded thick copper fine circuit board provided in embodiment 1 above.

[0062] Specifically, the structure of the high current-carrying embedded thick copper fine circuit board provided in this embodiment 2 is as follows: Please refer to the attached document. Figure 5As shown, the circuit includes an insulating intermediate layer 5 and two circuit patterns 4 fixedly disposed on opposite sides of the insulating intermediate layer 5. The copper thickness of the two circuit patterns 4 is ≥200μm, and the line spacing is 20-30μm. That is, both circuit patterns 4 exhibit ultra-thick copper and fine circuitry with micro-gap / micro-spacing. The two circuit patterns 4 are also electrically connected through the connecting copper layer 6. In addition, each circuit pattern 4 has a composite insulating layer 2 filling the gaps between its lines, and each circuit pattern 4 is flush with its corresponding composite insulating layer 2, so that the circuit pattern 4 exhibits an embedded structure.

[0063] Understandably, the high current-carrying embedded thick copper fine circuit substrate provided in this embodiment 2 can both carry large current and achieve high-density interconnection, which well meets the technical requirements of power management integrated circuits for packaging substrates.

[0064] Finally, it should be noted that the suffixes "A", "B", etc. in the component names in this application specification (such as intermediate plate A, intermediate plate B, etc.) are only for the purpose of clarity of description and are not intended to limit the scope of implementation of this invention patent.

[0065] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for processing a high current-carrying embedded thick copper fine circuit board, characterized in that: include: An intermediate board A is fabricated with a circuit substrate pattern (1) on both sides. The copper thickness of the circuit substrate pattern (1) is ≤20μm and the line spacing is 20~30μm. The two layers of the circuit substrate pattern (1) are electrically connected. A composite insulating layer (2) composed of at least two different types of film layers is stacked on both sides of the intermediate plate A, which is provided with the circuit substrate pattern (1). After hot pressing, a segmented curing process is performed to obtain the intermediate plate B. In the obtained intermediate plate B, the thickness of the two composite insulating layers (2) is 200-220 μm, and the peel strength between each composite insulating layer (2) and its adjacent circuit substrate pattern (1), as well as between any two adjacent film layers in each composite insulating layer (2), is 0.8 N / mm or more. Using laser grooving technology, contoured grooves (20) matching the shape of the circuit substrate pattern (1) are respectively processed on the two composite insulation layers (2) to completely expose the circuit substrate pattern (1). After cleaning and activating the contoured groove (20) and the circuit substrate pattern (1) located therein, a bottom-up electroplating copper growth operation is performed in the contoured groove (20) until the contoured groove (20) is filled with an electroplated copper layer (3) to obtain a circuit pattern prototype composed of the circuit substrate pattern (1) and the electroplated copper layer (3). The portion of the circuit pattern protruding beyond the contoured groove (20) is ground away to obtain a circuit pattern (4) with a copper thickness ≥200μm and a line spacing of 20~30μm.

2. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 1, characterized in that: The composite insulation layer (2) is composed of a BF film (21) and a PI film (22) stacked together, and the BF film (21) is located between the PI film (22) and the side of the intermediate plate A on which the circuit substrate pattern (1) is provided.

3. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 2, characterized in that: The thickness of the PI film (22) is 180-200 μm, and the thickness of the BF film (21) is 20-40 μm; The processing parameters for hot pressing are as follows: vacuum degree ≤ 50 Pa, pressing temperature 80~120℃, pressing pressure 0.3~1.5 MPa, and pressing time 10~30 min; The processing parameters for the above-mentioned segmented curing process are as follows: first, pre-curing at 120℃±5℃ for 20 minutes, then curing at 150℃±5℃ for 20 minutes, and finally curing at 190℃±5℃ for 60 minutes.

4. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 3, characterized in that: In the obtained intermediate plate B, the peel strength between each BF film (21) and its adjacent circuit substrate pattern (1) and PI film (22) reaches more than 0.8 N / mm; and the intermediate plate B does not delaminate or produce microcracks after 1000 thermal cycles at -55℃ to 125℃.

5. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 3, characterized in that: In the obtained intermediate plate B, the thickness uniformity of the two composite insulating layers (2) is controlled within ±5μm, and the surface roughness Ra≤0.3μm.

6. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 1, characterized in that: The processing conditions for the above laser grooving process are as follows: a CO2 laser or a UV laser is used, the laser power is 10-30W, the laser frequency is 20-50KHz, the laser pulse width is 10-30μs, the laser scanning speed is 100-500mm / s, and the number of laser scans is 2-5. The width of the contoured groove (20) is 1.2 to 1.8 times the line width of the circuit base pattern (1); in addition, based on the horizontal placement of the intermediate plate B, the inclination angle of the side wall of the contoured groove (20) relative to the horizontal plane is 70° to 90°.

7. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 1, characterized in that: Plasma cleaning and micro-etching activation treatment are performed on the contoured groove (20) and the circuit substrate pattern (1) located therein to remove organic residues and control the surface contact angle of the circuit substrate pattern (1) to be less than 20°. In addition, the processing parameters of the plasma cleaning process are as follows: a mixed gas composed of oxygen and carbon tetrafluoride is used, the radio frequency power is 500-1000W, and the processing time is 5-10min; the amount of micro-etching activated by the micro-etching process on the circuit substrate pattern (1) is controlled at 0.5-1.5μm.

8. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 1, characterized in that: The processing parameters for the above-mentioned electroplating copper growth operation are: current density of 1-10 A / dm³. 2 The electroplating time is 60 to 210 minutes.

9. The processing method of the high current-carrying embedded thick copper fine circuit board according to claim 1, characterized in that: The entire board is ground using non-woven fabric brush wheels and / or ceramic brush wheels to grind away the part of the circuit pattern protruding outside the contour groove (20) to obtain the circuit pattern (4), and at the same time obtain a semi-finished product with surface flatness ≤ ±5μm and surface roughness Ra≤0.2μm; The obtained semi-finished product is subjected to routine operations such as solder resist, surface treatment, molding, finished product testing and inspection, shipment inspection, and packaging and shipping to obtain the high current-carrying embedded thick copper fine circuit board.

10. A high current-carrying embedded thick copper fine circuit board, characterized in that: It is manufactured using the processing method of any one of claims 1-9 for a high current-carrying embedded thick copper fine circuit board.

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