Processing method of PTFE-based copper clad plate for high frequency circuit

Abstract

This invention discloses a processing method for PTFE-based copper-clad laminates for high-frequency circuits, comprising the following steps: The operator must wear clean cotton gloves throughout the entire blanking process; after inner layer etching, the lamination process is initiated within 4 hours, followed by browning treatment and baking at 115-125℃ for 1-2 hours, then lamination is completed within 4 hours; the drilling retraction speed is controlled at 40%-60% of the conventional FR-4 process retraction speed, and after drilling, the board is baked at 110-125℃ for 60-90 minutes; the drilled and baked PTFE board undergoes plasma treatment, followed by chemical copper plating within 4 hours; pre-copper plating treatment only involves high-pressure water washing, and the brush section is prohibited; pre-circuit pre-treatment only involves acid washing and sandblasting, and the brush section is prohibited, with the etching tolerance of key RF lines controlled within ±0.5mil; the forming process uses a counter-clockwise milling path, with the milling cutter life reduced by 30% and the feed rate reduced to 50% of the standard speed; after the finished product passes inspection, it is baked at 150℃ for 3 hours. The present invention provides a method for processing PTFE-based copper-clad laminates for high-frequency circuits, which systematically solves the problems of easy contamination, easy moisture absorption, easy mechanical damage, and low reliability of hole metallization in the processing of PTFE substrates in the prior art.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) manufacturing technology, and specifically to a processing method for PTFE-based copper-clad laminates for high-frequency circuits. Background Technology

[0002] With the rapid development of 5G communication, satellite navigation, and phased array radar technologies, the performance requirements for high-frequency circuit boards are becoming increasingly stringent. Polytetrafluoroethylene (PTFE) based copper clad laminates have become an ideal choice for high-frequency applications due to their extremely low dielectric loss, stable dielectric constant, and excellent weather resistance.

[0003] In existing technologies, the processing technology of PTFE substrates mostly borrows from or follows the manufacturing process of traditional FR-4 (epoxy glass cloth) copper clad laminates. For example, the conventional FR-4 substrate processing flow usually includes the following steps: blanking, inner layer circuitry, inner layer AOI, lamination, drilling, copper plating, pattern transfer, pattern electroplating, alkaline etching, solder mask, surface treatment, molding, testing, appearance inspection, and packaging.

[0004] However, PTFE material possesses unique physicochemical properties, such as extremely low surface energy (hydrophobic and oleophobic), softness, high coefficient of thermal expansion, hygroscopicity, and sensitivity to mechanical shock. Directly applying the FR-4 process to high-frequency circuit boards can lead to a series of serious quality problems, primarily manifested as follows:

[0005] 1. Moisture absorption and pollution out of control: PTFE materials are extremely prone to absorbing pollutants such as sweat and oil, which can lead to decreased adhesion and delamination during subsequent pressing and coating processes.

[0006] 2. Severe mechanical damage: Using conventional stacking, grinding, and drilling parameters can easily cause indentations, scratches, burrs at the hole openings, and internal delamination on the PTFE board surface. After the holes are metallized, cracks or open circuits are likely to occur.

[0007] 3. Poor dimensional stability: Due to the lack of strict control over the dwell time between processes, the PTFE substrate is prone to cracking or drastic dimensional changes after absorbing moisture, especially during subsequent high-temperature processes.

[0008] 4. Low reliability of hole metallization: Conventional pretreatment for chemical copper plating cannot effectively activate the PTFE surface, resulting in extremely poor adhesion between the chemical copper layer and the hole wall.

[0009] 5. High risk of thermal stress failure: Conventional post-curing and surface treatment process parameters are not matched with the temperature resistance characteristics of PTFE materials, which can easily lead to stress concentration inside the material and cause the board to explode.

[0010] Therefore, it is necessary to provide a processing method for PTFE-based copper-clad laminates for high-frequency circuits to solve the above-mentioned technical problems. Summary of the Invention

[0011] The purpose of this invention is to provide a processing method for PTFE-based copper-clad laminates for high-frequency circuits, so as to systematically solve the problems of easy contamination, easy moisture absorption, easy mechanical damage, and low reliability of hole metallization in the processing of PTFE substrates in the prior art.

[0012] A method for fabricating PTFE-based copper-clad laminates for high-frequency circuits includes the following steps:

[0013] Step S1, material cutting: Throughout the entire process, operators are required to wear clean cotton gloves, use steel frame turntables, and insert each cut board into a dedicated insert; stacking is strictly prohibited.

[0014] Step S2, Inner layer circuit and lamination: After the inner layer etching is completed, the lamination process is carried out within 4 hours. After browning treatment, it is baked at 115-125℃ for 1-2 hours, and then lamination is completed within 4 hours to prevent moisture absorption from causing lamination delamination. The lamination process adopts a special lamination program set for PTFE material, which is slow heating-long pressure holding-slow cooling.

[0015] Step S3, Drilling and Intermediate Baking: For boards with a thickness ≥ 1.5mm, drill holes per stack; for boards with a thickness ≤ 1.5mm, set the number of stacks according to the effective length of the drill bit, and the number of stacks is 80% of the standard board material, with each layer of PTFE board separated by white paper.

[0016] The retraction speed of the drill bit is controlled at 40%-60% of the retraction speed of the conventional FR-4 process. After drilling, in order to stabilize the dimensions and eliminate drilling stress, the hole is baked at 110-125℃ for 60-90 minutes, which helps to ensure the accuracy of the hole position after drilling.

[0017] Step S4, Plasma Activation: The drilled and baked PTFE board is subjected to plasma treatment, and chemical copper plating is completed within 4 hours after treatment.

[0018] Step S5, Copper Plating and Electroplating: The pretreatment for copper plating only involves high-pressure water washing, and the brush section must not be turned on; electroplating is performed immediately after copper plating is completed.

[0019] Step S6, Pattern Transfer and Etching: Only acid pickling and sandblasting are allowed in the pretreatment of the circuit; grinding is prohibited; the etching tolerance of key RF lines is controlled within ±0.5mil; the time from the completion of etching to the completion of solder mask silkscreen printing is controlled within 12 hours.

[0020] Step S7, solder resist and surface treatment;

[0021] Step S8, Shaping: Mill the plate path in a counterclockwise direction, reduce the milling cutter life by 30%, and reduce the feed rate to 50% of the standard speed;

[0022] Step S9, final curing and packaging: After the finished product passes inspection, it is baked at 150℃ for 3 hours, and immediately vacuum-packed with aluminum foil containing desiccant after cooling.

[0023] Furthermore, in the drilling step of step S3, the stacked plate structure consists of an upper cover plate, a PTFE plate, and a lower pad plate from top to bottom, wherein the upper cover plate is made of aluminum plate and phenolic board stacked together.

[0024] Furthermore, after the plasma activation step in step S4, there is also an effect detection step: draw lines on the treated PTFE test plate with a water-based pen. If the ink lines remain unchanged and do not shrink, the treatment is deemed qualified; if the ink lines shrink into water droplets, the treatment is deemed unqualified and needs to be reprocessed.

[0025] Furthermore, in the copper plating and electroplating steps of step S5, a thick edge strip 1-2 cm longer than the board is used to support the floating frame during electroplating and is fixed with a bottom clamping strip to prevent the board from deforming.

[0026] Furthermore, in the pattern transfer and etching step S6, the board to be processed is stored in a clean area with a temperature of 22±2℃ and a humidity of 50±5%.

[0027] Furthermore, in the forming step S8, the number of stacked plates is set according to 80% of the effective cutting length of the milling cutter, and the upper and lower plates are clamped with 1.0mm thick smooth plates, and the retraction speed is reduced by 30%.

[0028] Furthermore, boards that require rework should be scrapped immediately, and rewashing is prohibited.

[0029] Furthermore, in the surface treatment step S7, the surface treatment process uses immersion tin, immersion silver, or immersion gold.

[0030] Furthermore, when using tin plating as a surface treatment process, the tin plating temperature is below 255℃, and the pre-baking temperature before tin plating is 120-130℃.

[0031] Compared with the prior art, the processing method of PTFE-based copper-clad laminate for high-frequency circuits provided by the present invention has the following advantages:

[0032] The processing method of PTFE-based copper clad laminate for high-frequency circuits of the present invention effectively avoids the influence of sweat, oil stains and moisture on the substrate through full-process anti-pollution and strict control of dwell time, and completely solves the problems of high-temperature board explosion and delamination caused by moisture absorption and pollution.

[0033] Second, the processing method of the PTFE-based copper-clad laminate for high-frequency circuits of the present invention reduces hole wall damage through special drilling parameters; stress is eliminated by baking after drilling; and plasma activation and quantitative detection are combined to ensure that the hole wall obtains the best activation state, so that the bonding force between the chemical copper layer and the PTFE hole wall reaches more than 3 times that of the traditional process, eliminating the risk of hole wall separation.

[0034] Third, the processing method of the PTFE-based copper-clad laminate for high-frequency circuits of the present invention avoids internal delamination caused by mechanical processing stress by optimizing the stacking, drilling and milling parameters; by prohibiting rewashing and strictly controlling the etching to solder mask time, the stability of the circuit dimensions is guaranteed, and the tolerance of key radio frequency lines can be stably controlled within ±0.5mil.

[0035] IV. The processing method of the PTFE-based copper-clad laminate for high-frequency circuits of the present invention fully releases the internal stress of the material through multiple intermediate baking and final baking; the use of differentiated surface treatments such as low-temperature tin spraying avoids the impact of rapid heating and cooling on the PTFE material, enabling the product to pass the 260°C floating solder test without board explosion. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the stacked plate structure in the drilling process of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned objectives, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below.

[0039] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0040] Example 1

[0041] This embodiment provides a processing technology for PTFE-based copper-clad laminates for high-frequency circuits, used to process PTFE-based copper-clad laminates with a thickness of 1.5mm (approximately 59mil) and a dielectric constant DK=3.0, to manufacture a 5G power divider. The specific steps are as follows:

[0042] Step S1, material cutting:

[0043] Operators are required to wear clean cotton gloves throughout the entire process. In the cutting process, first use an air gun to blow away dust and debris from the work surface and the PCB separator; then cut the large PTFE substrate into the required working size; each cut board is inserted into a dedicated holder, and stacking is strictly prohibited to prevent indentations.

[0044] Step S2, Inner layer circuitry and lamination:

[0045] After the inner layer etching is completed, the board is transferred to the lamination process within 4 hours. After browning treatment, the board is baked at 120℃ for 1.5 hours, and then lamination is completed within 4 hours to prevent moisture absorption from causing delamination during lamination. The lamination process uses a PLC-controlled press, which calls a special lamination program set for PTFE material with "slow heating-long pressure holding-slow cooling".

[0046] Specifically, the pressing parameters are:

[0047] Heating rate: 1.0-2.0℃ / min;

[0048] Maximum temperature: Segmented heating, peak temperature 350°C-375°C;

[0049] Insulation time: 60-120 minutes (for boards with a thickness ≥3.0mm, extend by 15-20 minutes);

[0050] Pressure parameters: heating section 3.0-4.0 GPa, heat preservation section 3.5-4.5 GPa;

[0051] Cooling rate: 0.1-0.5℃ / min (slow cooling).

[0052] Step S3, Drilling and Intermediate Baking:

[0053] The board is 59 mil thick and drilled per stack. The stack structure is as follows: Figure 1 As shown, the stacked structure from top to bottom consists of: a 0.14mm aluminum plate + a 1mm phenolic board, a PTFE board to be drilled, and a 1mm backing plate.

[0054] During drilling, the spindle speed is maintained at 180,000 rpm, and the retraction speed is reduced to 0.9 m / min (1.5 m / min for conventional FR-4 process).

[0055] After drilling, immediately place the board in a clean oven and bake at 110-125℃ for 60-90 minutes to eliminate drilling pre-stress and ensure the accuracy of the hole positions after drilling. Before baking, check that there is no oil stain inside the oven and that the ventilation is normal. This step is used to eliminate drilling stress and whitening of the hole opening.

[0056] Step S4, Plasma activation:

[0057] The drilled PTFE board is placed into a plasma treatment device for processing, and copper plating is completed within 4 hours after the plasma treatment. An additional 1″×3″ PTFE bare board is suspended on the treatment rack as a test board. After the plasma activation treatment is completed, a continuous ink line is drawn on the test board with an ordinary water-based pen. If the ink line remains unchanged, does not shrink, and does not deform, the treatment effect is considered acceptable; if the ink line shrinks into a teardrop shape, it is considered unacceptable and needs to be reprocessed.

[0058] The plasma processing technology is as follows:

[0059] Processed gases: H2 (600 ml / min) + N2 (600 ml / min);

[0060] Process steps: Step 1, CF4 + O2 + N2 (cleaning filler); Step 2, N2 + H2 (modifying PTFE).

[0061] The RF source power is 1500–2500 W, preferably 2000 W;

[0062] The processing temperature is 60–150℃, preferably 150℃;

[0063] Processing time is 30–120 min, preferably 60 min;

[0064] Vacuum degree 20–50 Pa;

[0065] Plasma activation depth is 100–101 nm, which does not affect the bulk properties of the material.

[0066] Step S5, copper plating and electroplating:

[0067] Pretreatment before copper plating involves only high-pressure water washing; the brush section must not be opened. The copper plating bath solution must be confirmed to have a backlight level of 9.5 before the board is introduced. After copper plating is completed, the board is immediately plated for electroplating. A thick edge strip 1-2cm longer than the board is used to support the floating frame and is fixed with bottom clamps to prevent the board from deforming.

[0068] Step S6, Pattern Transfer and Etching:

[0069] Pre-treatment of the circuit board involves only acid pickling and sandblasting; grinding is prohibited. The etching tolerance for critical RF lines is controlled within ±0.5mil, and etching is performed with the circuit surface facing down. The time from etching completion to solder mask silkscreen completion is controlled within 12 hours. The boards to be processed are stored in a clean area with a temperature of 22±2℃ and a humidity of 50±5%.

[0070] Step S7, Solder resist and surface treatment:

[0071] The surface treatment process uses immersion tin, immersion silver or immersion gold; in this embodiment, tin spraying is used as the surface treatment process, the tin spraying temperature is below 255°C, and the pre-baking temperature before tin spraying is 125°C.

[0072] Step S8, molding:

[0073] The travel path of the gong cutter is set to counterclockwise;

[0074] Stacking parameters: The number of stacking plates is set according to 80% of the effective cutting length of the milling cutter, and the upper and lower plates are clamped together with 1.0mm thick smooth plates;

[0075] The end mill life is reduced by 30%, the feed rate is reduced to 50% of the standard, and the retraction speed is reduced by 30%.

[0076] Step S9, final curing and packaging:

[0077] After the finished product passes inspection, the boards are placed on a multi-layer rack and baked at 150℃ for 3 hours. After cooling, they are immediately vacuum-packed with aluminum foil containing desiccant.

[0078] The high-frequency circuit PTFE-based copper-clad laminate processing method described in this embodiment produces PTFE-based copper-clad laminates with smooth, burr-free hole walls, strong metallization bonding, and a bonding force between the chemical copper layer and the PTFE hole walls that is more than three times that of traditional processes. All samples successfully passed the 260℃ float soldering test without delamination or board bursting, and the dimensional tolerances of critical circuit lines were controlled within ±0.5 mil.

[0079] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations made to these embodiments without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for processing PTFE-based copper-clad laminates for high-frequency circuits, characterized in that, Includes the following steps: Step S1, material cutting: Throughout the entire process, operators are required to wear clean cotton gloves, use steel frame turntables, and insert each cut board into a dedicated insert; stacking is strictly prohibited. Step S2, Inner layer circuit and lamination: After the inner layer etching is completed, the lamination process is carried out within 4 hours. After browning treatment, the inner layer is baked at 115-125℃ for 1-2 hours, and then lamination is completed within 4 hours. The lamination process adopts a special lamination program for PTFE material, which is slow heating-long pressure holding-slow cooling. Step S3, Drilling and Intermediate Baking: For boards with a thickness ≥ 1.5mm, drill holes per stack; for boards with a thickness ≤ 1.5mm, set the number of stacks according to the effective length of the drill bit, and the number of stacks is 80% of the standard board material, with each layer of PTFE board separated by white paper. The retraction speed of the drilling tool should be controlled at 40%-60% of the retraction speed of the conventional FR-4 process; after drilling, bake at 110-125℃ for 60-90 minutes. Step S4, Plasma Activation: The drilled and baked PTFE board is subjected to plasma treatment, and chemical copper plating is completed within 4 hours after treatment. Step S5, Copper Plating and Electroplating: The pretreatment for copper plating only involves high-pressure water washing, and the brush section must not be turned on; electroplating is performed immediately after copper plating is completed. Step S6, Pattern Transfer and Etching: Only acid pickling and sandblasting are allowed in the pretreatment of the circuit; grinding is prohibited; the etching tolerance of key RF lines is controlled within ±0.5mil; the time from the completion of etching to the completion of solder mask silkscreen printing is controlled within 12 hours. Step S7, solder resist and surface treatment; Step S8, Shaping: Mill the plate path in a counterclockwise direction, reduce the milling cutter life by 30%, and reduce the feed rate to 50% of the standard speed; Step S9, final curing and packaging: After the finished product passes inspection, it is baked at 150℃ for 3 hours, and immediately vacuum-packed with aluminum foil containing desiccant after cooling.

2. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, In the drilling step of step S3, the stacked plate structure consists of an upper cover plate, a PTFE plate, and a lower pad plate from top to bottom. The upper cover plate is made of aluminum plate and phenolic board stacked together.

3. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, After the plasma activation step in step S4, there is also an effect detection step: draw lines on the treated PTFE test plate with a water-based pen. If the ink lines remain unchanged and do not shrink, the treatment is deemed qualified; if the ink lines shrink into water droplets, the treatment is deemed unqualified and needs to be reprocessed.

4. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, In step S5, during the copper plating and electroplating process, a thick edge strip 1-2 cm longer than the board is used to support the floating frame and is fixed with a bottom clamping strip to prevent the board from deforming.

5. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, In step S6, the pattern transfer and etching step, the board to be processed is stored in a clean area with a temperature of 22±2℃ and a humidity of 50±5%.

6. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, In the forming step S8, the number of stacked plates is set according to 80% of the effective cutting length of the milling cutter, and the upper and lower plates are clamped with 1.0mm thick smooth plates, and the retraction speed is reduced by 30%.

7. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, For boards that require rework, they should be scrapped immediately, and rewashing is prohibited.

8. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 1, characterized in that, In step S7, the surface treatment process uses immersion tin, immersion silver, or immersion gold.

9. The processing method of PTFE-based copper-clad laminate for high-frequency circuits according to claim 8, characterized in that, When using tin plating as a surface treatment process, the tin plating temperature is below 255℃, and the pre-baking temperature before tin plating is 120-130℃.

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