Chip test board and manufacturing method thereof

Abstract

The present application belongs to the chip technical field, and particularly relates to a chip test board and a manufacturing method thereof. The chip test board comprises the following steps: obtaining a plurality of double-sided panels, and performing circuit pattern processing on at least one side of the double-sided panels in the thickness direction; stacking the plurality of double-sided panels according to a first preset order, and placing prepreg between adjacent double-sided panels to form a sub-board through pressing; processing metallized through holes on the sub-board, and processing circuit patterns on the surface of the sub-board; obtaining a plurality of single-sided panels, processing circuit patterns on each single-sided panel except for at most one single-sided panel on which a blind hole is processed and filled in the hole; and stacking all the single-sided panels on the sub-board according to a second preset order after the processing of each single-sided panel is completed to form the chip test board through pressing. The whole multilayer board manufacturing can be completed by two times of lamination, the number of pressing is significantly reduced, the overall processing cycle and production delivery period are shortened, and the production efficiency is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, and in particular relates to a chip test board and its manufacturing method. Background Technology

[0002] Existing test boards typically use double-sided panels for layer-by-layer lamination during manufacturing, which is time-consuming and has low production efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a chip test board and its manufacturing method, which addresses the problems of long process time and low production efficiency caused by the existing double-sided laminated layer-by-layer lamination method.

[0004] To address the aforementioned technical problems, in one aspect, embodiments of the present invention provide a method for manufacturing a chip test board, comprising: Multiple double-sided boards are obtained, and circuit patterns are processed on at least one side of the double-sided boards in the thickness direction; After the graphic processing is completed, multiple double-sided panels are stacked in a first preset order, with a prepreg placed between adjacent double-sided panels, and then pressed together to form a sub-panel. Metallized through holes are machined on the sub-board, and circuit patterns are machined on the surface of the sub-board; Multiple single-sided boards are obtained, and except for processing blind holes and filling the holes on at most one of the single-sided boards, circuit patterns are processed on each of the other single-sided boards, and the holes are filled after processing the blind holes. After each single panel is processed, all the single panels are stacked on the sub-board in a second preset order and formed into a chip test board by pressing.

[0005] Optionally, the plurality of double-sided boards include a first outer layer, a second outer layer, and a plurality of intermediate layers. The step of obtaining the plurality of double-sided boards and processing circuit patterns on at least one side of the double-sided boards in the thickness direction includes: A first circuit pattern is processed on one side of the thickness direction of the first outer layer plate and on one side of the thickness direction of the second outer layer plate. A second circuit pattern is machined on both sides of the intermediate layer in the thickness direction; The first preset order is that the first outer layer plate and the second outer layer plate are placed opposite each other, and all the intermediate layer plates are stacked between the first outer layer plate and the second outer layer plate.

[0006] Optionally, the process of machining metallized through-holes on the sub-board and machining circuit patterns on the surface of the sub-board includes: Through holes are machined on the sub-plate; An electroplating layer is formed on the inner wall of the through hole and the surface of the sub-plate through an electroplating process; A third circuit pattern is created on the surface of the sub-board through exposure, development, and etching processes.

[0007] Optionally, the step of acquiring multiple single-sided boards, except for machining blind vias and filling the vias on at most one of the single-sided boards, machining circuit patterns on each of the other single-sided boards, and filling the vias after machining the blind vias, includes: Take one of the single-sided panels as the outer single-sided panel, and process blind holes on the outer single-sided panel and fill the holes; The remaining single-sided panels are referred to as inner single-sided panels. A fourth circuit pattern is processed on each inner single-sided panel, and the holes are filled after the blind holes are processed. The second preset order is to place the outermost single panel on the outermost layer, and then stack all the inner single panels on the outer single panel and the sub-panel in sequence. The side of the outer single panel with the blind hole and the side of the inner single panel with the blind hole are positioned close to the sub-panel.

[0008] Optionally, the method for manufacturing the chip test board further includes: A fifth circuit pattern is fabricated on the chip test board; The fifth circuit pattern is formed on the side of the outer single-sided panel opposite to the sub-panel.

[0009] Optionally, the step of acquiring multiple single-sided boards, except for machining blind vias and filling the vias on at most one of the single-sided boards, machining circuit patterns on each of the other single-sided boards, and filling the vias after machining the blind vias, includes: A fourth circuit pattern is machined on all single-sided boards, and the holes are filled after blind vias are machined. The second preset order is to stack all the single panels on the sub-board, with the side of each single panel having the blind hole positioned close to the sub-board.

[0010] Optionally, the single-sided panel includes a first dielectric layer and a first metal layer disposed on one side of the first dielectric layer. The first dielectric layer is made of a thermoplastic material, and the blind hole is formed on the first dielectric layer and filled inside the hole.

[0011] Optionally, the single-sided panel includes a first single-sided panel and a second single-sided panel. Among the plurality of first single-sided panels, except for at most one first single-sided panel where blind vias are machined and the vias are filled, each of the other first single-sided panels has circuit patterns machined and blind vias are filled after machining. Among the plurality of second single-sided panels, except for at most one second single-sided panel where blind vias are machined and the vias are filled, each of the other second single-sided panels has circuit patterns machined and blind vias are filled after machining. After each of the single-sided panels is processed, all the single-sided panels are stacked on the sub-board in a second preset order, and a chip test board is formed by lamination, including: All the first single-sided panels are stacked on one side of the sub-panel thickness direction according to the second preset order; All the second single-sided panels are stacked on the other side of the thickness direction of the sub-panel in a second preset order; The sub-board, all the first single-sided boards, and all the second single-sided boards are laminated together to form a chip test board.

[0012] On the other hand, embodiments of the present invention provide a chip test board, which is prepared by the chip test board manufacturing method as described in any of the preceding claims; The chip test board includes the sub-board and a plurality of single-sided boards stacked together. The sub-board includes a plurality of double-sided boards stacked together. A prepreg is disposed between two adjacent double-sided boards. The sub-board has metallized through-holes that penetrate the plurality of double-sided boards. A blind hole is disposed on the side of the single-sided board near the sub-board. The blind hole is filled with conductive paste.

[0013] Optionally, the single panel includes a first dielectric layer and a first metal layer disposed on one side of the first dielectric layer, and the blind via is disposed on the first dielectric layer. In a plurality of single panels, the first dielectric layer and the first metal layer are disposed alternately in sequence. The double-sided panel includes a second dielectric layer and a second metal layer disposed on both sides of the second dielectric layer.

[0014] The chip test board manufacturing method provided in this invention uses a single-sided board for HDI layers containing blind vias and a double-sided board for units without blind vias. The entire multilayer board fabrication is completed in two lamination steps. The first lamination is performed only on the double-sided board units without blind vias to form a sub-board, where metallized interconnect vias and outer layer circuit patterns are fabricated. The second lamination involves stacking the single-sided boards with blind vias and in-hole filling onto the sub-board according to a pre-defined board structure. A single lamination achieves a strong bond between the entire multilayer single-sided board. This significantly reduces the number of lamination steps, greatly shortens the overall processing cycle and production delivery time, significantly improves production efficiency, and enhances the competitiveness of HDI products. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for manufacturing a chip test board according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a double-sided panel provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of multiple double-sided panels stacked according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a sub-board provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a single-panel screen provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a sub-board and multiple single-sided boards stacked according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a chip test board provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the stacking of a sub-board and multiple single-sided boards according to another embodiment of the present invention; Figure 9 This is a schematic diagram of a chip test board provided in another embodiment of the present invention.

[0016] The reference numerals in the accompanying drawings are as follows: 1. Double-sided board; 1a. Second dielectric layer; 1b. Second metal layer; 11. First outer layer; 111. First circuit pattern; 12. Second outer layer; 13. Intermediate layer; 131. Second circuit pattern; 2. Prepreg; 3. Sub-board; 31. Metallized through-hole; 32. Third circuit pattern; 4. Single-sided board; 41. First dielectric layer; 411. Blind via; 42. First metal layer; 421. Fourth circuit pattern; 4a. First single-sided board; 4b. Second single-sided board; 5. Fifth route diagram. Detailed Implementation

[0017] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] like Figures 1 to 9 As shown, an embodiment of the present invention provides a method for manufacturing a chip test board, comprising: S1. Obtain multiple double-sided panels 1, and perform circuit pattern processing on at least one side of the double-sided panel 1 in the thickness direction; among the multiple double-sided panels 1, single-sided circuit processing or double-sided circuit processing can be flexibly selected according to design requirements, that is, some double-sided panels 1 have circuit patterns processed on one side, and other double-sided panels 1 have circuit patterns processed on both sides.

[0019] S2. After the graphic processing is completed, multiple double-sided panels 1 are stacked in the first preset order, and a semi-cured sheet 2 is placed between adjacent double-sided panels 1. Sub-panel 3 is formed by pressing. Multiple double-sided boards 1 are arranged from top to bottom. A prepreg (PP sheet) is placed between two adjacent double-sided boards 1 as an adhesive and insulating medium. The stacked double-sided boards 1 are pressed together, so that the prepreg 2 melts, flows and solidifies, which can fill the gaps in the circuits on the double-sided boards 1 and combine the multiple double-sided boards 1 into one, forming a sub-board 3.

[0020] S3. Machine metallized through holes 31 on sub-board 3, and machine circuit patterns on the surface of sub-board 3. Specifically, through-holes are formed on the sub-board 3 by mechanical drilling or laser drilling. Subsequently, a copper layer is uniformly deposited on the inner wall of the through-hole through copper plating or electroplating, thereby obtaining the metallized through-hole 31. This metallized through-hole 31 serves as an interlayer interconnection through-hole, which can stably realize the circuit conduction and signal transmission between the multilayer double-sided boards 1. At the same time, copper layers are simultaneously deposited on the upper and lower surfaces of the sub-board 3. On the upper and lower surfaces of the sub-board 3, circuit patterns are created through exposure, development, and etching processes to form the outer layer circuit of the sub-board 3.

[0021] S4. Obtain multiple single-sided boards 4. Except for processing blind holes 411 on at most one single-sided board 4 and filling the holes, process circuit patterns on each of the other single-sided boards 4 and fill the holes after processing the blind holes 411. Select a single-sided board 4 as a layer addition unit for sub-board 3. For at most one single-sided board 4, only blind holes 411 are processed and conductive paste is filled into the blind holes 411. For the other single-sided boards 4, in addition to processing blind holes 411 and filling the blind holes 411 with conductive paste, circuit patterns also need to be made.

[0022] S5. After each single-sided board 4 is processed, all single-sided boards 4 are stacked on the sub-board 3 in the second preset order, and formed into a chip test board by pressing.

[0023] In the chip test board, the HDI layer containing blind vias 411 is fabricated using a single-sided board 4, while the units without blind vias 411 are fabricated using a double-sided board 1. The entire multilayer board fabrication is completed in two lamination steps. The first lamination is performed only on the double-sided board 1 units without blind vias 411, forming a sub-board 3. Metallized interconnect vias and outer layer circuit patterns are then fabricated on the sub-board 3. The second lamination involves stacking the single-sided board 4 (with blind vias 411 and hole filling completed) onto the sub-board 3 according to a pre-defined board structure. These two laminations achieve a robust bond to the overall multilayer structure.

[0024] By adopting the above manufacturing method, the manufacturing process of traditional multi-stage HDI boards can be simplified to only two laminations, significantly reducing the number of laminations, greatly shortening the overall processing cycle and production delivery time, greatly improving production efficiency, and enhancing the competitiveness of HDI products.

[0025] Furthermore, the thickness of existing chip test boards is generally greater than 4mm. Due to the thickness of the boards, the electroplating of the vias in HDI boards is quite difficult. The solution is to mill the board edges thinner before electroplating, but for multi-stage HDI boards, this solution would lengthen the processing flow and seriously affect the delivery time. In this application, a process of filling the blind vias 411 with conductive paste is used instead of electroplating the blind vias 411, which can further shorten the processing flow of multi-stage HDI boards for chip test boards. Moreover, by setting the blind vias 411 on the single-sided board 4, since the single-sided board 4 is thinner, the blind vias 411 have a smaller depth and a lower aspect ratio. Compared with the existing blind vias 411 fabricated on the double-sided board 1 stacked structure, the blind vias 411 in this application are easier to fill with, the filling material is denser and fuller, there are no voids or depressions, the surface flatness of the hole is higher, and the conductivity reliability and interlayer bonding stability of the blind vias 411 are improved.

[0026] In one embodiment, such as Figure 2 , Figure 3 As shown, the multiple double-sided panels 1 include a first outer layer 11, a second outer layer 12 and multiple intermediate layers 13. The multiple double-sided panels 1 are divided into a first outer layer 11, a second outer layer 12 and intermediate layers 13 according to their stacking position, and are processed for different materials.

[0027] In step S1, obtaining multiple double-sided panels 1 and processing circuit patterns on at least one side of the double-sided panel 1 in the thickness direction includes: S11. A first circuit pattern 111 is processed on one side of the thickness direction of the first outer layer plate 11 and on one side of the thickness direction of the second outer layer plate 12. For the first outer layer 11, i.e. the second outer layer 12, the first circuit pattern 111 is made on only one of its surfaces in the thickness direction, while the other surface retains its original copper surface.

[0028] S12. A second circuit pattern 131 is machined on both sides of the intermediate layer 13 in the thickness direction. It should be noted that the first circuit pattern 111 and the second circuit pattern 131 mentioned above are only used to distinguish the circuits of different boards, and do not mean that the first outer layer board 11 and the second outer layer board 12 have the same pattern, nor do they mean that the patterns on both sides of the middle layer board 13 are the same.

[0029] like Figure 3 As shown, the first preset order is that the first outer layer 11 and the second outer layer 12 are placed opposite each other, and all the intermediate layers 13 are stacked between the first outer layer 11 and the second outer layer 12.

[0030] The first outer layer 11 and the second outer layer 12 are placed with their circuit surfaces facing each other and their non-circuit surfaces facing away from each other. All the intermediate layers 13 are placed between the first outer layer 11 and the second outer layer 12, and a prepreg 2 is placed between adjacent layers. During the pressing process under high temperature and high pressure, the prepreg 2 melts and flows, fully filling the gaps between the circuit patterns of each layer, and simultaneously bonding the two layers together to form a sub-board 3. After this pressing process, the upper surface of the sub-board 3 is the original copper layer of the first outer layer 11, and the lower surface of the sub-board 3 is the original copper layer of the second outer layer 12, providing a processing basis for fabricating circuits on the surface of the sub-board 3 in subsequent steps.

[0031] In this application, multiple double-sided boards 1 are distinguished according to a first preset order, and different circuit processing processes are performed on each. The first outer layer board 11 and the second outer layer board 12, on which only one side of the circuit pattern is made, are arranged on the outermost side, using their original copper surface without circuits as the outer interface for lamination. The middle layer board 13 is not affected by lamination, and circuit patterns are made on both sides. After the overall lamination is completed to form the sub-board 3, the outer layer circuit pattern is then made on the original copper surface on the outer side. This effectively avoids problems such as pattern deformation and scratches during the high temperature and high pressure lamination process of the outer layer circuit, ensuring the accuracy and electrical performance of the outer layer circuit.

[0032] In one embodiment, such as Figure 3As shown, taking three double-sided boards 1 as an example, the upper one is the first outer layer 11, the lower one is the second outer layer 12, and the middle one is the intermediate layer 13. For the first outer layer 11 and the second outer layer 12, a first circuit pattern 111 is formed on one side surface of the first outer layer 11 and one side surface of the second outer layer 12 through film lamination, exposure, development, and etching processes. For the intermediate layer 13, the same film lamination, exposure, development, and etching processes are used to sequentially form a second circuit pattern 131 on both sides of its thickness direction.

[0033] In one embodiment, in step S2, after the patterns of the first outer layer 11, the second outer layer 12, and the plurality of intermediate layer 13 are processed, they are stacked sequentially from top to bottom in the order of the first outer layer 11, the plurality of intermediate layer 13, and the second outer layer 12. A prepreg 2 is placed between each adjacent double-sided panel 1 as an adhesive and insulating medium, so that each double-sided panel 1 is completely separated by the prepreg 2. After high temperature and high pressure vacuum pressing, the prepreg 2 melts, fills the gaps in the circuit and solidifies, bonding the multiple double-sided panels 1 into one piece to form a sub-board 3.

[0034] In one embodiment, such as Figure 4 As shown, in step S3, the machining of metallized through holes 31 on the sub-board 3 and the machining of circuit patterns on the surface of the sub-board 3 include: S31. A through hole is processed on the sub-board 3. A through hole that penetrates the entire thickness of the sub-board 3 is formed by mechanical drilling or laser drilling. The hole wall is cleaned to ensure that the hole wall is free of dust and oil, so as to provide a good bonding interface for subsequent metallization and conduction.

[0035] S32. An electroplating layer is formed on the inner wall of the through hole and the surface of the sub-plate 3 through an electroplating process; The drilled sub-board 3 is subjected to copper electroplating treatment, and a dense, continuous and strongly adherent conductive electroplating layer is uniformly deposited on the inner wall of the through hole to form a metallized through hole 31 to achieve interlayer electrical conduction between the multi-layer double-sided boards 1 inside the sub-board 3; at the same time, a uniformly thickened electroplated copper layer is formed on the original copper surface on the upper and lower sides of the sub-board 3.

[0036] The thickened electroplated copper layer is formed on the original copper layer of the first outer layer plate 11 and on the original copper layer of the second outer layer plate 12. The original copper layers of the first outer layer plate 11 and the second outer layer plate 12 are thickened through the electroplating process.

[0037] S33. A third circuit pattern 32 is fabricated on the surface of the sub-board 3 through exposure, development, and etching processes. Dry film is sequentially laminated, exposed, and developed on the electroplated copper layers on the upper and lower surfaces of the sub-board 3 to transfer the third circuit pattern 32 onto the dry film. After development, the copper surface to be etched is exposed. The copper layer in the non-circuit areas is then removed using an etching solution. Finally, the dry film is removed, precisely forming the third circuit pattern 32 conforming to the design requirements on the surface of the sub-board 3, serving as the outer layer circuit of the sub-board 3. During etching, both the electroplated copper layer in the non-circuit areas and the original copper layer are etched away.

[0038] In this application, by forming continuous and dense metallized vias 31 on the sub-board 3, the inner layer circuits of each double-sided board 1 inside the sub-board 3 can be connected vertically, constructing a reliable interlayer conductive path. This provides a stable conductive foundation for the circuit interconnection after the sub-board 3 and the single-sided board 4 are laminated and pressed together, ensuring the effective transmission of signals, power and ground lines between the functional layers of the overall chip test board.

[0039] In one embodiment, such as Figure 5 , Figure 6 As shown, in step S4, obtaining multiple single-sided panels 4, except for machining blind vias 411 and filling the vias on at most one single-sided panel 4, machining circuit patterns on each of the other single-sided panels 4, and filling the vias after machining the blind vias 411, includes: Take one of the single-sided panels, 4, and denote it as the outer single-sided panel (i.e. Figure 6 The top and bottom single-sided panels are processed with blind holes 411 and filled with the holes. The remaining single-sided panels are referred to as inner single-sided panels. A fourth circuit pattern 421 is processed on each inner single-sided panel, and the blind holes 411 are filled with the holes after processing.

[0040] The single-sided panel 4 includes a first dielectric layer 41 and a first metal layer 42 disposed on one side of the first dielectric layer 41. One of the multiple single-sided panels 4 is defined as the outer single-sided panel. A blind via 411 is processed on the first dielectric layer 41 of the outer single-sided panel using laser drilling. The blind via 411 is recessed from the side of the outer single-sided panel closer to the sub-board 3 to the side farther away from the sub-board 3. The depth of the blind via 411 is controlled to be consistent with the thickness of the first dielectric layer 41. After the blind via 411 is processed, conductive paste is filled into the blind via 411. The first metal layer 42 of the outer single-sided panel is not processed with circuit patterns. All the remaining single-sided panels 4 are uniformly defined as inner single-sided panels. Blind vias 411 are made on the inner single-sided panels from bottom to top and filled with conductive paste. In addition, for each inner single-sided panel, a standard circuit fabrication process of lamination, exposure, development, and etching is used to process a fourth circuit pattern 421 on the first metal layer 42 of each inner single-sided panel.

[0041] In this embodiment, as Figure 6As shown, the second preset order is to place the outermost single panel on the outermost layer, and then stack all the inner single panels on the outer single panel and the sub-panel 3 in sequence. The side of the outer single panel with blind hole 411 and the side of the inner single panel with blind hole 411 are positioned close to the sub-panel 3.

[0042] The layers are stacked according to the second preset order, with the overall stacking order from top to bottom being: outer single-sided board, multiple inner single-sided boards, and sub-board 3. The first metal layer 42 of the outer single-sided board is not processed with circuit patterns and retains its original copper surface intact. After lamination and curing, the upper surface of the chip test board is the original copper surface of the outer single-sided board, providing a processing basis for subsequent circuit fabrication on the chip test board.

[0043] In one embodiment, such as Figure 7 As shown, the method for fabricating a chip test board also includes: S6. Process the fifth circuit pattern 5 on the chip test board; The fifth circuit pattern 5 is formed on one side of the outer single-sided back ion board 3, that is, the fifth circuit pattern 5 is formed on the first metal layer 42 of the outer single-sided board. Based on the first metal layer 42 of the outer single-sided board, the fifth circuit pattern 5 is formed on the first metal layer 42 through conventional processes such as film lamination, exposure, development, etching and film removal.

[0044] When the single-sided panel 4 is pressed in the second preset order of stacking the outer single-sided panel, multiple inner single-sided panels, and sub-board 3, the first metal layer 42 of the outer single-sided panel retains the copper layer. In step S6, the fifth circuit pattern 5 is processed on the first metal layer 42 of the outer single-sided panel, which can be used to lay out the external connection pads required for chip testing.

[0045] In another embodiment, such as Figure 8 As shown, in step S4, obtaining multiple single-sided panels 4, except for machining blind vias 411 and filling the vias on at most one single-sided panel 4, machining circuit patterns on each of the other single-sided panels 4, and filling the vias after machining the blind vias 411, includes: A fourth circuit pattern 421 is machined on all single-sided boards 4, and the holes are filled after the blind holes 411 are machined.

[0046] The single-sided panel 4 includes a first dielectric layer 41 and a first metal layer 42 disposed on one side of the first dielectric layer 41. For each single-sided panel 4, a standard process of lamination, exposure, development, and etching is used to fabricate a fourth circuit pattern 421 on the first metal layer 42, realizing the layout and routing of the internal signal, power, and ground lines of each single-sided panel 4. Subsequently, blind vias 411 are processed on the first dielectric layer 41 using laser drilling. The blind vias 411 are recessed from the side of the single-sided panel 4 closest to the sub-board 3 to the side furthest from the sub-board 3, and the depth of the blind vias 411 is controlled to be consistent with the thickness of the first dielectric layer 41. After the blind vias 411 are processed, conductive paste is filled into the blind vias 411.

[0047] In this embodiment, as Figure 8 As shown, the second preset order is to stack all the single-panel panels 4 on the sub-panel 3, with each single-panel panel 4 having a blind hole 411 on one side close to the sub-panel 3.

[0048] The layers are stacked according to this second preset order, with the overall stacking order from top to bottom being multi-layer single-sided panels 4 and sub-panels 3. After pressing and molding, the blind holes 411 that have been filled and cured on the single-sided panels 4 form vertical conductive interconnection channels, realizing the electrical conduction of the fourth circuit pattern 421 circuits of adjacent layers.

[0049] In one embodiment, such as Figure 5 As shown, the single-sided panel 4 includes a first dielectric layer 41 and a first metal layer 42 disposed on one side of the first dielectric layer 41. The first dielectric layer 41 is made of thermoplastic material. Blind holes 411 are formed on the first dielectric layer 41 and filled inside the holes.

[0050] The characteristic of thermoplastic materials is that they can re-enter the molten state when the temperature reaches the TG point. For example, liquid crystal polymer (LCP) can be used to press multiple single-panel panels 4 together without placing an adhesive medium (such as a prepreg 2) between adjacent single-panel panels 4. During high-temperature and high-pressure pressing, the thermoplastic material melts and flows, which can fill the gaps between the lines of adjacent layers and bond the multiple single-panel panels 4 together.

[0051] By using thermoplastic material to make the first medium layer 41, it can play the role of insulation, gap filling and interlayer bonding during the pressing process. There is no need to add an extra special adhesive medium layer, which can effectively reduce the overall thickness of the board and make the structure lighter and more compact.

[0052] When the second preset order is to place the outermost single panel on the outermost layer, and all the inner single panels are stacked sequentially between the outer single panel and sub-panel 3, as follows: Figure 6 As shown, since the first metal layer 42 of the outer single-sided panel is not patterned, the top layer retains a complete copper layer after lamination. After the fifth circuit pattern 5 is completed, the first dielectric layer 41 of the outer single-sided panel will be exposed.

[0053] When the second preset order is to stack all single-panel boards 4 on sub-board 3, as follows: Figure 8 As shown, all single-sided panels 4 have a fourth circuit pattern 421 made before lamination. In this way, during lamination, the gaps in the circuit pattern of the outermost single-sided panel 4 will be filled by molten thermoplastic material. Under normal circumstances, the gaps will be filled, so that the surface of the filled thermoplastic material is basically flush with the surface of the first metal layer 42, and the overall panel surface is flat and uniform, without obvious depressions or step differences.

[0054] In one embodiment, the first metal layer 42 is a copper layer.

[0055] In one embodiment, the single-sided panel 4 includes a first single-sided panel 4a and a second single-sided panel 4b. Among the plurality of first single-sided panels 4a, except for at most one first single-sided panel 4a on which blind vias 411 are machined and filled, each of the remaining first single-sided panels 4a has a circuit pattern machined and the blind vias 411 are filled after machining. Therefore, two second preset sequences are set for the first single-sided panels 4a, specifically: One of the first single-sided panels 4a is designated as the first outer single-sided panel. A blind hole 411 is machined on the first outer single-sided panel and the hole is filled. The remaining first single-sided panels 4a are designated as the first inner single-sided panels. A fourth circuit pattern 421 is machined on each of the first inner single-sided panels, and the hole is filled after the blind hole 411 is machined.

[0056] The first second preset order of all first single-panel panels 4a is: place the first outer single-panel panel on the outermost layer, and stack all the first inner single-panel panels in sequence between the first outer single-panel panel and the sub-panel 3.

[0057] Alternatively, a fourth circuit pattern 421 may be machined on all first single-sided panels 4a, and the holes may be filled after the blind vias 411 are machined.

[0058] The second preset order for all first single-panel panels 4a is: stack all first single-panel panels 4a on sub-panel 3.

[0059] In a plurality of second single-sided panels 4b, except for at most one second single-sided panel 4b on which blind vias 411 are machined and filled, each of the other second single-sided panels 4b has a circuit pattern machined and the blind vias 411 are filled after machining. Therefore, two second preset sequences are also set for the second single-sided panels 4b, specifically: One of the second single-sided panels 4b is designated as the second outer single-sided panel. A blind hole 411 is machined on the second outer single-sided panel and the hole is filled. The remaining second single-sided panels 4b are designated as the second inner single-sided panels. A fourth circuit pattern 421 is machined on each of the second inner single-sided panels, and the hole is filled after the blind hole 411 is machined.

[0060] The third second preset order for all second single panels 4b is: place the second outer single panel on the outermost layer, and stack all the second inner single panels in sequence between the second outer single panel and the sub-panel 3.

[0061] Alternatively, a fourth circuit pattern 421 may be machined on all second single-sided panels 4b, and the holes may be filled after the blind vias 411 are machined.

[0062] The fourth preset order for all second single-panel panels 4b is: stack all second single-panel panels 4b on sub-panel 3.

[0063] In step S5, after each single-sided panel 4 is processed, all single-sided panels 4 are stacked on the sub-board 3 in a second preset order, and a chip test board is formed by pressing them together, including: S51. Stack all the first single-panel panels 4a on one side of the thickness direction of the sub-panel 3 according to the second preset order; at this time, all the first single-panel panels 4a can be placed according to the first second preset order or the second second preset order.

[0064] S52. Stack all the second single-panel panels 4b on the other side of the thickness direction of the sub-panel 3 in the second preset order; all the second single-panel panels 4b can be placed in the third or fourth second preset order.

[0065] S53. The sub-board 3, all first single-sided boards 4a and all second single-sided boards 4b are laminated to form a chip test board.

[0066] Thus, the resulting chip test board has a variety of different structures, as shown in the following examples: like Figure 7 As shown, chip test board one: a sub-board 3 is obtained by laminating multiple double-sided boards 1. Multiple first single-sided boards 4a are laminated on one side of the sub-board 3 according to a first-second-preset sequence, and multiple second single-sided boards 4b are laminated on the other side of the sub-board 3 according to a third-second-preset sequence, thus obtaining chip test board one. After lamination is completed, a fifth circuit pattern 5 is formed on the upper and lower surfaces of chip test board one, that is, a pattern is formed on the first metal layer 42 of the first outer single-sided board and a pattern is formed on the first metal layer 42 of the second outer single-sided board.

[0067] like Figure 9 As shown, chip test board two: a sub-board 3 is obtained by pressing multiple double-sided boards 1 together. Multiple first single-sided boards 4a are pressed together on one side of the sub-board 3 in a second preset order. Multiple second single-sided boards 4b are pressed together on the other side of the sub-board 3 in a fourth preset order, thereby obtaining chip test board two.

[0068] In this embodiment, by pressing multiple first single-sided panels 4a onto one side of the sub-plate 3 and pressing multiple second single-sided panels 4b onto the other side of the sub-plate 3, the stress on both sides of the sub-plate 3 tends to be balanced, avoiding stress concentration caused by unilateral lamination and reducing warping.

[0069] In one embodiment, the first single-panel 4a and the second single-panel 4b on both sides of the sub-plate 3 are symmetrically arranged, that is, the number of layers of the first single-panel 4a is the same as the number of layers of the second single-panel 4b. For example, the first single-panel 4a is provided with 7 layers and the second single-panel 4b is provided with 7 layers. At this time, the single-panel 4 is symmetrically arranged on both sides of the sub-plate 3, the stress is balanced, and the warping of the test plate can be effectively suppressed.

[0070] In other embodiments, the first single-panel 4a and the second single-panel 4b on both sides of the sub-panel 3 may also be asymmetrically arranged, that is, the number of layers of the first single-panel 4a and the number of layers of the second single-panel 4b are different, such as the first single-panel 4a having 7 layers and the second single-panel 4b having 5 layers.

[0071] On the other hand, embodiments of the present invention provide a chip test board, which is prepared by the chip test board manufacturing method described in any of the above claims.

[0072] The chip test board includes a sub-board 3 and multiple single-sided boards 4 stacked together. The multiple single-sided boards 4 and the sub-board 3 are formed into one piece by pressing. The sub-board 3 includes multiple double-sided boards 1 stacked together. A prepreg 2 is placed between two adjacent double-sided boards 1. Circuit patterns are set on both sides of the double-sided boards 1. The prepreg (PP sheet) serves as an adhesive and insulating medium. The stacked double-sided boards 1 are pressed together, causing the prepreg 2 to melt, flow, and solidify, filling the gaps in the circuits on the double-sided boards 1 and bonding the multiple double-sided boards 1 into one piece to form the sub-board 3.

[0073] The sub-board 3 is provided with metallized through holes 31, which penetrate multiple double-sided boards 1; the metallized through holes 31 enable interlayer electrical conduction between the multiple double-sided boards 1 inside the sub-board 3. A blind hole 411 is provided on the side of the single-sided board 4 near the sub-board 3. The blind hole 411 is filled with conductive paste. After the conductive paste cures, it forms a continuous conductive path, which can directly connect the circuits of the upper and lower single-sided boards 4.

[0074] In one embodiment, the single-sided panel 4 includes a first dielectric layer 41 and a first metal layer 42 disposed on one side of the first dielectric layer 41. A blind via 411 is disposed on the first dielectric layer 41, and the depth of the blind via 411 is the same as the thickness of the first dielectric layer 41. After multiple single-sided panels 4 are laminated onto a sub-board 3 to form a chip test board, the first dielectric layer 41 and the first metal layer 42 are alternately disposed in sequence. Each first dielectric layer 41 is provided with a blind via 411, and the blind via 411 is filled with conductive paste. The first metal layer 42 is formed into circuit patterns through exposure, development and etching processes. After the conductive paste is cured, the blind via 411 filled with conductive paste can directly connect the upper and lower circuit patterns.

[0075] The double-sided board 1 includes a second dielectric layer 1a and second metal layers 1b disposed on both sides of the second dielectric layer 1a. The double-sided board 1 structure allows circuit patterns to be fabricated on the surfaces of the second metal layers 1b on both the upper and lower sides, and interlayer conductivity is achieved through metallized vias 31 on the sub-board 3.

[0076] The first dielectric layer 41 is made of a thermoplastic material, such as a liquid crystal polymer; the second dielectric layer 1a is FR-4 or other conventional materials; the first metal layer 42 is a copper layer; and the second metal layer 1b is a copper layer.

[0077] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a chip test board, characterized in that, include: Multiple double-sided boards are obtained, and circuit patterns are processed on at least one side of the double-sided boards in the thickness direction; After the graphic processing is completed, multiple double-sided panels are stacked in a first preset order, with a prepreg placed between adjacent double-sided panels, and then pressed together to form a sub-panel. Metallized through holes are machined on the sub-board, and circuit patterns are machined on the surface of the sub-board; Multiple single-sided boards are obtained, and except for processing blind holes and filling the holes on at most one of the single-sided boards, circuit patterns are processed on each of the other single-sided boards, and the holes are filled after processing the blind holes. After each single panel is processed, all the single panels are stacked on the sub-board in a second preset order and formed into a chip test board by pressing.

2. The method for manufacturing a chip test board according to claim 1, characterized in that, The plurality of double-sided boards include a first outer layer, a second outer layer, and a plurality of intermediate layers. The step of obtaining the plurality of double-sided boards and processing circuit patterns on at least one side of the double-sided boards in the thickness direction includes: A first circuit pattern is processed on one side of the thickness direction of the first outer layer plate and on one side of the thickness direction of the second outer layer plate. A second circuit pattern is machined on both sides of the intermediate layer in the thickness direction; The first preset order is that the first outer layer plate and the second outer layer plate are placed opposite each other, and all the intermediate layer plates are stacked between the first outer layer plate and the second outer layer plate.

3. The method for manufacturing a chip test board according to claim 1, characterized in that, The process of machining metallized through holes on the sub-board and machining circuit patterns on the surface of the sub-board includes: Through holes are machined on the sub-plate; An electroplating layer is formed on the inner wall of the through hole and the surface of the sub-plate through an electroplating process; A third circuit pattern is created on the surface of the sub-board through exposure, development, and etching processes.

4. The method for manufacturing a chip test board according to claim 1, characterized in that, The process of acquiring multiple single-sided boards, except for machining blind vias and filling them on at most one of the single-sided boards, involves machining circuit patterns on each of the remaining single-sided boards, and filling the vias after machining the blind vias, including: Take one of the single-sided panels as the outer single-sided panel, and process blind holes on the outer single-sided panel and fill the holes; The remaining single-sided panels are referred to as inner single-sided panels. A fourth circuit pattern is processed on each inner single-sided panel, and the holes are filled after the blind holes are processed. The second preset order is to place the outermost single panel on the outermost layer, and then stack all the inner single panels on the outer single panel and the sub-panel in sequence. The side of the outer single panel with the blind hole and the side of the inner single panel with the blind hole are positioned close to the sub-panel.

5. The method for manufacturing a chip test board according to claim 4, characterized in that, The method for manufacturing the chip test board also includes: A fifth circuit pattern is fabricated on the chip test board; The fifth circuit pattern is formed on the side of the outer single-sided panel opposite to the sub-panel.

6. The method for manufacturing a chip test board according to claim 1, characterized in that, The process of acquiring multiple single-sided boards, except for machining blind vias and filling them on at most one of the single-sided boards, involves machining circuit patterns on each of the remaining single-sided boards, and filling the vias after machining the blind vias, including: A fourth circuit pattern is machined on all single-sided boards, and the holes are filled after blind vias are machined. The second preset order is to stack all the single panels on the sub-board, with the side of each single panel having the blind hole positioned close to the sub-board.

7. The method for manufacturing a chip test board according to claim 4 or 6, characterized in that, The single-sided panel includes a first dielectric layer and a first metal layer disposed on one side of the first dielectric layer. The first dielectric layer is made of thermoplastic material, and the blind hole is formed on the first dielectric layer and filled inside the hole.

8. The method for manufacturing a chip test board according to claim 4 or 6, characterized in that, The single-sided panel includes a first single-sided panel and a second single-sided panel. Among the plurality of first single-sided panels, except for at most one first single-sided panel where blind holes are machined and filled, each of the other first single-sided panels has circuit patterns machined and blind holes are filled after machining. Among the plurality of second single-sided panels, except for at most one second single-sided panel where blind holes are machined and filled, each of the other second single-sided panels has circuit patterns machined and blind holes are filled after machining. After each of the single-sided panels is processed, all the single-sided panels are stacked on the sub-board in a second preset order, and a chip test board is formed by lamination, including: All the first single-sided panels are stacked on one side of the sub-panel thickness direction according to the second preset order; All the second single-sided panels are stacked on the other side of the thickness direction of the sub-panel in a second preset order; The sub-board, all the first single-sided boards, and all the second single-sided boards are laminated together to form a chip test board.

9. A chip test board, characterized in that, It is prepared by the method of manufacturing the chip test board according to any one of claims 1-8; The chip test board includes the sub-board and a plurality of single-sided boards stacked together. The sub-board includes a plurality of double-sided boards stacked together. A prepreg is disposed between two adjacent double-sided boards. The sub-board has metallized through-holes that penetrate the plurality of double-sided boards. A blind hole is disposed on the side of the single-sided board near the sub-board. The blind hole is filled with conductive paste.

10. The chip test board according to claim 9, characterized in that, The single-sided panel includes a first dielectric layer and a first metal layer disposed on one side of the first dielectric layer. The blind via is disposed on the first dielectric layer. In a plurality of single-sided panels, the first dielectric layer and the first metal layer are disposed alternately in sequence. The double-sided panel includes a second dielectric layer and a second metal layer disposed on both sides of the second dielectric layer.

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