Memory cell array and memory device including memory cell array

Abstract

Memory cell arrays and memory devices including memory cell arrays are provided. The memory cell arrays can include a first memory cell including a first transistor structure and a first capacitor structure, a second memory cell including a second transistor structure and a second capacitor structure, and a first word line contact connected to the first transistor structure and the second transistor structure, where the first capacitor structure is spaced apart from the first transistor structure in a first direction and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0019959, filed with the Korean Patent Office on February 17, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to memory cell arrays and memory devices including memory cell arrays. Background Technology

[0003] Dynamic random access memory (DRAM) devices are widely used as the main memory of processors. DRAM devices can store data in the form of charge stored in capacitors, which are included in each of multiple memory cells. Summary of the Invention

[0004] In line with recent technological trends toward larger capacity and greater integration in DRAM devices, various techniques are being researched to implement a greater number of memory cells in small-area memory cell arrays. However, as a larger number of memory cells are implemented in small-area memory cell arrays, the spacing between the capacitors of the memory cells can become too narrow. In this case, the reliability of the data stored in the DRAM device can be degraded due to the interaction between the capacitors.

[0005] Some aspects of this disclosure help to address the aforementioned technical challenges. For example, some aspects of this disclosure provide a memory cell array and a memory device including the memory cell array, wherein the capacitors of each of the plurality of memory cells are arranged with wider spacing.

[0006] A memory cell array according to some embodiments of the present disclosure may include: a first memory cell including a first transistor structure and a first capacitor structure; a second memory cell including a second transistor structure and a second capacitor structure; and a first word line contact connected to the first transistor structure and the second transistor structure, wherein the first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.

[0007] A memory cell array including one or more dynamic random access memory (DRAM) cells according to some embodiments of the present disclosure may include: a substrate; a channel layer formed on the substrate and including a first transistor structure; and a capacitor layer including a first capacitor structure electrically connected to the first transistor structure, wherein a first point on the substrate corresponding to the first transistor structure is different from a second point on the substrate corresponding to the first capacitor structure.

[0008] A memory device according to some embodiments of the present disclosure may include: a memory cell array; a plurality of word lines connected to the memory cell array; and a plurality of bit lines connected to the memory cell array, wherein: the plurality of word lines include a first word line, the memory cell array includes a first plurality of memory cells connected to the first word line, the first plurality of memory cells each including a first plurality of capacitor structures, and the capacitor spacing for the first plurality of capacitor structures is larger than the bit line spacing for the plurality of bit lines.

[0009] A memory cell array according to some embodiments of the present disclosure may include: a plurality of word line contacts extending along a first direction; and a plurality of memory cells, each including a plurality of capacitor structures arranged in a matrix along the first direction and a second direction perpendicular to the first direction, wherein: the plurality of capacitor structures include a first capacitor structure and a second capacitor structure arranged along the first direction and adjacent to each other, the plurality of memory cells include a first memory cell including a first capacitor structure and a second memory cell including a second capacitor structure, and the first memory cell and the second memory cell are connected to different word line contacts among the plurality of word line contacts. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example of a memory device.

[0011] Figure 2 It is shown Figure 1 A block diagram illustrating an example configuration of a memory cell array.

[0012] Figure 3 It is shown Figure 2 A block diagram of a portion of a memory cell array.

[0013] Figure 4 yes Figure 1 A layout diagram of an example memory cell array.

[0014] Figure 5 It shows the basis Figure 4 A diagram showing an example of the arrangement of capacitors.

[0015] Figure 6 yes Figure 1 A layout diagram of an example memory cell array.

[0016] Figure 7 It shows the basis Figure 6 A diagram showing an example of the arrangement of capacitors.

[0017] Figures 8 to 10 To show in more detail Figure 6 An example diagram illustrating the structure of a memory cell array.

[0018] Figure 11 yes Figure 1 A layout diagram of an example memory cell array.

[0019] Figure 12 It shows the basis Figure 11 A diagram showing an example of the arrangement of capacitors.

[0020] Figures 13 to 16 To show in more detail Figure 11 An example diagram illustrating the structure of a memory cell array.

[0021] Figure 17 yes Figure 1 A layout diagram of an example memory cell array.

[0022] Figure 18 yes Figure 1 A layout diagram of an example memory cell array.

[0023] Figure 19 This is a block diagram illustrating an example configuration of a memory system. Detailed Implementation

[0024] It will be apparent to those skilled in the art that various changes and modifications can be made to the examples described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0025] The components described in the detailed description using terms such as "driver," "block," etc., will be implemented in software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include electrical circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0026] Figure 1 This is a block diagram illustrating an example of a memory device. (See reference...) Figure 1 The memory device MD may include a memory cell array 100, a row decoder 200, an input / output circuit 300, and a control logic circuit 400.

[0027] The memory cell array 100 may include multiple memory cells. These memory cells may be connected to multiple word lines (WL) and multiple bit lines (BL). For simplicity, it is assumed below that each of the multiple memory cells is implemented as a dynamic random access memory (DRAM) cell. For example, each of the multiple memory cells may include a capacitor structure.

[0028] The line decoder 200 can control multiple word lines WL. For example, the line decoder 200 can activate some of the multiple word lines WL based on the address ADDR provided to the control logic circuit 400.

[0029] The input / output circuit 300 can be connected to multiple bit lines BL. The input / output circuit 300 can output data DATA stored in the memory cell array 100 to an external source based on the voltage levels of the multiple bit lines BL. The input / output circuit 300 can also write externally supplied data DATA into the memory cell array 100 by controlling the voltage levels of the multiple bit lines BL.

[0030] The control logic circuit 400 can receive commands CMD and addresses ADDR. The control logic circuit 400 can control the overall operation of the memory device MD based on the commands CMD and addresses ADDR. For example, the control logic circuit 400 can control the operation of the line decoder 200 and the input / output circuit 300 based on the commands CMD and addresses ADDR.

[0031] Figure 2 To show in more detail Figure 1 A block diagram illustrating the configuration of the memory cell array. (Refer to...) Figure 1 and Figure 2 The memory cell array 100 may include multiple memory cells MC. The multiple memory cells MC may be arranged in a matrix.

[0032] Multiple memory cells MC can be connected to multiple word lines WL. Multiple memory cells MC can be connected to multiple bit lines BL. For a simpler explanation, memory cells MC connected to the first word lines WL1 to the fourth word lines WL4 and the first bit lines BL1 to the fourth bit lines BL4 are representatively shown in [the diagram]. Figure 2 However, the number of components is not limited to this. For example, the scope of this disclosure is not limited to... Figure 2 The number of word lines (WL), bit lines (BL), and memory cells (MC) shown in the figure.

[0033] Each of the multiple memory cells MC can be a DRAM cell. For example, each of the multiple memory cells MC may include a transistor TR and a capacitor CAP, and data may be stored based on the amount of charge stored in the capacitor CAP.

[0034] Figure 3 To show in more detail Figure 2 A block diagram of a portion of a memory cell array. (Refer to...) Figures 1 to 3The second word line WL2 can be connected to the first memory cell MCa through the fourth memory cell MCd. The first memory cell MCa through the fourth memory cell MCd can be connected to the first bit line BL1 through the fourth bit line BL4, respectively. For a simpler explanation, the relationship between the memory cells MC connected to the second word line WL2 will be described below as a representative example. However, it will be understood that the disclosed configuration can be applied to other word lines and bit lines.

[0035] The input / output circuit 300 can simultaneously perform read operations on at least a portion of the memory cells MC connected to a single word line WL. For example, the input / output circuit 300 can simultaneously perform read operations on first memory cells MCa through fourth memory cells MCd.

[0036] Error correction for data read from memory cell array 100 can be performed based on the cells from which data is read simultaneously from memory cells MC. For example, when read operations are performed simultaneously for first memory cells MCa to fourth memory cells MCd, an error correction code (ECC) can be applied to a set of bits (or qubits) read from first memory cells MCa to fourth memory cells MCd.

[0037] The number of correctable bits based on the error correction code can be predetermined depending on the type of error correction code. For example, the correction capability of the error correction code may be "1 bit". In this case, if the bits read simultaneously from the memory cell MC include more than "1 bit" of error bits, error correction based on the error correction code may fail, and therefore the reliability of the memory device MD may be degraded. In other words, for error correction based on the error correction code to succeed, it may be necessary for the error not to occur simultaneously in two or more of the memory cells MCs being read simultaneously (e.g., multiple memory cells MCs connected to a single word line WL).

[0038] In some cases, the number of bits that an error-correcting code can correct may be a trade-off with the storage efficiency of the memory device (MD). Therefore, it may be difficult to apply error-correcting codes with relatively high correction capabilities (such as "2 bits").

[0039] In some embodiments, error correction codes may be executed in a host device (not shown) that controls the memory device MD. However, the scope of this disclosure is not limited thereto, and error correction codes may also be executed in the memory device MD (e.g., in the input / output circuitry 300). For example, the memory device MD may be implemented to support on-die error correction codes (on-die ECC). That is, the scope of this disclosure is not limited to the specific location and manner in which error correction codes are executed.

[0040] The physical gap (e.g., interval or spacing) between capacitors CAP in adjacent memory cells MC connected to a word line WL can be referred to as capacitor gap ITV_cap. For example, a first memory cell MCa may include a first transistor TRa and a first capacitor CAPa. A second memory cell MCb may include a second transistor TRb and a second capacitor CAPb. In this case, the physical gap between the first capacitor CAPa and the second capacitor CAPb can be referred to as capacitor gap ITV_cap.

[0041] In some implementations, the capacitor spacing ITV_cap can vary depending on various factors such as process variations for capacitor CAP. For example, the capacitor spacing ITV_cap between the first capacitor CAPa and the second capacitor CAPb can be larger or smaller than the expected size (e.g., the design or planned value of the capacitor spacing ITV_cap).

[0042] If the capacitor spacing ITV_cap is not large enough, adjacent capacitors CAP may electrically interfere with each other. For example, due to various factors such as process variations, the capacitor spacing ITV_cap between the first capacitor CAPa and the second capacitor CAPb may become too small than expected (e.g., smaller than a certain threshold). In this case, the amount of charge in the second capacitor CAPb may change depending on the amount of charge in the first capacitor CAPa (e.g., influenced by the amount of charge in the first capacitor CAPa), and the amount of charge in the first capacitor CAPa may change depending on the amount of charge in the second capacitor CAPb (e.g., influenced by the amount of charge in the second capacitor CAPb). In this situation, the data stored in the first capacitor CAPa and the data stored in the second capacitor CAPb may be corrupted.

[0043] For example, if the capacitor spacing ITV_cap is not designed to be large enough, the capacitor spacing ITV_cap between some capacitors CAP can become too small due to various reasons such as process variations. In this case, the probability of errors occurring simultaneously in two or more memory cells MC that are read at the same time is very high, and therefore, the probability of uncorrectable errors occurring in the data stored in the memory device MD is very high.

[0044] When the capacitor spacing ITV_cap is too small (e.g., smaller than a certain threshold), adjacent capacitors CAP can influence each other in various ways. For example, when adjacent capacitors CAP are in direct contact with each other, the charge stored in the capacitors CAP can move directly through the conductive path formed between the capacitors CAP. As another example, even if adjacent capacitors CAP are not in direct contact, electrical coupling can occur between adjacent capacitors CAP, and therefore the amount of charge stored in the capacitors CAP can vary. That is, the scope of this disclosure is not limited to the specific reasons why adjacent capacitors CAP influence each other.

[0045] However, based on the description provided herein, the physical spacing between capacitors CAP included in memory cells MC connected to a word line WL can be sufficiently large (e.g., wide). That is, according to some embodiments of this disclosure, the capacitor spacing ITV_cap can be sufficiently large. In this case, even if the capacitor spacing ITV_cap becomes smaller than expected due to process errors or other reasons, the probability that the capacitor spacing ITV_cap becomes small enough that adjacent capacitors CAP electrically interfere with each other can be very small. In this case, the probability of errors occurring simultaneously in two or more memory cells MC being read at the same time can be greatly reduced, and therefore the probability of uncorrectable errors occurring in the data stored in the memory device MD can be greatly reduced. Therefore, according to some embodiments of this disclosure, the reliability of the data stored in the memory device MD can be improved.

[0046] The following will refer to Figures 6 to 18 A more detailed example of a specific scheme for making the physical spacing (e.g., capacitor spacing ITV_cap) between capacitors CAP included in a memory cell MC connected to a word line WL sufficiently large.

[0047] In some implementations, the error correction code may have a correction capability of 2 bits or more. Even in this case, the probability of errors exceeding the correction capability of the error correction code (i.e., uncorrectable errors) occurring in a memory cell MC connected to a word line WL can be reduced. That is, the scope of this disclosure is not limited to the specific correction capability of the error correction code applied to data stored in a memory device MD.

[0048] Figure 4 It is based on the comparison example Figure 1 A layout diagram of an example memory cell array. (Refer to...) Figures 1 to 4 , Figure 1 The memory cell array 100 can be implemented as Figure 4 The memory cell array 10.

[0049] The memory cell array 10 may include a plurality of bit line contacts 12. The plurality of bit line contacts 12 may be spaced apart from each other in a first direction D1 and extend in a second direction D2. The plurality of bit line contacts 12 may be respectively connected to the referenced above. Figure 2 The description corresponds to multiple bit lines BL. The interval or period between multiple bit line contacts 12 can be referred to as the bit line interval ITV_BL.

[0050] The plurality of bit line contacts 12 may comprise doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the plurality of bit line contacts 12 may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof. However, the scope of this disclosure is not limited thereto. For example, the plurality of bit line contacts 12 may include two-dimensional semiconductor materials (such as graphene, carbon nanotubes, etc.).

[0051] Multiple transistor structures TRS can be formed on multiple bit line contacts 12. For example, the multiple transistor structures TRS can be arranged in a matrix on the multiple bit line contacts 12, spaced apart in a first direction D1 and a second direction D2. Each of the multiple transistor structures TRS may include a channel structure 13 and a gate insulating layer 15. Each of the multiple transistor structures TRS can be compared with the above-referenced... Figure 2 The transistor TRs of the different memory cells MC are described.

[0052] Each of the plurality of channel structures 13 may have a width along a first direction D1 and a height along a third direction D3. In some embodiments, the height of the channel structure 13 may be greater than the width of the channel structure 13. For example, the height of the channel structure 13 may be 2 to 10 times the width of the channel structure 13, but the scope of this disclosure is not limited thereto.

[0053] In some embodiments, the channel structure 13 may include various types of oxide semiconductors (such as In...). x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Znx Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y (O, etc. or combinations thereof). However, the scope of this disclosure is not limited thereto. For example, the channel structure 13 may include two-dimensional semiconductor materials (such as graphene, carbon nanotubes, etc.).

[0054] In some embodiments, the channel structure 13 may have a bandgap energy greater than that of silicon. For example, the channel structure 13 may have a bandgap energy of 1.5 eV to 5.6 eV. As another example, the channel structure 13 may have a bandgap energy of 2.0 eV to 4.0 eV. However, the scope of this disclosure is not limited thereto.

[0055] The gate insulating layer 15 may surround the outer surface of the channel structure 13 (e.g., a surface perpendicular to the third direction D3).

[0056] In some embodiments, the gate insulating layer 15 may be formed of a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. The high-k dielectric layer may be made of a metal oxide or a metal oxide-nitride. For example, the high-k dielectric layer that can be used as the gate insulating layer 15 may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but the scope of this disclosure is not limited thereto.

[0057] In some implementations, the transistor structure TRS may be referred to as a vertical channel transistor. However, the scope of this disclosure is not limited to this type of transistor.

[0058] The memory cell array 10 may include a plurality of word line contacts 14. The plurality of word line contacts 14 may be spaced apart from each other in a second direction D2 and extend in a first direction D1. The plurality of word line contacts 14 may contact the outer surface of the transistor structure TRS (e.g., the gate insulating layer 15).

[0059] Multiple word line contacts 14 can be respectively connected to the above reference. Figure 2 The description corresponds to multiple word lines WL. The interval or period between multiple word line contacts 14 can be referred to as the word line interval ITV_WL.

[0060] In some embodiments, the word line contact 14 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line contact 14 may be doped with polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x Or a combination thereof. However, the scope of this disclosure is not limited thereto.

[0061] Capacitor structures 18 can be placed on each of the transistor structures TRS. For example, capacitor structures 18 can be arranged to be vertically stacked with each of the channel structures 13. Therefore, a plurality of capacitor structures 18 can be arranged in a matrix form spaced apart in a first direction D1 and a second direction D2. Each of the plurality of capacitor structures 18 can be referenced above. Figure 2 The capacitors CAP of the different memory cells MC are described.

[0062] In some embodiments, the lower portion of the channel structure 13 (e.g., the portion adjacent to the bit line contact 12) may be used as a first source / drain region, and the upper portion of the channel structure 13 (e.g., the portion adjacent to the capacitor structure 18) may be used as a second source / drain region. The portion between the first source / drain region and the second source / drain region of the channel structure 13 may be used as the channel of the transistor structure TRS.

[0063] In other words, according to Figure 4 An example of this is a memory cell MC, which includes a transistor structure TRS and a capacitor structure 18, located at each intersection of a plurality of bit line contacts 12 and a plurality of word line contacts 14.

[0064] Figure 5 It is simpler to show according to Figure 4 A diagram illustrating the arrangement of capacitors as an example. (Refer to...) Figures 1 to 5 The capacitor CAP connected to the memory cell MC on the first word line WL1 can be designed to be arranged at a bit-line spacing ITV_BL on the first word line WL1. Similarly, the capacitor CAP connected to the memory cell MC on the second word line WL2 can be designed to be arranged at a bit-line spacing ITV_BL on the second word line WL2.

[0065] In other words, according to Figure 4 For example, the spacing between capacitors CAP of multiple memory cells MC connected to a word line WL can be designed to have a size corresponding to the bit line spacing ITV_BL. In other words, according to Figure 4 For example, the capacitor spacing ITV_cap can be designed to have a size corresponding to the bit line spacing ITV_BL.

[0066] According to some embodiments of this disclosure, the capacitor spacing ITV_cap can be designed to have a value larger than the bit line spacing ITV_BL. In this case, even if the capacitor spacing ITV_cap becomes smaller than expected due to various reasons such as process tolerances, the probability of capacitors connected to memory cells MC on a word line WL interfering with each other can be reduced. (Refer to below...) Figures 6 to 18 This describes in more detail the specific way in which the capacitor spacing ITV_cap is designed to have a value larger than the bit line spacing ITV_BL.

[0067] Figure 6 yes Figure 1 A layout diagram of an example memory cell array. (Refer to...) Figures 1 to 3 and Figure 6 , Figure 1 The memory cell array 100 can be implemented as Figure 6 The memory cell array 100a.

[0068] The memory cell array 100a may include a plurality of bit line contacts 120, a plurality of word line contacts 140, a plurality of transistor structures TRS, a plurality of spacer contacts 160, and a plurality of capacitor structures 180. Each of the plurality of transistor structures TRS may include a channel structure 130 and a gate insulating layer 150. The configuration and function of the bit line contacts 120, word line contacts 140, channel structure 130, and gate insulating layer 150 are consistent with those described above. Figure 4 The bit line contact 12, word line contact 14, channel structure 13 and gate insulating layer 15 are configured and function similarly, and therefore their detailed descriptions are omitted.

[0069] Each of the plurality of transistor structures TRS can be connected to the spacer contact 160. For example, the spacer contact 160 can be connected to the upper surface of each of the plurality of transistor structures TRS (e.g., the surface opposite to the surface of the transistor structure TRS contact bit line contact 120).

[0070] The spacer contact 160 connected to each of the plurality of transistor structures TRS may extend in one of the second direction D2 and the direction opposite to the second direction D2. That is, in the following, an example is typically described in which each spacer contact 160 extends in a direction parallel to the direction in which the bit line contact 120 extends. However, the scope of this disclosure is not limited thereto, and the spacer contact 160 connected to each of the plurality of transistor structures TRS may extend in one of the following: an arbitrary direction perpendicular to the third direction D3 and a direction symmetrical to the third direction D3 relative to the first direction D1. For example, the spacer contact 160 connected to each of the plurality of transistor structures TRS may extend in a direction not parallel to the bit line contact 120. Reference will be made below. Figure 18 Another example is described in more detail where the spacer contact 160 extends in a direction that is not parallel to the bit line contact 120.

[0071] Each of the multiple bit line contacts 120 can be classified as odd bit line contacts 120_odd and even bit line contacts 120_even according to their arrangement order.

[0072] The spacer contact 160 connected to the transistor structure TRS connected to the odd-numbered bit line contact 120_odd may extend along the second direction D2. The spacer contact 160 connected to the transistor structure TRS connected to the even-numbered bit line contact 120_even may extend in a direction opposite to the second direction D2.

[0073] That is to say, according to some implementation methods (such as...) Figure 6 As shown in the diagram, spacer contacts 160 connected to some of the transistor structures TRS connected to a word line contact 140 may extend along a second direction D2, and spacer contacts 160 connected to other transistor structures TRS connected to a word line contact 140 may extend in a direction opposite to the second direction D2. For example, two adjacent transistor structures TRS connected to a word line contact 140 may be connected to spacer contacts 160 extending in different (e.g., opposite) directions.

[0074] In some embodiments, the lengths of the spacer contacts 160 connected to each of the plurality of transistor structure TRS may be the same. For example, the length along the second direction D2 of the spacer contacts 160 connected to each of the transistor structure TRS connected to the odd-numbered bit line contacts 120_odd may be the same as the length along the opposite direction D2 of the spacer contacts 160 connected to each of the transistor structure TRS connected to the even-numbered bit line contacts 120_even. However, the scope of this disclosure is not limited to this length configuration.

[0075] Capacitor structure 180 may be connected to spacer contact 160. For example, each spacer contact 160 may include a first contact point connected to a transistor structure TRS (e.g., channel structure 130 of transistor structure TRS) and a second contact point connected to the capacitor structure 180 (e.g., lower electrode 182 of capacitor structure 180). The second contact point may be spaced apart from the first contact point along the direction in which the spacer contact 160 extends. In some embodiments, the first and second contact points may be located on different surfaces of the spacer contact 160. Each of the plurality of capacitor structures 180 may be connected to the spacer contact 160 referenced above. Figure 2 The capacitors CAP of the different memory cells MC are described.

[0076] Therefore, in some implementations (such as) Figure 6 As shown in the diagram, the capacitor structure 180 corresponding to the transistor structure TRS connected to the odd bit line contact 120_odd can be spaced apart from the corresponding transistor structure TRS along the second direction D2; and the capacitor structure 180 corresponding to the transistor structure TRS connected to the even bit line contact 120_even can be spaced apart from the corresponding transistor structure TRS along the opposite direction of the second direction D2.

[0077] A transistor structure TRS, spacer contact 160, and capacitor structure 180 can form a memory cell MC. For example, a channel structure 130 included in the transistor structure TRS can be electrically connected to the capacitor structure 180 via spacer contact 160. In some embodiments, spacer contact 160 may comprise various types of conductive materials (such as metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, etc.). However, the scope of this disclosure is not limited to this particular composition of spacer contact 160.

[0078] Therefore, in some embodiments, the capacitor structure 180 may not be formed on the corresponding transistor structure TRS. For example, the capacitor structure 180 may be spaced apart from the transistor structure TRS by spacer contacts 160.

[0079] Figure 7 It is simpler to show according to Figure 6 A diagram showing the arrangement of the capacitors. (Refer to...) Figures 1 to 3 and Figures 6 to 7 The capacitors CAP connected to memory cells MC on different word lines WL can be shown in different patterns. In the following explanation, for the sake of brevity, the arrangement of capacitors CAP shown with horizontal stripes (i.e., capacitors CAP connected to memory cells MC on the second word line WL2) will be used as a representative example. However, the scope of this disclosure is not limited thereto, and capacitors connected to memory cells on other word lines can also be arranged in a similar manner.

[0080] The capacitors CAP connected to the memory cell MC connected to the second word line WL2 can be arranged in a zigzag pattern. For example, the capacitors CAP included in the memory cell MC connected to the odd-numbered bit lines (more specifically, odd-numbered bit line contact 120_odd) connected to the second word line WL2 can be arranged on the first straight line SLa. The capacitors CAP included in the memory cell MC connected to the even-numbered bit lines (more specifically, even-numbered bit line contact 120_even) connected to the second word line WL2 can be arranged on the second straight line SLb. The first straight line SLa and the second straight line SLb can be parallel to each other.

[0081] In this way, the capacitor spacing ITV_cap can be designed to have a larger value than the bit line spacing ITV_BL. In this case, even if the capacitor spacing ITV_cap becomes smaller than expected due to various reasons such as process errors, the probability of capacitors connected to memory cells MC on a word line WL interfering with each other can be reduced.

[0082] In some embodiments, the interval between the first straight line SLa and the second straight line SLb described above may be the word line interval ITV_WL. For example, the interval between the transistor structure TRS and the corresponding capacitor structure 180 included in the memory cell MC connected to the odd-numbered bit lines, and the interval between the transistor structure TRS and the corresponding capacitor structure 180 included in the memory cell MC connected to the even-numbered bit lines, may both be half of the word line interval ITV_WL. However, the scope of this disclosure is not limited thereto, and the gap between the transistor structure TRS and the corresponding capacitor structure 180 included in the memory cell MC connected to the odd-numbered bit lines and the gap between the transistor structure TRS and the corresponding capacitor structure 180 included in the memory cell MC connected to the even-numbered bit lines may be different from each other. For example, the length of the spacing contact 160 connected to the transistor structure TRS connected to the odd-numbered bit line contact 120_odd may be different from the length of the spacing contact 160 connected to the transistor structure TRS connected to the even-numbered bit line contact 120_even. However, in the following text, it will be assumed that the lengths of the plurality of spaced contacts 160 included in the memory cell array 100a are the same as each other, and that the spacing (or gap) between the plurality of transistor structures TRS included in the memory cell array 100a and the plurality of capacitor structures 180 corresponding thereto are the same as each other.

[0083] In some implementations, when the interval between the first straight line SLa and the second straight line SLb is the word line interval ITV_WL, the size of the capacitor interval ITV_cap of the memory cell MC connected to the second word line WL2 can be designed as the square root of the sum of the square of the word line interval ITV_WL and the square of the bit line interval ITV_BL.

[0084] In some embodiments, when the interval between the first straight line SLa and the second straight line SLb is the word line interval ITV_WL and the memory cells MC connected to other word lines WL are arranged in a similar manner, the plurality of capacitor structures 180 included in the memory cell array 100a may be arranged in a matrix structure along the first direction D1 and the second direction D2. For example, the capacitor CAP included in a portion of the memory cells MC connected to the first word line WL1 may be arranged on the first straight line SLa; and the capacitor CAP included in a portion of the memory cells MC connected to the third word line WL3 may be arranged on the second straight line SLb.

[0085] As a result, when the structure of the memory cell array 100a is compared with that of the reference... Figure 4 and Figure 5 When compared to the described memory cell array 10a, the memory cell array 100a can be implemented with an area substantially the same as that of the memory cell array 10a, and the capacitor spacing ITV_cap for the memory cells MC connected to a word line WL can be maximized. Therefore, the probability of errors simultaneously occurring in bits stored in the memory cells MC connected to a word line WL (e.g., uncorrectable errors) can be reduced, thereby improving the reliability of the memory device MD.

[0086] Furthermore, according to some embodiments of this disclosure, the capacitor CAP closest to the capacitor CAP included in the memory cell MC connected to a specific word line can be the capacitor CAP included in the memory cell MC connected to another word line WL. Therefore, even if a bit stored in one capacitor CAP is corrupted and it causes a bit stored in another capacitor CAP closest to that capacitor CAP to be corrupted, the probability of successful error correction based on the error correction code can be increased because the corrupted bit exists in memory cells connected to different word lines.

[0087] For a simpler explanation, in Figure 7An embodiment with a single-gate transistor structure is described exemplary, in which the transistor structure TRS is surrounded by word line contacts 140, but the scope of this disclosure is not limited thereto. For example, the word line contacts 140 may be implemented to contact only one side of the transistor structure TRS. Furthermore, the transistor structure TRS may be implemented as a dual-gate transistor structure, in which the transistor structure TRS contacts not only the word line contacts 140 but also a back gate contact (not shown). Reference is made below. Figures 11 to 17 An embodiment of the transistor structure TRS with a dual-gate transistor structure is described in more detail.

[0088] Figures 8 to 10 To show in more detail Figure 6 A diagram illustrating an example structure of a memory cell array. For example, Figure 8 To show in more detail Figure 6 A three-dimensional diagram of the structure of a memory cell array. Figure 9 It is along Figure 6 The sectional view taken by line A1-A1', and Figure 10 It is along Figure 6 The sectional view taken by line B1-B1'.

[0089] For a simpler explanation, in Figure 8 An example of a single-gate transistor structure is described exemplarily, in which the transistor structure TRS is surrounded by word line contacts 140, but the scope of this disclosure is not limited thereto. For example, the word line contacts 140 may be implemented to contact only one side of the transistor structure TRS. Furthermore, the transistor structure TRS may be implemented as a dual-gate transistor structure, in which the transistor structure TRS contacts not only the word line contacts 140 but also a back gate contact (not shown). Reference is made below. Figures 11 to 17 A more detailed description of the transistor structure TRS is provided, including an example of a dual-gate transistor structure.

[0090] Reference Figures 1 to 3 and Figures 6 to 10 The memory cell array 100a may include a substrate 110, a channel layer LCH, a capacitor spacer layer LCS, and a capacitor layer LCAP.

[0091] The channel layer LCH may be located on the substrate 110. The channel layer LCH may include a lower insulating layer 112, bit line contacts 120, a first insulating pattern 122, a channel structure 130, an insulating structure 132, word line contacts 140, and a gate insulating layer 150.

[0092] The capacitor spacer layer LCS may be located on the channel layer LCH. The capacitor spacer layer LCS may include a plurality of spacer contacts 160 and a second insulating pattern 162.

[0093] The capacitor layer LCAP may be located on the capacitor spacer layer LCS. The capacitor layer LCAP may include an etch stop layer 170 and multiple capacitor structures 180.

[0094] A lower insulating layer 112 may be located on a substrate 110. On the lower insulating layer 112, a plurality of bit line contacts 120 may be arranged spaced apart from each other in a first direction D1 and extend in a second direction D2. A first insulating pattern 122 may be arranged on the lower insulating layer 112 to fill the space between the plurality of bit line contacts 120. The first insulating pattern 122 may extend in the second direction D2, and the upper surface of the first insulating pattern 122 may be at the same level as the upper surfaces of the plurality of bit line contacts 120. Each of the plurality of bit line contacts 120 may serve as a bit line BL.

[0095] Multiple channel structures 130 may be arranged in a matrix form spaced apart along a first direction D1 and a second direction D2 on multiple bit line contacts 120. Each of the multiple channel structures 130 may have a first width along the first direction D1 and a first height along the third direction D3. The side surface of each of the multiple channel structures 130 (e.g., a side surface parallel to the third direction D3) may be surrounded by a gate insulating layer 150.

[0096] Multiple word line contacts 140 may be spaced apart from each other in a second direction D2 and extend in a first direction D1. The multiple word line contacts 140 may contact the side surface of the transistor structure TRS (e.g., gate insulating layer 150).

[0097] An insulating structure 132 may be formed on the first insulating pattern 122 and the plurality of bit line contacts 120. The insulating structure 132 may fill any remaining space within the channel layer LCH that is not filled by the transistor structures TRS and word line contacts 140. For example, the insulating structure 132 may be implemented to fill the space between the word line contacts 140, the space between the plurality of word line contacts 140 and the capacitor spacer layer LCS, and the space between the plurality of word line contacts 140 and the plurality of bit line contacts 120. The upper surface of the insulating structure 132 may be at the same level as the upper surfaces of the plurality of transistor structures TRS (e.g., the level of the upper surface of the channel layer LCH).

[0098] The scope of this disclosure is not limited to Figures 8 to 10 The configuration of the insulating structure 132 is shown. For example, the insulating structure 132 may be implemented as a combination of two or more insulating structures (e.g., insulating patterns) comprising insulating material.

[0099] Multiple spacer contacts 160 may be formed on the channel layer LCH. The multiple spacer contacts 160 may be connected to the upper surfaces of different transistor structures TRS. Each of the multiple spacer contacts 160 may extend from a contact point of the transistor structure TRS in a second direction D2 or in a direction opposite to the second direction D2. A second insulating pattern 162 may fill any remaining space within the capacitor spacer layer LCS that is not filled by the multiple spacer contacts 160.

[0100] An etch stop layer 170 may be located on the capacitor spacer layer LCS. The etch stop layer 170 may be implemented as an insulator. Multiple capacitor structures 180 may be arranged on the etch stop layer 170. However, for the purpose of clarifying the clear relationship between the main technical components of this disclosure, the etch stop layer 170 is shown in... Figure 8 The middle part is omitted.

[0101] Each capacitor structure 180 may include a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. In some embodiments, multiple capacitor structures 180 may share an upper electrode 186 configured to receive a plate voltage from an external source. However, the scope of this disclosure is not limited thereto.

[0102] The lower electrode 182 can penetrate the etch stop layer 170 and is electrically connected to a surface (e.g., the upper surface) of the spacer contact 160. The lower electrode 182 can be formed as a pillar type extending in the third direction D3, but the scope of this disclosure is not limited thereto.

[0103] Thus, in some embodiments, the first point on the substrate 110 corresponding to the transistor structure TRS (e.g., the first position in coordinates D1, D2) may differ from the second point on the substrate 110 corresponding to the capacitor structure 180 electrically connected to the transistor structure TRS (e.g., the second position in coordinates D1, D2). For example, the transistor structure TRS may extend in the third direction D3 from a point spaced a first distance from the first position on the substrate 110 in the third direction D3, and the capacitor structure 180 electrically connected to the transistor structure TRS may extend in the third direction D3 from a point spaced a second distance from the second position on the substrate 110 in the third direction D3. The first position of the first line contacting the substrate 110 may differ from the second position of the second line contacting the substrate 110, wherein the first line extends in the opposite direction of the third direction D3 from the point of the transistor structure TRS contact bit line contact 120, and wherein the second line extends in the opposite direction of the third direction D3 from the point of the capacitor structure 180 electrically connected to the transistor structure TRS contact spacer contact 160.

[0104] Figure 11 yes Figure 1 A layout diagram of another example of a memory cell array. (Refer to...) Figures 1 to 3 and Figure 11 , Figure 1 The memory cell array 100 can be implemented as Figure 11 The memory cell array 100b.

[0105] The memory cell array 100b may include a plurality of bit line contacts 120, a plurality of word line contacts 140, a plurality of back gate contacts 140BG, and a plurality of transistor structures TRS. Each of the plurality of transistor structures TRS may include a channel structure 130 and a gate insulating layer 150. That is, as referenced above... Figure 6 The description provided for memory cell array 100a differs from that provided for memory cell array 100b, which may further include a plurality of back gate contacts 140BG. The plurality of back gate contacts 140BG may correspond to the back gate terminals of a plurality of transistor structures TRS. For example, the plurality of back gate contacts 140BG may define the bulk potential of the plurality of transistor structures TRS. In some embodiments, each of the plurality of back gate contacts 140BG and the plurality of word line contacts 140 may be referred to as a gate contact.

[0106] As already referred to above Figure 6 The configuration and function of the bit line contacts 120, channel structure 130, multiple word line contacts 140, and gate insulating layer 150 are described, therefore their detailed descriptions are omitted. The differences between memory cell array 100b and memory cell array 100a will be explained below.

[0107] Multiple word line contacts 140 may extend in a first direction D1 and may contact a first side surface of a transistor structure TRS. Multiple back gate contacts 140BG may extend in the first direction D1 and may contact a second surface located opposite the first side surface of the transistor structure TRS. In some embodiments, each of the multiple transistor structures TRS may contact one word line contact 140 and one back gate contact 140BG.

[0108] Each of the plurality of word line contacts 140 can be classified as odd number line contacts 140_odd and even number line contacts 140_even according to the arrangement order. Each of the plurality of back gate contacts 140BG can be classified as odd number back gate contacts 140BG_odd and even number back gate contacts 140BG_even according to the arrangement order.

[0109] Odd-number line contacts 140_odd can contact the transistor structure TRS along the second direction D2, and even-number line contacts 140_even can contact the transistor structure TRS along the opposite direction of the second direction D2. Odd-number back gate contacts 140BG_odd can contact the transistor structure TRS along the opposite direction of the second direction D2, and even-number back gate contacts 140BG_even can contact the transistor structure TRS along the second direction D2.

[0110] Therefore, the multiple word line contacts 140 and the multiple back gate contacts 140BG can be arranged alternately in pairs along the second direction D2. Thus, the spacing between the multiple word line contacts 140 may not be uniform (it can be variable). For example, the spacing between the multiple word line contacts 140 can be determined by one of a first word line spacing ITV_WLa and a second word line spacing ITV_WLb.

[0111] The first word line spacing ITV_WLa can refer to the spacing between two adjacent word line contacts 140 when no back gate contact 140BG is placed between the word line contacts 140. The second word line spacing ITV_WLb can refer to the spacing between two adjacent word line contacts 140 when a back gate contact 140BG is placed between the word line contacts 140.

[0112] The spacer contact 160, connected to each of the multiple transistor structures TRS, may extend in the second direction D2 or in a direction opposite to the second direction D2. A capacitor structure 180 may be connected to each of the spacer contacts 160. The specific scheme of how the capacitor structure 180 is connected to each of the multiple transistor structures TRS via the spacer contacts 160 is the same as described above. Figure 6 The described solutions are similar, therefore detailed descriptions have been omitted.

[0113] Figure 12 It is simpler to show according to Figure 11 A diagram showing the arrangement of the capacitors. (Refer to...) Figures 1 to 3 and Figures 11 to 12 The capacitors CAP connected to memory cells MC on different word lines WL are shown in different patterns. For example, the arrangement of capacitors CAP connected to memory cells MC on the second word line WL2, shown in horizontal stripes, will be described representatively below. However, the scope of this disclosure is not limited thereto, and capacitors connected to memory cells on other word lines may also be arranged in a similar manner.

[0114] Reference above Figure 7Similarly, the capacitors CAP connected to the memory cells MC connected to the second word line WL2 can be arranged in a zigzag pattern. For example, the capacitors CAP included in the memory cells MC connected to the odd-numbered bit lines (more specifically, the odd-numbered bit line contact BL_odd) can be arranged on the first straight line SLa. The capacitors CAP included in the memory cells MC connected to the even-numbered bit lines (more specifically, the even-numbered bit line contact BL_even) can be arranged on the second straight line SLb. In this way, the capacitor spacing ITV_cap can be designed to be larger than the bit line spacing ITV_BL.

[0115] The interval between the first line SLa and the second line SLb can be called the average word line interval ITV_WL_AVG. The average word line interval ITV_WL_AVG can be the average of the first word line interval ITV_WLa and the second word line interval ITV_WLb.

[0116] In some implementations, the size of the capacitor spacing ITV_cap for the memory cell MC connected to the second word line WL2 can be designed as the square root of the sum of the square of the average word line spacing ITV_WL_AVG and the square of the bit line spacing ITV_BL.

[0117] The capacitors CAP connected to the memory cells MC of other word lines WL can be arranged in a similar manner. In this case, the plurality of capacitor structures 180 included in the memory cell array 100b can be arranged in a matrix along the first direction D1 and the second direction D2. For example, the capacitors CAP included in some of the memory cells MC connected to the first word line WL1 can be arranged on the first straight line SLa; and the capacitors CAP included in some of the memory cells MC connected to the third word line WL3 can be arranged on the second straight line SLb.

[0118] As a result, in some implementations, the above reference is made... Figure 6 and Figure 7 Similar to the described memory cell array 100a, the capacitor spacing ITV_cap for memory cells MC connected to a word line WL can be increased. Therefore, when Figure 1 When the memory cell array 100 is implemented as memory cell array 100b, the probability of an error occurring simultaneously in bits stored in memory cells MC connected to a word line WL (e.g., the probability of an uncorrectable error occurring) can be reduced, and thus the reliability of the memory device MD can be improved.

[0119] Figures 13 to 16 To show in more detail Figure 11A diagram illustrating an example structure of a memory cell array. For example, Figure 13 To show in more detail Figure 11 A three-dimensional diagram of the structure of a memory cell array. Figure 14 It is along Figure 11 The sectional view taken by line A2-A2'. Figure 15 It is along Figure 11 The sectional view taken by line A3-A3', and Figure 16 It is along Figure 11 The sectional view taken by line B2-B2'.

[0120] Reference Figures 1 to 3 and Figures 13 to 16 The memory cell array 100b may include a substrate 110, a channel layer LCH, a capacitor spacer layer LCS, and a capacitor layer LCAP.

[0121] A channel layer LCH may be located on a substrate 110. The channel layer LCH may include a lower insulating layer 112, bit line contacts 120, a first insulating pattern 122, a channel structure 130, an insulating structure 132, word line contacts 140, a back gate contact 140BG, and a gate insulating layer 150. A capacitor spacer layer LCS may be located on the channel layer LCH. The capacitor spacer layer LCS may include multiple spacer contacts 160 and a second insulating pattern 162. A capacitor layer LCAP may be located on the capacitor spacer layer LCS. The capacitor layer LCAP may include an etch stop layer 170 and multiple capacitor structures 180. The following description will primarily refer to the above. Figures 8 to 10 The differences in the structure of the described memory cell array 100a; for Figures 8 to 10 The provided description may be applied in other ways. Figures 13 to 16 .

[0122] The lower insulating layer 112 may be located on the substrate 110. A plurality of bit line contacts 120 and a first insulating pattern 122 may be arranged on the lower insulating layer 112.

[0123] Multiple channel structures 130 can be arranged in a matrix form spaced apart along a first direction D1 and a second direction D2 on multiple bit line contacts 120. The side surface of each of the multiple channel structures 130 can be surrounded by a gate insulating layer 150. That is, multiple transistor structures TRS can be arranged as shown above. Figures 6 to 10 Arranged in a similar manner as described.

[0124] Multiple word line contacts 140 and multiple back gate contacts 140BG may be spaced apart from each other in a second direction D2 and may extend in a first direction D1. Each of the multiple word line contacts 140 and multiple back gate contacts 140BG is accessible to the opposite side surface of the transistor structure TRS (e.g., gate insulating layer 15). (Referring above...) Figure 11 The order in which the multiple word line contacts 140 and the multiple back gate contacts 140BG are arranged is described, therefore a detailed description thereof is omitted.

[0125] Multiple spacer contacts 160 may be formed on the channel layer LCH. Multiple capacitor structures 180 may be arranged on the capacitor spacer layer LCS.

[0126] Figure 17 yes Figure 1 A layout diagram of an example memory cell array. (Refer to...) Figures 1 to 3 , Figure 11 as well as Figure 17 , Figure 1 The memory cell array 100 can be implemented as Figure 17 The memory cell array 100c. The memory cell array 100c can be compared with the above reference. Figure 11 The memory cell array 100b described is implemented similarly. The differences between memory cell array 100c and memory cell array 100b will be explained below.

[0127] The memory cell array 100c can be implemented as a single back gate contact 140BG, comprising odd-numbered back gate contacts 140BG_odd and even-numbered back gate contacts 140BG_even that are adjacent to each other in the memory cell array 100b. In this case, the plurality of word line contacts 140 and the plurality of back gate contacts 140BG included in the memory cell array 100c can be arranged along the second direction D2, alternating with one back gate contact and two word line contacts.

[0128] The arrangement and spacing of each capacitor structure 180 included in the memory cell array 100c are as described above. Figures 11 to 16 The layout and spacing are described similarly, and therefore, their detailed descriptions are omitted.

[0129] Figure 18 yes Figure 1 A layout diagram of an example memory cell array. (Refer to...) Figures 1 to 18 , Figure 1 The memory cell array 100 can be implemented as Figure 18 The memory cell array 100d. The differences between memory cell array 100d and memory cell array 100a will be explained below.

[0130] The memory cell array 100d may include a plurality of bit line contacts 120, a plurality of word line contacts 140, a plurality of transistor structures TRS, a plurality of spacer contacts 160, and a plurality of capacitor structures 180. Since the configuration and arrangement of the bit line contacts 120, word line contacts 140, and the plurality of transistor structures TRS are similar to those described above with reference to the memory cell array 100a, their detailed descriptions are omitted.

[0131] Spacer contacts 160 may be connected to the upper surface of each of the plurality of transistor structures TRS. The spacer contacts 160 connected to each of the plurality of transistor structures TRS may extend in one of any particular direction perpendicular to the third direction D3 and in a direction symmetrical to the first direction D1 (e.g., a direction reflected across the first direction D1).

[0132] For example, each spacer contact 160 may extend from a contact point with the corresponding transistor structure TRS along one of a fourth direction D4 and a fifth direction D5, the fourth direction D4 being perpendicular to the third direction D3 and having an angle of "+a degrees" relative to the first direction D1, and the fifth direction D5 being perpendicular to the third direction D3 and having an angle of "-a degrees" relative to the first direction D1. The fourth direction D4 and the fifth direction D5 may be symmetrical with respect to the first direction D1. In some embodiments, reference is made to the above. Figure 6 The example described corresponds to the case where angle "a" is "90 degrees".

[0133] The spacer contact 160 connected to each of the plurality of transistor structures TRS connected to the odd-numbered bit line contact 120_odd may extend along the fourth direction D4. The spacer contact 160 connected to each of the plurality of transistor structures TRS connected to the even-numbered bit line contact 120_even may extend along the fifth direction D5.

[0134] Figure 18 An example of spacer contact 160 extending in a straight line is shown, but the scope of this disclosure is not limited to a particular shape of spacer contact 160. For example, spacer contact 160 may be implemented in a curved shape (such as the shape of the letter "L").

[0135] Capacitor structure 180 may be connected to each of the spacer contacts 160. For example, spacer contacts 160 may include a first contact connected to transistor structure TRS and a second contact connected to capacitor structure 18. In this case, the second contact may be spaced apart from the first contact along the direction in which spacer contacts 160 extend. For example, capacitor structure 18 may be spaced apart from the corresponding transistor structure TRS along a fourth direction D4 or along a fifth direction D5. In this case, referencing the above... Figure 6 and Figure 7The description is similar, and the size of the capacitor spacing ITV_cap for a memory cell MC connected to a word line WL can be designed as the square root of the sum of the square of the word line spacing ITV_WL and the square of the bit line spacing ITV_BL.

[0136] For a more concise explanation, Figure 18 Representative description with Figure 6 The memory cell array 100d is configured in a similar manner to the memory cell array 100a, but the scope of this disclosure is not limited thereto. For example, the extending direction of the spacer contact 160 and the arrangement of the capacitor structure 180 described in the memory cell array 100d can be applied in a similar manner to the above-mentioned reference. Figure 11 The memory cell array 100b described above or referenced above Figure 17 The memory cell array 100c is described.

[0137] Figure 19 This is a block diagram illustrating an example configuration of a memory system. (See reference...) Figures 1 to 19 The memory system 1000 may include a host device 1100 and a memory device 1200.

[0138] The host device 1100 can control the memory device 1200 by issuing various types of commands (CMD) and addresses (ADDR). For example, the host device 1100 can issue a read command to read data DATA from the memory device 1200, or issue a write command to store data DATA in the memory device 1200.

[0139] In some implementations, the host device 1100 can issue various types of commands (CMD) and addresses (ADDR) in the form of command / address signals (C / A).

[0140] In some implementations, host device 1100 may include one of various types of processors, such as central processing unit (CPU), graphics processing unit (GPU), etc.

[0141] In some implementations, host device 1100 may execute error correction codes. For example, host device 1100 may execute a single error correction code (SEC). In this case, host device 1100 can correct errors in the read data only if one bit or less of an error occurs in the data read simultaneously from memory device 1200.

[0142] The memory device 1200 can be implemented as described above. Figures 1 to 18The memory device MD is described. For example, memory device 1200 may include a memory cell array 100 in which capacitors CAP connected to a plurality of memory cells MC connected to a word line WL are arranged in a zigzag pattern. In this case, the probability of 2-bit or more bit errors occurring in data simultaneously read from memory device 1200 by host device 1100 can be minimized. Specifically, if host device 1100 is implemented to perform SEC, the probability of uncorrectable errors occurring in data simultaneously read from memory device 1200 by host device 1100 can be reduced. Therefore, the operational reliability of memory system 1000 can be improved.

[0143] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual implementations in this disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in a particular combination, in some cases one or more features from the combination may be removed from that combination, and the combination may involve sub-combinations or variations thereof.

[0144] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. A memory cell array, comprising: The first memory cell includes a first transistor structure and a first capacitor structure; The second memory cell includes a second transistor structure and a second capacitor structure; as well as The first word line contact is electrically connected to the first transistor structure and the second transistor structure. The first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.

2. The memory cell array according to claim 1, wherein: The first letter contact extends upwards on the third side, and The first and second directions are symmetric about the third direction.

3. The memory cell array according to claim 2, wherein: The second direction is opposite to the first direction.

4. The memory cell array according to claim 1, wherein: The first gap between the first capacitor structure and the first transistor structure is the same as the second gap between the second capacitor structure and the second transistor structure.

5. The memory cell array according to claim 1, wherein: The first memory cell also includes a first spacer contact electrically connected between the first transistor structure and the first capacitor structure. The second memory cell also includes a second spacer contact electrically connected between the second transistor structure and the second capacitor structure. The first spacer contact includes a first contact point and a second contact point. The first spacer contact is electrically connected at the first contact point to a first channel structure included in the first transistor structure, and at the second contact point to a first lower electrode included in the first capacitor structure. The second spacer contact includes a third contact point and a fourth contact point. The second spacer contact is electrically connected at the third contact point to a second channel structure included in the second transistor structure, and at the fourth contact point to a second lower electrode included in the second capacitor structure. The second contact point is spaced apart from the first contact point in the first direction, and The fourth contact point is spaced apart from the third contact point in the second direction.

6. The memory cell array according to claim 1, wherein: The first transistor structure is connected to the first bit line contact, and The second transistor structure is connected to a second bit line contact that is adjacent to the first bit line contact among a plurality of sequentially arranged bit line contacts.

7. The memory cell array according to claim 6, wherein: The capacitor spacing between the first capacitor structure and the second capacitor structure is larger than the bit line spacing between the first bit line contact and the second bit line contact.

8. The memory cell array according to claim 1, further comprising: A third memory cell includes a third transistor structure electrically connected to a first word line contact, wherein the third memory cell includes a third capacitor structure; and The fourth memory cell includes a fourth transistor structure electrically connected to the first word line contact, wherein the fourth memory cell includes a fourth capacitor structure. The first capacitor structure and the third capacitor structure are arranged on a first straight line, and the second capacitor structure and the fourth capacitor structure are arranged on a second straight line parallel to the first straight line.

9. The memory cell array according to claim 8, further comprising: The fifth memory cell includes a fifth transistor structure and a fifth capacitor structure; The sixth memory cell includes a sixth transistor structure and a sixth capacitor structure; The second word line contact is electrically connected to the fifth transistor structure; as well as The third word line contact is electrically connected to the sixth transistor structure. The fifth transistor structure is arranged on the first straight line, and the sixth transistor structure is arranged on the second straight line.

10. The memory cell array according to claim 9, wherein: The first letter spacing is the spacing between the first letter contact and the second letter contact. The second letter spacing is the spacing between the first letter contact and the third letter contact. The average of the first and second character line intervals is the first length. The bit line spacing between the bit line contacts of the memory cell array is the second length, and The capacitor spacing between the first capacitor structure and the second capacitor structure is the square root of the sum of the square of the first length and the square of the second length.

11. A memory cell array, comprising: Base; A channel layer, on a substrate, wherein the channel layer includes a first transistor structure; and A capacitor layer includes a first capacitor structure, wherein the first capacitor structure is electrically connected to a first transistor structure. The first point on the substrate corresponding to the first transistor structure is different from the second point on the substrate corresponding to the first capacitor structure.

12. The memory cell array according to claim 11, wherein: At a third point, spaced a first distance from the first point along a first direction perpendicular to the substrate, the first transistor structure extends along the first direction. At a fourth point, spaced a second distance from the second point along the first direction, the first capacitor structure extends along the first direction.

13. The memory cell array according to claim 11, further comprising: A capacitor spacer layer includes a first spacer contact that electrically connects a first transistor structure and a first capacitor structure, wherein the capacitor spacer layer is located between a channel layer and a capacitor layer.

14. The memory cell array according to claim 13, wherein: The first spacer contact extends in a second direction, wherein the second direction is parallel to the direction from the first point to the second point.

15. The memory cell array according to claim 14, wherein: The channel layer also includes a second transistor structure. The capacitor layer also includes a second capacitor structure corresponding to the second transistor structure. The capacitor spacer layer also includes a second spacer contact that electrically connects the second transistor structure and the second capacitor structure. The first transistor structure and the second transistor structure are electrically connected to the first word line contact, and The second spacer contact extends upward in a third direction, different from the second direction.

16. The memory cell array according to claim 15, wherein: The first transistor structure is electrically connected to the first bit line contact, and The second transistor structure is electrically connected to a second bit line contact that is adjacent to the first bit line contact among a plurality of bit line contacts.

17. A memory device comprising: Memory cell array; Multiple word lines are electrically connected to the memory cell array; as well as Multiple bit lines are electrically connected to the memory cell array, wherein: The plurality of character lines includes the first character line. The memory cell array includes a first plurality of memory cells electrically connected to a first word line. The first plurality of memory cells each include a first plurality of capacitor structures, and The capacitor spacing for the first plurality of capacitor structures is larger than the bit line spacing for the plurality of bit lines.

18. The memory device according to claim 17, wherein: The multiple character lines also include a second character line. The memory cell array also includes a second plurality of memory cells electrically connected to the second word line. The second plurality of memory cells each include a second plurality of capacitor structures, and Each capacitor structure in the second plurality of capacitor structures is spaced equidistant from its corresponding capacitor structure in the first plurality of capacitor structures along a first direction.

19. The memory device according to claim 17, wherein: The multiple bit lines include multiple odd-numbered bit lines and multiple even-numbered bit lines. The first plurality of memory cells includes a third plurality of memory cells and a fourth plurality of memory cells, wherein the third plurality of memory cells are electrically connected to the plurality of odd-numbered bit lines, and the fourth plurality of memory cells are electrically connected to the plurality of even-numbered bit lines. The capacitor structure, including those in the third and a half memory cells, is arranged on the first straight line, and The capacitor structure included in the fourth plurality of memory cells is arranged on a second straight line parallel to the first straight line.

20. The memory device according to claim 17, wherein: The capacitor spacing is the square root of the sum of the squares of the average word line spacing and the squares of the bit line spacing for the multiple word lines.

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