Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is provided, including a substrate including a cell block region; a first bit line extending in a first direction on the cell block region; and a landing pattern extending in a second direction crossing the first direction. The landing pattern includes a first landing pattern crossing the first bit line, and a second landing pattern spaced apart from the first landing pattern in the first direction. An end of the first bit line is located between the first landing pattern and the second landing pattern.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0016644, filed on February 10, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor, and more specifically, to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices have gained attention as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices for storing, for example, logic data; semiconductor logic devices for calculating and processing logic data; and hybrid semiconductor devices that include both memory and logic components.

[0004] Recently, with the increasing speed and low power consumption of electronic devices, the semiconductor devices embedded within them also require high operating speeds and low operating voltages. To meet these requirements, semiconductor devices are becoming more highly integrated, and much research is underway in this area. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved integration and a method for manufacturing the semiconductor device.

[0006] This disclosure also provides semiconductor devices with improved electrical characteristics and reliability.

[0007] The technical objectives of this invention are not limited to those described above, and other technical objectives not mentioned can be clearly understood by those skilled in the art from the following description.

[0008] An embodiment of the present invention provides a semiconductor device comprising: a substrate including a cell block region; a first line extending in a first direction over the cell block region; and a bonding pattern extending in a second direction intersecting the first direction, wherein the bonding pattern comprises: a first bonding pattern intersecting the first line; and a second bonding pattern spaced apart from the first bonding pattern in the first direction, and one end of the first line being located between the first bonding pattern and the second bonding pattern.

[0009] In an embodiment of the present invention, a semiconductor device includes: a substrate including a cell block region; a first line extending in a first direction over the cell block region; and a bonding pattern extending in a second direction intersecting the first direction, wherein the bonding pattern includes: a first bonding pattern intersecting the first line; and a second bonding pattern spaced apart from the first bonding pattern in the first direction, the first line including a first end adjacent to the first bonding pattern, the second bonding pattern spaced apart from the first end in the first direction, and the second bonding pattern having a greater thickness than the first bonding pattern.

[0010] In an embodiment of the present invention, a semiconductor device includes: a substrate including a cell block region; a first bit line and a second bit line extending over the cell block region in a first direction and approaching each other in a second direction intersecting the first direction; a bonding pattern extending in the second direction; and a contact plug electrically connected to the second bit line, wherein the bonding pattern includes: a first bonding pattern intersecting the first bit line and the second bit line; and a second bonding pattern spaced apart from the first bonding pattern in the first direction, the first bit line including a first end adjacent to the first bonding pattern, the second bonding pattern spaced apart from the first end in the first direction, and the second bonding pattern being located between the first bonding pattern and the contact plug.

[0011] In an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a first line extending in a first direction on a substrate including a cell block region; forming a word line intersecting the first line; and forming an attachment pattern extending in a second direction intersecting the first direction, wherein the attachment pattern includes a first attachment pattern intersecting the first line and a second attachment pattern spaced apart from the first attachment pattern in the first direction, and an end of the first line is located between the first attachment pattern and the second attachment pattern.

[0012] In an embodiment, the method for manufacturing a semiconductor device may further include: forming a bonding insulating pattern between a first bonding pattern and a second bonding pattern, wherein the end of the first line may vertically overlap with the bonding insulating pattern.

[0013] In one embodiment, the bottom surface of the bonding insulating pattern may be located at a lower level than the bottom surface of the first bonding pattern.

[0014] In an embodiment, the first bonding pattern may have a lower height than the second bonding pattern.

[0015] In an embodiment, the method for manufacturing a semiconductor device may further include: forming a bit line capping pattern on a first bit line, wherein a first bonding pattern may vertically overlap with the bit line capping pattern, and a second bonding pattern may be spaced apart from the bit line capping pattern in a first direction.

[0016] In an embodiment, forming a bonding pattern may include: forming a bonding pad layer on a cell block region; forming an insulating via by etching the bonding pad layer; and filling the insulating via with an insulating material.

[0017] In an embodiment, etching the bonding pad layer may include: forming a mask pattern on the bonding pad layer; and performing an etching process by using the mask pattern as a mask, wherein the mask pattern may be positioned to vertically overlap with the portion forming the bonding pattern.

[0018] In an embodiment, the insulating hole may include a first insulating hole that exposes a bit line capping pattern and a second insulating hole that exposes a polysilicon portion, and the first insulating hole may have a shallower depth than the second insulating hole.

[0019] In an embodiment, the method for manufacturing a semiconductor device may further include: forming a second bit line close to the first bit line in a second direction; forming a bit line pad connected to the second bit line; and forming a contact plug on the bit line pad, wherein the second bit line can be connected to the contact plug through the bit line pad, and a second bonding pattern can be located between the first bonding pattern and the contact plug.

[0020] In an embodiment, the second bonding pattern may vertically overlap with at least a portion of the bit line pad. Attached Figure Description

[0021] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0022] Figure 1 This is a diagram showing a substrate on which a semiconductor device according to an embodiment of the present invention is integrated;

[0023] Figure 2A and Figure 2B Is with Figure 1 The enlarged view corresponding to X1 in the image;

[0024] Figure 3 It shows Figure 2A and Figure 2B A diagram of the unit block group region in the diagram;

[0025] Figure 4 It shows Figure 3 A plan view of the unit block region in the diagram, serving as a diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention;

[0026] Figure 5A Is with Figure 4 The cross-sectional view corresponding to line A-A' in the diagram;

[0027] Figure 5B Is with Figure 4 The cross-sectional view corresponding to line B-B' in the diagram;

[0028] Figure 5C Is with Figure 4 The cross-sectional view corresponding to line C-C' in the diagram;

[0029] Figure 6A It shows Figure 3 A plan view of the unit block region in the diagram, serving as a diagram illustrating a semiconductor device of a comparative example according to the concept of the present invention;

[0030] Figure 6B Is with Figure 6A The cross-sectional view corresponding to line C-C' in the diagram; and

[0031] Figures 7A to 12C This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0032] In the following description, embodiments of the invention will be described in more detail with reference to the accompanying drawings, so as to illustrate the inventive concept more specifically.

[0033] Articles described herein in a singular form may be provided in a plural form, as can be seen, for example, in the accompanying drawings. Therefore, a description of a single article provided in a plural form should be understood to apply to the remaining multiple articles, unless the context otherwise indicates.

[0034] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise requires. On the other hand, the term “composed of” indicates that the component is formed solely by the listed elements.

[0035] It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on top of" another element, the element may be directly connected or coupled to that other element or directly on that other element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or "in contact" with another element (or in any form that uses the word "in contact"), there is no intermediate element at the point of contact.

[0036] Ordinal numbers such as "first," "second," and "third" can simply be used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0037] Terms such as “identical,” “equal,” “constant,” and “flat” as used herein are intended to encompass meanings including typical variations resulting from conventional manufacturing processes and / or tolerances acceptable in the manufacturing processes of semiconductor devices, unless the context or other statements indicate otherwise. For example, “identical” and “equal” can cover identical or nearly identical. The term “substantially” may be used herein to emphasize this meaning.

[0038] Figure 1 This is a diagram showing a substrate on which a semiconductor device according to an embodiment of the present invention is integrated. Figure 2A and Figure 2B Is with Figure 1 The enlarged view corresponding to X1 in the image. Figure 3 It shows Figure 2A and Figure 2B The diagram of the unit block group region in the diagram.

[0039] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3 The substrate 100 may include chip regions CH on which a semiconductor integrated circuit is located, and scribe lane regions SL located between the chip regions CH. The substrate 100 may be any type of semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In this specification, each of the expressions "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any one of the items listed together with its corresponding expression, or all possible combinations thereof.

[0040] The chip region CH can be arranged two-dimensionally along a first direction D1 and a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1. The first direction D1 and the second direction D2 can each be parallel to the lower surface of the substrate 100. Each chip region CH can be surrounded by a scribe line region SL.

[0041] The scribing region SL may include a plurality of first scribing regions extending in a first direction D1, and a plurality of second scribing regions intersecting the first scribing regions and extending in a second direction D2. The scribing region SL may include a cutting lane region cut by a saw or cutter, and an edge lane region located between the chip region CH and the cutting lane region. The edge lane regions may each surround the chip region CH. For example, in a plan view, the cutting lane region may be located between adjacent chip regions CH, and the edge lane region may be positioned between the chip region CH and the cutting lane region.

[0042] Semiconductor devices may be disposed on the chip region CH of substrate 100. For example, semiconductor memory devices (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, and resistive random access memory (RRAM)) may be disposed on the chip region CH. As another example, processors (such as microelectromechanical systems (MEMS) devices, optoelectronic devices, CPUs, or DSPs) may be disposed on the chip region CH. As yet another example, standard cells comprising semiconductor devices (such as logic AND gates or logic product gates) may be disposed on the chip region CH of substrate 100.

[0043] Each chip region (CH) can include a peripheral region (PER) and a cell block group region (CBS). Peripheral circuitry can be located on the peripheral region (PER). Peripheral circuitry can perform command / addressing, power generation, and / or data input / output (DQ).

[0044] Each chip region (CH) may include a single peripheral region (PER) or multiple peripheral regions (PER), and may include a single cell block group region (CBS) or multiple cell block group regions (CBS). For example, Figure 2A As shown, the chip region CH may include a pair of cell block group regions CBS that are close to each other in the first direction D1, and a peripheral region PER between the pair of cell block group regions CBS. For example, as... Figure 2B As shown, the chip region CH may include a pair of peripheral regions PER that are close to each other in the first direction D1, and a cell block group region CBS between the pair of peripheral regions PER. However, this is an example, and the inventive concept is not limited thereto.

[0045] The cell block group region CBS can be located close to the surrounding regions PER and SL in the first direction D1. The surrounding regions PER and SL can include the outer region PER and the lane region SL. For example, as Figure 2AAs shown, the cell block group region CBS can be located between the peripheral regions PER and the lane marking region SL (specifically, the edge lane region) that are close to each other in the first direction D1. For example, as... Figure 2B As shown, the cell block group region CBS can be located between the peripheral regions PER that are close to each other in the first direction D1.

[0046] Reference Figure 3 The cell block group region (CBS) may include multiple cell block regions (CB) and a core region (COR) surrounding the multiple cell block regions (CB). Core circuitry may be disposed on the core region (COR). The core circuitry may sense / control bit lines (BL) and / or word lines (WL) on the cell block regions (CB). For example, the core circuitry may include a sense amplifier circuit (SA) for sensing the bit line (BL) and a sub-word line driver circuit (SWD) for controlling the word line (WL). The sense amplifier circuits (SA) may face each other in a first direction (D1), with the cell block regions (CB) situated between the sense amplifier circuits (SA). The sub-word line driver circuits (SWD) may face each other in a second direction (D2), with the cell block regions (CB) situated between the sub-word line driver circuits (SWD).

[0047] The cell block regions CB can be configured to be spaced apart from each other in a first direction D1 and a second direction D2. For example, the cell block regions CB can include cell block columns R arranged along the first direction D1, and multiple cell block columns R can be spaced apart from each other in the second direction D2. The cell block columns R can include edge cell block regions CBe arranged at both ends along the first direction D1, and a central cell block region CBc between the edge cell block regions CBe. The edge cell block regions CBe can be located on the edges of the cell block group region CBS along the first direction D1. Compared to the central cell block region CBc, the edge cell block regions CBe can be more adjacent to the surrounding regions PER and SL. For example, one surface of the edge cell block region CBe can be adjacent to the surrounding regions PER and SL, and another surface opposite to one surface of the edge cell block region CBe can be adjacent to the core region COR. The central cell block region CBc can be surrounded by the core region COR.

[0048] Figure 4 It shows Figure 3 The diagram shows a plan view of a unit block region, serving as a diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figure 5A Is with Figure 4 The cross-sectional view corresponding to line A-A' in the diagram. Figure 5B Is with Figure 4 The cross-sectional view corresponding to line B-B' in the diagram. Figure 5C Is with Figure 4 The cross-sectional view corresponding to line C-C' in the diagram. (Refer to...) Figures 3 to 5CThe component separation pattern 120 may be disposed in the substrate 100 and may define an active pattern ACT. The active pattern ACT may be disposed on a cell block region CB of the substrate 100. The active pattern ACT may protrude in a third direction D3 perpendicular to the lower surface of the substrate 100. For example, the active pattern ACT may be a portion of the substrate 100 surrounded by the component separation pattern 120. For ease of description, unless otherwise described separately, the portion of the substrate 100 other than the active pattern ACT is defined in this specification as the portion of the substrate 100 other than the active pattern ACT. The active patterns ACT may be spaced apart from each other in a first direction D1 and a second direction D2. Each active pattern ACT may have the shape of a separate island (or a single body) and may have the form of a longer strip in a fourth direction D4. The fourth direction D4 may be parallel to the lower surface of the substrate 100 and may intersect with the first direction D1 and the second direction D2. The component separation pattern 120 may include an insulating material, such as at least one of silicon oxide, silicon nitride, or combinations thereof. The component separation pattern 120 may be a monolayer made of a single material or a composite layer comprising at least two materials.

[0049] Each active pattern ACT may include a pair of edge portions 111 and a center portion 112. The pair of edge portions 111 may be the two ends (or terminals) of the active pattern ACT relative to the fourth direction D4. The center portion 112 may be the portion of the active pattern ACT between the pair of edge portions 111, and more specifically, may be the portion of the active pattern ACT between the pair of word lines WL described later. The pair of edge portions 111 and center portion 112 may be doped with impurities (charge carrier dopants), such as N-type or P-type impurities.

[0050] Word lines WL can be set in an active pattern ACT. Multiple word lines WL can be set. Word lines WL can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Word lines WL can be set in grooves provided in the active pattern ACT and the component separation pattern 120. For example, a pair of word lines WL adjacent to each other in the first direction D1 can intersect an active pattern ACT.

[0051] Each word line WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate cap pattern GC. The gate electrode GE may penetrate the active pattern ACT and the device separation pattern 120 in the second direction D2. The gate dielectric pattern GI may be located between the gate electrode GE and the active pattern ACT, and between the gate electrode GE and the device separation pattern 120. The gate cap pattern GC may cover the upper surface of the gate electrode GE.

[0052] Buffer pattern 210 may be disposed on substrate 100. Buffer pattern 210 may cover active pattern ACT, component separation pattern 120, and word line WL. For example, buffer pattern 210 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Buffer pattern 210 may be a monolayer made of a single material or a composite layer comprising at least two materials.

[0053] Bit line contacts DC can be provided on each active pattern ACT, and multiple contacts can be provided. Bit line contacts DC can be connected to the center portion 112 of the active pattern ACT, respectively. In this specification, expressions such as "A connected to B" can include not only the meaning of A being in contact with B, but also the meaning of A not being in contact with B but being electrically connected to B. Bit line contacts DC can be spaced apart from each other in the first direction D1 and the second direction D2. Bit line contacts DC can be respectively located between the active pattern ACT and the bit line BL described later. Bit line contacts DC can connect the corresponding bit line BL to the center portion 112 of the corresponding active pattern ACT.

[0054] Bit line contacts DC can be respectively disposed in the first recessed region RS1. The first recessed region RS1 can be disposed on the upper part of the active pattern ACT and on the element separation pattern 120 adjacent to the upper part of the active pattern ACT. The first recessed regions RS1 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0055] Reference Figure 4 Bit lines BL can be disposed on the cell block region CB. Multiple bit lines BL can be provided. Each bit line BL can extend longitudinally in a first direction D1 and can be spaced apart from each other in a second direction D2. Bit lines BL can include metallic materials. For example, bit lines BL can include at least one of tungsten, rubidium, molybdenum, titanium, or combinations thereof. An item, layer, or portion of an item or layer described as extending "longitudinally" in a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0056] Bit lines BL may include a first bit line BL1 and a second bit line BL2 that are close to each other in the second direction D2. Each bit line in the first bit line BL1 and the second bit line BL2 may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.). For example, the first bit line BL1 and the second bit line BL2 may include the same material as each other.

[0057] One end of the second bit line BL2 can be connected to the bit line pad PD. Alternatively, one end of the first bit line BL1 may not be connected to the bit line pad PD. The bit line pad PD can electrically connect the bit line BL to the contact plug CP, which will be described later. The width of the bit line pad PD in the second direction D2 can be greater than the width of the bit line BL in the second direction D2. The bit line pad PD can have a hammer profile. The bit line pad PD can comprise the same material as the bit line BL and can be connected to the second bit line BL2 without a boundary surface.

[0058] Reference Figures 3 to 5C The polysilicon pattern 310 can be disposed between the bit line BL and the buffer pattern 210, and between bit line contacts DC that are close to each other in the first direction D1. Multiple polysilicon patterns 310 can be provided. For example, each of the multiple polysilicon patterns 310 can be spaced apart from each other in the first direction D1 and the second direction D2. The upper surface of the polysilicon pattern 310 can be located at substantially the same height as the upper surface of the bit line contact DC, and can be coplanar with each other. The polysilicon pattern 310 may include doped polysilicon.

[0059] Reference Figure 4 , Figure 5B and Figure 5C The cell block region CB may include a memory cell array region MCA and an interface region IA, and the interface region IA may be adjacent to the edge of the memory cell array region MCA. The memory cell array region MCA may be an area where unit cells are arranged in a regular repeating pattern to form an array. Two adjacent memory cell array regions MCA may be separated from each other by this periodically interrupted region, thereby allowing the memory cell array regions MCA to be clearly distinguished from each other.

[0060] The area where the repetition is interrupted (i.e., the area between two adjacent memory cell array areas MCA) can be the interface area IA and / or the core area COR. For example, the interface area IA can be configured to electrically connect the first bit line BL1 to other functional areas (e.g., the sense amplifier circuit SA) via conductive patterns (such as contact plugs CP and bit line pads PD).

[0061] In some embodiments, each cell block region CB may include multiple interface regions IA. For example, the first bit line BL1 can be electrically connected to the first sense amplifier circuit SA through the first interface region IA as shown in the figure, and the second bit line BL2 can be electrically connected to the second sense amplifier circuit through another interface region (not shown in the figure). The two interface regions may be located on opposite sides of the corresponding cell block regions CB.

[0062] Reference Figures 3 to 5CA first blocking pattern 320 may be disposed between the bit line BL and the bit line contact DC, between the bit line BL and the polysilicon pattern 310, and between the bit line pad PD and the polysilicon pattern 310. The first blocking patterns 320 may extend along the bit line BL in a first direction D1 and may be spaced apart from each other in a second direction D2. The first blocking pattern 320 may include a conductive metal nitride, such as titanium nitride or tantalum nitride. A first ohmic pattern (not shown) may also be located between the bit line BL and the bit line contact DC, and between the bit line BL and the polysilicon pattern 310. The first ohmic pattern may include a metal silicide.

[0063] Bit line capping patterns 350 can be disposed on the upper surface of the bit line BL. Multiple bit line capping patterns 350 can be provided. The bit line capping patterns 350 can each extend along the corresponding bit line BL in a first direction D1 and can be spaced apart from each other in a second direction D2. The bit line capping patterns 350 can vertically overlap with the bit line BL. The bit line capping patterns 350 can consist of a single layer or multiple layers. For example, the bit line capping patterns 350 can include a first capping pattern 351, a second capping pattern 352, and a third capping pattern 353 stacked sequentially. The first capping pattern 351, the second capping pattern 352, and the third capping pattern 353 can include silicon nitride. As another example, additional capping patterns such as a fourth capping pattern and a fifth capping pattern (not shown) can also be included.

[0064] Spacer structure 360 ​​can be disposed on the side surface of bit line BL and the side surface of bit line capping pattern 350. Spacer structure 360 ​​can cover the side surface of bit line BL and the side surface of bit line capping pattern 350. Bit line groove BTR can be disposed between bit lines BL, and spacer structure 360 ​​can cover the inner surface of bit line groove BTR (see...). Figure 4 The bit line trench BTR and the spacer structure 360 ​​may extend along the first direction D1. Multiple spacer structures 360 may be configured.

[0065] The spacer structure 360 ​​may include a plurality of spacers. For example, the spacer structure 360 ​​may include a first spacer 362, a second spacer 364, and a third spacer 366. The third spacer 366 may be disposed on the side surface of the bit line BL and the side surface of the bit line capping pattern 350. The first spacer 362 may be located between the bit line BL and the third spacer 366, and between the bit line capping pattern 350 and the third spacer 366. The second spacer 364 may be located between the first spacer 362 and the third spacer 366. For example, each of the first spacer 362, the second spacer 364, and the third spacer 366 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. As another example, the second spacer 364 may include an air gap that spaces the first spacer 362 and the third spacer 366 apart from each other.

[0066] The buried insulating pattern 250 can fill each first recessed region RS1. The buried insulating pattern 250 can fill the interior of the first recessed region RS1. For example, the buried insulating pattern 250 can cover at least a portion of the inner surface of the first recessed region RS1 and the side surface of the bit line contact DC (e.g., at least a portion of the side surface of the bit line contact DC in the first recessed region RS1). The buried insulating pattern 250 can include at least one of silicon oxide, silicon nitride, or combinations thereof. The buried insulating pattern 250 can be a single layer made of a single material or a composite layer comprising at least two materials.

[0067] The capping spacer 370 may be located on the spacer structure 360. The capping spacer 370 may cover the upper part of the side surface of the spacer structure 360. For example, the capping spacer 370 may include silicon nitride.

[0068] The memory node contacts BC can be disposed between closely spaced bit lines BL. For example, the memory node contacts BC can be located between spacer structures 360. Multiple memory node contacts BC can be provided, and they can be spaced apart from each other in a first direction D1 and a second direction D2. The memory node contacts BC can be spaced apart from each other in the first direction D1 by a fence pattern FN on the word line WL. For example, some memory node contacts BC can be located between the first bit line BL1 and the second bit line BL2. The memory node contacts BC can include a conductive material. For example, the memory node contacts BC can include at least one of polysilicon (e.g., polysilicon including impurities) or a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.).

[0069] The second barrier pattern 410 may conformally cover the spacer structure 360 ​​and the memory node contact BC. The second barrier pattern 410 may include a metal nitride such as titanium nitride or tantalum nitride. A second ohmic pattern (not shown) may also be located between the second barrier pattern 410 and the memory node contact BC. The second ohmic pattern may include a metal silicide.

[0070] A bonding pad LP can be disposed on the storage node contact BC. Multiple bonding pads LP can be provided, and they can be spaced apart from each other in a first direction D1 and a second direction D2. The bonding pad LP can be connected to the corresponding storage node contact BC. The bonding pad LP can cover the upper surface of the bit line capping pattern 350. The lower region of the bonding pad LP can vertically overlap with the storage node contact BC. The upper region of the bonding pad LP can be offset from the lower region of the bonding pad LP in the second direction D2. The bonding pad LP can include a metallic material, such as tungsten, titanium, or tantalum.

[0071] The fill pattern 440 may surround the bonding pad LP. The fill pattern 440 may be located between bonding pads LP that are close to each other. In a plan view, the fill pattern 440 may have the form of a mesh including holes penetrating through the bonding pads LP. For example, the fill pattern 440 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. As another example, the fill pattern 440 may include empty spaces (e.g., air gaps) containing an air layer.

[0072] A contact plug CP can be disposed on a bit line pad PD. The contact plug CP can penetrate the fill pattern 440 and the bit line cap pattern 350 (e.g., a first cap pattern 351) on a third-direction D3 and can be connected to the bit line pad PD. The contact plug CP can comprise the same material as the bonding pad LP.

[0073] Contact wiring can be connected to contact plugs CP on fill pattern 440. Contact wiring may include at least one wiring layer. Contact wiring can be connected to core circuitry on core region COR. Bit line BL can be connected to core circuitry (e.g., sense amplifier circuitry SA) via bit line pads PD, contact plugs CP, and contact wiring.

[0074] Data storage pattern DSPs can be disposed on bonding pads LP. Multiple data storage pattern DSPs can be disposed, and they can be spaced apart from each other in the first direction D1 and the second direction D2. Data storage pattern DSPs can be connected to corresponding edge portions 111 via corresponding bonding pads LP and corresponding storage node contacts BC.

[0075] For example, a data storage pattern DSP can be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device according to the present invention can be dynamic random access memory (DRAM). As another example, a data storage pattern DSP can include a magnetic tunnel junction pattern. In this case, the semiconductor memory device according to the present invention can be magnetic random access memory (MRAM). As yet another example, a data storage pattern DSP can include a phase change material or a variable resistance material. In this case, the semiconductor memory device according to the present invention can be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, these are examples, and the present invention is not limited thereto, and the data storage pattern DSP can include various structures and / or materials capable of storing data.

[0076] Will refer again Figures 4 to 5C The LP pad is described in more detail.

[0077] Polysilicon portion POL and gate portion FNC can be located on the edge portion of the cell block region CBc. Multiple polysilicon portion POLs and multiple gate portion FNCs can be set. Polysilicon portion POLs may not be directly connected to bit lines. Polysilicon portion POLs may be portions connected to bonding pads LP. Polysilicon portion POLs may include conductive material. Polysilicon portion POLs may include portions not connected to actual circuitry.

[0078] The barrier portion FNC can be disposed between adjacent polysilicon portions POL. The barrier portion FNC can penetrate vertically through the polysilicon portion POL. Adjacent barrier portions FNC can be spaced apart from each other in the first direction D1. The barrier portion FNC may include insulating material to block electrical connections between adjacent polysilicon portions POL.

[0079] An interlayer insulating layer IL can be disposed on the polysilicon portion POL and the gate portion FNC. The interlayer insulating layer IL can include at least one of silicon oxide, silicon nitride, a low-dielectric material, or a combination thereof. A low-dielectric material is a material with a dielectric constant lower than that of silicon oxide.

[0080] The bonding patterns LPDa and LPDb can be disposed on the cell block region CBc. The bonding patterns LPDa and LPDb can be disposed on the edge portion of the cell block region CBc. The bonding patterns LPDa and LPDb can be dummy patterns formed on the edge portion when bonding pads LP are formed. The bonding patterns LPDa and LPDb can intersect the bit line BL to extend in the second direction D2. The bonding patterns LPDa and LPDb can include a first bonding pattern LPDa and a second bonding pattern LPDb spaced apart from each other in the first direction D1. The bonding patterns LPDa and LPDb can include the same material as the bonding pads LP. For example, the bonding patterns LPDa and LPDb can include metallic materials such as tungsten, titanium, or tantalum.

[0081] The bonding patterns LPDa and LPDb described herein may be dummy bonding pads that may not have any electrical connection to any integrated circuit of the semiconductor device according to embodiments of the present invention. However, the dummy bonding pads LPDa and LPDb may have the same or similar structure and / or shape as the normal bonding pad LP of the semiconductor device, including being formed of the same material (e.g., formed by the same material layers at the same level). For example, the upper surfaces of the dummy bonding pads LPDa and LPDb and the bonding pad LP of the semiconductor device may be coplanar. The dummy bonding pads may not be used to transmit signals or power (unlike normal bonding pads connected to the internal circuitry of the semiconductor chip to transmit signals and / or power). In some examples, the dummy bonding pads may form all or part of electrically floating (e.g., not (directly or indirectly) electrically connected to any other conductor) electrical nodes. In some examples, the dummy bonding pads and normal bonding pads may be covered by the same insulating layer, which is subsequently patterned to expose the dummy chip pads and normal chip pads. For example, the memory node contact BC can be electrically connected to the substrate, the bonding pad LP can be disposed on and electrically connected to the memory node contact BC, the data storage pattern DSP can be disposed on and electrically connected to the bonding pad LP, and the bonding patterns LPDa and LPDb may not have any electrical connections to any integrated circuit that functions during the normal operation of the semiconductor device.

[0082] In the manufacturing process, dummy patterns (or bonding patterns) LPDa and LPDb can be used to reduce non-uniformity (e.g., loading effect) in the photolithography process, which is caused by irregular pattern density in different areas. According to some embodiments of the invention, two types of dummy patterns (e.g., a first bonding pattern LPDa and a second bonding pattern LPDb) can exist in the interface region IA. For example, the first bonding pattern LPDa can be used to reduce the depth variation of the recessed region formed in the third capping layer 353L, which can be caused by the etching process used to form the bonding pad LP. The second bonding pattern LPDb can be used to reduce etch damage to the first line sidewall BL_SW, which can be caused by the etching process used to form the bonding pad LP.

[0083] Although each of the first and second joining patterns LPDb is in Figure 4 The figure is shown as a single body extending in the second direction D2, but in some embodiments, a plurality of each of the first attachment pattern LPDa and the second attachment pattern LPDb may be arranged in a series (or row) extending in the second direction D2, and a plurality of each of the first attachment pattern LPDa and the second attachment pattern LPDb may be spaced apart from each other.

[0084] The first landing pattern LPDa can cross more bit lines BL than the second landing pattern LPDb. The first landing pattern LPDa can be set on the first bit line BL1 and the second bit line BL2 to cross the first bit line BL1 and the second bit line BL2. The second landing pattern LPDb can be not set on the first bit line BL1, and therefore can only cross the second bit line BL2.

[0085] The second bonding pattern LPDb can be disposed on the polysilicon portion POL and the gate portion FNC. The second bonding pattern LPDb can vertically overlap with at least either the polysilicon portion POL or the gate portion FNC. The bottom surface of the second bonding pattern LPDb can contact either the upper surface of the polysilicon portion POL or the upper surface of the gate portion FNC. Furthermore, the first bonding pattern LPDa can be spaced apart from the polysilicon portion POL and the gate portion FNC in the first direction D1, without vertically overlapping with the polysilicon portion POL and the gate portion FNC.

[0086] In the plan view, the second bonding pattern LPDb may be located between the first bonding pattern LPDa and the contact plug CP. The second bonding pattern LPDb may be disposed on the bit line pad PD connected to the second bit line BL2. The second bonding pattern LPDb may vertically overlap at least a portion of the bit line pad PD to intersect with the bit line pad PD.

[0087] For example, a third contact pattern can be additionally provided on the first direction D1, spaced apart from the first contact pattern LPDa and the second contact pattern LPDb. The number of contact patterns can be two or more. However, any of these multiple contact patterns may not vertically overlap with the end (or terminal) of the bit line BL. For example, the third contact pattern may be located between the second contact pattern LPDb and the contact plug CP.

[0088] The width W1 of the first bonding pattern LPDA can be different from the width W2 of the second bonding pattern LPDb. For example, the width W1 of the first bonding pattern LPDA can be greater than the width W2 of the second bonding pattern LPDb. The height (vertical thickness) of the first bonding pattern LPDA can be less than the height of the second bonding pattern LPDb. The maximum height of the first bonding pattern LPDA can be less than the maximum height of the second bonding pattern LPDb.

[0089] The first bonding pattern LPDa can be disposed on the bit line capping pattern 350 to vertically overlap with the bit line capping pattern 350. Furthermore, the second bonding pattern LPDb may not vertically overlap with the bit line capping pattern 350. The second bonding pattern LPDb may be spaced apart from the bit line capping pattern 350 in the first direction D1.

[0090] The bonding insulating pattern LIP may be located between the first bonding pattern LPDa and the second bonding pattern LPDb. The first bonding pattern LPDa and the second bonding pattern LPDb may be spaced apart from each other in the first direction D1 by the bonding insulating pattern LIP. The bonding insulating pattern LIP may at least partially vertically overlap with the first line BL1. The bonding insulating pattern LIP may include an insulating material. The bonding insulating pattern LIP may include the same material as the interlayer insulating layer IL. The bonding insulating pattern LIP may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. For example, the bonding insulating pattern LIP may include empty spaces (e.g., air gaps) containing an air layer.

[0091] The upper surface of the first bonding pattern LPDA can be located at a substantially the same level as the upper surface of the second bonding pattern LPDb. The bottom surface of the second bonding pattern LPDb can be located at a lower level than the bottom surface of the first bonding pattern LPDA. The bottom surface of the second bonding pattern LPDb can be located at a substantially the same level as the bottom surface of the bonding insulating pattern LIP. The bottom surface of the bonding insulating pattern LIP can be located at a lower level than the bottom surface of the first bonding pattern LPDA.

[0092] The first line BL1 may include a first end EG1 adjacent to the bonding patterns LPDa and LPDb. The first end EG1 of the first line BL1 may not vertically overlap with the bonding patterns LPDa and LPDb. In a plan view, the first end EG1 of the first line BL1 may be located between the first bonding pattern LPDa and the second bonding pattern LPDb. The first end EG1 may vertically overlap with the bonding insulation pattern LIP.

[0093] The first end EG1 may include a first line sidewall BL_SW. The first bonding pattern LPDa may include a first bonding sidewall LP_SW1 adjacent to the second bonding pattern LPDb, and the second bonding pattern LPDb may include a second bonding sidewall LP_SW2 adjacent to the first bonding pattern LPDa. The first bonding sidewall LP_SW1 and the second bonding sidewall LP_SW2 may face each other.

[0094] The first end EG1 can be located between the first contact sidewall LP_SW1 and the second contact sidewall LP_SW2. The first line sidewall BL_SW of the first end EG1 can be located between the first contact sidewall LP_SW1 and the second contact sidewall LP_SW2. The first line sidewall BL_SW can be offset in the horizontal direction from each of the first contact sidewall LP_SW1 and the second contact sidewall LP_SW2.

[0095] The shortest distance in the first direction D1 between the first contact sidewall LP_SW1 and the second contact sidewall LP_SW2 can be defined as the first gap SP1. The first gap SP1 can be the shortest distance in the first direction D1 between the first contact pattern LPDa and the second contact pattern LPDb. The first gap SP1 can be the width of the contact insulation pattern LIP in the first direction D1. The shortest distance in the first direction D1 between the second contact sidewall LP_SW2 and the first line sidewall BL_SW of the first end EG1 can be defined as the second gap SP2. The first gap SP1 can be greater than the second gap SP2.

[0096] The bonding spacer LPS can be disposed on the first line sidewall BL_SW of the first line BL1 and on the side surface of the bit line capping pattern 350. The bonding spacer LPS can extend to the upper surface of the element separation pattern 120 to be disposed below the bottom surface of the polysilicon portion POL. The gate portion FNC can penetrate the bonding spacer LPS. The bonding spacer LPS can be positioned between the first line BL1 and the polysilicon portion POL to prevent electrical connection between them. The bonding spacer LPS can include an insulating material. However, in another example, the bonding spacer LPS can be omitted, such that the first line BL1 and the polysilicon portion POL are in contact with each other.

[0097] Figure 6A It shows Figure 3 The diagram shows a plan view of the cell block region, serving as a diagram illustrating a semiconductor device as a comparative example of the concept according to the present invention. Figure 6B Is with Figure 6A The cross-sectional view corresponding to line C-C' in the diagram. Refer to... Figure 6A and Figure 6B A comparative example based on the concept of the present invention will be described in more detail. References will be omitted. Figures 3 to 5C The technical features described are repetitive technical features.

[0098] It should be understood that the examples and comparative examples described herein are intended to illustrate the invention and should not be construed as limiting the scope of the invention in any way. The comparative examples are provided to better understand certain advantages and distinguishing features of the invention and are therefore considered part of this disclosure.

[0099] Reference Figure 6A and Figure 6B A single, rather than multiple, alignment pattern LPD can be set on the cell block region CBc. The width W3 of the alignment pattern LPD can be greater than... Figure 4 The widths W1 and W2 of the bonding patterns LPDa and LPDb are given. Therefore, the bonding pattern LPD can vertically overlap with the first end EG1 of the first bit line BL1. The bonding pattern LPD can be a dummy pattern. For example, in a manufacturing process, a dummy pattern can be used to reduce non-uniformity (e.g., load effect) in a photolithography process caused by irregular pattern density in different areas. For example, the dummy pattern LPD can help reduce the variation in depth of the recessed region formed in the third capping layer 353L, which can be caused by the etching process used to form the bonding pad LP.

[0100] The bonding pattern LPD can extend along the upper surface of the bit line capping pattern 350. The bonding pattern LPD can be disposed on the first blocking pattern 410, but the first blocking pattern 410 can be omitted. The bottom surface LP_B of the bonding pattern LPD can be located at a level lower than the upper surface of the polysilicon portion POL. The bottom surface LP_B of the bonding pattern LPD can be located at a level lower than the upper surface of the bit line BL. The bottom surface LP_B of the bonding pattern LPD can contact the bit line sidewall BL_SW of the first bit line BL1. In this case, the bonding spacer LPS (such as...) can be omitted. Figure 5C As shown in the figures, electrical interference and short circuits may occur between the bonding pattern LPD and the bit line BL, and between the polysilicon portion POL and the bit line BL. Therefore, the electrical characteristics and reliability of the semiconductor device may deteriorate. In some embodiments, although not shown in the figures, it can be... Figure 5CThe method shown uses a bonding spacer LPS to minimize the contact between the bit line sidewall BL_SW of the first bit line BL1 and the bonding pattern LPD. Therefore, although the bonding pattern LPD vertically (or in a plan view) overlaps with the first end EG1 of the first bit line BL1, the bonding pattern LPD can be spaced apart from the first end EG1 of the first bit line BL1 by the bonding spacer LPS (e.g., in a cross-sectional view).

[0101] Furthermore, according to the present invention, the first end EG1 of the first line BL1 may not vertically overlap with the bonding patterns LPDa and LPDb. The first end EG1 of the first line BL1 may be located between the first bonding pattern LPDa and the second bonding pattern LPDb. Since the first end EG1 of the first line BL1 vertically overlaps with the bonding insulation pattern LIP to be spaced apart from the second bonding insulation pattern LPDb in the first direction D1, the first line BL1 may not contact the bonding insulation patterns LPDa and LPDb. Therefore, electrical interference and short circuits between the first line BL1 and the bonding patterns LPDa and LPDb can be prevented or suppressed.

[0102] Figures 7A to 12C This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. More specifically, Figure 7A , Figure 8A , Figure 9A and Figure 12A Is with Figure 4 The cross-sectional view corresponding to line A-A' in the diagram. Figure 7B , Figure 8B , Figure 9B , Figure 10A , Figure 11A and Figure 12B Is with Figure 4 The cross-sectional view corresponding to line B-B' in the diagram. Figure 9C , Figure 10B , Figure 11B and Figure 12C Is with Figure 4 The cross-sectional view corresponding to line C-C' in the diagram.

[0103] In the following text, reference will be made to Figures 7A to 12C Methods for manufacturing semiconductor devices according to some embodiments of the present invention are described. For the sake of simplicity, repetitive descriptions of those described above will be omitted, and the differences from those descriptions will be primarily described.

[0104] Reference Figure 7A and Figure 7BA substrate 100 including a unit block region CB can be fabricated. A component separation pattern 120 and an active pattern ACT can be formed on the substrate 100. Forming the component separation pattern 120 and the active pattern ACT can include: forming a groove in the substrate 100 by patterning; and forming the component separation pattern 120 by filling the groove with an insulating material. The active pattern ACT can include regions of the substrate 100 where no groove is formed.

[0105] Word lines WL can be formed in trenches formed on the upper part of the substrate 100. Forming word lines WL may include: forming a mask pattern on an active pattern ACT and a component separation pattern 120; forming trenches by performing an anisotropic etching process using the mask pattern; and filling the trenches with word lines WL. The word lines WL may be spaced apart from each other in a first direction D1 and may extend in the active pattern ACT in a second direction D2. For example, filling word lines WL may include: conformally depositing a gate dielectric pattern GI on the inner surface of each trench; filling the interior of the trench with a conductive layer; forming a gate electrode GE by an etch-back process and / or a polishing process on the conductive layer; and forming a gate cap pattern GC on the gate electrode GE to fill the remaining portion of the trench. A pair of word lines WL may intersect with the active pattern ACT and may define a central portion 112 of the active pattern ACT defined between the pair of word lines WL. The remaining portion of the active pattern ACT, spaced apart from the center portion 112, can be defined as the edge portion 111, with each word line in a pair of word lines WL located between the remaining portion and the center portion 112.

[0106] A first buffer layer 210La and a first polysilicon layer 310La can be sequentially formed on the substrate 100. The first buffer layer 210La and the first polysilicon layer 310La can cover the upper surface of the active pattern ACT, the upper surface of the element separation pattern 120, and the upper surface of the word line WL.

[0107] Reference Figure 8A and Figure 8B A first recessed region RS1 can be formed on the upper part of the active pattern ACT. Multiple first recessed regions RS1 can be configured. The first recessed regions RS1 can be spaced apart from each other in a first direction D1 and a second direction D2. The first recessed region RS1 can be formed on the central portion 112 of the active pattern ACT. Forming the first recessed region RS1 can include performing an anisotropic etching process. A second buffer layer 210Lb and a second polysilicon layer 310Lb can be formed from the first buffer layer 210La and the first polysilicon layer 310La, respectively, using the anisotropic etching process. The first recessed region RS1 can partially expose each of the central portion 112, the element separation pattern 120, and the gate cap pattern GC to the outside.

[0108] A preliminary bit line contact (DCL) can be formed to fill the first recessed region RS1. Multiple preliminary bit line contacts (DCLs) can be provided, and each preliminary bit line contact (DCL) can be formed on the central portion 112 of the active pattern ACT. The upper surface of the preliminary bit line contact (DCL) can be formed at a height substantially the same as the upper surface of the second polysilicon layer 310Lb, and the upper surface of the preliminary bit line contact (DCL) can be coplanar with the upper surface of the second polysilicon layer 310Lb.

[0109] A first barrier layer 320L, a bit line layer BLL, a first capping layer 351L, a second capping layer 352L, and a third capping layer 353L can be sequentially formed on the initial bit line contact portion DCL and the second polysilicon layer 310Lb. The first barrier layer 320L, the bit line layer BLL, the first capping layer 351L, the second capping layer 352L, and the third capping layer 353L can completely cover the cell block region CB, the surrounding regions PER and SL, and the core region COR of the substrate 100.

[0110] Reference Figures 9A to 9C A first mask pattern MP1 can be formed on the third capping layer 353L. Using the first mask pattern MP1 as a mask, an etching process can be performed on the first buffer layer 210La, the first polysilicon layer 310La, the first barrier layer 320L, the bit line layer BLL, the first capping layer 351L, the second capping layer 352L, and the third capping layer 353L. Each of the first buffer layer 210La, the first polysilicon layer 310La, the first barrier layer 320L, the bit line layer BLL, the first capping layer 351L, the second capping layer 352L, and the third capping layer 353L can be partially and selectively removed during the etching process. The component separation pattern 120 can be exposed during the etching process. The exposed portion of the component separation pattern 120 can be part of the polysilicon portion POL and the gate portion FNC.

[0111] The bit line layer BLL can be partially etched to form the first end EG1 of the first bit line BL1. Each of the first capping layer 351L, the second capping layer 352L, and the third capping layer 353L can be partially etched to form a first capping pattern 351, a second capping pattern 352, and a third capping pattern 353, respectively. The formed first capping pattern 351, second capping pattern 352, and third capping pattern 353 can constitute a bit line capping pattern 350. The bit line capping pattern 350 can include the sidewalls of the capping pattern trench 350_TR formed in the etching process. The sidewalls of the capping pattern trench 350_TR can extend in the vertical direction and can have a curved cross-section.

[0112] Reference Figure 10A and Figure 10BThe first mask pattern MP1 can be removed, and the bonding spacer LPS can be conformally formed. The bonding spacer LPS can cover the upper surface of the third capping pattern 353, the sidewalls of the capping pattern trench 350_TR, and the upper surface of the exposed element separation pattern 120. The bonding spacer LPS can include an insulating material. For example, the bonding spacer LPS can include at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0113] A polysilicon portion POL can be formed on the bonding spacer LPS. The polysilicon portion POL can have a greater height than the bit line BL. The polysilicon portion POL can have a higher upper surface than the bit line BL, but the inventive concept is not limited thereto. For example, the polysilicon portion POL can have a lower upper surface than the bit line BL. The polysilicon portion POL may not be formed on the bit line BL and the bit line capping pattern 350. The polysilicon portion POL may include a conductive material.

[0114] Reference Figure 11A and Figure 11B Multiple barrier portions FNCs can be formed between polysilicon portions POL. The barrier portions FNC can penetrate vertically through the polysilicon portions POL. The barrier portions FNC can penetrate the bonding spacer LPS to extend into the component separation pattern 120. The barrier portions FNC may include insulating material and can be positioned between the polysilicon portions POL to block electrical connections.

[0115] A bonding pad layer LPL can be formed on the front surface of the cell block region CBc. A first barrier pattern 410 can be formed before forming the bonding pad layer LPL. The bonding pad layer LPL can cover the upper surface of each of the spacer LPS, the polysilicon portion POL, and the gate portion FNC. In the bonding pad layer LPL, the height of the portions formed on the polysilicon portion POL and the gate portion FNC can be greater than the height of the portions formed on the bit line capping pattern 350. The bonding pad layer LPL can include a metallic material, such as tungsten, titanium, or tantalum.

[0116] Reference Figures 12A to 12C A second mask pattern MP2 can be formed on the unit block region CBc. The second mask pattern MP2 can be formed on which... Figure 4 The bonding patterns LPDa and LPDb, and the bonding pads LP formed thereon, can be etched onto the bonding pad layer LPL using a second mask pattern MP2 as a mask. The bonding spacers LPS can be partially etched during the etching process. However, the polysilicon portion POL and the gate portion FNC can be left unremoved.

[0117] The bonding pad layer LPL can be partially etched to form insulating vias. The bonding pad layer LPL can be etched to form a first bonding pattern LPDa and bonding pad LP. The bit line capping pattern 350 can be exposed through the first insulating via. The polysilicon portion POL and the gate portion FNC can be exposed through a second insulating via. The depth of the first insulating via can be shallower than the depth of the second insulating via. The third insulating via LPHA can expose the end of the first bit line BL1.

[0118] The fill pattern 440, the bonding insulation pattern LIP, and the interlayer insulation layer IL can be formed by filling the insulating holes with insulating material. Specifically, the fill pattern 440 can be formed by filling the first insulating hole with insulating material. The interlayer insulation layer IL can be formed by filling the second insulating hole with insulating material. The bonding insulation pattern can be formed by filling the third insulating hole with insulating material. The fill pattern 440 can be formed to cover the exposed portions of the bonding pad LP and the contact plug CP and surround each of the bonding pad LP and the contact plug CP.

[0119] Contact plugs (CP) can be formed on bit line pads (PD). Forming contact plugs (CP) can include: forming contact holes on bit line pads (PD); forming contact plug layers that fill the contact holes; and forming contact plug layers by etching the contact plug layers. For example, contact plugs (CP) can be formed together with bonding pad layers and a second bonding pattern (LPDb).

[0120] Data storage patterns (DSPs) can be formed on each bonding pad (LP). Contact wiring can be formed on the contact plug (CP).

[0121] According to the present invention, bonding patterns intersecting with bit lines can be provided on a cell block region. In this case, the ends of the bit lines can be located between the bonding patterns, so that the ends of the bit lines do not vertically overlap with the bonding patterns. Therefore, electrical short circuits occurring between the bonding patterns and the ends of the bit lines can be prevented or suppressed. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0122] The above description of embodiments of the inventive concept provides examples for describing the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and those skilled in the art can make various modifications and changes within the technical spirit of the inventive concept, such as combining the above embodiments.

Claims

1. A semiconductor device, comprising: Substrate, including unit block regions; The first line extends in a first direction over the unit block region; as well as The connecting pattern extends in a second direction that intersects with the first direction. The bonding pattern includes: The first stitch pattern intersects with the first bit line; and The second bonding pattern is spaced apart from the first bonding pattern in the first direction, and One end of the first bit line is located between the first bonding pattern and the second bonding pattern.

2. The semiconductor device according to claim 1, wherein, In the first direction, the first bonding pattern has a width different from that of the second bonding pattern.

3. The semiconductor device according to claim 1, wherein, The first bonding pattern has a smaller thickness in the vertical direction than the second bonding pattern.

4. The semiconductor device according to claim 1, further comprising: The bit line cover pattern is on the first bit line. Wherein, the first bonding pattern and the bit line sealing pattern vertically overlap, and The second bonding pattern is spaced apart from the bit line cover pattern in the first direction.

5. The semiconductor device according to claim 1, further comprising: The bonding insulation pattern is located between the first bonding pattern and the second bonding pattern.

6. The semiconductor device according to claim 5, wherein, The bonding insulation pattern at least partially overlaps vertically with the first bit line.

7. The semiconductor device according to claim 5, wherein, The bottom surface of the bonding insulation pattern is located at a lower level than the bottom surface of the first bonding insulation pattern.

8. The semiconductor device according to claim 5, wherein, The bottom surface of the bonding insulation pattern is coplanar with the bottom surface of the second bonding insulation pattern.

9. The semiconductor device according to claim 1, further comprising: The second bit line extends in the first direction and is close to the first bit line in the second direction; Bit line pads are connected to the second bit line; as well as Contact plugs, on the bit line pads, The second bit line is connected to the contact plug via the bit line pad, and The second mating pattern is located between the first mating pattern and the contact plug.

10. The semiconductor device according to claim 9, wherein, The second bonding pattern vertically overlaps with at least a portion of the bit line pad.

11. A semiconductor device, comprising: Substrate, including unit block regions; The first line extends in a first direction over the unit block region; as well as The connecting pattern extends in a second direction that intersects with the first direction. The bonding pattern includes: The first stitch pattern intersects with the first bit line; and The second bonding pattern is spaced apart from the first bonding pattern in the first direction. The first bit line includes a first end adjacent to the first bonding pattern. The second bonding pattern is spaced apart from the first end in the first direction, and The second bonding pattern has a greater thickness in the vertical direction than the first bonding pattern.

12. The semiconductor device according to claim 11, further comprising: The bonding insulation pattern is located between the first bonding pattern and the second bonding pattern.

13. The semiconductor device according to claim 12, wherein, The first end is vertically overlapped with the bonding insulation pattern.

14. The semiconductor device according to claim 12, wherein, The bottom surface of the bonding insulation pattern is located at a lower level than the bottom surface of the first bonding insulation pattern.

15. The semiconductor device according to claim 11, further comprising: The first interval is defined as the shortest distance between the first bonding pattern and the second bonding pattern in the first direction; as well as The second interval is defined as the shortest distance between the second bonding pattern and the first end in the first direction. Wherein, the first interval is greater than the second interval.

16. A semiconductor device, comprising: Substrate, including unit block regions; The first line and the second line extend in a first direction over the unit block region and approach each other in a second direction that intersects the first direction; The connecting pattern extends in the second direction; as well as The contact plug is electrically connected to the second bit line. The bonding pattern includes: The first stitch pattern intersects with the first bit line and the second bit line; and The second bonding pattern is spaced apart from the first bonding pattern in the first direction. The first bit line includes a first end adjacent to the first bonding pattern. The second bonding pattern is spaced apart from the first end in the first direction, and The second mating pattern is located between the first mating pattern and the contact plug.

17. The semiconductor device according to claim 16, wherein, In the first direction, the first bonding pattern has a width different from that of the second bonding pattern.

18. The semiconductor device of claim 16, further comprising: The bonding insulation pattern is located between the first bonding pattern and the second bonding pattern. Wherein, the first end is vertically overlapped with the bonding insulation pattern.

19. The semiconductor device according to claim 18, wherein, The bottom surface of the bonding insulation pattern is located at a lower level than the bottom surface of the first bonding insulation pattern.

20. The semiconductor device of claim 16, further comprising: Bit line pads are connected to the second bit line. The second bonding pattern vertically overlaps with at least a portion of the bit line pad.

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