Memory device and method of manufacturing the same

Abstract

A memory device includes a cell semiconductor layer including subcell regions arranged in a first direction and contact regions between the subcell regions, respectively, wherein the subcell regions include memory cells, and a circuit semiconductor layer on the cell semiconductor layer and including a circuit configured to control the memory cells. The cell semiconductor layer includes subword lines extending in the first direction from the subcell regions to adjacent contact regions, odd-numbered word line interconnect lines extending from odd-numbered subcell regions to adjacent contact regions, and even-numbered word line interconnect lines extending from even-numbered subcell regions to adjacent contact regions.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0019908, filed on February 17, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to memory devices and methods of manufacturing the same. Background Technology

[0003] To meet the demands for miniaturization, multifunctionality, and high performance in electronic products, high-capacity integrated circuit devices are required. As the feature size of memory devices (such as dynamic random access memory (DRAM) devices) decreases, efficient arrangement of the circuitry used to drive these memory devices is necessary.

[0004] To reduce the area of ​​memory devices, cell wafers and circuit wafers are fabricated and can be stacked, for example, in a cell-on-periphery (CoP) or cell-on-periphery (PoC) structure. For example, the area of ​​the memory device can be reduced when the sub-word line driver, bit line sense amplifier, and other circuitry corresponding to each sub-cell are located in the region of the circuit wafer corresponding to each sub-cell of the cell wafer. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor device that can improve the driving capability of word lines and also improve the efficiency of interconnects.

[0006] According to one aspect of an example embodiment, a memory device includes: a cell semiconductor layer, each including a plurality of sub-cell regions arranged in a first direction and a plurality of contact regions between the plurality of sub-cell regions, wherein the plurality of sub-cell regions include a plurality of memory cells; and a circuit semiconductor layer, on the cell semiconductor layer and including circuitry configured to control the plurality of memory cells. The cell semiconductor layer includes: sub-word lines extending in the first direction from the plurality of sub-cell regions to adjacent contact regions, wherein the sub-word lines are spaced apart along a second direction intersecting the first direction; and word line interconnects. The word line interconnect includes: an odd-number word line interconnect extending from an odd-numbered sub-unit region among the plurality of sub-unit regions to an adjacent contact region, wherein the odd-number word line interconnect overlaps with an odd-numbered sub-word line in the odd-numbered sub-unit region and an odd-numbered sub-word line in an even-numbered sub-unit region adjacent to the odd-numbered sub-unit region in a first direction in a third direction, wherein the third direction intersects with the first direction and the second direction; and an even-number word line interconnect extending from an even-numbered sub-unit region among the plurality of sub-unit regions to an adjacent contact region, wherein the even-number word line interconnect overlaps with an even-numbered sub-word line in the even-numbered sub-unit region and an even-numbered sub-word line in an odd-numbered sub-unit region adjacent to the even-numbered sub-unit region in a first direction in a third direction.

[0007] According to another aspect of an example embodiment, a memory device includes: a plurality of sub-cell regions, each including a plurality of memory cells and arranged in a first direction; a plurality of contact regions between the plurality of sub-cell regions; a plurality of sub-word lines extending from the plurality of sub-cell regions to adjacent contact regions in the first direction, wherein the plurality of sub-word lines are spaced apart along a second direction intersecting the first direction; and a plurality of word line interconnects superimposed on at least some of the plurality of sub-cell regions, wherein the plurality of word line interconnects extend from the at least some of the plurality of sub-cell regions to adjacent contact regions in the first direction, and are superimposed on sub-word lines adjacent to the superimposed sub-word lines in the adjacent contact regions. At least some of the plurality of word line interconnects are connected to the superimposed sub-word lines in the adjacent contact regions, and the plurality of word line interconnects are connected to sub-word line drivers superimposed on at least some of the plurality of sub-cell regions.

[0008] According to another aspect of an example embodiment, a method of manufacturing a memory device includes: forming a cell structure layer, the cell structure layer including a memory cell structure having sub-word lines extending in a first direction in a plurality of sub-cell regions defined on a first substrate, wherein the sub-word lines are spaced apart in a second direction intersecting the first direction; inverting the cell structure layer and grinding the first substrate; forming a cell interconnect layer on an upper surface of the cell structure layer, the cell interconnect layer including word line interconnects alternately superimposed with the sub-word lines in the first and second directions in the plurality of sub-cell regions, the word line interconnects extending to adjacent contact regions to superimpose with adjacent sub-word lines; forming a circuit element layer by forming sub-word line drivers in a plurality of unit regions defined on a second substrate; forming a circuit interconnect layer on an upper surface of the circuit element layer; and bonding the cell interconnect layer and the circuit interconnect layer such that the plurality of sub-cell regions and the plurality of unit regions are superimposed on each other.

[0009] According to one or more example embodiments, because the word line interconnect connected to the sub-word line driver can be connected to the sub-word line in the contact areas at both ends of the sub-cell area, the sub-word line can be driven at both ends, and the driving capability of the sub-word line can be improved.

[0010] According to one or more example embodiments, because a word line interconnect connects to the sub-word line of an adjacent sub-cell region, the word line interconnects are alternately arranged, and bit line interconnects can be arranged in regions where no word line interconnects are provided. That is, the interconnection efficiency of the sub-cell regions can be improved.

[0011] According to one or more example embodiments, because the gap between word line interconnects can be increased, the coupling capacitance between word line interconnects can be reduced, and the risk of short-circuit faults between word line interconnects can be reduced.

[0012] The aspects to be addressed by this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the following description other aspects not mentioned herein. Attached Figure Description

[0013] The above and other aspects, features and advantages will become clearer from the following description of exemplary embodiments taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a view showing the circuit structure of a memory device according to an example embodiment.

[0015] Figure 2 This is a perspective view illustrating a memory device according to an example embodiment.

[0016] Figure 3 It shows a reference. Figure 2A perspective view of a portion of the described memory device.

[0017] Figure 4 This is a view showing the bonding surface of a memory device according to an example embodiment.

[0018] Figure 5 This is a cross-sectional view showing a portion of a memory device, wherein (A) includes... Figure 3 A sectional view of line II′, and (B) includes Figure 3 A sectional view of line II-II′.

[0019] Figure 6 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0020] Figure 7A and Figure 7B yes Figure 6 A cross-sectional view taken along the letter lines.

[0021] Figure 8 and Figure 9 This is a view showing the structure of the memory cell region and core control circuitry of a memory device according to an example embodiment.

[0022] Figure 10A , Figure 10B and Figure 10C This is a view showing the structure of the core control circuit according to an example embodiment.

[0023] Figure 11 This is a diagram illustrating the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0024] Figure 12A and Figure 12B yes Figure 11 A cross-sectional view taken along the letter lines.

[0025] Figure 13 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0026] Figure 14A and Figure 14B yes Figure 13 A cross-sectional view taken along the letter lines.

[0027] Figure 15 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0028] Figure 16A , Figure 16B and Figure 16C yes Figure 15 A cross-sectional view taken along the letter lines.

[0029] Figure 17 and Figure 18 This is a perspective view illustrating a memory device according to an example embodiment.

[0030] Figure 19 This is a perspective view showing the memory cell structure of a memory device according to an example embodiment.

[0031] Figure 20 This is a flowchart illustrating a method for manufacturing a memory device according to an example embodiment. Detailed Implementation

[0032] In the following description, exemplary embodiments will be described with reference to the accompanying drawings. Throughout the specification, the same components are designated by the same reference numerals, and repeated descriptions of them are omitted. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure.

[0033] Figure 1 This is a view showing the circuit structure of a memory device according to an example embodiment.

[0034] Reference Figure 1 The memory device 100 may include various circuits, including control logic circuitry 110, address register 121, bank control logic (i.e., bank control circuitry) 122, refresh counter 123, row address multiplexer 124, column address latch 125, row decoder 126, column decoder 127, memory core circuitry 141, sense amplifier 142, input / output gating circuitry 143, and data input / output buffer 150.

[0035] The memory core circuit 141 may include multiple memory core circuits 141a to 141h. In addition, multiple row decoders (126: 126a to 126h), multiple column decoders (127: 127a to 127h), and multiple sense amplifiers (142: 142a to 142h) may be respectively connected to the multiple memory core circuits 141a to 141h.

[0036] Each of the multiple memory core circuits 141a to 141h, the multiple sense amplifiers 142a to 142h, the multiple column decoders 127a to 127h, and the multiple row decoders 126a to 126h can respectively form multiple memory banks.

[0037] Each of the multiple memory core circuits 141a to 141h may include a memory cell array MCA and a core control circuit CCC. The memory cell array MCA may include multiple word lines, multiple bit lines, and multiple memory cells connected to the multiple word lines and multiple bit lines.

[0038] The core control circuit (CCC) may include circuitry configured to control the memory cell array (MCA). For example, the CCC may include sub-word line driver circuitry for driving multiple word lines, and bit line sense amplifier circuitry for detecting voltage changes on the multiple bit lines and amplifying those voltage changes.

[0039] Address register 121 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from a memory controller connected to memory device 100. Address register 121 can provide the received bank address BANK_ADDR to bank control logic 122, provide the received row address ROW_ADDR to row address multiplexer 124, and provide the received column address COL_ADDR to column address latch 125.

[0040] The memory bank control logic 122 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the row decoder corresponding to the memory bank address BANK_ADDR among the plurality of row decoders 126a to 126h can be activated, and the column decoder corresponding to the memory bank address BANK_ADDR among the plurality of column decoders 127a to 127h can be activated.

[0041] The row address multiplexer 124 can receive the row address ROW_ADDR from the address register 121 and the refresh row address REF_ADDR from the refresh counter 123. The row address multiplexer 124 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 124 can be applied to each of the plurality of row decoders 126a to 126h.

[0042] The refresh counter 123 can sequentially increase or decrease the refresh row address REF_ADDR according to the control of the control logic circuit 110.

[0043] In the multiple row decoders 126a to 126h, the row decoder activated by the memory bank control logic 122 can decode the row address RA output from the row address multiplexer 124 and can activate the word line corresponding to the row address. For example, the activated row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0044] Column address latch 125 can receive column address COL_ADDR from address register 121 and can temporarily store the received column address COL_ADDR. Furthermore, column address latch 125 can gradually increase the received column address COL_ADDR in burst mode. Column address latch 125 can apply the temporarily stored or gradually increased column address COL_ADDR to each of the multiple column decoders 127a to 127h.

[0045] Among the multiple column decoders 127a to 127h, the column decoder activated by the memory bank control logic 122 can activate the sense amplifier corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the corresponding input / output gate circuit 143.

[0046] The input / output gating circuit 143 may include input data masking logic, a read data latch for storing data output from multiple memory core circuits 141a to 141h, a write driver for writing data to the multiple memory core circuits 141a to 141h, and circuitry for gating input / output data.

[0047] The data signal DQ to be read from one of the memory bank arrays of the multiple memory core circuits 141a to 141h can be detected by a sense amplifier corresponding to that memory bank array and can be stored in a read data latch. The data signal DQ stored in the read data latch can be provided to the memory controller together with the data strobe signal DQS.

[0048] The data signal DQ to be written to a memory cell array MCA included in one of the multiple memory core circuits 141a to 141h can be provided to the input / output gating circuit 143 via the data input / output buffer 150. The input / output gating circuit 143 can write the data signal DQ to the target page of the memory cell array MCA via the write driver.

[0049] The data input / output buffer 150 can provide the data signal DQ to the input / output gating circuit 143 during a write operation, and can provide the data signal DQ provided from the input / output gating circuit 143 to the memory controller during a read operation.

[0050] Control logic circuitry 110 can control the operation of memory device 100. For example, control logic circuitry 110 can generate control signals that cause memory device 100 to perform write or read operations. Control logic circuitry 110 may include a command decoder 111 for decoding commands (CMD) received from the memory controller and a mode register 112 for setting the operating mode of memory device 100.

[0051] For example, the command decoder 111 can decode the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc., to generate control signals corresponding to the command CMD.

[0052] To reduce the area of ​​the memory device 100, the memory cell array (MCA) and the circuitry configured to control the MCA can be stacked, for example, in a cell-on-periphery (CoP) or cell-on-periphery (PoC) structure. For example, the area of ​​the memory device 100 can be reduced when the area occupied by the MCA and the core control circuitry (CCC) can be stacked on top of each other in a direction perpendicular to the substrate.

[0053] According to the example embodiment, the efficiency of the interconnect between the memory cell array MCA and the core control circuit CCC can be improved to more effectively reduce the area of ​​the memory device 100, and an interconnect structure that can also improve the driving capability of word lines is proposed. In the following, before describing the interconnect structure in detail, reference will be made to... Figures 2 to 4 The structure of a memory device according to an example embodiment is described.

[0054] Figure 2 This is simply a perspective view of a memory device according to an example embodiment.

[0055] Reference Figure 2 The memory device 200 may include a first semiconductor layer 210 and a second semiconductor layer 220. The first semiconductor layer 210 and the second semiconductor layer 220 may be stacked in a third direction (Z direction) perpendicular to the upper surface of the substrate of the memory device 200.

[0056] The first semiconductor layer 210 may include a memory cell array MCA, and the second semiconductor layer 220 may include a core control circuit CCC. Figure 2 The memory cell array MCA and core control circuit CCC can be compared with the reference Figure 1 The memory cell array MCA and the core control circuit CCC are described. The first semiconductor layer 210 can be referred to as the cell semiconductor layer, and the second semiconductor layer 220 can be referred to as the circuit semiconductor layer.

[0057] Figure 2The example illustrates a memory device 200 comprising a memory cell array (MCA) and a core control circuit (CCC), but the example embodiment is not limited thereto. For instance, the memory device 200 may include multiple memory cell arrays (MCAs) and multiple core control circuits (CCCs).

[0058] In an example embodiment, the memory device 200 may have a CoP structure in which a first semiconductor layer 210 is stacked on a second semiconductor layer 220.

[0059] The second semiconductor layer 220 may also include peripheral circuitry PC. For example, the peripheral circuitry PC may include, as shown in reference... Figure 1 The described control logic circuit 110, address register 121, memory control logic 122, refresh counter 123, row address multiplexer 124, column address latch 125, row decoder 126, column decoder 127, memory core circuit 141, sense amplifier 142, input / output gating circuit 143, and data input / output buffer 150 are described.

[0060] Figure 2 The illustration shows a case where the peripheral circuitry PC and the core control circuitry CCC are included in the same semiconductor layer; however, the peripheral circuitry PC and the core control circuitry CCC may be included in different semiconductor layers. For example, a memory device according to an example embodiment may have a three-layer structure in which the memory cell array MCA, the core control circuitry CCC, and the peripheral circuitry PC are stacked sequentially.

[0061] The memory cell array (MCA) may include multiple sub-cell arrays. The multiple sub-cell arrays may be arranged in a first direction (X direction) and a second direction (Y direction) that are parallel to and intersect each other with the upper surface of the substrate of the memory device 200. Figure 2 The diagram shows the multiple sub-cell regions MAT included in each of the sub-cell arrays.

[0062] Each of the multiple subcell arrays may include multiple subword lines extending in a first direction (X direction), multiple bit lines extending in a second direction (Y direction), and multiple memory cells connected to the multiple subword lines and the multiple bit lines.

[0063] When the memory cell array (MCA) is divided into multiple sub-cell arrays, the number of memory cells connected to a sub-word line is reduced, and the load used to drive the word line can be reduced.

[0064] The core control circuit CCC may include multiple unit control circuits configured to control multiple sub-unit arrays. Figure 2 The diagram shows multiple unit regions UA included in each of the multiple unit control circuits.

[0065] In an example embodiment, a unit region UA ​​may be superimposed on a sub-cell region MAT in a third direction (Z direction) and may control a sub-cell array. For example, a unit region UA ​​may include sub-word line driver circuitry for driving word lines included in the sub-cell array, bit line sense amplifier circuitry for detecting and amplifying signals of bit lines included in the sub-cell array, line decoder circuitry for generating control signals for word lines, and power supply circuitry for supplying power to circuitry included in the unit control circuitry.

[0066] However, the example embodiments are not limited to stacking a unit region UA ​​with a sub-cell region MAT, and a unit region UA ​​can be stacked with multiple adjacent sub-cell regions MAT and can control multiple sub-cell arrays.

[0067] Figure 3 It shows a reference. Figure 2 A perspective view of a portion of the described memory device.

[0068] Figure 3 It is shown in the reference Figure 2 The memory device 200 described has a structure of a sub-cell region MAT and a unit region UA ​​superimposed on the sub-cell region MAT in the third direction (Z direction).

[0069] The first semiconductor layer 210 may include a cell structure layer 211 and a cell interconnect layer 212. The cell structure layer 211 may include memory cell structures in sub-cell regions MAT. The memory cell structures may include multiple sub-word lines SWL, multiple bit lines BL, and multiple memory cells MC connected to the multiple sub-word lines SWL and the multiple bit lines BL. In an example embodiment, the multiple sub-word lines SWL may extend in a first direction (X direction), and the multiple bit lines BL may extend in a second direction (Y direction).

[0070] Cell interconnect layer 212 may include cell interconnects for electrically connecting multiple subword lines SWL and multiple bit lines BL to components of the second semiconductor layer 220. In an example embodiment, the cell interconnects may include a metallic element, such as tungsten (W).

[0071] The second semiconductor layer 220 may include a circuit element layer 221 and a circuit interconnect layer 222. The circuit element layer 221 may include semiconductor components included in the core control circuitry for controlling the memory cell structure in a unit region UA.

[0072] The circuit interconnect layer 222 may include circuit interconnects for electrically connecting semiconductor components included in the core control circuitry. In an example embodiment, the circuit interconnects may include a metallic element, such as tungsten (W).

[0073] For example, the core control circuit may include a sub-word line driver circuit electrically connected to multiple sub-word lines SWL and a bit line sense amplifier circuit electrically connected to multiple bit lines BL.

[0074] In an example embodiment, the first semiconductor layer 210 and the second semiconductor layer 220 may be joined in a Cu-Cu bonding manner. For example, the cell interconnect layer 212 may include a first bonding surface 213 containing a first bonding pad, and the circuit interconnect layer 222 may include a second bonding surface 223 containing a second bonding pad. The bonding pad may include a metallic element, such as copper (Cu). The first bonding surface 213 and the second bonding surface 223 may be joined, and the first bonding pad and the second bonding pad may be joined, such that the interconnects of the cell interconnect layer 212 and the interconnects of the circuit interconnect layer 222 are electrically connected.

[0075] Figure 4 This is a view showing the bonding surface of a memory device according to an example embodiment.

[0076] Figure 4 A bonding surface BS corresponding to a sub-cell region MAT or unit region UA ​​of a memory device is shown. The bonding surface BS can be referenced... Figure 3 The first mating surface 213 and the second mating surface 223 are joined together to form the described structure.

[0077] The mating surface BS may include multiple mating pads. Figure 4 In the example, the bonding surface BS may include bit line pads BLP and word line pads WLP. The number of each of the bit line pads BLP and word line pads WLP may be equal to the number of each of the bit lines BL and sub-word lines SWL included in a memory cell structure within a sub-cell region MAT.

[0078] Figure 4 The illustration shows a configuration where the bit line pad BLP is positioned relative to the second direction (Y direction) on the edge of the bonding surface BS, and the word line pad WLP is positioned at the center of the bonding surface BS. However, the example embodiment is not limited to this. For example, the positions of the bit line pad BLP and the word line pad WLP can be determined based on the positions of the bit line sense amplifier circuit and the sub-word line driver circuit within the unit region UA.

[0079] According to already referenced Figure 3 and Figure 4 The described content indicates that the sub-cell region MAT, the unit region UA, and the bonding surface BS can be stacked on top of each other in the third direction (Z direction). That is, because the memory cell structure and the core control circuitry can be stacked on top of each other in the third direction (Z direction), the area required for the memory device 200 can be reduced.

[0080] If the interconnect structure used to electrically connect the memory cell structure and the core control circuitry can also be superimposed on the sub-cell region MAT and the unit region UA ​​as much as possible, the area of ​​the memory device 200 can be reduced more effectively. According to an example embodiment, an interconnect structure is proposed in which the driving capability for driving the sub-word line SWL can be improved while also increasing area efficiency.

[0081] Figure 5 This is a cross-sectional view showing a portion of a memory device, wherein (A) includes... Figure 3 A sectional view of line II′, and (B) includes Figure 3 A sectional view of line II-II′.

[0082] According to already referenced Figure 3 As described, the memory device 200 may include a first semiconductor layer 210 and a second semiconductor layer 220. Figure 5 The diagram shows a cell structure layer 211 and a cell interconnect layer 212 included in the first semiconductor layer 210, and a circuit element layer 221 and a circuit interconnect layer 222 included in the second semiconductor layer 220.

[0083] Reference Figure 5 The cell structure layer 211 may include a memory cell structure and an insulating layer 201 covering the memory cell structure. The memory cell structure includes multiple cell capacitors CC, cell transistors CT, sub-word lines SWL, and bit lines BL. The multiple cell capacitors CC may be arranged in a first direction (X direction) and a second direction (Y direction). The multiple cell transistors CT may be arranged in the first direction (X direction) and the second direction (Y direction) and may be electrically connected to the multiple cell capacitors CC. A cell capacitor CC and a cell transistor CT connected to each other can form a memory cell. In an example embodiment, the cell transistor CT may be a vertical channel transistor (VCT) having a channel extending in a third direction (Z direction).

[0084] Bit lines BL can extend in a second direction (Y direction) and be arranged in a first direction (X direction). Each bit line BL can contact a cell transistor CT arranged in the second direction (Y direction) in a third direction (Z direction). Sub-word lines SWL can extend in the first direction (X direction) and can be arranged in the second direction (Y direction). Each sub-word line SWL can contact a cell transistor CT arranged in the first direction (X direction) in the second direction (Y direction).

[0085] Cell interconnect layer 212 may include a plurality of cell interconnect layers CM1 to CM4. Each of the plurality of cell interconnect layers CM1 to CM4 may include a cell interconnect line and may include a via CV that electrically connects the cell interconnect line between the cell interconnect layers CM1 to CM4. Cell interconnect layer 212 may include an insulating layer 202 covering the cell interconnect line and the via CV.

[0086] The interconnect structure formed by cell interconnects and vias CV can electrically connect each of the multiple sub-word lines SWL in the cell structure layer 211 to the word line pad WLP, and can electrically connect each of the bit lines BL to the bit line pad BLP.

[0087] The circuit element layer 221 may include a substrate 203 and semiconductor components formed on one surface of the substrate 203. The semiconductor components may form a bit line sense amplifier (BLSA) and a sub-word line driver (SWD).

[0088] Interconnect layer 222 may include a plurality of interconnect layers PM1 to PM6. Each of the plurality of interconnect layers PM1 to PM6 may include a circuit interconnect line and may include a via PV that electrically connects the circuit interconnect lines between interconnect layers PM1 to PM6. Interconnect layer 222 may include an insulating layer 204 covering (or surrounding) the circuit interconnect lines and the via PV.

[0089] The interconnect structure formed by circuit interconnects and vias (PV) allows the bit line sense amplifier (BLSA) to be electrically connected to the bit line pad (BLP), and the sub-word line driver (SWD) to be electrically connected to the word line pad (WLP).

[0090] Figure 5 Four cell interconnect layers CM1 to CM4 and six circuit interconnect layers PM1 to PM6 are shown, but the number of cell interconnect layers and circuit interconnect layers is not limited to this.

[0091] The first surface of the cell interconnect layer 212 may contact the cell structure layer 211, and the second surface opposite to the first surface may contact the circuit interconnect layer 222. The first surface of the circuit interconnect layer 222 may contact the circuit element layer 221, and the second surface opposite to the first surface may contact the cell interconnect layer 212. The bonding surface BS of the cell interconnect layer 212 and the circuit interconnect layer 222 may include a plurality of word line pads (WLPs) and a plurality of bit line pads (BLPs).

[0092] Reference Figure 5 In (B), the sub-word line driver SWD can be stacked with the memory cell structure, and at least a portion of the interconnect structure used to electrically connect the sub-word line driver SWD and the sub-word line SWL can be stacked with the memory cell structure. Based on the interconnect structure, the integration of the memory device and the driving capability of the sub-word line SWL can be determined.

[0093] For example, a sub-word line driver SWD can be shared by adjacent sub-word lines SWL included in adjacent sub-cell regions MAT. For example, the sub-word line driver SWD can be electrically connected to adjacent sub-word lines SWL in adjacent sub-cell regions MAT. By sharing the sub-word line driver SWD with adjacent sub-word lines SWL, the core control circuitry can be integrated within a unit region UA.

[0094] Furthermore, the driving capability of a sub-word line SWL can be improved by forming electrical connections with the sub-word line driver SWD at two or more locations. For example, the cell interconnect layer 212 may include word line interconnects that can electrically connect the two ends of the sub-word line SWL to the sub-word line driver SWD.

[0095] For example, word line interconnects can be disposed in the first unit interconnect layer CM1. The word line interconnects can be electrically connected to the sub-word line driver SWD, can be stacked with the sub-word line SWL in the third direction (Z direction), and can be electrically connected to both ends of the sub-word line SWL via contacts. Because the sub-word line SWL can be driven from both ends, the driving performance can be improved compared to the case where the sub-word line SWL is driven from only one end.

[0096] However, as the pitch of the sub-word lines (SWLs) decreases, it may be difficult to efficiently configure the word line interconnects to overlap with both ends of each sub-word line (SWL). For example, the pitch of the sub-word lines may be as small as one unit of the pitch of the interconnects in the cell interconnect layer 212. When the word line interconnects are formed at one-unit intervals in one of the interconnect layers of the cell interconnect layer 212, the efficiency of wiring the bit line (BL) to the bit line sense amplifier (BLSA) may be reduced.

[0097] Specifically, to connect the bit line BL to the bit line pad BLP, all interconnects in interconnect layers CM1 to CM4 should be connected between the bit line BL and the bit line pad BLP. When word line interconnects are spaced one unit apart within the sub-cell region MAT in the first interconnect layer CM1, it may be difficult to configure the bit line interconnects for connecting the bit line BL to the bit line pad BLP within the sub-cell region MAT. In this case, additional area may be required for configuring the bit line interconnects.

[0098] Furthermore, when word line interconnects are spaced at one unit interval within the subcell region MAT, the coupling capacitance between word line interconnects can increase, and there is a risk of short-circuit defects between word line interconnects.

[0099] According to an example embodiment, word line interconnects can be arranged across multiple sub-unit regions in a pattern similar to a chessboard. The word line interconnect arrangement according to the example embodiment can increase the pitch of the word line interconnects and simultaneously provide enhanced drive capability to the sub-word lines (SWLs).

[0100] Figure 6 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0101] For reference Figure 2 As described, the region of the memory cell array MCA may include multiple sub-cell regions MAT arranged in a first direction (X direction) and a second direction (Y direction). Figure 6 This diagram illustrates multiple sub-cell regions (MAT: MAT_O, MAT_E) arranged in a first direction (X direction). The multiple sub-cell regions MAT may include a first sub-cell region and a second sub-cell region alternately arranged in the first direction (X direction). The first sub-cell region may be referred to as the odd-numbered sub-cell region MAT_O, and the second sub-cell region may be referred to as the even-numbered sub-cell region MAT_E.

[0102] The contact area CON can be set between multiple sub-cell areas MAT. That is, the contact area CON can be set between adjacent odd-numbered sub-cell areas MAT_O and even-numbered sub-cell areas MAT_E.

[0103] In multiple sub-unit regions MAT, sub-word lines SWL can be arranged in a first direction (X direction) and a second direction (Y direction). A sub-unit region MAT may include sub-word lines SWL extending in the first direction (X direction) and arranged in the second direction (Y direction). The sub-word lines SWL may extend to the contact areas CON on both sides of the sub-unit region MAT in the first direction (X direction).

[0104] Sub-word lines (SWLs) set in a sub-cell region MAT may include a first sub-word line and a second sub-word line alternately arranged in a second direction (Y direction). The first sub-word line may be referred to as the odd-numbered sub-word line, and the second sub-word line may be referred to as the even-numbered sub-word line. The odd-numbered sub-word lines arranged in the first direction (X direction) may form odd-numbered lines (WL_O: WL_O1 to WL_O4), and the even-numbered sub-word lines arranged in the first direction (X direction) may form even-numbered lines (WL_E: WL_E1 to WL_E4).

[0105] For reference Figure 5 As described in (B), the word line interconnects for electrically connecting the sub-word line SWL to the sub-word line driver SWD can be disposed in the cell interconnect layer. Figure 6 In the example, the word line interconnect WLM can be overlaid with the sub-word line SWL in the third direction (Z direction).

[0106] According to an example embodiment, the word line interconnect (WLM) can be configured to alternately overlap with sub-word lines arranged in a first direction (X direction) and sub-word lines arranged in a second direction (Y direction). That is, the word line interconnect (WLM) can be arranged in a pattern similar to a chessboard pattern in multiple sub-cell regions (MAT).

[0107] The word line interconnects WLM may include odd-number word line interconnects superimposed on the odd-number sub-word lines WL_O of the odd-number sub-cell region MAT_O and even-number word line interconnects superimposed on the even-number sub-word lines WL_E of the even-number sub-cell region MAT_E.

[0108] Each word line interconnect (WLM) may be superimposed on a sub-word line (SWL) in a sub-cell region (MAT) and may extend to contact regions (CON) on both sides of the sub-cell region (MAT). Each word line interconnect (WLM) may be superimposed on a sub-word line in contact regions (CON) on both sides, wherein the sub-word line is adjacent to the superimposed sub-word line (SWL) in a first direction (X direction).

[0109] For example, each of the odd-numbered line interconnects can be superimposed with an odd-numbered sub-word line in the odd-numbered sub-cell region MAT_O, and additionally superimposed with an odd-numbered sub-word line in the adjacent even-numbered sub-cell region MAT_E in the contact region CON. Similarly, each of the even-numbered line interconnects can be superimposed with an even-numbered sub-word line in the even-numbered sub-cell region MAT_E, and additionally superimposed with an even-numbered sub-word line in the adjacent odd-numbered sub-cell region MAT_O in the contact region CON.

[0110] The core control circuit CCC region may include a unit region UA ​​superimposed on each of the multiple sub-unit regions MAT in the third direction (Z direction). Each unit region UA ​​may include a sub-word line driver block (SWDB: SWDB_O, SWDB_E). The sub-word line driver block SWDB may include a sub-word line driver for driving each of the multiple sub-word lines.

[0111] The unit region superimposed on the odd-numbered sub-cell region MAT_O may include an odd-numbered sub-word line driver block SWDB_O for driving the odd-numbered sub-word lines. Additionally, the unit region superimposed on the even-numbered sub-cell region MAT_E may include an even-numbered sub-word line driver block SWDB_E for driving the even-numbered sub-word lines.

[0112] The contact area CON may include a first contact CNT1 for connecting the sub-word line SWL and the word line interconnect (or word line pattern) WLM. The sub-cell area MAT may include a second contact CNT2 for connecting the word line interconnect WLM and the sub-word line driver.

[0113] According to an example embodiment, the word line interconnects (WLMs) in each of the sub-cell regions (MAT) can be configured to alternately overlap with the sub-word lines (SWLs), thereby increasing the spacing between the word line interconnects (WLMs). For example, when the pitch of the sub-word line (SWL) is one unit of the interconnect pitch, the pitch of the word line interconnect (WLM) can be two units.

[0114] According to an example embodiment, the bit line interconnects for electrically connecting the bit lines and bit line sense amplifiers can be disposed in the region between the word line interconnects (WLMs). Therefore, the additional region for setting the bit line interconnects outside the sub-cell region (MAT) is unnecessary, and the interconnect efficiency of the memory device can be improved. Furthermore, the coupling capacitance between the word line interconnects (WLMs) can be reduced, and the risk of short-circuit faults in the word line interconnects (WLMs) can be decreased.

[0115] Furthermore, each word line interconnect (WLM) can drive sub-word lines stacked in the sub-cell regions on both sides, and can also drive sub-word lines adjacent to the stacked sub-word lines. Based on the interconnect structure of the WLM, sub-word lines (SWLs) can be driven at both ends, and the driving performance of the sub-word lines (SWLs) can be improved.

[0116] Figure 7A and Figure 7B yes Figure 6 A cross-sectional view taken along the letter lines. Figure 7A yes Figure 6 A cross-sectional view taken along the odd-numbered line WL_O, and Figure 7B yes Figure 6 A sectional view taken along the even-numbered line WL_E.

[0117] Reference Figure 7A In the odd-numbered sub-word lines forming the odd-numbered sub-word lines WL_O, the sub-word lines and word line patterns WLM set in the odd-numbered sub-unit region MAT_O can be superimposed on each other. The word line pattern WLM can extend to the contact region CON and can be superimposed on the odd-numbered sub-word lines of the adjacent even-numbered sub-unit region MAT_E.

[0118] The word line pattern WLM can be electrically connected to the stacked odd-numbered sub-word lines via the first contact CNT1. The word line pattern WLM located in the odd-numbered sub-cell region MAT_O can be electrically connected to the odd-numbered sub-word line driver SWD_O stacked with the odd-numbered sub-cell region MAT_O via the second contact CNT2 and the word line pad WLP.

[0119] Each of the first contact CNT1 and the second contact CNT2 may include a via, but the example embodiment is not limited thereto. For example, each of the first contact CNT1 and the second contact CNT2 may include a plurality of vias and interconnects formed in one or more interconnect layers.

[0120] According to the example embodiment, since the odd-numbered sub-word lines disposed in the odd-numbered sub-cell region MAT_O can be electrically connected at both ends to the overlaid word line pattern WLM, the odd-numbered sub-word lines can be driven at both ends. Furthermore, the odd-numbered sub-word lines disposed in the even-numbered sub-cell region MAT_E can be electrically connected at both ends to the word line pattern WLM overlaid with the adjacent odd-numbered sub-cell region MAT_O. Even if the word line pattern WLM for the odd-numbered sub-word lines is not disposed in the even-numbered sub-cell region MAT_E, the odd-numbered sub-word lines disposed in the even-numbered sub-cell region MAT_E can still be driven at both ends. Therefore, the driving performance of the sub-word lines can be improved.

[0121] In areas where no word line pattern (WLM) is provided, a bit line pattern (or bit line interconnect) (BLM) for electrically connecting bit lines to bit line sense amplifiers can be provided. Therefore, interconnect efficiency can be improved.

[0122] Reference Figure 7B In the even-numbered sub-word lines included in the even-numbered sub-cell region MAT_E, the sub-word lines and word line patterns WLM set in the even-numbered sub-cell region MAT_E can be superimposed on each other. The word line pattern WLM can extend to the contact region CON and can be superimposed on the even-numbered sub-word lines of the adjacent odd-numbered sub-cell region MAT_O.

[0123] The word line pattern WLM can be electrically connected to the stacked even-numbered sub-word lines via the first contact CNT1. The word line pattern WLM located in the even-numbered sub-cell region MAT_E can be electrically connected to the even-numbered sub-word line driver SWD_E stacked with the even-numbered sub-cell region MAT_E via the second contact CNT2 and the word line pad WLP.

[0124] With reference Figure 7A The description is similar, because each of the even-numbered subword lines located in the odd-numbered subcell region MAT_O and the even-numbered subcell region MAT_E can be driven at both ends, thus improving the driving performance of the subword lines. Furthermore, because the bit line pattern (BLM) can be set in the regions where no word line pattern (WLM) is set, interconnect efficiency can be improved.

[0125] Figure 6 , Figure 7A and Figure 7B This illustrates a case where each of the word lines WL_O and WL_E is divided into multiple sub-word lines. However, the example embodiment is not limited to this. In the following text, reference will be made to... Figure 8 and Figure 9 A memory device according to an example embodiment is described.

[0126] Figure 8 and Figure 9This is a view showing the structure of the memory cell region and core control circuitry of a memory device according to an example embodiment.

[0127] Figure 8 The memory device may have the same Figure 6 The structure is similar to that of the memory device. However, the multiple sub-word lines arranged in the first direction (X direction) may not be separated in the contact area CON, but may extend across multiple sub-cell areas (MAT: MAT_O, MAT_E) to form a single word line WL.

[0128] Word lines WL can be electrically connected to sub-word line drivers stacked with sub-cell regions MAT via contact areas on both sides of the sub-cell region MAT, or to sub-word line drivers stacked with adjacent sub-cell regions. Therefore, even if a word line WL extends across multiple sub-cell regions MAT, each of the connected sub-word lines can be driven at both ends. Thus, this configuration can achieve the same driving performance as when multiple sub-word lines are separated by contact areas CON.

[0129] Figure 9 The memory device may have the same Figure 8 The structure is similar to that of the memory device. However, in each of the contact areas CON, a first contact CNT1 of each word line WL can be connected to the word line interconnect WLM. For example... Figure 8 The same situation applies. Figure 9 The word line WL can also be electrically connected to the sub-word line driver via contact areas on both sides of the sub-cell region MAT. Therefore, compared with the reference... Figure 6 and Figure 8 The memory devices described are similar, and this situation can result in improved drive performance.

[0130] In reference Figures 6 to 9 In the described memory device, among the circuitry included in each unit region UA, sub-word line driver blocks (SWDB: SWDB_O, SWDB_E) are simply shown. Each unit region UA ​​may include circuitry such as the sub-word line driver block SWDB and the bit line sense amplifier block BLSAB. The circuitry in each unit region UA ​​can be arranged in various patterns.

[0131] Figures 10A to 10C This is a view showing the structure of the core control circuit according to an example embodiment.

[0132] Figure 10A This illustrates a situation such as: Figures 6 to 9As shown, sub-word line driver blocks (SWDB: SWDB_O, SWDB_E) are positioned in the middle region of each unit region UA ​​based on a second direction (Y direction), and bit line sense amplifier blocks (BLSAB) are positioned in the edge regions. The sub-word line driver blocks (SWDB) and bit line sense amplifier blocks (BLSAB) may extend within the unit region UA ​​in a first direction (X direction). The bit line sense amplifier blocks (BLSAB) may include multiple bit line sense amplifiers connected to each bit line included in the corresponding sub-unit region.

[0133] Figure 10B The illustration shows a configuration where the bit line sense amplifier block BLSAB is positioned in the middle region based on a second direction (Y direction) and the sub-word line driver block SWDB is positioned in the edge region. The sub-word line driver block SWDB and the bit line sense amplifier block BLSAB can extend within a unit region UA ​​in a first direction (X direction).

[0134] Figure 10C The illustration shows a configuration where the bit line sense amplifier block BLSAB is positioned in the middle region based on a first direction (X direction) and the sub-word line driver block SWDB is positioned in the edge region. The sub-word line driver block SWDB and the bit line sense amplifier block BLSAB can extend in a second direction (Y direction) within a unit region UA.

[0135] The pattern used to set the subword line driver block SWDB and the bit line sense amplifier block BLSAB is not limited to... Figures 10A to 10C The pattern shown in the figure. The interconnect efficiency of word lines and bit lines can be determined based on whether the sub-word line driver block SWDB and the bit line sense amplifier block BLSAB extend in the first direction (X direction) or the second direction (Y direction).

[0136] In the example embodiment, the sub-word line driver block (SWDB) and the bit line sense amplifier block (BLSAB) can be arranged in a windmill pattern. In the areas of the unit region UA ​​where the sub-word line driver block (SWDB) and the bit line sense amplifier block (BLSAB) are not present, the line decoder circuitry, power supply circuitry, etc., can be installed.

[0137] In the case of an edge sub-cell region located at the edge within a sub-cell region MAT arranged in the first direction (X direction), adjacent sub-cell regions may be located on one side, but sub-cell regions may not be located on opposite sides. When word line interconnects and sub-word lines are alternately stacked in the edge sub-cell region, it may be difficult to connect the sub-word line driver to the two ends of the sub-word line where the word line interconnects are not stacked.

[0138] In the following text, refer to Figures 11 to 16CAn example of a memory device structure capable of providing the sub-word line with the same level of drive performance as the remaining sub-word lines.

[0139] Figure 11 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0140] For reference Figure 6 As described, the memory cell array (MCA) may include multiple sub-cell regions (MAT) arranged in a first direction (X direction). Figure 11 The diagram shows the edge odd-numbered sub-cell region MAT_OE located on the edge of the multiple sub-cell regions MAT of the memory cell array MCA, and the even-numbered sub-cell region MAT_E adjacent to the edge odd-numbered sub-cell region MAT_OE.

[0141] The contact area CON can be set between the edge odd-numbered sub-cell region MAT_OE and the adjacent even-numbered sub-cell region MAT_E. Furthermore, the edge contact area ECON can be set in the opposite direction to the edge odd-numbered sub-cell region MAT_OE.

[0142] In the edge odd-numbered sub-cell region MAT_OE, the sub-word line SWL may include a sub-word line SWL extending in a first direction (X direction) and arranged in a second direction (Y direction) intersecting the first direction (X direction). The sub-word line SWL may extend to both sides based on the sub-cell region MAT.

[0143] The edge odd-number subcell region MAT_OE may include odd-number line interconnects superimposed on the odd-number subword lines. Furthermore, the unit region UA ​​superimposed on the edge odd-number subcell region MAT_OE may include an odd-number subword line driver block SWDB_O electrically connected to the odd-number line interconnects via a second contact CNT2.

[0144] According to an example embodiment, the memory cell array MCA may further include a dummy region DUM adjacent to the edge contact region ECON in a first direction (X direction). Furthermore, the core control circuit CCC may also include an edge region EA superimposed on the dummy region DUM.

[0145] Edge region EA may include an edge subword line driver block SWDB_EE for driving the even-numbered subword lines of edge odd-numbered subcell region MAT_OE. Dummy region DUM may include an edge word line interconnect EWLM for electrically connecting the edge subword line driver block SWDB_EE and the even-numbered subword lines.

[0146] The edge word line interconnect (EWLM) extends from the dummy region (DUM) to the edge contact region (ECON) and can be connected to even-numbered sub-word lines via the first contact (CNT1) in the edge contact region (ECON). Furthermore, the edge word line interconnect (EWLM) can be connected to the edge sub-word line driver block (SWDB_EE) via the second contact (CNT2) in the dummy region (DUM).

[0147] Figure 12A and Figure 12B yes Figure 11 A cross-sectional view taken along the letter lines. Figure 12A yes Figure 11 A cross-sectional view taken along the odd-numbered line WL_O, and Figure 12B yes Figure 11 A sectional view taken along the even-numbered line WL_E.

[0148] Reference Figure 12A The odd-numbered sub-word lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be electrically connected to the odd-numbered line interconnects via the first contact CNT1 provided in the contact region CON and the edge contact region ECON. Therefore, the odd-numbered sub-word lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be driven at both ends.

[0149] Reference Figure 12B The even-numbered sub-word lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be connected to the even-numbered line interconnect WLM superimposed on the adjacent even-numbered sub-cell region MAT_E via the first contact CNT1 located in the contact region CON. The even-numbered line interconnect WLM can be connected to the even-numbered sub-word line driver SWD_E via the second contact CNT2 and the word line pad WLP.

[0150] Furthermore, even-numbered sub-word lines can be connected to the edge word line interconnect EWLM via the first contact CNT1 located in the edge contact area ECON. The edge word line interconnect EWLM can be connected to the edge sub-word line driver SWD_EE via the second contact CNT2 and the word line pad WLP.

[0151] According to an example embodiment, even-numbered subword lines located in the edge odd-numbered sub-cell region MAT_OE can be provided with the same level of drive performance as the remaining subword lines. The memory cell array MCA may also include edge even-numbered sub-cell regions, and the same level of drive performance can be provided to the odd-numbered subword lines located in the edge even-numbered sub-cell regions in the same manner.

[0152] Figure 13 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0153] Reference Figure 13 The edge odd-numbered sub-cell region MAT_OE and the even-numbered sub-cell region MAT_E adjacent to the edge odd-numbered sub-cell region MAT_OE are shown among the multiple sub-cell regions MAT of the memory cell array MCA.

[0154] The contact area CON can be located between the edge odd-numbered sub-cell region MAT_OE and the adjacent even-numbered sub-cell region MAT_E. Furthermore, the edge contact area ECON can be located in the opposite direction to the contact area CON relative to the edge odd-numbered sub-cell region MAT_OE. The core control circuit CCC may include an edge unit region EUA superimposed on the edge odd-numbered sub-cell region MAT_OE.

[0155] According to an example embodiment, the edge unit region EUA may further include an edge subword line driver block SWDB_EE and an odd subword line driver block SWDB_O for driving even-numbered subword lines. The edge odd-numbered subunit region MAT_OE may further include an edge word line interconnect EWLM that overlaps with the even-numbered subword lines and extends to the edge contact region ECON.

[0156] The edge word line interconnect EWLM can be connected to the even-numbered sub-word line via the first contact CNT1 in the edge contact region ECON. Furthermore, the edge word line interconnect EWLM can be connected to the edge sub-word line driver block SWDB_EE via the second contact CNT2 in the edge odd-numbered sub-cell region MAT_OE. The edge word line interconnect EWLM may not extend completely across the edge odd-numbered sub-cell region MAT_OE. That is, the length of the edge word line interconnect EWLM in the first direction (X direction) may be shorter than the sum of the lengths of the edge contact region ECON and the edge odd-numbered sub-cell region MAT_OE in the first direction (X direction).

[0157] Figure 14A and Figure 14B yes Figure 13 A cross-sectional view taken along the letter lines. Figure 14A yes Figure 13 A cross-sectional view taken along the odd-numbered line WL_O, and Figure 14B yes Figure 13 A sectional view taken along the even-numbered line WL_E.

[0158] Reference Figure 14A , as reference Figure 12A As described, the odd-numbered subword lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be driven at both ends.

[0159] Reference Figure 14BThe even-numbered sub-word lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be connected to the even-numbered sub-word line driver SWD_E superimposed on the adjacent even-numbered sub-cell region MAT_E through the first contact CNT1 set in the contact region CON.

[0160] Furthermore, even-numbered sub-word lines can be connected to the edge word line interconnect EWLM via the first contact CNT1 located in the edge contact area ECON. The edge word line interconnect EWLM can be connected to the edge sub-word line driver SWD_EE via the second contact CNT2 and the word line pad WLP.

[0161] According to the example embodiment, the same level of drive performance as the remaining subword lines can be provided to the even subword lines located in the edge odd sub-cell region MAT_OE, and the same level of drive performance can be provided to the odd subword lines located in the edge even sub-cell region in the same manner.

[0162] Furthermore, because edge word line interconnects (EWLMs) do not cross edge odd-numbered subcell regions (MAT_OE), bit line interconnects (BLMs) can be set in the regions of word line interconnects where edge odd-numbered subcell regions (MAT_OE) are not defined. Therefore, word line interconnects and bit line interconnects can be effectively configured.

[0163] Figure 15 This is a view showing the structure of the memory cell array and core control circuitry of a memory device according to an example embodiment.

[0164] Reference Figure 15 The diagram shows the edge odd-numbered sub-cell region MAT_OE located on the edge of the multiple sub-cell regions MAT of the memory cell array MCA, and the even-numbered sub-cell region MAT_E adjacent to the edge odd-numbered sub-cell region MAT_OE.

[0165] The contact area CON can be located between the edge odd-numbered sub-cell region MAT_OE and the adjacent even-numbered sub-cell region MAT_E. Furthermore, the edge contact area ECON can be located in the opposite direction to the contact area CON relative to the edge odd-numbered sub-cell region MAT_OE. The core control circuit CCC may include an edge unit region EUA superimposed on the edge odd-numbered sub-cell region MAT_OE.

[0166] According to an example embodiment, the edge unit region EUA may further include an edge subword line driver block SWDB_EE and an odd subword line driver block SWDB_O for driving even-numbered subword lines. Figure 15In the example, the edge subword driver block SWDB_EE can drive fewer subwords than the number of even subwords set in the edge odd subcell region MAT_OE, and can occupy more than Figure 13 The area of ​​the edge subword line driver block SWDB_EE in the example is small.

[0167] The edge subword driver block SWDB_EE can drive some of the even-numbered subword lines among multiple even-numbered subword lines. For example, the edge subword driver block SWDB_EE can drive the even-numbered subword lines that form the fourth even-numbered subword line WL_E4.

[0168] According to an example embodiment, the edge odd-numbered sub-cell region MAT_OE may further include word line interconnects extending from the even-numbered sub-cell region MAT_E to the edge contact region ECON and overlapping with the remaining even-numbered sub-word lines. The remaining even-numbered sub-word lines can be connected via word line interconnects to the even-numbered sub-word line driver block SWDB_E overlapping with the adjacent even-numbered sub-cell region MAT_E.

[0169] The length of the edge word line interconnect (EWLM) in the first direction (X direction) can be shorter than the sum of the lengths of the edge contact region (ECON) and the edge odd-numbered sub-cell region (MAT_OE) in the first direction (X direction). See reference. Figure 15 The edge odd-numbered sub-cell region MAT_OE may include a region where the pitch of the word line interconnects (WLMs) is one unit of the interconnect pitch and a region where the pitch of the word line interconnects (WLMs) is two units. According to an example embodiment, the bit line interconnects may be located in the region between the word line interconnects (WLMs) with a pitch of two units.

[0170] Figures 16A to 16C yes Figure 15 A cross-sectional view taken along the letter lines. Figure 16A yes Figure 15 A cross-sectional view taken along the odd-number line WL_O. Figure 16B yes Figure 15 A sectional view taken along the even-numbered line WL_E4, and Figure 16C yes Figure 15 A sectional view taken along the even-numbered lines WL_E1, WL_E2, and WL_E3.

[0171] Reference Figure 16A ,and Figure 14A Similarly, odd-numbered subword lines superimposed on the edge odd-numbered sub-cell regions MAT_OE can be driven at both ends.

[0172] Reference Figure 16B ,and Figure 14BSimilarly, some of the even-numbered subword lines superimposed on the edge odd-numbered subcell region MAT_OE can be connected to the even-numbered subword line driver SWD_E superimposed on the adjacent even-numbered subcell region MAT_E via the first contact CNT1 located in the contact region CON. Furthermore, bit line interconnects (BLMs) can be located in areas where no word line interconnects are provided.

[0173] Reference Figure 16C Some of the remaining even-numbered sub-word lines superimposed on the edge odd-numbered sub-cell region MAT_OE can be connected to the word line interconnect line WLM extending from the adjacent even-numbered sub-cell region MAT_E and the even-numbered sub-word line driver SWD_E superimposed on the adjacent even-numbered sub-cell region MAT_E via the first contact CNT1 set in the contact region CON and the edge contact region ECON.

[0174] According to the example embodiment, the same level of drive performance as the remaining subword lines can be provided to the even subword lines located in the edge odd sub-cell region MAT_OE, and the same level of drive performance can be provided to the odd subword lines located in the edge even sub-cell region in the same manner.

[0175] Furthermore, because bit line interconnects (BLMs) can be configured to overlap with some of the even-numbered sub-word lines, interconnect efficiency can be improved. In an interconnect layer where word line interconnects are located, the bit line interconnect (BLM) can occupy a localized area, much like a contact. Therefore, even if the word line interconnect (BLM) is not overlapped with only some of the even-numbered sub-word lines, such as the even-numbered sub-word lines forming the fourth even-numbered sub-word line WL_E4, a bit line interconnect (BLM) can be configured for all bit lines located in the edge odd-numbered sub-cell region MAT_OE.

[0176] Reference Figures 2 to 16C Example embodiments have been described in which a unit semiconductor layer is disposed on a circuit semiconductor layer, and the circuit interconnect layer of the circuit semiconductor layer and the unit interconnect layer of the unit semiconductor layer are bonded to each other. However, the example embodiments are not limited thereto. Hereinafter, reference will be made to... Figure 17 and Figure 18 The structure of a memory device according to an example embodiment is described.

[0177] Figure 17 and Figure 18 This is simply a perspective view of a memory device according to an example embodiment.

[0178] Reference Figure 17The memory device 300 may include a first semiconductor layer 310 and a second semiconductor layer 320 stacked on the first semiconductor layer 310 in a third direction (Z direction). The memory device 300 may have a PoC structure in which circuit semiconductor layers are stacked on unit semiconductor layers.

[0179] The first semiconductor layer 310 may include a cell structure layer 311 and a cell interconnect layer 312. The cell structure layer 311 and the cell interconnect layer 312 may have the same characteristics as referenced layers. Figure 3 The described unit structure layer 211 and unit interconnection layer 212 have similar structures.

[0180] The second semiconductor layer 320 may include a circuit element layer 321 and a circuit interconnect layer 322. The circuit element layer 321 and the circuit interconnect layer 322 may have the same characteristics as the reference layer. Figure 3 The circuit element layer 221 and the circuit interconnect layer 222 have similar structures.

[0181] In an example embodiment, the first semiconductor layer 310 and the second semiconductor layer 320 can be joined by a Cu-Cu bonding method. The first bonding surface 313 of the cell interconnect layer 312 and the second bonding surface 323 of the circuit interconnect layer 322 can be joined to each other, and the first bonding pad formed on the first bonding surface 313 and the second bonding pad formed on the second bonding surface 323 can be joined to each other, so that the interconnects of the cell interconnect layer 312 and the interconnects of the circuit interconnect layer 322 can be electrically connected.

[0182] According to an example embodiment, the cell interconnect layer 312 may include word line interconnects configured to alternately overlap with sub-word lines arranged in a first direction (X direction) and a second direction (Y direction) across multiple sub-cell regions. Furthermore, bit line interconnects may be disposed between the word line interconnects.

[0183] Reference Figure 18 The memory device 400 may include a first semiconductor layer 410 and a second semiconductor layer 420. The first semiconductor layer 410 may be stacked on the second semiconductor layer 420 in the third direction (Z direction). The first semiconductor layer 410 may include a cell structure layer 411 and a cell interconnect layer 412, and the second semiconductor layer 420 may include a circuit element layer 421 and a circuit interconnect layer 422.

[0184] In an example embodiment, the first bonding surface 413 of the cell structure layer 411 and the second bonding surface 423 of the circuit interconnect layer 422 can be bonded to each other, thereby bonding the first semiconductor layer 410 and the second semiconductor layer 420. Interconnects in the cell interconnect layer 412 can be electrically connected to interconnects in the circuit interconnect layer 422 via through-silicon vias (TSVs, or through-silicon vias), which penetrate the cell structure layer 411 to connect to the cell interconnect layer 412.

[0185] According to an example embodiment, the cell interconnect layer 412 may include word line interconnects configured to alternately overlap with sub-word lines arranged in a first direction (X direction) and a second direction (Y direction) across multiple sub-cell regions. Furthermore, bit line interconnects may be disposed between the word line interconnects.

[0186] For reference Figure 5 As described, the memory device may include a memory cell structure having a VCT as a unit transistor. (See reference...) Figure 19 An example describing the structure of a memory cell.

[0187] Figure 19 This is a perspective view showing the memory cell structure of a memory device according to an example embodiment.

[0188] Reference Figure 19 The integrated circuit device 500 may include a substrate 510, multiple first conductive lines 520, a channel layer 530, a gate electrode 540, and a capacitor structure 580. The integrated circuit device 500 may be a memory device including a VCT. A vertical channel transistor may refer to a structure in which the channel length of the channel layer 530 extends from the substrate 510 in a vertical direction (or vertical direction).

[0189] A lower insulating layer 512 may be disposed on a substrate 510, and a plurality of first conductive lines 520 may be spaced apart from each other in a first direction (X direction) and may extend in a second direction (Y direction) on the lower insulating layer 512. The plurality of first conductive lines 520 may be used as bit lines of an integrated circuit device 500.

[0190] In an example embodiment, the plurality of first conductive lines 520 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. The plurality of first conductive lines 520 may comprise a single layer or multiple layers of the aforementioned materials.

[0191] The channel layer 530 can be arranged in a matrix on multiple first conductive lines 520, wherein the channel layers 530 are spaced apart from each other in a first direction (X direction) and a second direction (Y direction). The bottom of the channel layer 530 can be used as a first source / drain region, the upper part of the channel layer 530 can be used as a second source / drain region, and the portion of the channel layer 530 between the first source / drain region and the second source / drain region can be used as a channel region.

[0192] In an example embodiment, the channel layer 530 may include an oxide semiconductor. The channel layer 530 may be polycrystalline or amorphous, but the example embodiment is not limited thereto. In an example embodiment, the channel layer 530 may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or combinations thereof.

[0193] The gate electrode 540 may extend in a first direction (X direction) on both sidewalls of the channel layer 530. The gate electrode 540 may include a first sub-gate electrode 540P1 facing the first sidewall of the channel layer 530 and a second sub-gate electrode 540P2 facing the second sidewall of the channel layer 530 opposite to the first sidewall. Because a channel layer 530 is disposed between the first sub-gate electrode 540P1 and the second sub-gate electrode 540P2, the integrated circuit device 500 may have a dual-gate transistor structure. However, the exemplary embodiment is not limited thereto, and a single-gate transistor structure can be achieved by omitting the second sub-gate electrode 540P2 and forming only the first sub-gate electrode 540P1 facing the first sidewall of the channel layer 530.

[0194] The gate electrode 540 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0195] The gate insulating layer 550 may surround the sidewall of the channel layer 530 and may be disposed between the channel layer 530 and the gate electrode 540. For example, as Figure 19 As shown, the entire sidewall of the channel layer 530 may be surrounded by the gate insulating layer 550, and a portion of the sidewall of the gate electrode 540 may contact the gate insulating layer 550. In other example embodiments, the gate insulating layer 550 may extend in a first direction (X direction) along which the gate electrode 540 extends, and only two sidewalls of the channel layer 530 facing the gate electrode 540 may contact the gate insulating layer 550.

[0196] In an example embodiment, the gate insulating layer 550 may be formed of a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than that of the silicon oxide film, or a combination thereof. The high-k dielectric film may be formed of a metal oxide or a metal oxynitride.

[0197] Capacitor contacts 560 may be disposed on the channel layer 530. The capacitor contacts 560 may be configured to be vertically stacked with the channel layer 530, and the capacitor contacts 560 may be arranged in a matrix form in which the capacitor contacts 560 are spaced apart from each other in a first direction (X direction) and a second direction (Y direction).

[0198] Capacitor structure 580 may be included on capacitor contact 560. Capacitor structure 580 may include a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode.

[0199] The lower electrode may be electrically connected to the upper surface of the capacitor contact 560. The lower electrode may be formed as a column extending in a third direction (Z direction), but the example embodiment is not limited thereto. In the example embodiment, the lower electrode may be configured to be vertically stacked with the capacitor contact 560, and the lower electrodes may be arranged in a matrix form in which the lower electrodes are spaced apart from each other in a first direction (X direction) and a second direction (Y direction). Optionally, a landing pad may be further provided between the capacitor contact 560 and the lower electrode, such that the lower electrode may be arranged in a hexagonal shape.

[0200] Figure 20 This is a flowchart illustrating a method for manufacturing a memory device according to an example embodiment.

[0201] Reference Figure 20 The method for manufacturing a memory device may include operations such as forming a first semiconductor layer (S100), forming a second semiconductor layer (S200), and bonding the first semiconductor layer and the second semiconductor layer (S300). In an example embodiment, operations S100 and S200 may be performed in parallel.

[0202] Operation S100 may include operations S110 to S150.

[0203] In operation S110, multiple cell array regions and contact regions can be defined on the first substrate. For example, multiple cell array regions can be arranged in a first direction and a second direction parallel to the upper surface of the first substrate. Contact regions can be defined between the multiple cell array regions arranged in the first direction.

[0204] In operation S120, a memory cell structure including sub-word lines can be formed in each of the multiple cell array regions. A cell structure layer can be formed by covering the memory cell structure with an insulating layer.

[0205] In operation S130, the unit structure layer can be inverted, and the first substrate on the unit structure layer can be removed by grinding.

[0206] In operation S140, a unit interconnect layer including word line interconnects can be formed on the upper surface of the unit structure layer, with word line interconnects and sub-word lines alternately stacked.

[0207] For example, a plurality of sub-cell regions arranged in a first direction may include sub-word lines arranged in both the first and second directions. Word line interconnects may be configured to alternately overlap with the sub-word lines arranged in the first and second directions. Each of the word line interconnects may extend to an adjacent contact region. Each of the word line interconnects may overlap with a sub-word line in the sub-cell region, and may overlap with the sub-word line adjacent to that sub-word line and the adjacent contact region.

[0208] In operation S150, a first bonding pad may be formed on the upper surface of the cell interconnect layer. For example, the first bonding pad may include a word line pad electrically connected to a sub-word line and a bit line pad electrically connected to a bit line.

[0209] Operation S200 may include operations S210 to S230.

[0210] In operation S210, a circuit element layer can be formed by forming circuit elements in each of a plurality of unit regions defined on a second substrate. For example, the circuit elements may include elements of core control circuitry, including sub-word line drivers and bit line sense amplifiers.

[0211] In operation S220, a circuit interconnect layer can be formed by forming circuit interconnects on the upper surface of the circuit element layer and covering the circuit interconnects with an insulating layer. The circuit interconnects electrically connect the circuit elements to provide the core control circuitry.

[0212] In operation S230, a second bonding pad may be formed on the upper surface of the circuit interconnect layer. For example, the second bonding pad may include a word line pad electrically connected to a sub-word line driver and a bit line pad electrically connected to a bit line sense amplifier.

[0213] In operation S300, the first semiconductor layer and the second semiconductor layer can be bonded such that the first bonding pad and the second bonding pad are stacked on top of each other. By bonding the first semiconductor layer and the second semiconductor layer, multiple unit regions and multiple sub-unit regions can also be stacked on top of each other, and sub-word line drivers and sub-word lines can be electrically connected to each other, and bit line sensing amplifiers and bit lines can be electrically connected to each other.

[0214] According to the example embodiment, because the word line interconnects are configured to alternately overlap with sub-word lines in the sub-cell region, sufficient spacing for setting up bit line interconnects can be ensured between the word line interconnects even when the pitch of the sub-word lines decreases. Therefore, the efficiency of interconnects in the sub-cell region can be improved.

[0215] Furthermore, because the alternately arranged word line interconnects can also be electrically connected to adjacent sub-word lines, each of the sub-word lines can be electrically connected to a sub-word line driver at both ends. Since the sub-word lines can be driven at both ends, drive performance can be improved.

[0216] While aspects of exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A unit semiconductor layer includes a plurality of sub-unit regions arranged in a first direction and a plurality of contact regions between the plurality of sub-unit regions, wherein the plurality of sub-unit regions include a plurality of memory cells; and A circuit semiconductor layer, on the unit semiconductor layer, includes circuitry configured to control the plurality of memory units. The unit semiconductor layer includes: Sub-line, extending in a first direction from the plurality of sub-unit regions to adjacent contact regions, wherein the sub-line is spaced apart along a second direction intersecting the first direction; and Word line interconnects, and Among them, word line interconnects include: Odd-number interconnects extend from an odd-numbered sub-unit region among the plurality of sub-unit regions to an adjacent contact region. These odd-number interconnects overlap in a third direction with odd-numbered sub-words in the odd-numbered sub-unit region and odd-numbered sub-words in the even-numbered sub-unit region adjacent to the odd-numbered sub-unit region in a first direction, wherein the third direction intersects with both the first and second directions; and Even-numbered line interconnects extend from an even-numbered sub-unit region among the plurality of sub-unit regions to an adjacent contact region. The even-numbered line interconnects overlap with even-numbered sub-word lines in the even-numbered sub-unit region in a third direction and even-numbered sub-word lines in the odd-numbered sub-unit region adjacent to the even-numbered sub-unit region in a first direction.

2. The memory device according to claim 1, wherein, The unit semiconductor layer includes contacts in the plurality of contact regions for connecting odd-numbered line interconnects to stacked odd-numbered sub-word lines and contacts for connecting even-numbered line interconnects to stacked even-numbered sub-word lines.

3. The memory device according to claim 1, wherein, The circuit semiconductor layer includes multiple unit regions stacked in a third direction with the plurality of sub-unit regions, and Each of the plurality of unit regions includes a plurality of subword line drivers.

4. The memory device according to claim 3, wherein, The plurality of sub-word line drivers are connected to word line interconnects that are superimposed on the corresponding sub-cell regions.

5. The memory device according to claim 3, wherein, The unit semiconductor layer includes: The unit structure layer includes the plurality of memory cells and sub-word lines; and The cell interconnect layer includes a first interconnect layer, and word line interconnects are disposed in the first interconnect layer. The circuit semiconductor layer includes: The circuit element layer includes the semiconductor components of the plurality of sub-word line drivers; and The circuit interconnect layer includes interconnects that electrically connect semiconductor components.

6. The memory device according to claim 3, wherein, Each of the plurality of unit regions further includes a plurality of bit line sensing amplifiers, and The plurality of bit line sense amplifiers are connected to bit lines via bit line interconnects, and the bit lines are connected to the plurality of memory cells. The bit line interconnects are formed in an interconnect layer at the same level as the word line interconnects.

7. The memory device according to claim 1, wherein, The unit semiconductor layer also includes: A dummy region is separated from the edge odd-numbered sub-unit regions among the plurality of sub-unit regions in a first direction; The edge contact region, between the edge odd-numbered sub-unit region and the dummy region; and Edge word line interconnects are superimposed on the dummy region and the edge contact region, and connect to the even-numbered sub-word lines of the edge odd-numbered sub-cell regions in the edge contact region. The circuit semiconductor layer includes: an edge circuit region, superimposed on the dummy region in a third-order direction and including an edge sub-word line driver; and The edge sub-word line driver is connected to the edge word line interconnect.

8. The memory device according to claim 1, wherein, The unit semiconductor layer further includes edge contact regions that are adjacent to the edge odd-numbered sub-unit regions among the plurality of sub-unit regions in a first direction, and are disposed in the opposite direction to the adjacent contact regions among the plurality of contact regions. The edge odd-numbered sub-cell region includes edge word line interconnects that connect to the even-numbered sub-word lines of the edge odd-numbered sub-cell region, and The circuit semiconductor layer also includes an edge sub-word line driver, which is stacked on the edge odd-numbered sub-cell region in the third direction and connected to the edge word line interconnect.

9. The memory device according to claim 8, wherein, In the first direction, the length of the edge word line interconnect is shorter than the sum of the length of the edge contact region and the length of the edge odd-numbered sub-cell region.

10. The memory device according to claim 1, wherein, The unit semiconductor layer further includes edge contact regions that are adjacent to the edge odd-numbered sub-unit regions among the plurality of sub-unit regions in a first direction, and are disposed in the opposite direction to the adjacent contact regions among the plurality of contact regions. The odd-numbered sub-unit regions at the edges include: A first edge word line interconnect extends from a first even-numbered word line interconnect in an adjacent even-numbered sub-cell region to an edge contact region, wherein the first edge word line interconnect connects to a first even-numbered sub-word line in an edge odd-numbered sub-cell region; and The second edge word line interconnect is spaced apart from the second even-numbered word line interconnect of the adjacent even-numbered sub-cell region, wherein the second edge word line interconnect connects to the second even-numbered sub-word line of the edge odd-numbered sub-cell region in the edge contact region, and The circuit semiconductor layer also includes an edge sub-word line driver, which is stacked on the edge odd-numbered sub-cell region in the third direction and connected to the second edge word line interconnect.

11. The memory device according to claim 10, wherein, In the first direction, the length of the second edge word line interconnect is shorter than the sum of the length of the edge contact region and the length of the edge odd-numbered sub-cell region.

12. The memory device according to claim 10, wherein, The circuit semiconductor layer includes a plurality of edge sub-word line drivers, the plurality of edge sub-word line drivers including the edge sub-word line drivers, and The number of the plurality of edge subword line drivers is smaller than the number of even subword lines in the edge odd sub-cell regions.

13. The memory device according to claim 1, wherein, The sub-character lines arranged in the first direction in the plurality of sub-unit regions are connected to each other.

14. The memory device according to claim 1, wherein, The memory device has a peripheral upper cell structure, in which the cell semiconductor layer is located on the circuit semiconductor layer.

15. The memory device according to claim 1, wherein, The memory device has a cell-top peripheral structure, in which the circuit semiconductor layer is located on the cell semiconductor layer.

16. A memory device, comprising: Multiple sub-unit regions, each including multiple memory units and arranged in a first direction; Multiple contact areas are located between the multiple sub-unit areas; Multiple sub-character lines extend from the multiple sub-unit regions to adjacent contact regions in a first direction, wherein the multiple sub-character lines are spaced apart along a second direction intersecting the first direction; and Multiple word line interconnects are superimposed on at least some of the multiple sub-cell regions, wherein the multiple word line interconnects extend from at least some of the multiple sub-cell regions to adjacent contact regions in a first direction, and are superimposed on sub-word lines adjacent to the superimposed sub-word lines in the adjacent contact regions in the first direction. Wherein, at least some of the plurality of word line interconnects are connected to stacked sub-word lines in adjacent contact areas, and the plurality of word line interconnects are connected to sub-word line drivers stacked with at least some of the plurality of sub-cell areas.

17. The memory device of claim 16, further comprising: Multiple bit lines extend in a second direction in at least some of the multiple sub-cell regions, wherein the multiple bit lines are spaced apart in a first direction; Bit line sensing amplifier, in each of the plurality of sub-unit regions; and An interconnect structure connects the multiple bit lines and bit line sensing amplifiers. The interconnect structure includes bit line interconnects at the same level as the multiple word line interconnects.

18. The memory device according to claim 17, wherein, Each of the plurality of memory cells includes a cell capacitor and a cell transistor, the cell transistor being in contact with the cell capacitor in a third upward direction perpendicular to the first and second directions, and The unit transistor is in contact with the plurality of bit lines aligned in a third direction and with the plurality of subword lines aligned in a second direction.

19. A method for manufacturing a memory device, comprising the following steps: A cell structure layer is formed, comprising a memory cell structure having sub-word lines extending in a first direction in a plurality of sub-cell regions, the plurality of sub-cell regions being defined on a first substrate, wherein... The sub-lines are spaced apart in a second direction that intersects with the first direction; Invert the unit structure layer and grind the first substrate; A cell interconnect layer is formed on the upper surface of the cell structure layer. The cell interconnect layer includes word line interconnects that are alternately superimposed with sub-word lines in the first and second directions in the plurality of sub-cell regions. The word line interconnects extend to adjacent contact regions to superimpose with adjacent sub-word lines. A circuit element layer is formed by forming sub-word line drivers in multiple unit regions defined on a second substrate; A circuit interconnect layer is formed on the upper surface of the circuit element layer; as well as The cell interconnect layer and the circuit interconnect layer are joined together such that the plurality of sub-cell regions and the plurality of unit regions are superimposed on each other.

20. The method of manufacturing a memory device according to claim 19, the method further comprising: A first bonding pad is formed on the surface of the cell interconnect layer; as well as A second bonding pad is formed on the surface of the circuit interconnect layer. The step of joining the cell interconnect layer and the circuit interconnect layer includes joining the first bonding pad and the second bonding pad.

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