Semiconductor device

Abstract

A semiconductor device includes a substrate having a cell active pattern, a cell gate structure on the cell active pattern, and a bit line structure connected to the cell active pattern. The cell gate structure includes a cell gate insulating layer on the cell active pattern, a cell gate conductive layer on the cell gate insulating layer, and a cell gate capping layer on the cell gate conductive layer and including an insulating material and hydrogen.

Description

Cross-reference of related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0019972, filed on February 17, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device. Background Technology

[0003] Semiconductors can be located in the intermediate region between a conductor and an insulator and can conduct electricity under certain conditions. These semiconductor materials can be used to manufacture various semiconductor devices, such as memory devices. Such semiconductor devices can be used in a variety of electronic devices.

[0004] As electronic devices become smaller and more integrated, there is a growing desire to finely pattern the structures that make up semiconductor devices. As the width of these micropatterns gradually decreases, the manufacturing process may become more difficult, and the defect rate of semiconductor devices may increase. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device that utilizes hydrogen to passivate dangling bonds present at the interface between the cell gate insulating layer and the cell active pattern, while improving hydrogen supply distribution and preventing reliability degradation in the upper wiring structure, data storage pattern, and peripheral gate structure due to hydrogen diffusion paths.

[0006] According to one aspect, a semiconductor device includes a substrate comprising a cell active pattern, a cell gate structure located on the cell active pattern, and a bit line structure connected to the cell active pattern, wherein the cell gate structure includes a cell gate insulating layer located on the cell active pattern, a cell gate conductive layer located on the cell gate insulating layer, and a cell gate capping layer located on the cell gate conductive layer and comprising an insulating material and hydrogen.

[0007] According to another aspect, a semiconductor device includes: a substrate; bit lines located on the substrate, spaced apart in a first direction and extending in a second direction different from the first direction; a first word line and a second word line located on the bit lines, the first word line and the second word line extending in the first direction and alternately spaced apart in the second direction; a first active pattern and a second active pattern located on the bit lines, the first active pattern and the second active pattern being spaced apart in the first direction and located between the first word line and the second word line, and the first active pattern being positioned closer to the first word line and the second active pattern being positioned closer to the second word line; a back gate electrode located on the bit lines, extending in the first direction and located between the first active pattern and the second active pattern; a gate hydrogen diffusion pattern located on the first word line and the second word line; and a back gate hydrogen diffusion pattern located on the back gate electrode, wherein the gate hydrogen diffusion pattern and the back gate hydrogen diffusion pattern comprise an insulating material and hydrogen.

[0008] According to another aspect, a semiconductor device includes: a substrate; bit lines located on the substrate, spaced apart in a first direction and extending in a second direction different from the first direction; a first word line and a second word line located on the bit lines, the first word line and the second word line extending in the first direction and alternately spaced apart in the second direction; a first active pattern and a second active pattern located on the bit lines, the first active pattern and the second active pattern being spaced apart in the first direction and located between the first word line and the second word line, the first active pattern being positioned closer to the first word line and the second active pattern being positioned closer to the second word line; a gate hydrogen diffusion pattern located on the first word line and the second word line; and a hydrogen diffusion barrier layer located on the gate hydrogen diffusion pattern, wherein the hydrogen diffusion barrier layer has a lower hydrogen diffusivity than the gate hydrogen diffusion pattern.

[0009] According to an embodiment of the present invention, a semiconductor device is provided that utilizes hydrogen to passivate dangling bonds present at the interface between the cell gate insulating layer and the cell active pattern, while improving hydrogen supply distribution and preventing reliability degradation in wiring structures, data storage patterns, and peripheral gate structures due to hydrogen diffusion paths. Attached Figure Description

[0010] Figure 1 It is a plan view of a semiconductor device according to some implementation methods.

[0011] Figure 2 yes Figure 1 A magnified view of region E1 in the middle.

[0012] Figure 3 It is along Figure 2 The cross-sectional view taken by lines B-B' and C-C'.

[0013] Figure 4 It is along Figure 2A cross-sectional view taken from line A-A'.

[0014] Figure 5 It is along Figure 2 The cross-sectional view taken by line B-B'.

[0015] Figure 6 It is along Figure 2 The cross-sectional view taken from line C-C'.

[0016] Figure 7 Semiconductor devices according to some implementation methods and Figure 4 The corresponding cross-sectional view.

[0017] Figure 8 It is a plan view of a semiconductor device according to some implementation methods.

[0018] Figure 9 It is along Figure 8 The cross-sectional view taken by lines A-A' and B-B'.

[0019] Figure 10 It is along Figure 8 The cross-sectional view taken from line C-C'.

[0020] Figure 11 yes Figure 10 A magnified view of region P1.

[0021] Figure 12 Semiconductor devices according to some implementation methods and Figure 11 The corresponding cross-sectional view.

[0022] Figure 13 Semiconductor devices according to some implementation methods and Figure 11 The corresponding cross-sectional view.

[0023] Figure 14 Semiconductor devices according to some implementation methods and Figure 11 The corresponding cross-sectional view. Detailed Implementation

[0024] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0025] The accompanying drawings and description should be considered illustrative rather than restrictive. Throughout the description, the same reference numerals denote the same elements.

[0026] For better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are indicated randomly, and this disclosure is not necessarily limited to those shown. In the drawings, the thicknesses of layers, regions, etc., are exaggerated for clarity. Furthermore, in the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0027] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. The terms "on" or "above" indicate that it is disposed on or below an object portion, and do not necessarily indicate that it is disposed on the upper side of the object portion based on the direction of gravity.

[0028] Furthermore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “containing” will be understood to imply inclusion of the stated element but not exclusion of any other element.

[0029] Furthermore, in this specification, the expression "on a plane" means the target portion as viewed from above, and the expression "on a cross section" means the cross section formed by vertically cutting the object portion as viewed from the side.

[0030] Furthermore, throughout the specification, two directions parallel to the upper surface of the substrate and intersecting each other are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as the third direction D3. For example, the first direction D1 and the second direction D2 may be orthogonal to each other.

[0031] Figure 1 It is a plan view of a semiconductor device according to some implementation methods. Figure 2 yes Figure 1 A magnified view of region E1 in the middle. Figure 3 It is along Figure 2 The cross-sectional views taken along lines B-B' and C-C' show the memory transistor area, data storage pattern area, and wiring area. Figure 4 It is along Figure 2 A cross-sectional view taken from line A-A', in which the memory transistor region is magnified. Figure 5 It is along Figure 2 A cross-sectional view taken by line B-B', in which the memory transistor region is magnified. Figure 6 It is along Figure 2 The cross-sectional view taken from line C-C' shows the enlarged peripheral gate structure.

[0032] Reference Figures 1 to 6The semiconductor device may include a memory transistor region (MTR) on a substrate 1100, a data storage pattern region (DSR) on the MTR, and a wiring region (LLR) on the DSR. The MTR may be a region including multiple memory transistors and / or circuitry. The DSR may be a region including multiple data storage patterns. The LLR may be a region including multiple wirings connected to the multiple transistors and / or circuitry.

[0033] For example, when the semiconductor device is a memory semiconductor device, the substrate 1100 of the memory transistor region MTR may include a cell region CAR containing a cell array and a peripheral region PAR containing peripheral circuitry for driving the cell array. For example, the peripheral region PAR may surround the cell region CAR.

[0034] The cell area (CAR) can be a region in which memory cells are arranged. The peripheral area (PAR) can be a region in which word line drivers, sense amplifiers, row decoders, column decoders, and control circuitry are located. On the other hand, when the semiconductor device is not a memory device, the memory transistor region (MTR) may not include the cell array of the cell area (CAR).

[0035] The semiconductor device may include a substrate 1100. For example, substrate 1100 may be a semiconductor substrate. For example, substrate 1100 may include silicon, germanium, silicon-germanium, or a III-V compound semiconductor substrate (such as GaP or GaAs). In some embodiments, substrate 1100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Substrate 1100 may have a plate shape extending in a plane along a first direction D1 and a second direction D2.

[0036] The substrate 1100 may include a cell region CAR and a peripheral region PAR surrounding the cell region CAR. The substrate 1100 may also include a dummy region DAR located between the cell region CAR and the peripheral region PAR. The cell region CAR, the dummy region DAR, and the peripheral region PAR may be separated by a first direction D1 and a second direction D2 plane.

[0037] The cell region CAR of substrate 1100 may include a cell active pattern CAP. The upper part of the cell region CAR of substrate 1100 protruding in the third direction D3 may be defined as the cell active pattern CAP. The cell active patterns CAP may be spaced apart from each other in the first direction D1.

[0038] Device isolation layer 1020 may be located within the cell region CAR of substrate 1100. Device isolation layer 1020 may define a cell active pattern CAP. Each of the cell active patterns CAP may be surrounded by device isolation layer 1020. Device isolation layer 1020 may include an insulating material. For example, device isolation layer 1020 may include silicon oxide, silicon nitride, or a combination thereof.

[0039] The insulating structure 1010 may be located within the substrate 1100. The insulating structure 1010 may be located between the cell region (CAR) and the peripheral region (PAR). The insulating structure 1010 may also be located between the dummy region (DAR) and the peripheral region (PAR). The insulating structure 1010 may include a first insulating layer 1011, a second insulating layer 1012 located on the first insulating layer 1011, and a third insulating layer 1013 located on the second insulating layer 1012. For example, the first insulating layer 1011 may include silicon oxide, the second insulating layer 1012 may include silicon nitride, and the third insulating layer 1013 may include silicon oxide.

[0040] Cell gate structure 1150 may be located on the cell region CAR and dummy region DAR of substrate 1100. Cell gate structure 1150 may extend in a first direction D1. Cell gate structures 1150 may be spaced apart in a second direction D2. Cell gate structure 1150 may be located on device isolation layer 1020, insulating structure 1010, and cell active pattern CAP. Cell gate structure 1150 may be a buried gate structure embedded within device isolation layer 1020, insulating structure 1010, and cell active pattern CAP. Memory transistors may be defined by cell gate structure 1150 and cell active pattern CAP.

[0041] The cell gate structure 1150 may include a cell gate insulating layer 1151 located on the cell active pattern CAP, a cell gate conductive layer 1152 located on the cell gate insulating layer 1151, and a cell gate capping layer 1153 located on the cell gate conductive layer 1152.

[0042] The cell gate insulating layer 1151 may include an insulating material. For example, the cell gate insulating layer 1151 may include silicon oxide.

[0043] The unit gate conductive layer 1152 may include a conductive material. In some embodiments, the unit gate structure 1150 may further include a second conductive layer 1155 located on the unit gate conductive layer 1152. The second conductive layer 1155 may be located between the unit gate conductive layer 1152 and the unit gate capping layer 1153. For example, the unit gate conductive layer 1152 may include a metal, and the second conductive layer 1155 may include polysilicon.

[0044] The cell gate capping layer 1153 may include an insulating material and hydrogen. In other words, the cell gate capping layer 1153 may be a hydrogen-rich (H-rich) insulating layer. The cell gate capping layer 1153 may be annealed to provide hydrogen to the boundary between the surrounding structure (e.g., the cell gate insulating layer 1151 and the cell active pattern CAP), and may utilize hydrogen to passivate dangling bonds. After providing hydrogen to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP, the cell gate capping layer 1153 may still include hydrogen.

[0045] For example, the annealing process for diffusing hydrogen can be performed for 15 to 60 minutes or 30 to 45 minutes at a pressure of 10 to 40 Torr or 20 to 30 Torr, and at a temperature of 400°C to 475°C or 375°C to 400°C. The annealing process can be performed at a temperature below the temperature range that causes the material to crystallize in the active pattern CAP of the unit (e.g., below 600°C).

[0046] The insulating material of the cell gate capping layer 1153 may include silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), or a combination thereof. For example, by depositing SiH4 and O2 as raw materials, a hydrogen-rich cell gate capping layer 1153 comprising silicon oxide and hydrogen can be formed. Alternatively, by depositing SiH4 and NH3 as raw materials, a hydrogen-rich cell gate capping layer 1153 comprising silicon nitride and hydrogen can be formed. In this case, deposition can be performed using methods such as atomic pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD). Alternatively, after depositing silicon oxide or silicon nitride, hydrogen plasma can be doped into the silicon oxide or silicon nitride to form the hydrogen-rich cell gate capping layer 1153. For example, the cell gate capping layer 1153 may be a TEOS layer including tetraethyl orthosilicate (TEOS), and the cell gate capping layer 1153 may be an HDP layer including a high-density plasma CVD (HDP CVD) dielectric material.

[0047] The cell gate capping layer 1153 may include hydrogen, deuterium, tritium, or a combination thereof. Hydrogen may be hydrogen atoms or hydrogen molecules. Since deuterium or tritium is heavier than hydrogen, if the cell gate capping layer 1153 includes deuterium or tritium, it can reduce the loss of deuterium or tritium into the air compared to when it includes hydrogen. For example, the cell gate capping layer 1153 may include 90% or more hydrogen relative to the sum of hydrogen, deuterium, and tritium.

[0048] For example, the cell gate capping layer 1153 may include hydrogen in an amount greater than 0 at% (e.g., 1 at% or more, 2 at% or more, 3 at% or more, or 4 at% or more) based on the total amount of the cell gate capping layer 1153, and may include hydrogen in an amount of 5 at% or less (e.g., 4 at% or less, 3 at% or less, or 2 at% or less), and for example, it may include hydrogen in an amount greater than 0 at% and less than or equal to 5 at%.

[0049] Furthermore, the ratio of the hydrogen peak intensity of the cell gate capping layer 1153 measured by secondary ion mass spectrometry (SIMS) to the hydrogen peak intensity of the cell active pattern CAP of the adjacent cell gate structure 1150 measured by secondary ion mass spectrometry (SIMS) can be 10 or greater: 1, for example, 100 or greater: 1 or 1000 or greater: 1.

[0050] For example, when the cell gate insulating layer 1151 includes silicon dioxide (SiO2) and the cell active pattern CAP includes silicon (Si), hydrogen passivation can be performed on the dangling bonds present at the interface between silicon dioxide (SiO2) and silicon (Si).

[0051] Therefore, as described later, the upper wiring structure 1370 may include an upper wiring hydrogen diffusion layer 1372, which includes an insulating material covering the upper wiring layer 1371 and hydrogen. After the upper wiring hydrogen diffusion layer 1372 is formed and annealed, the hydrogen in the upper wiring hydrogen diffusion layer 1372 can be supplied to the cell gate structure 1150 through the data storage pattern DSP in the cell region CAR, and can diffuse to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP. Furthermore, the hydrogen in the upper wiring hydrogen diffusion layer 1372 can be supplied to the end of the cell gate structure 1150 through the second lower contact 1213, the conductive structure 1191, and the peripheral gate structure 1160 in the peripheral region PAR, and can diffuse to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP.

[0052] However, hydrogen diffusion from the upper wiring hydrogen diffusion layer 1372 can reduce the reliability of the upper wiring structure 1370, the data storage pattern DSP, and the peripheral gate structure 1160 due to hydrogen diffusion paths. For example, in the upper wiring structure 1370, hydrogen embrittlement of the copper (Cu) wiring may be degraded due to hydrogen diffusion, and moisture absorption vulnerability may occur due to the deterioration of interfacial adhesion. In the peripheral gate structure 1160, negative bias temperature instability (NBTI) may be degraded due to residual hydrogen from hydrogen diffusion, and in the data storage pattern DSP, reliability may decrease with increasing hydrogen ion (H) concentration due to hydrogen diffusion. + The oxygen vacancies in the dielectric layer 1253 are reduced by binding.

[0053] According to some embodiments, the cell gate structure 1150 includes a cell gate capping layer 1153, which includes an insulating material on the cell gate conductive layer 1152 and hydrogen. Therefore, hydrogen can diffuse from the cell gate capping layer 1153 to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP. This direct diffusion of hydrogen from the cell gate capping layer 1153 to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP is advantageous in terms of hydrogen supply diffusion and avoids the reliability degradation of the upper wiring structure 1370, the data storage pattern DSP, and the peripheral gate structure 1160 caused by the hydrogen diffusion path.

[0054] The insulating pattern 1121 may be located on the cell gate capping layer 1153, the device isolation layer 1020, and the insulating structure 1010 of the cell gate structure 1150. The insulating pattern 1121 may include an insulating material. In some embodiments, the insulating pattern 1121 may include multiple insulating layers.

[0055] The substrate 1100 may include a peripheral active pattern located within the peripheral region PAR. The upper portion of the peripheral region PAR of the substrate 1100 protruding along the third direction D3 may be defined as the peripheral active pattern.

[0056] The peripheral gate structure 1160 may be located on the peripheral region PAR of the substrate 1100. The peripheral gate structure 1160 may be located on the peripheral active pattern. In some embodiments, the peripheral gate structure 1160 may be the gate of the peripheral transistor constituting a sub-word line driver.

[0057] The peripheral gate structure 1160 may include a peripheral gate insulating layer 1161, a first peripheral gate conductive layer 1163, a second peripheral gate conductive layer 1162, a peripheral gate capping layer 1164, and a gate sidewall capping structure 1167. The second peripheral gate conductive layer 1162 may be located on the peripheral gate insulating layer 1161, the first peripheral gate conductive layer 1163 may be located on the second peripheral gate conductive layer 1162, and the peripheral gate capping layer 1164 may be located on the first peripheral gate conductive layer 1163.

[0058] The peripheral gate insulating layer 1161 may include an insulating material. In some embodiments, the peripheral gate insulating layer 1161 may include multiple insulating layers. For example, the peripheral gate insulating layer 1161 may include silicon dioxide (SiO2) or hafnium oxide (HfO). The second peripheral gate conductive layer 1162 may include a conductive material. For example, the second peripheral gate conductive layer 1162 may include titanium nitride or polysilicon. The first peripheral gate conductive layer 1163 may include a conductive material. For example, the first peripheral gate conductive layer 1163 may include tungsten (W). The peripheral gate capping layer 1164 may include an insulating material. For example, the peripheral gate capping layer 1164 may include silicon nitride.

[0059] The gate sidewall capping structure 1167 may include an insulating material. For example, the gate sidewall capping structure 1167 may include silicon nitride. For example, the gate sidewall capping structure 1167 may not include silicon oxide. The gate sidewall capping structure 1167 may include multiple insulating layers.

[0060] The dummy line structure 1140 may be located in the dummy area DAR. The dummy line structure 1140 may extend in the second direction D2. The dummy line structure 1140 may be located on the insulating pattern 1121. The dummy line structure 1140 may include a first dummy line conductive layer 1143, a second dummy line conductive layer 1142, a dummy line capping layer 1144, and a dummy line sidewall capping structure 1147. The second dummy line conductive layer 1142 may be located on the insulating pattern 1121, the first dummy line conductive layer 1143 may be located on the second dummy line conductive layer 1142, and the dummy line capping layer 1144 may be located on the first dummy line conductive layer 1143.

[0061] The dummy line sidewall capping structure 1147 can contact the sidewall of the dummy line capping layer 1144. The dummy line sidewall capping structure 1147 can contact the upper surface of the insulating pattern 1121. Through the dummy line sidewall capping structure 1147, the sidewall of the dummy line capping layer 1144 can be separated from the peripheral etch stop layer 1310.

[0062] The peripheral etch stop layer 1310 may be located on the insulating pattern 1121, the dummy line structure 1140, and the peripheral gate structure 1160. The peripheral etch stop layer 1310 may extend in the first direction D1. The peripheral etch stop layer 1310 may include an insulating material. For example, the peripheral etch stop layer 1310 may include a nitride.

[0063] The peripheral etch stop layer 1310 may cover the dummy line structure 1140 and the peripheral gate structure 1160. The peripheral etch stop layer 1310 may contact the upper surfaces of the peripheral gate capping layer 1164 and the dummy line capping layer 1144. The sidewalls of the peripheral gate insulating layer 1161, the second peripheral gate conductive layer 1162, the first peripheral gate conductive layer 1163, and the peripheral gate capping layer 1164 may be separated from the peripheral etch stop layer 1310 through the gate sidewall capping structure 1167.

[0064] Through the dummy line sidewall capping structure 1147, the sidewalls of the second dummy line conductive layer 1142, the first dummy line conductive layer 1143, and the dummy line capping layer 1144 can be spaced apart from the peripheral etch stop layer 1310.

[0065] The filler insulating layer 1181 may be located on the peripheral etch stop layer 1310. The upper surface of the filler insulating layer 1181 may be at the same level as the upper surface of the peripheral etch stop layer 1310. The filler insulating layer 1181 may include an insulating material.

[0066] The cover insulating layer 1320 may be located on the fill insulating layer 1181 and the peripheral etch stop layer 1310. The cover insulating layer 1320 may extend in the first direction D1. The cover insulating layer 1320 may include an insulating material. For example, the cover insulating layer 1320 may include silicon nitride.

[0067] Conductive structure 1191 may be located on the overlay insulating layer 1320. Conductive structure 1191 may include conductive material. At least one of conductive structures 1191 may include a conductive contact 1191_C electrically connected to the cell gate structure 1150. Furthermore, at least one of conductive structures 1191 may include a conductive contact 1191_C electrically connected to a peripheral active pattern.

[0068] The first separation structure 1260 may be located on the covering insulating layer 1320. The first separation structure 1260 may separate the conductive structure 1191. The first separation structure 1260 may include an insulating material. In some embodiments, the first separation structure 1260 and the subsequent second separation structure 1250 may have a unified structure with no boundary connection.

[0069] Bit line structure 1130 may be located on cell region CAR of substrate 1100. Bit line structure 1130 may extend in a second direction D2. Bit line structures 1130 may be spaced apart in a first direction D1. Bit line structure 1130 may be located on insulating pattern 1121 and cell active pattern CAP. Bit line structure 1130 may be electrically connected to cell active pattern CAP.

[0070] The bitline structure 1130 may include a bitline contact 1131, a first bitline conductive layer 1133, a second bitline conductive layer 1132, a bitline insulating layer 1134, a cell etch stop layer 1135, a bitline capping layer 1136, and a bitline spacer 1137. The bitline contact 1131 and the second bitline conductive layer 1132 may be arranged alternately in a first direction D1. The bitline contact 1131 may be located on the cell active pattern CAP. The bitline contact 1131 may extend through the insulating pattern 1121.

[0071] The second bit line conductive layer 1132 may be located on the insulating pattern 1121. The first bit line conductive layer 1133 may be located on the bit line contact 1131 or the second bit line conductive layer 1132. The bit line insulating layer 1134 may be located on the first bit line conductive layer 1133. The unit etch stop layer 1135 may be located on the bit line insulating layer 1134. The bit line capping layer 1136 may be located on the unit etch stop layer 1135.

[0072] The first bit line conductive layer 1133, the second bit line conductive layer 1132, and the bit line insulating layer 1134 of the bit line structure 1130 may be similar in material and thickness to the first peripheral gate conductive layer 1163, the second peripheral gate conductive layer 1162, and the peripheral gate capping layer 1164 of the peripheral gate structure 1160. The cell etch stop layer 1135 may comprise the same material as the peripheral etch stop layer 1310. For example, the cell etch stop layer 1135 may comprise silicon nitride. In some embodiments, the thickness of the cell etch stop layer 1135 may be the same as the thickness of the peripheral etch stop layer 1310. As an example, the thickness of the cell etch stop layer 1135 in the third direction D3 may be the same as the thickness of the portion of the peripheral etch stop layer 1310 that overlaps with the peripheral gate structure 1160 in the third direction D3.

[0073] Bit line spacer 1137 may cover the sidewalls of bit line contact 1131, the second bit line conductive layer 1132, the first bit line conductive layer 1133, the bit line insulating layer 1134, the unit etch stop layer 1135, and the bit line capping layer 1136. Bit line spacer 1137 may include an insulating material. In some embodiments, bit line spacer 1137 may include multiple insulating layers.

[0074] Node contacts NC may be located on the cell active pattern CAP. Node contacts NC may be located between adjacent bit line structures 1130. Node contacts NC may be located on the sidewalls of bit line structures 1130. Node contacts NC may include a conductive material. For example, node contacts NC may include polysilicon.

[0075] The landing pad LP may be located on the node contact NC. The landing pad LP may include a conductive material. For example, the landing pad LP may include metal. In some embodiments, a metal silicide layer may be located between the node contact NC and the landing pad LP. In some embodiments, a barrier layer may be located between the node contact NC and the landing pad LP.

[0076] An insulating barrier 1240 may be located on the cell gate capping layer 1153. The insulating barrier 1240 may be located between adjacent bit line structures 1130 in the first direction D1. The insulating barrier 1240 may include an insulating material.

[0077] The second separation structure 1250 may be located on the insulating fence 1240. The second separation structure 1250 may separate the landing pads LP from each other. The second separation structure 1250 may surround the landing pads LP. The second separation structure 1250 may include insulating material.

[0078] The data storage pattern DSP may be located on the landing pad LP. The data storage pattern DSP is electrically connected to the cell active pattern CAP via the landing pad LP and the node contact NC. In some embodiments, each of the data storage pattern DSPs may be a capacitor including a lower electrode 1251, a dielectric layer 1253, and an upper electrode 1255. In this case, the semiconductor device including the data storage pattern DSP may be dynamic random access memory (DRAM).

[0079] The lower electrode 1251 of the data storage pattern DSP may, for example, have a cylindrical or closed-bottom cylindrical shape. The lower electrode 1251 may, for example, include doped polysilicon, metal, metal nitride, metal silicide, polysilicide, or a combination thereof.

[0080] The dielectric layer 1253 may conformally cover the lower electrode 1251. The dielectric layer 1253 may, for example, include oxides, nitrides, silicides, oxynitrides, or silicate oxynitrides containing hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), or combinations thereof.

[0081] The upper electrode 1255 may cover the dielectric layer 1253. For example, if the lower electrode 1251 has a closed-bottom cylindrical shape, the upper electrode 1255 may fill the interior of the cylinder. The upper electrode 1255 may, for example, comprise silicon germanium doped with impurities.

[0082] In some embodiments, each of the data storage pattern DSPs may include a magnetic tunnel junction pattern. In this case, the semiconductor device including the data storage pattern DSP may be a magnetic random access memory (MRAM). In some embodiments, the data storage pattern DSP may include a phase change material or a variable resistance material. In this example, the semiconductor device including the data storage pattern DSP may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). In some embodiments, each of the data storage pattern DSPs may include various structures and / or materials for data storage.

[0083] The lower interlayer insulating layer 1210 may cover the peripheral gate structure 1160 on the peripheral region PAR and the data storage pattern DSP on the cell region CAR. For example, the lower interlayer insulating layer 1210 may include borosilicate glass (BPSG), TOSZ, undoped silicate glass (USG), spin-coated glass (SOG), flowable oxide (FOX), tetraethyl orthosilicate (TEOS), high-density plasma chemical vapor deposition (HDP CVD) dielectric material, or silsesquioxane (HSQ).

[0084] A wiring region LLR may include an interlayer insulating layer, a low-dielectric-constant layer, and wiring layers formed therein. For example, a wiring region LLR may include sequentially laminated first to third low-dielectric-constant layers LK1, LK2, and LK3, an upper interlayer insulating layer 1350 on the third low-dielectric-constant layer LK3, and an upper wiring structure 1370 on the upper interlayer insulating layer 1350. The first low-dielectric-constant layer LK1, the second low-dielectric-constant layer LK2, and the third low-dielectric-constant layer LK3 may each have a first lower wiring layer 1331, a second lower wiring layer 1333, and a third lower wiring layer 1335 respectively located therein. The number of low-dielectric-constant layers and lower wiring layers is not limited and can be varied.

[0085] For example, a low dielectric constant layer refers to an insulating layer having a dielectric constant less than 4.4. For example, the first to third low dielectric constant layers LK1, LK2, and LK3 may comprise SiCOH. The first to third lower wiring layers 1331, 1333, and 1335 may comprise copper (Cu) or tungsten (W). The first to third low dielectric constant layers LK1, LK2, and LK3 may be formed from the same material, but are not limited thereto, and some of the first to third low dielectric constant layers LK1, LK2, and LK3 may be formed from materials with different dielectric constants or different compositions.

[0086] The second lower routing layer 1333 and the third lower routing layer 1335 may include vias VI disposed on the lower surface of a linear structure extending in one direction. The upper width of the first to third lower routing layers 1331, 1333, 1335 may be greater than the lower width, but this disclosure is not limited to this example.

[0087] A portion of the first lower wiring layer 1331 on the cell region CAR can be connected to the upper part of the data storage pattern DSP via the first lower contact 1211, for example, to the upper electrode 1255 of a capacitor. A portion of the first lower wiring layer 1331 on the peripheral region PAR can be connected to a conductive contact 1191_C via a second lower contact 1213, which is electrically connected to the peripheral active pattern. The lower surface of the second lower contact 1213 may be located at a lower level than the lower surface of the first lower contact 1211. The upper surfaces of the first lower contact 1211 and the second lower contact 1213 may be located at substantially the same level. The first lower contact 1211 and the second lower contact 1213 may comprise tungsten (W), titanium (Ti), tantalum (Ta), or nitrides of these materials.

[0088] The lower interface layer LE may be located between the first low dielectric constant layer LK1 and the lower interlayer insulating layer 1210. The upper interface layer UE may be located between the third low dielectric constant layer LK3 and the upper interlayer insulating layer 1350. For example, the lower interface layer LE may be an interface layer contacting the bottom layer among the first to third low dielectric constant layers LK1, LK2, and LK3, and the upper interface layer UE may be an interface layer contacting the upper layer among the first to third low dielectric constant layers LK1, LK2, and LK3. The first intermediate interface layer ME1 and the second intermediate interface layer ME2 may be located between the first to third low dielectric constant layers LK1, LK2, and LK3. For example, the first intermediate interface layer ME1 may be located between the first low dielectric constant layer LK1 and the second low dielectric constant layer LK2, and the second intermediate interface layer ME2 may be located between the second low dielectric constant layer LK2 and the third low dielectric constant layer LK3. Some of the lower interface layer LE, upper interface layer UE, and first intermediate interface layer ME1 and second intermediate interface layer ME2 may include multiple insulating layers with different properties. For example, the upper interface layer UE may include multiple interface layers. Conversely, the lower interface layer LE, first intermediate interface layer ME1, and second intermediate interface layer ME2 may be a single layer. Each of the lower interface layer LE, upper interface layer UE, first intermediate interface layer ME1, and second intermediate interface layer ME2 may, for example, include silicon nitride (SiN) or silicon carbonitride (SiCN). For example, the upper interface layer UE may include silicon nitride (SiN), and the lower interface layer LE, first intermediate interface layer ME1, and second intermediate interface layer ME2 may include silicon carbonitride (SiCN).

[0089] The upper interlayer insulating layer 1350 may be located on the third low dielectric constant layer LK3. The upper interlayer insulating layer 1350 may be an insulating layer having a higher dielectric constant than the first to third low dielectric constant layers LK1, LK2, and LK3. For example, each of the upper interlayer insulating layers 1350 may have a dielectric constant of 4.4 or greater. The upper interlayer insulating layer 1350 may include borophosphosilicate glass (BPSG), Tonen silazane (TOSZ), undoped silicate glass (USG), spin-coated glass (SOG), flowable oxide (FOX), tetraethyl orthosilicate (TEOS), high-density plasma CVD (HDP CVD) dielectric material, or hydrogen silsesquioxane (HSQ).

[0090] The upper contact 1351 may be located in the upper interlayer insulating layer 1350. The upper contact 1351 may extend through the upper interlayer insulating layer 1350 and the upper interface layer UE, and may contact the third lower wiring layer 1335. The upper contact 1351 may be electrically connected to the first to the third lower wiring layers 1331, 1333, 1335, and the first lower contact 1211 and the second lower contact 1213. For example, the upper contact 1351 may include tungsten (W), titanium (Ti), tantalum (Ta), or nitrides thereof.

[0091] At least a portion of the first lower contact 1211 and the second lower contact 1213, the first lower wiring layer to the third lower wiring layer 1331, 1333, 1335, or the upper contact 1351 may include a barrier layer Ba. The barrier layer Ba may be located on the lower surface and sidewalls of at least a portion of the first lower contact 1211 and the second lower contact 1213, the first lower wiring layer to the third lower wiring layer 1331, 1333, 1335, or the upper contact 1351. The barrier layer Ba may include a conductive metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN).

[0092] The upper wiring structure 1370 may include an upper wiring layer 1371, an upper wiring hydrogen diffusion layer 1372, and an upper wiring hydrogen diffusion barrier layer 1373. The upper wiring structure 1370 may be located in the cell region CAR and / or the peripheral region PAR. Therefore, the upper wiring layer 1371, the upper wiring hydrogen diffusion layer 1372, and the upper wiring hydrogen diffusion barrier layer 1373 may also be located in the cell region CAR and / or the peripheral region PAR.

[0093] The upper wiring layer 1371 may be located within the upper wiring hydrogen diffusion barrier layer 1373. The upper wiring layer 1371 may contact the upper surface of the upper contact 1351. The upper wiring layer 1371 may be electrically connected to the upper contact 1351, the first to third lower wiring layers 1331, 1333, 1335, and the first lower contact 1211 and the second lower contact 1213. For example, the upper width of the upper wiring layer 1371 may be smaller than the lower width.

[0094] For example, the upper wiring layer 1371 may include tungsten (W), titanium (Ti), tantalum (Ta), or nitrides thereof. In some embodiments, the upper contact 1351 and the upper wiring layer 1371 may include a conductive material different from the first to third lower wiring layers 1331, 1333, 1335. For example, the first to third lower wiring layers 1331, 1333, 1335 may include a first metal, and the upper contact 1351 and the upper wiring layer 1371 may include a second metal different from the first metal. For example, the upper contact 1351 and the upper wiring layer 1371 may include aluminum (Al).

[0095] The upper wiring hydrogen diffusion layer 1372 may be located on the upper wiring layer 1371. The upper wiring hydrogen diffusion layer 1372 may conformally cover the upper surface of the upper wiring layer 1371. The upper wiring hydrogen diffusion layer 1372 may be located within the upper wiring hydrogen diffusion barrier layer 1373.

[0096] The upper wiring hydrogen diffusion layer 1372 may include an insulating material and hydrogen. In other words, the upper wiring hydrogen diffusion layer 1372 may be a hydrogen-rich (H-rich) insulating layer. Through annealing, hydrogen in the upper wiring hydrogen diffusion layer 1372 can be supplied to the cell gate structure 1150 through the data storage pattern DSP in the cell region CAR, and can diffuse to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP. Furthermore, hydrogen in the upper wiring hydrogen diffusion layer 1372 can be supplied to the end of the cell gate structure 1150 through the second lower contact 1213, conductive structure 1191, and peripheral gate structure 1160 in the peripheral region PAR, and can diffuse to the boundary between the cell gate insulating layer 1151 and the cell active pattern CAP. For example, if the cell gate insulating layer 1151 comprises silicon dioxide (SiO2) and the cell active pattern CAP comprises silicon (Si), hydrogen can be used to passivate the dangling bonds present at the interface between silicon dioxide (SiO2) and silicon (Si). Even after hydrogen diffusion is achieved through annealing, the upper wiring hydrogen diffusion layer 1372 can still include hydrogen.

[0097] For example, the annealing process for diffused hydrogen can be performed at a pressure of 10 to 40 Torr (e.g., 20 to 30 Torr) and a temperature of 400 to 475°C or 375 to 400°C for 15 to 60 minutes (e.g., 30 to 45 minutes). The annealing process can be performed at temperatures below the temperature range for material crystallization of the induced active pattern CAP (e.g., below 600°C).

[0098] The insulating material of the upper wiring hydrogen diffusion layer 1372 may include silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), or combinations thereof. For example, when SiH4 and O2 are used as raw materials for deposition, a hydrogen-rich upper wiring hydrogen diffusion layer 1372 comprising silicon oxide and hydrogen can be formed. Furthermore, if SiH4 and NH3 are used for deposition, a hydrogen-rich upper wiring hydrogen diffusion layer 1372 comprising silicon nitride and hydrogen can be formed. In this case, the deposition can be a method such as atomic pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD). Alternatively, after depositing silicon oxide or silicon nitride, plasma-doped silicon oxide or silicon nitride can be used to form the hydrogen-rich upper wiring hydrogen diffusion layer 1372.

[0099] For example, the upper wiring hydrogen diffusion layer 1372 may be a TEOS layer including tetraethyl orthosilicate (TEOS), and the upper wiring hydrogen diffusion layer 1372 may be an HDP layer including a high-density plasma CVD (HDP CVD) dielectric material.

[0100] The upper wiring hydrogen diffusion layer 1372 may include hydrogen, deuterium, tritium, or a combination thereof. Hydrogen may be atomic hydrogen or molecular hydrogen. Since deuterium or tritium is heavier than hydrogen, if the upper wiring hydrogen diffusion layer 1372 includes deuterium or tritium, the loss of deuterium or tritium to the air can be reduced compared to including only hydrogen. For example, the upper wiring hydrogen diffusion layer 1372 may include 90% or more hydrogen relative to the sum of hydrogen, deuterium, and tritium.

[0101] For example, the upper wiring hydrogen diffusion layer 1372 may include an amount of hydrogen greater than 0 at% (e.g., 1 at% or more, 2 at% or more, 3 at% or more, or 4 at% or more) based on the total amount of the upper wiring hydrogen diffusion layer 1372, which may include an amount of hydrogen of 5 at% or less (e.g., 4 at% or less, 3 at% or less, or 2 at% or less), and for example, it may include an amount of hydrogen greater than 0 at% and less than or equal to 5 at%.

[0102] At this point, the upper wiring hydrogen diffusion layer 1372 may have a lower hydrogen concentration than the cell gate capping layer 1153. Therefore, the primary source of hydrogen may be the cell gate capping layer 1153, and the upper wiring hydrogen diffusion layer 1372 may be a secondary source of hydrogen. As described above, due to the hydrogen diffusion path, hydrogen diffusion from the upper wiring hydrogen diffusion layer 1372 may lead to a decrease in the reliability of the upper wiring structure 1370, the data storage pattern DSP, and the peripheral gate structure 1160. Therefore, the upper wiring hydrogen diffusion layer 1372 may assist the cell gate capping layer 1153.

[0103] The upper wiring hydrogen diffusion barrier layer 1373 may be located on the upper interlayer insulating layer 1350. The upper wiring hydrogen diffusion barrier layer 1373 may cover the upper wiring layer 1371 and the upper wiring hydrogen diffusion barrier layer 1372.

[0104] For example, the upper wiring hydrogen diffusion barrier layer 1373 may have a lower hydrogen diffusivity than the upper wiring hydrogen diffusion layer 1372. The upper wiring hydrogen diffusion barrier layer 1373 may include silicon nitride with low hydrogen diffusivity.

[0105] Here, hydrogen diffusivity refers to the rate at which hydrogen diffuses, which is higher in silicon, germanium, or silicon oxide than in silicon nitride or dielectric layers (such as Al₂O₃ or ZrO₂), and higher in metals than in silicon, germanium, or silicon oxide. For example, the hydrogen diffusivity of molecular hydrogen (H₂) in silicon can be approximately 2.39E⁻⁷ cm⁻¹ at 400 °C. 2 The hydrogen diffusivity of molecular hydrogen (H2) in silicon oxide at 400 °C can be approximately 2.43E-07 cm / s. 2 The hydrogen diffusivity of molecular hydrogen (H2) in silicon nitride at 400 °C can be approximately 1.73E-25 cm / s. 2 The hydrogen diffusivity of molecular hydrogen (H2) in Al2O3 at 400℃ is approximately 9.32E-27 cm / s. 2 The hydrogen diffusivity of molecular hydrogen (H2) in aluminum (Al) at 400 °C can be approximately 7.03E-06 cm / s. 2 / s, and the hydrogen diffusivity of molecular hydrogen (H2) in tungsten (W) can be approximately 4.84E-06 cm⁻¹ at 400 °C. 2 / s.

[0106] The upper wiring hydrogen diffusion barrier layer 1373 may have a lower hydrogen concentration than the upper wiring hydrogen diffusion layer 1372. In other words, a hydrogen source, such as SiH4 or NH3, may not be used when forming the upper wiring hydrogen diffusion barrier layer 1373. The upper wiring hydrogen diffusion barrier layer 1373 may include 1 at% or less of hydrogen based on the total amount of the upper wiring hydrogen diffusion barrier layer 1373, or may not contain hydrogen. The upper wiring hydrogen diffusion barrier layer 1373 prevents hydrogen from diffusing from the upper wiring hydrogen diffusion layer 1372 upwards, for example, diffusing to the outside of the semiconductor device.

[0107] Passivation layer 1390 may be located on upper wiring structure 1370. For example, passivation layer 1390 may include silicon nitride (SiN). The hydrogen permeability of passivation layer 1390 may be higher than the hydrogen permeability of upper wiring hydrogen diffusion barrier layer 1373.

[0108] In some embodiments, the semiconductor device may also include a dielectric layer located below the upper wiring structure 1370 in the cell region CAR of the substrate 1100.

[0109] The dielectric layer may include a first layer containing aluminum oxide, a second layer containing zirconium, or a composite layer in which the first and second layers are alternately stacked. For example, the dielectric layer may be a ZrO2 / Al2O3 composite layer or a ZrO2 / Al2O3 / ZrO2 composite layer. The ZrO2 / Al2O3 composite layer, by utilizing the grain size difference between ZrO2 and Al2O3, helps to block the diffusion path of hydrogen. Therefore, such a dielectric layer can prevent hydrogen from diffusing from the cell gate capping layer 1153 to the upper part, for example, to the upper wiring structure 1370.

[0110] For example, the dielectric layer may be located below the upper electrode 1255 of the data storage pattern DSP, and for example, the dielectric layer may be a dielectric layer 1253 located between the lower electrode 1251 and the upper electrode 1255 of the data storage pattern DSP. In other words, the dielectric layer 1253 of the data storage pattern DSP may be a ZrO2 / Al2O3 composite layer or a ZrO2 / Al2O3 / ZrO2 composite layer. However, it is not limited to this example. The dielectric layer may be a first low dielectric constant layer to a third low dielectric constant layer LK1, LK2, LK3 sequentially stacked in the wiring region LLR.

[0111] In the peripheral region PAR of substrate 1100, such a dielectric layer may not be included. Specifically, when the upper wiring structure 1370 includes an upper wiring hydrogen diffusion layer 1372, in other words, when it is intended to diffuse hydrogen from the upper wiring hydrogen diffusion layer 1372 through the second lower contact 1213, the conductive structure 1191, and the peripheral gate structure 1160 to the end of the cell gate structure 1150, the peripheral region PAR of substrate 1100 may not include a dielectric layer. However, even in this case, by including a dielectric layer in the cell region CAR of substrate 1100, during hydrogen diffusion from the upper wiring hydrogen diffusion layer 1372, degradation of the reliability of the first to third lower wiring layers 1331, 1333, 1335 and the data storage pattern DSP in the cell region CAR due to the hydrogen diffusion path can be prevented.

[0112] Figure 7 Semiconductor devices according to some implementation methods and Figure 4 The corresponding cross-sectional view. For ease of description, the focus will be on the description and usage. Figures 1 to 6 The different points described.

[0113] Reference Figure 7 The cell gate structure 1150 may further include a cell gate hydrogen diffusion barrier layer 1154 on the cell gate capping layer 1153. The cell gate hydrogen diffusion barrier layer 1154 may cover the cell gate capping layer 1153. The cell gate hydrogen diffusion barrier layer 1154 may be located below the bit line structure 1130 and may be located between the cell gate capping layer 1153 and the bit line structure 1130.

[0114] For example, the gate hydrogen diffusion barrier layer 1154 may have a lower hydrogen diffusivity than the gate capping layer 1153. The gate hydrogen diffusion barrier layer 1154 may include silicon nitride with a low hydrogen diffusivity. The gate hydrogen diffusion barrier layer 1154 may have a lower hydrogen concentration than the gate capping layer 1153. In other words, a hydrogen source such as SiH4 or NH3 may not be used when forming the gate hydrogen diffusion barrier layer 1154. The gate hydrogen diffusion barrier layer 1154 may include 1 at% or less of hydrogen based on the total amount of the gate hydrogen diffusion barrier layer 1154, or may not contain hydrogen at all. The gate hydrogen diffusion barrier layer 1154 is capable of preventing hydrogen from diffusing upwards from the gate capping layer 1153, such as into the data storage pattern DSP or the upper wiring structure 1170.

[0115] Figure 8 It is a plan view of a semiconductor device according to some implementation methods. Figure 9 It is along Figure 8 The cross-sectional view taken by lines A-A' and B-B'. Figure 10 It is along Figure 8 The cross-sectional view taken from line C-C'. Figure 11 yes Figure 10 A magnified view of region P1.

[0116] A semiconductor device according to some embodiments may include a plurality of memory cells, the plurality of memory cells including vertical channel transistors (VCTs). However, this is illustrative, and the semiconductor device according to some embodiments is not limited thereto, and various changes may be made.

[0117] Reference Figures 8 to 11 A semiconductor device according to some embodiments may include a substrate 2100, a peripheral circuit structure (PSR) on the substrate 2100, a memory transistor region (MTR) on the PSR, a data storage pattern region (DSR) on the MSR, and a wiring region (LLR) on the DSR. The MSR may be a region including multiple memory transistors. The DSR may be a region including multiple data storage patterns. The LLR may be a region including multiple wirings connected to the multiple transistors.

[0118] The substrate 2100 may include a cell region CAR and a peripheral region PAR defined around the cell region CAR. For example, the peripheral region PAR may be positioned adjacent to the cell region CAR and may surround the cell region CAR. However, the arrangement relationship between the cell region CAR and the peripheral region PAR is not limited to this and can be varied.

[0119] In the cell area CAR, multiple memory cell structures, including memory transistors MT and data storage patterns DSP, are placed, and in the peripheral area PAR, multiple contacts and contact wiring connected to the components located in the cell area CAR can be placed.

[0120] The memory cell structure may include a single memory transistor MT and a single data storage pattern DSP. Two distinguishable states can be determined based on the presence or absence of charge stored in the data storage pattern DSP, and the data storage pattern DSP can be used as a storage element.

[0121] The gate electrode of the memory transistor MT can be connected to the first word line WL1 and the second word line WL2, the first source / drain electrode of the memory transistor MT can be connected to a terminal of the data storage pattern DSP, and the second source / drain electrode of the memory transistor MT can be connected to the bit line BL.

[0122] The substrate 2100 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but is not limited thereto, and the materials included in the substrate 2100 may vary.

[0123] In some embodiments, the peripheral circuit structure PSR and the memory cell structure placed on the substrate 2100 can be arranged to overlap in the vertical direction. For example, the peripheral circuit structure PSR and the memory cell structure can be stacked sequentially on the substrate 2100. That is, the memory cell structure can be located on the peripheral circuit structure PSR. However, it is not limited to this, and the stacking relationship between the memory cell structure and the peripheral circuit structure PSR can be changed differently. For example, the memory cell structure can be placed adjacent to the peripheral circuit structure PSR in the horizontal direction. As another example, the memory cell structure can be placed below the peripheral circuit structure PSR and overlap with the peripheral circuit structure PSR in the vertical direction. In the following, for illustration, it is assumed that the structure in which the memory cell structure is located on the peripheral circuit structure PSR is assumed.

[0124] The peripheral circuit structure PSR can be located on the substrate 2100. The peripheral circuit structure PSR can be located between the substrate 2100 and the memory cell structure.

[0125] The peripheral circuit structure PSR can be positioned across the cell region CAR and the peripheral region PAR of the substrate 2100. That is, a portion of the peripheral circuit structure PSR can be located in the cell region CAR of the substrate 2100, and the remainder can be located in the peripheral region PAR.

[0126] In some implementations, the peripheral circuitry structure (PSR) may include a core region and a peripheral region. The core region and the peripheral region may be collectively referred to as the logic region or the peripheral circuitry region.

[0127] The core area may include a core library, and the core library may include core circuitry such as word line drivers, sense amplifiers, row decoders, column decoders, and read / write (R / W) circuitry.

[0128] The peripheral area may include peripheral circuits such as timing registers, address registers, data input registers, data output registers, and data input / output terminals.

[0129] The peripheral circuitry structure (PSR) may include peripheral circuitry (PC) for driving components located within the memory cell structure. For example, the peripheral circuitry (PC) may include core circuitry and / or peripheral circuitry.

[0130] The peripheral circuit structure PSR may include peripheral circuit PC, first peripheral circuit contacts to third peripheral circuit contacts PCT1, PCT2, PCT3, first peripheral circuit wiring PCL1 and second peripheral circuit wiring PCL2, peripheral circuit insulation layer 2212, first bonding insulation layer 2214 and first bonding pad 2221.

[0131] The peripheral circuit PC may be located on the substrate 2100. The peripheral circuit PC may be, for example, a readout transistor, a transfer transistor, or a drive transistor. However, the type of transistor in the peripheral circuit PC may vary depending on the design of the semiconductor device.

[0132] The peripheral circuit insulating layer 2212 may cover the peripheral circuit PC. In other words, the peripheral circuit insulating layer 2212 may cover the side surface and top surface of the peripheral circuit PC. The peripheral circuit insulating layer 2212 may include an insulating material. For example, the peripheral circuit insulating layer 2212 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material, but is not limited thereto.

[0133] The first peripheral circuit contact to the third peripheral circuit contact PCT1, PCT2, PCT3, as well as the first peripheral circuit wiring PCL1 and the second peripheral circuit wiring PCL2, may be located within the peripheral circuit insulation layer 2212.

[0134] The first peripheral circuit wiring PCL1 can be connected to the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring PCL1 can be connected to the source / drain region located on at least one side of the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring PCL1 and the second peripheral circuit wiring PCL2 can be connected via the second peripheral circuit contact PCT2.

[0135] For example, the peripheral circuit insulation layer 2212 has been shown as a single layer, but is not limited thereto, and the peripheral circuit insulation layer 2212 may be formed as a multilayer comprising the same material and / or different materials.

[0136] When the peripheral circuit insulation layer 2212 is made of multiple layers, at least some of the first peripheral circuit contact PCT1, the second peripheral circuit contact PCT2, the third peripheral circuit contact PCT3, the first peripheral circuit wiring PCL1, and the second peripheral circuit wiring PCL2 may be located in the same or different layers.

[0137] The first bonding insulating layer 2214 may be located on the peripheral circuit insulating layer 2212. The first bonding insulating layer 2214 may include an insulating material. For example, the first bonding insulating layer 2214 may include silicon carbide, but is not limited thereto. In another example, the first bonding insulating layer 2214 may also include silicon oxide, silicon oxynitride, silicon carbonitride, or silicon nitride.

[0138] The third peripheral circuit contact PCT3 may be located within the peripheral circuit insulating layer 2212 and the first bonding insulating layer 2214. That is, a portion of the third peripheral circuit contact PCT3 may be located within the peripheral circuit insulating layer 2212, and the remainder may be located within the first bonding insulating layer 2214.

[0139] The first bonding pad 2221 may be located within the first bonding insulating layer 2214. The first bonding insulating layer 2214 may surround the first bonding pad 2221. The first bonding insulating layer 2214 may surround the side and bottom surfaces of the first bonding pad 2221. The upper surface of the first bonding insulating layer 2214 is located at substantially the same level as the upper surface of the first bonding pad 2221, and the first bonding insulating layer 2214 may expose the upper surface of the first bonding pad 2221. The first bonding pad 2221 may be connected to the second peripheral circuit wiring PCL2 via the third peripheral circuit contact PCT3.

[0140] For example, the peripheral circuit structure PSR and memory cell structure can be semiconductor devices bonded using a Cu-to-Cu (C2C) wafer bonding method. Alternatively, the peripheral circuit structure PSR and memory cell structure can be semiconductor devices bonded using a hybrid copper bonding (HCB) method. However, the bonding method for the peripheral circuit structure PSR and memory cell structure is not limited to these methods and can be varied.

[0141] In some implementations, the memory cell structure and the peripheral circuit structure PSR can be connected via a single through-hole using a direct bonding method. For example, the memory cell structure and the peripheral circuit structure PSR can be connected to a single through-hole extending from the peripheral circuit structure PSR to the memory cell structure.

[0142] For example, the memory cell structure may include a second bonding insulating layer 2216 that contacts a first bonding insulating layer 2214 of a peripheral circuit structure PSR. The second bonding insulating layer 2216 may include the same material as the first bonding insulating layer 2214 located in the peripheral circuit structure PSR and may be located on the first bonding insulating layer 2214.

[0143] The second bonding pad 2222 may be located within the second bonding insulating layer 2216 in the memory cell structure. The second bonding insulating layer 2216 may surround the second bonding pad 2222. The second bonding insulating layer 2216 may surround the side surface and top surface of the second bonding pad 2222. The bottom of the second bonding insulating layer 2216 is located at substantially the same level as the bottom of the second bonding pad 2222, and the second bonding insulating layer 2216 may expose the bottom of a plurality of second bonding pads 2222.

[0144] The second bonding pad 2222 located within the second bonding insulating layer 2216 can directly contact the first bonding pad 2221 located within the first bonding insulating layer 2214, thereby forming a metal bonding. The upper surface of the first bonding pad 2221 and the lower surface of the second bonding pad 2222 can contact each other. The first bonding pad 2221 and the second bonding pad 2222 are located at the boundary region between the peripheral circuit structure PSR and the memory cell structure, and can contact each other.

[0145] Furthermore, the first bonding insulating layer 2214 located in the peripheral circuit structure PSR and the second bonding insulating layer 2216 located in the memory cell structure can contact each other to form a bonding insulating layer.

[0146] Therefore, one surface of the memory cell structure and one surface of the peripheral circuit structure PSR can be bonded. In other words, the first bonding pad 2221 and the first bonding insulating layer 2214 located in the peripheral circuit structure PSR constitute one surface or bonding surface of the peripheral circuit structure PSR, and the second bonding pad 2222 and the second bonding insulating layer 2216 located in the memory cell structure can constitute one surface or bonding surface of the memory cell structure.

[0147] The first bonding pad 2221 of the peripheral circuit structure PSR and the second bonding pad 2222 of the memory cell structure can be coupled together to provide an electrical connection path between the peripheral circuit structure PSR and the memory cell structure. For example, cell connection wiring 2232 connected to components included in the memory cell structure can be connected via the first bonding pad 2221 and the second bonding pad 2222 to peripheral circuit PC and / or first peripheral circuit wiring PCL1 and second peripheral circuit wiring PCL2 included in the peripheral circuit structure PSR.

[0148] The memory cell structure may include cell connection wiring contacts 2231 and cell connection wiring 2232, both located within a second bonding insulating layer 2216. Cell connection wiring 2232 connects to components located at the memory cell structure, and cell connection wiring contacts 2231 may connect a second bonding pad 2222 to the cell connection wiring 2232. For example, cell connection wiring 2232 may connect to a memory cell located at the memory cell structure, the memory cell including a memory transistor MT and a data storage pattern DSP, as well as bit lines BL connected to a first word line WL1, a second word line WL2, and bit lines connected to them.

[0149] The first peripheral circuit contacts to the third peripheral circuit contacts PCT1, PCT2, and PCT3 located in the peripheral circuit structure PSR, the first peripheral circuit wiring PCL1 and the second peripheral circuit wiring PCL2, and the cell connection wiring contacts 2231 and 2232 located in the memory cell structure may each include a conductive material. For example, they may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), or tantalum (Ta), but are not limited thereto.

[0150] The memory cell structure may include a bit line BL, a first word line WL1 and a second word line WL2 disposed on the bit line BL, a first active pattern AP1 and a second active pattern AP2 disposed on the bit line BL and located between the first word line WL1 and the second word line WL2, and a gate hydrogen diffusion pattern 2145 disposed on the first word line WL1 and the second word line WL2.

[0151] The bit lines BL may be parallel to each other and extend in a second direction D2 that intersects a first direction D1 parallel to the upper surface of the substrate 2100. The bit lines BL may be spaced apart from each other on the substrate 2100 along the first direction D1.

[0152] Bit line BL may include a polysilicon layer 2161, a first metal layer 2163, a second metal layer 2165, and a bit line capping layer 2167, which are stacked sequentially.

[0153] The polysilicon layer 2161 may include doped polysilicon, and the first metal layer 2163 and the second metal layer 2165 may include conductive materials. For example, the first metal layer 2163 may include a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and the second metal layer 2165 may include a metal (e.g., tungsten, titanium, or tantalum).

[0154] Furthermore, at least one of the first metal layer 2163 and the second metal layer 2165 may include a metal silicide, such as titanium silicide, cobalt silicide, or nickel silicide. However, the materials included in the first metal layer 2163 and the second metal layer 2165 are not limited thereto and may be varied.

[0155] Bit line capping layer 2167 may include an insulating material, such as silicon nitride or silicon oxynitride.

[0156] In some embodiments, the bit line BL may include 2D and 3D materials. For example, the bit line BL may include one of carbon-based 2D materials such as graphene, 3D materials such as carbon nanotubes, or combinations thereof.

[0157] Bit line BL can be placed adjacent to the peripheral circuit structure PSR. Because bit line BL is placed adjacent to the peripheral circuit structure PSR, the electrical connection path between bit line BL and peripheral circuit PC can be shortened.

[0158] In some embodiments, the semiconductor device may further include a bit line shielding pattern BS and a spacer insulating layer 2175 located between the peripheral circuit structure PSR and the memory cell structure.

[0159] The bit line shielding pattern BS can be located between the peripheral circuit structure PSR and the bit line BL. Furthermore, the bit line shielding pattern BS can be located between adjacent bit lines BL and can extend in the second direction D2. In other words, the bit line shielding pattern BS can be arranged alternately with the bit lines BL and spaced apart in the first direction D1.

[0160] The spacer insulating layer 2175 may be conformally located on the bit line BL. The spacer insulating layer 2175 may cover the opposite sides and the upper surface of the bit line BL. The spacer insulating layer 2175 may define a gap region between the bit lines BL. The gap region of the spacer insulating layer 2175 may extend in a second direction D2 parallel to the bit line BL.

[0161] Bit line shielding pattern BS may include a conductive material. For example, bit line shielding pattern BS may include metallic materials such as tungsten (W), titanium (Ti), nickel (Ni), or cobalt (Co). In another example, bit line shielding pattern BS may include a two-dimensional conductive material such as graphene, but is not limited thereto.

[0162] The spacer insulation layer 2175 may include an insulating material. For example, it may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material.

[0163] The bit line shielding pattern BS may be located on the spacer insulation layer 2175. The bit line shielding pattern BS may be located within the gap area of ​​the spacer insulation layer 2175.

[0164] Bit line shielding pattern BS may include line portions located between adjacent bit lines BL, and connecting portions that commonly connect the line portions.

[0165] The line portion of the bit line shielding pattern BS can be located between bit lines BL and within a plurality of gap regions defined by the spacer insulating layer 2175. Therefore, the side of the line portion of the bit line shielding pattern BS and the bit line BL can be separated, with the spacer insulating layer 2175 located between the side of the line portion of the bit line shielding pattern BS and the bit line BL.

[0166] The connecting portion of the bit line shielding pattern BS is connected to the line portion and can be integrated with the line portion. The connecting portion of the bit line shielding pattern BS is located on the line portion and can connect the line portions located between adjacent bit lines BL. However, it is not limited to this, and in some embodiments, the line portion and the connecting portion of the bit line shielding pattern BS can be composed of separate components.

[0167] In some embodiments, the connecting portion of the bit line shielding pattern BS may extend from the cell region CAR to the peripheral region PAR. Therefore, the end of the connecting portion of the bit line shielding pattern BS may be located in the peripheral region PAR. The connecting portion of the bit line shielding pattern BS located in the peripheral region PAR may be connected to a bit line shielding contact.

[0168] The semiconductor device may further include a bit line shielding capping layer 2179, a first unit insulating layer 2177 located between a spacer insulating layer 2175 and a second bonding insulating layer 2216, a second unit insulating layer 2173 located on the spacer insulating layer 2175, and a device isolation layer STI located on the second unit insulating layer 2173.

[0169] The bit line shielding cover layer 2179 may be located between the bit line shielding pattern BS and the second bonding insulation layer 2216, and may cover the bit line shielding pattern BS.

[0170] The first unit insulating layer 2177 may be located on the second bonding insulating layer 2216. The upper surface of the first unit insulating layer 2177 may contact the spacer insulating layer 2175, and the side of the first unit insulating layer 2177 may contact the ends of the bit line shielding pattern BS and the bit line shielding capping layer 2179.

[0171] The second unit insulation layer 2173 may be located on the spacer insulation layer 2175.

[0172] The second unit insulating layer 2173 may contact and cover the end of the bit line BL. However, this is illustrative, and the second unit insulating layer 2173 may be spaced apart from the end of the bit line BL.

[0173] The device isolation layer STI may be located on the second cell insulating layer 2173. A portion of the device isolation layer STI may overlap with the bit line BL on the third direction D3.

[0174] The bit line shield capping layer 2179, the first unit insulating layer 2177, the second unit insulating layer 2173, and the device isolation layer STI may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. For example, the bit line shield capping layer 2179 may comprise silicon nitride, and the first unit insulating layer 2177, the second unit insulating layer 2173, and the device isolation layer STI may comprise silicon oxide. However, these are merely examples, and the materials included in each of the bit line shield capping layer 2179, the first unit insulating layer 2177, the second unit insulating layer 2173, and the device isolation layer STI may vary.

[0175] The first active pattern AP1 and the second active pattern AP2 are located between the first word line WL1 and the second word line WL2. For example, the first active pattern AP1 may be arranged on one side of the first word line WL1, and the second active pattern AP2 may be arranged on one side of the second word line WL2. In other words, the first active pattern AP1 may be arranged closer to the first word line WL1 than the second active pattern AP2, and the second active pattern AP2 may be arranged closer to the second word line WL2 than the first active pattern AP1. The first active pattern AP1 and the second active pattern AP2 may be alternately arranged on the bit line BL along the second direction D2. For example, the first active pattern AP1 and the second active pattern AP2 may be arranged two-dimensionally on a plane along the first direction D1 and the second direction D2.

[0176] For example, the first active pattern AP1 and the second active pattern AP2 can each be made of a single-crystal semiconductor material. For example, the first active pattern AP1 and the second active pattern AP2 can each be made of single-crystal silicon. However, this is not limiting, and the materials included in the first active pattern AP1 and the second active pattern AP2 can vary. For example, the first active pattern AP1 and the second active pattern AP2 can include polycrystalline semiconductors, oxide semiconductors, two-dimensional materials, or combinations thereof. For example, the polycrystalline semiconductor can be polycrystalline silicon. In another example, the oxide semiconductor can be indium gallium zinc oxide (IGZO). In yet another example, the two-dimensional material can be MoS2, WS2, MoSe2, or WSe2.

[0177] In some embodiments, the semiconductor device may include a back gate electrode BG extending between a first active pattern AP1 and a second active pattern AP2 in a direction different from the bit line BL.

[0178] The back gate electrode BG is located between the first active pattern AP1 and the second active pattern AP2, which are adjacent to each other in the second direction D2, and can extend intersecting the bit line BL along the first direction D1. That is, the back gate electrode BG can extend in a direction different from the extension direction of the bit line BL.

[0179] The back gate electrode BG may be located on the bit line BL and the bit line shielding pattern BS. The first active pattern AP1 may be located on one side of the back gate electrode BG in the second direction D2, and the second active pattern AP2 may be located on the other side of the back gate electrode BG in the second direction D2.

[0180] The back gate electrode BG may be located between an adjacent pair of first word lines WL1 and second word lines WL2 in the second direction D2. For example, the first active pattern AP1 may be located between the first word line WL1 and the back gate electrode BG, and the second active pattern AP2 may be located between the second word line WL2 and the back gate electrode BG. However, this is exemplary, and the arrangement relationship between the first active pattern AP1 and the second active pattern AP2, the first word line WL1 and the second word line WL2, and the back gate electrode BG is not limited to this, but may be varied.

[0181] The back gate electrode (BG) may include a conductive material. For example, the back gate electrode (BG) may include doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or a combination thereof. However, this is exemplary, and the conductive material may vary.

[0182] During the operation of a semiconductor device, a negative voltage can be applied to the back gate electrode (BG), thereby increasing the threshold voltage of the vertical channel transistor. In other words, as vertical channel transistors are miniaturized, a decrease in threshold voltage and a deterioration in leakage current characteristics can be prevented.

[0183] The semiconductor device may also include a first back gate insulating pattern 2111 and a second back gate insulating pattern 2117.

[0184] The first back gate insulating pattern 2111 and the second back gate insulating pattern 2117 may be located between the first active pattern AP1 and the second active pattern AP2 that are adjacent to each other in the second direction D2. The first back gate insulating pattern 2111 and the second back gate insulating pattern 2117 may extend parallel to the back gate electrode BG in the first direction D1.

[0185] The first back gate insulating pattern 2111 may contact the first active pattern AP1 and the second active pattern AP2. The first back gate insulating pattern 2111 may extend in the third direction D3 along each side of the first active pattern AP1 and the second active pattern AP2 that face each other in the second direction D2.

[0186] The first back gate insulating pattern 2111 may extend along both sides of the back gate electrode BG, and the second back gate insulating pattern 2117 may be located between the lower surface of the back gate electrode BG and the bit line BL.

[0187] The first back gate insulating pattern 2111 and the second back gate insulating pattern 2117 may include insulating materials. The first back gate insulating pattern 2111 and the second back gate insulating pattern 2117 may each include silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. However, the materials included in the first back gate insulating pattern 2111 and the second back gate insulating pattern 2117 are not limited thereto and may vary.

[0188] The first word line WL1 and the second word line WL2 may be located on the bit line BL and the bit line shielding pattern BS. The first word line WL1 and the second word line WL2 may extend in a first direction D1 that intersects with a second direction D2, which is the extension direction of the bit line BL. The first word line WL1 and the second word line WL2 may be positioned to be spaced apart from each other in the second direction D2.

[0189] The first active pattern AP1 and the second active pattern AP2 can be located between the first word line WL1 and the second word line WL2, which are adjacent on the second direction D2.

[0190] The first word line WL1 and the second word line WL2 may overlap with the bit line BL and the bit line shielding pattern BS in a third direction D3. The first word line WL1 and the second word line WL2 may extend in a third direction D3 that intersects the first direction D1 and the second direction D2 perpendicularly.

[0191] The first word line WL1 and the second word line WL2 may be located between the bit line BL and the gate hydrogen diffusion pattern 2145, which will be described later, and may extend on the third direction D3.

[0192] For example, the first word line WL1 and the second word line WL2 are shown as having a rectangular cross-section, but the cross-sectional shape of the first word line WL1 and the second word line WL2 is not limited to this and can be varied. For example, each of the first word line WL1 and the second word line WL2 can have an "L" shaped cross-section.

[0193] The first word line WL1 and the second word line WL2 may comprise conductive materials. For example, the first word line WL1 and the second word line WL2 may comprise doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional materials, metals, or combinations thereof. However, the conductive materials are not limited to these.

[0194] The semiconductor device may further include a gate insulating pattern GOX located on the side of the first word line WL1 and the second word line WL2, a gate isolation pattern 2141 located between the first word line WL1 and the second word line WL2, and a gate capping pattern 2147 located on the lower surface of the first word line WL1 and the second word line WL2.

[0195] The gate insulating pattern GOX may contact the first active pattern AP1 and the second active pattern AP2. The gate insulating pattern GOX may extend in the third direction D3 along the sides of the first active pattern AP1 and the second active pattern AP2 that face each other in the second direction D2.

[0196] The gate isolation pattern 2141 may be located between the first word line WL1 and the second word line WL2 spaced apart in the second direction D2. The gate isolation pattern 2141 may be located between the gate cap pattern 2147 and the contact interlayer insulating layer 2271 described later.

[0197] The gate isolation pattern 2141 may contact the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be separated and insulated by the gate isolation pattern 2141. The gate isolation pattern 2141 may extend in a third direction D3 between the first word line WL1 and the second word line WL2.

[0198] The lower surface of the gate isolation pattern 2141 may be located at a level lower than the lower surfaces of the first word line WL1 and the second word line WL2, and the upper surface may be located at a level higher than the upper surfaces of the first word line WL1 and the second word line WL2.

[0199] The gate cap pattern 2147 may be located below the first word line WL1 and the second word line WL2. The gate cap pattern 2147 may cover the lower surface of the first word line WL1 and the second word line WL2.

[0200] The lower surface and adjacent sides of the gate isolation pattern 2141 may be covered by the gate capping pattern 2147, and the upper surface may be covered by the contact interlayer insulating layer 2271.

[0201] The gate insulating pattern GOX may include silicon oxide, silicon oxynitride, a high-k dielectric material having a higher dielectric constant than silicon oxide, or a combination thereof. For example, high-k dielectric materials may include, but are not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof.

[0202] The gate isolation pattern 2141 and the gate cap pattern 2147 may include silicon oxide, silicon nitride, or a combination thereof. For example, the gate isolation pattern 2141 may include silicon oxide, and the gate cap pattern 2147 may include silicon nitride, but are not limited thereto.

[0203] The gate hydrogen diffusion pattern 2145 may be located on the first word line WL1 and the second word line WL2. In other words, the gate hydrogen diffusion pattern 2145 may be positioned to overlap with the first word line WL1 and the second word line WL2 on a third direction D3. The gate hydrogen diffusion pattern 2145 may be located between the first word line WL1 and the second word line WL2 and the data storage pattern DSP. The gate hydrogen diffusion pattern 2145 may be located between the upper surface of the first word line WL1 and the second word line WL2 and the lower surface of the memory contact BC, which will be described later.

[0204] The gate hydrogen diffusion pattern 2145 may include an insulating material and hydrogen. In other words, the gate hydrogen diffusion pattern 2145 may be a hydrogen-rich (H-rich) insulating layer. The gate hydrogen diffusion pattern 2145 is capable of supplying hydrogen to the boundary between the peripheral structure (e.g., the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2) by annealing, and thus can passivate the dangling bonds with hydrogen. Even after supplying hydrogen to the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2, the gate hydrogen diffusion pattern 2145 may still include hydrogen.

[0205] For example, the annealing process for diffusing hydrogen can be carried out at a pressure of 10 to 40 Torr (e.g., 20 to 30 Torr) and a temperature of 400 to 475°C or 375 to 400°C for 15 to 60 minutes (e.g., 30 to 45 minutes). The annealing process can be carried out at a temperature below the temperature range that induces the crystallization of the first active pattern AP1 and the second active pattern AP2 (e.g., below 600°C).

[0206] The insulating material of the gate hydrogen diffusion pattern 2145 may include silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), or a combination thereof. For example, a hydrogen-rich gate hydrogen diffusion pattern 2145 comprising silicon oxide and hydrogen can be formed by depositing SiH4 and O2 as source materials. Alternatively, a hydrogen-rich gate hydrogen diffusion pattern 2145 comprising silicon nitride and hydrogen can be formed by depositing SiH4 and NH3 as source materials. In this case, deposition can be performed using methods such as atomic pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD). Alternatively, after depositing silicon oxide or silicon nitride, hydrogen can be plasma-doped into the silicon oxide or silicon nitride to form the hydrogen-rich gate hydrogen diffusion pattern 2145.

[0207] For example, the gate hydrogen diffusion pattern 2145 may be a TEOS layer including tetraethyl orthosilicate (TEOS), and the gate hydrogen diffusion pattern 2145 may be an HDP layer including a high-density plasma CVD (HDP CVD) dielectric material.

[0208] The gate hydrogen diffusion pattern 2145 may include hydrogen, deuterium, tritium, or a combination thereof. Hydrogen may be hydrogen atoms or hydrogen molecules. Because deuterium or tritium is heavier than hydrogen, when the gate hydrogen diffusion pattern 2145 includes deuterium or tritium, the loss of deuterium or tritium into the air is reduced compared to when it includes hydrogen. For example, the gate hydrogen diffusion pattern 2145 may include 90% or more of hydrogen relative to the sum of hydrogen, deuterium, and tritium.

[0209] For example, the gate hydrogen diffusion pattern 2145 may include a total amount of hydrogen greater than 0 at% (e.g., 1 at% or more, 2 at% or more, 3 at% or more, or 4 at% or more) based on the gate hydrogen diffusion pattern 2145, and it may include a total amount of hydrogen of 5 at% or less (e.g., 4 at% or less, 3 at% or less, or 2 at% or less), and for example, it may include a total amount of hydrogen greater than 0 at% and less than or equal to 5 at%.

[0210] Furthermore, the ratio of the hydrogen peak intensity of the gate hydrogen diffusion pattern 2145 as measured by secondary ion mass spectrometry (SIMS) to the hydrogen peak intensity of the adjacent first active pattern AP1 and second active pattern AP2 as measured by secondary ion mass spectrometry (SIMS) can be 10 or greater: 1, for example, 100 or greater: 1 or 1000 or greater: 1.

[0211] For example, when the gate insulating pattern GOX comprises silicon dioxide (SiO2) and the first active pattern AP1 and the second active pattern AP2 comprise silicon (Si), the dangling bonds present at the interface between silicon dioxide (SiO2) and silicon (Si) can be hydrogen passivated.

[0212] Therefore, as described later, the upper wiring structure 2370 may include an upper wiring hydrogen diffusion layer 2372 covering the upper wiring layer 2371 and including an insulating material and hydrogen. After the upper wiring hydrogen diffusion layer 2372 is formed and then annealed, the hydrogen in the upper wiring hydrogen diffusion layer 2372 can be supplied through the data storage pattern DSP in the cell region CAR to the first word line WL1 and the second word line WL2, and can diffuse until the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2.

[0213] However, when hydrogen diffuses from the upper wiring hydrogen diffusion layer 2372, the hydrogen diffusion path may cause a decrease in reliability in the upper wiring structure 2370 and the data storage pattern DSP. Furthermore, hydrogen from the upper wiring hydrogen diffusion layer 2372 can also diffuse into the peripheral circuit PC via the peripheral circuit contacts PCT1, PCT2, PCT3 and the peripheral circuit wirings PCL1, PCL2 in the peripheral region PAR, and this hydrogen diffusion path can also cause a decrease in reliability in the peripheral circuit PC.

[0214] For example, in the upper wiring structure 2370, hydrogen embrittlement of the copper (Cu) wiring may be deteriorated due to hydrogen diffusion, and moisture absorption vulnerability may occur due to the deterioration of interfacial adhesion. In the data storage pattern DSP, hydrogen ions (H+) in the dielectric layer 2253 may also become embrittled due to hydrogen diffusion. + The combination of hydrogen with oxygen vacancies can reduce reliability. In the peripheral circuit PC, negative bias temperature instability (NBTI) may deteriorate due to residual hydrogen from hydrogen diffusion.

[0215] According to some embodiments, a gate hydrogen diffusion pattern 2145, including insulating material and hydrogen, is located on the first word line WL1 and the second word line WL2. Therefore, hydrogen can diffuse from the gate hydrogen diffusion pattern 2145 to the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2. It is advantageous in terms of hydrogen supply diffusion by directly diffusing hydrogen from the gate hydrogen diffusion pattern 2145 to the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2, and the upper wiring structure 2370, the data storage pattern DSP, and the peripheral circuitry PC do not experience a decrease in reliability due to the hydrogen diffusion path.

[0216] In some embodiments, the semiconductor device may include a back-gate hydrogen diffusion pattern 2115 located on a back-gate electrode BG. The back-gate hydrogen diffusion pattern 2115 may be positioned to overlap with the back-gate electrode BG in a third direction D3. The back-gate hydrogen diffusion pattern 2115 may extend on the back-gate electrode BG along the third direction D3. The back-gate hydrogen diffusion pattern 2115 may be located between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other in a second direction D2.

[0217] The back-gate hydrogen diffusion pattern 2115 may include an insulating material and hydrogen. In other words, the back-gate hydrogen diffusion pattern 2115 may be a hydrogen-rich (H-rich) insulating layer. The back-gate hydrogen diffusion pattern 2115 may supply hydrogen to the boundaries of surrounding structures (e.g., the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2) by annealing, and may use hydrogen to passivate dangling bonds. Even after hydrogen is supplied to the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2, the back-gate hydrogen diffusion pattern 2115 may still include hydrogen.

[0218] The insulating material of the back-gate hydrogen diffusion pattern 2115 may include silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), or combinations thereof. For example, if SiH4 and O2 are used as raw materials for deposition, a hydrogen-rich back-gate hydrogen diffusion pattern 2115 comprising silicon oxide and hydrogen can be formed. Furthermore, when SiH4 and NH3 are used as raw materials for deposition, a hydrogen-rich back-gate hydrogen diffusion pattern 2115 comprising silicon nitride and hydrogen can be formed. In this case, deposition can be performed using methods such as atomic pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD). Alternatively, after depositing silicon oxide or silicon nitride, the hydrogen-rich back-gate hydrogen diffusion pattern 2115 can be formed by doping the silicon oxide or silicon nitride with hydrogen plasma.

[0219] For example, the back-gate hydrogen diffusion pattern 2115 may be a TEOS layer including tetraethyl orthosilicate (TEOS), and the back-gate hydrogen diffusion pattern 2115 may be an HDP layer including a high-density plasma CVD (HDP CVD) dielectric material.

[0220] The back-gate hydrogen diffusion pattern 2115 may include hydrogen, deuterium, tritium, or a combination thereof. Hydrogen may be hydrogen atoms or hydrogen molecules. Because deuterium or tritium is heavier than hydrogen, when the back-gate hydrogen diffusion pattern 2115 includes deuterium or tritium, it can reduce the loss of deuterium or tritium into the air compared to when it includes hydrogen. For example, the back-gate hydrogen diffusion pattern 2115 may include 90% or more of hydrogen relative to the sum of hydrogen, deuterium, and tritium.

[0221] For example, the back-gate hydrogen diffusion pattern 2115 may include a total amount of hydrogen greater than 0 at% (e.g., 1 at% or more, 2 at% or more, 3 at% or more, or 4 at% or more) based on the back-gate hydrogen diffusion pattern 2115, which may include a amount of hydrogen of 5 at% or less (e.g., 4 at% or less, 3 at% or less, or 2 at% or less), and for example, it may include a amount of hydrogen greater than 0 at% and less than or equal to 5 at%.

[0222] Furthermore, the ratio of the hydrogen peak intensity of the back-gate hydrogen diffusion pattern 2115 measured by secondary ion mass spectrometry (SIMS) to the hydrogen peak intensity of the adjacent first active pattern AP1 and second active pattern AP2 measured by secondary ion mass spectrometry (SIMS) can be 10 or greater: 1, for example, 100 or greater: 1 or 1000 or greater: 1.

[0223] The semiconductor device may further include a contact interlayer insulating layer 2271, a pad isolation insulating layer 2273, and a contact etch stop layer 2275 sequentially stacked on a first active pattern AP1 and a second active pattern AP2.

[0224] The interlayer insulating layer 2271 may be located on the first active pattern AP1 and the second active pattern AP2. The interlayer insulating layer 2271 may cover the first back gate insulating pattern 2111, the gate hydrogen diffusion pattern 2145, the back gate hydrogen diffusion pattern 2115, the gate isolation pattern 2141 and the device isolation layer STI.

[0225] The interlayer insulating layer 2271, the pad isolation insulating layer 2273, and the contact etch stop layer 2275 may comprise silicon oxide, silicon nitride, or a combination thereof. For example, the interlayer insulating layer 2271 may comprise silicon oxide, and the pad isolation insulating layer 2273 and the etch stop layer 2275 may comprise silicon nitride, but these layers are not limited thereto.

[0226] In the cell area CAR of the memory cell structure, the storage contact BC, landing pad LP, and data storage pattern DSP can be stacked sequentially.

[0227] Semiconductor devices may include storage contacts BC.

[0228] Storage contacts BC can extend through the interlayer insulation layer 2271. Storage contacts BC can be connected to the first active pattern AP1 and the second active pattern AP2, respectively. Adjacent storage contacts BC can be separated and insulated from each other through the interlayer insulation layer 2271.

[0229] The storage contact BC can be arranged in a matrix pattern on a plane along a first direction D1 and a second direction D2. Figure 8 In the diagram, the storage contact BC is shown as having a circular shape in a plane, but this disclosure is not limited thereto, and the storage contact BC may have various shapes in the plane, such as ellipse, rectangle, square, rhombus or hexagon.

[0230] The storage contact BC may include a conductive material. For example, the conductive material may include impurity-doped polysilicon, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, 2D materials, metals, or combinations thereof. For example, the storage contact BC may include polysilicon doped with n-type impurities. However, the materials included in the storage contact BC are not limited to these and may vary.

[0231] The semiconductor device may include landing pads LP. Each of the landing pads LP may be located on a corresponding storage contact BC.

[0232] The landing pads LP can be arranged in a matrix shape on a plane along a first direction D1 and a second direction D2. Figure 8In the diagram, the landing pad LP is shown as having a circular shape on a plane; however, it is not limited to this shape, and the landing pad LP can have various shapes on the plane, such as ellipse, rectangle, square, rhombus, or hexagon.

[0233] The pad isolation insulation layer 2273 may be located between the landing pads LP. The upper surface of the landing pads LP may be located at substantially the same level as the upper surface of the pad isolation insulation layer 2273.

[0234] The landing pad (LP) may include a conductive material. The conductive material may include, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or a combination thereof.

[0235] The semiconductor device may include a data storage pattern DSP. The data storage pattern DSP may be arranged in a matrix pattern along a first direction D1 and a second direction D2, such as... Figure 8 As shown.

[0236] Each data storage pattern DSP can be located on a landing pad LP. The data storage pattern DSP can fully or partially overlap with each of the landing pads LP on a third-party direction D3. Each data storage pattern DSP can be connected to a first active pattern AP1 and a second active pattern AP2.

[0237] For example, a data storage pattern DSP may include a capacitor, which includes a first electrode 2251, a second electrode 2255, and a dielectric layer 2253 located between the first electrode 2251 and the second electrode 2255.

[0238] The first electrode 2251 may be connected to the landing pad LP through the contact etch stop layer 2275. The first electrode 2251 may extend on the landing pad LP in a third direction D3.

[0239] The first electrode 2251 may include a metal, a conductive metal nitride, or a combination thereof. For example, the first electrode 2251 may include TiN, Ru, TaN, WN, Pt, Ir, or a combination thereof. However, the material included in the first electrode 2251 is not limited to this and may vary.

[0240] The dielectric layer 2253 may extend conformally along the upper and side contours of the first electrode 2251. That is, the dielectric layer 2253 may cover the side and upper surfaces of the first electrode 2251. A portion of the dielectric layer 2253 may be located on the upper surface of the contact etch stop layer 2275. That is, a portion of the dielectric layer 2253 may be located between the contact etch stop layer 2275 and the second electrode 2255.

[0241] The dielectric layer 2253 may include tantalum oxide (Ta2O5), aluminum oxide (Al2O3), titanium oxide (TiO2), or a combination thereof. However, it is not limited to these, and the materials included in the dielectric layer 2253 may vary.

[0242] The second electrode 2255 may be located on the dielectric layer 2253. The second electrode 2255 may completely cover the first electrode 2251. That is, the second electrode 2255 may cover the upper surface and side surface of the first electrode 2251.

[0243] The second electrode 2255 may include a metallic material such as W, Ti, Ru, or SiGe. For example, the second electrode 2255 may include tungsten (W). However, the material included in the second electrode 2255 is not limited to this and may vary. For example, the second electrode 2255 may include a conductive metal nitride, a metal silicide, or a combination thereof.

[0244] The semiconductor device may also include a third unit insulating layer 2277 and a fourth unit insulating layer 2279 sequentially stacked on the contact etch stop layer 2275.

[0245] In addition, the semiconductor device may also include a first unit wiring contact 2261 and a first unit wiring 2262 located within a third unit insulating layer 2277, and a second unit wiring contact 2263 and a second unit wiring 2264 located within a fourth unit insulating layer 2279.

[0246] The third unit insulating layer 2277 can completely cover the data storage pattern DSP. In other words, the third unit insulating layer 2277 can cover the top and side surfaces of the data storage pattern DSP.

[0247] The data storage pattern DSP can be connected to the first unit wiring 2262 via the first unit wiring contact 2261, and the first unit wiring 2262 can be connected to the second unit wiring 2264 via the second unit wiring contact 2263.

[0248] The first unit wiring contact 2261, the first unit wiring 2262, the second unit wiring contact 2263, and the second unit wiring 2264 may include metals such as copper Cu, aluminum Al, tungsten W, titanium Ti, tantalum Ta, or combinations thereof.

[0249] The semiconductor device may also include an upper wiring structure 2370 located on the fourth unit insulating layer 2279.

[0250] The upper wiring structure 2370 may include an upper wiring layer 2371, an upper wiring hydrogen diffusion layer 2372, and an upper wiring hydrogen diffusion barrier layer 2373. The upper wiring structure 2370 may be located in the cell region CAR and / or the peripheral region PAR. Therefore, the upper wiring layer 2371, the upper wiring hydrogen diffusion layer 2372, and the upper wiring hydrogen diffusion barrier layer 2373 may also be located in the cell region CAR and / or the peripheral region PAR.

[0251] The upper wiring layer 2371 may be located within the upper wiring hydrogen diffusion barrier layer 2373. The upper wiring layer 2371 may be in contact with the upper surface of the second unit wiring 2264. The upper wiring layer 2371 may be electrically connected to the first unit wiring 2262 and the second unit wiring 2264. For example, the upper width of the upper wiring layer 2371 may be shorter than the lower width.

[0252] For example, the upper wiring layer 2371 may include tungsten (W), titanium (Ti), tantalum (Ta), or nitrides thereof. In some embodiments, the upper wiring layer 2371 may include a conductive material different from the first unit wiring 2262 and the second unit wiring 2264. For example, the first unit wiring 2262 and the second unit wiring 2264 may include a first metal, and the upper wiring layer 2371 may include a second metal different from the first metal. For example, the upper wiring layer 2371 may include aluminum (Al).

[0253] The upper wiring hydrogen diffusion layer 2372 may be located on the upper wiring layer 2371. The upper wiring hydrogen diffusion layer 2372 may conformally cover the upper surface of the upper wiring layer 2371. The upper wiring hydrogen diffusion layer 2372 may be located within the upper wiring hydrogen diffusion barrier layer 2373.

[0254] The upper wiring hydrogen diffusion layer 2372 may include insulating material and hydrogen. In other words, the upper wiring hydrogen diffusion layer 2372 may be a hydrogen-rich (H-rich) insulating layer.

[0255] Annealing allows hydrogen present in the upper wiring hydrogen diffusion layer 2372 to be supplied to the cell region CAR via the data storage pattern DSP, and diffused to the boundary between the gate insulating pattern GOX and the first active pattern AP1 and the second active pattern AP2 via the first word line WL1 and the second word line WL2.

[0256] For example, when the gate insulating pattern GOX comprises silicon dioxide (SiO2) and the first active pattern AP1 and the second active pattern AP2 comprise silicon (Si), the dangling bonds present at the interface between silicon dioxide (SiO2) and silicon (Si) can be hydrogen passivated. The upper wiring hydrogen diffusion layer 2372 can still include hydrogen even after hydrogen diffusion by annealing.

[0257] For example, the annealing process for diffusing hydrogen can be carried out at a pressure of 10 to 40 Torr (e.g., 20 to 30 Torr) and a temperature of 400 to 475°C or 375 to 400°C for 15 to 60 minutes (e.g., 30 to 45 minutes). The annealing process can be carried out at a temperature below the temperature range that causes the material to crystallize the first active pattern AP1 and the second active pattern AP2 (e.g., below 600°C).

[0258] The insulating material of the upper wiring hydrogen diffusion layer 2372 may include silicon nitride, silicon oxide, tetraethyl orthosilicate (TEOS), or a combination thereof. For example, by depositing SiH4 and O2 as raw materials, a hydrogen-rich upper wiring hydrogen diffusion layer 2372 comprising silicon oxide and hydrogen can be formed. Alternatively, by depositing SiH4 and NH3 as raw materials, a hydrogen-rich upper wiring hydrogen diffusion layer 2372 comprising silicon nitride and hydrogen can be formed. In this case, deposition can be performed using methods such as atomic pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD). Alternatively, after depositing silicon oxide or silicon nitride, hydrogen can be plasma-doped into the silicon oxide or silicon nitride to form the hydrogen-rich upper wiring hydrogen diffusion layer 2372.

[0259] For example, the upper wiring hydrogen diffusion layer 2372 may be a TEOS layer including tetraethyl orthosilicate (TEOS), and the upper wiring hydrogen diffusion layer 2372 may be an HDP layer including a high-density plasma CVD (HDP CVD) dielectric material.

[0260] The upper wiring hydrogen diffusion layer 2372 may include hydrogen, deuterium, tritium, or a combination thereof. Hydrogen may be hydrogen atoms or hydrogen molecules. Because deuterium or tritium is heavier than hydrogen, when the upper wiring hydrogen diffusion layer 2372 includes deuterium or tritium, it can reduce the loss of deuterium or tritium into the air compared to when it includes hydrogen. For example, the upper wiring hydrogen diffusion layer 2372 may include 90% or more hydrogen relative to the sum of hydrogen, deuterium, and tritium.

[0261] As an example, the upper wiring hydrogen diffusion layer 2372 may include an amount of hydrogen greater than 0 at% (e.g., 1 at% or more, 2 at% or more, 3 at% or more, or 4 at% or more) based on the total amount of the upper wiring hydrogen diffusion layer 2372, which may include an amount of hydrogen of 5 at% or less (e.g., 4 at% or less, 3 at% or less, or 2 at% or less), and for example, it may include an amount of hydrogen greater than 0 at% and less than or equal to 5 at%.

[0262] In this configuration, the upper wiring hydrogen diffusion layer 2372 may have a lower hydrogen concentration than the gate hydrogen diffusion pattern 2145. Therefore, the primary hydrogen source can be the gate hydrogen diffusion pattern 2145, and the upper wiring hydrogen diffusion layer 2372 can serve as a supplementary hydrogen source. As previously mentioned, hydrogen diffusion from the upper wiring hydrogen diffusion layer 2372 can potentially reduce the reliability of the upper wiring structure 2370 and the data storage pattern DSP due to the hydrogen diffusion path. Therefore, the upper wiring hydrogen diffusion layer 2372 can be used to support the gate hydrogen diffusion pattern 2145.

[0263] The upper wiring hydrogen diffusion barrier layer 2373 may be located on the fourth unit insulating layer 2279. The upper wiring hydrogen diffusion barrier layer 2373 may cover the upper wiring layer 2371 and the upper wiring hydrogen diffusion layer 2372.

[0264] For example, the upper wiring hydrogen diffusion barrier layer 2373 may have a lower hydrogen diffusivity than the upper wiring hydrogen diffusion layer 2372. The upper wiring hydrogen diffusion barrier layer 2373 may comprise silicon nitride with a low hydrogen diffusivity. The hydrogen concentration in the upper wiring hydrogen diffusion barrier layer 2373 may be lower than the hydrogen concentration in the upper wiring hydrogen diffusion layer 2372. In other words, the formation of the upper wiring hydrogen diffusion barrier layer 2373 may not involve the use of a hydrogen source such as SiH4 or NH3. The upper wiring hydrogen diffusion barrier layer 2373 may comprise 1 at% or less hydrogen across the entire layer, or may not contain any hydrogen. The upper wiring hydrogen diffusion barrier layer 2373 prevents hydrogen from diffusing upwards from the upper wiring hydrogen diffusion layer 2372, for example, diffusing outwards from the semiconductor device.

[0265] Passivation layer 2390 may be located on upper wiring structure 2370. For example, passivation layer 2390 may include silicon nitride (SiN). The hydrogen permeability of passivation layer 2390 may be higher than the hydrogen permeability of upper wiring hydrogen diffusion barrier layer 2373.

[0266] Figure 12 Semiconductor devices according to some implementation methods and Figure 11 Corresponding cross-sectional view. For ease of explanation, the description will focus on its use. Figures 8 to 11 The differences in description.

[0267] Reference Figure 12 The semiconductor device may further include a gate hydrogen diffusion barrier layer 2146 on the gate hydrogen diffusion pattern 2145. The gate hydrogen diffusion barrier layer 2146 may cover the gate hydrogen diffusion pattern 2145. The gate hydrogen diffusion barrier layer 2146 may be located below the storage contact BC and may be located between the gate hydrogen diffusion pattern 2145 and the storage contact BC.

[0268] For example, the gate hydrogen diffusion barrier layer 2146 may have a lower hydrogen diffusivity than the gate hydrogen diffusion pattern 2145. The gate hydrogen diffusion barrier layer 2146 may include silicon nitride with a low hydrogen diffusivity. The gate hydrogen diffusion barrier layer 2146 may have a lower hydrogen concentration than the gate hydrogen diffusion pattern 2145. In other words, a hydrogen source such as SiH4 or NH3 may not be used during the formation of the gate hydrogen diffusion barrier layer 2146. The gate hydrogen diffusion barrier layer 2146 may include 1 at% or less of hydrogen throughout the entire gate hydrogen diffusion barrier layer 2146, or it may not include hydrogen at all. The gate hydrogen diffusion barrier layer 2146 prevents hydrogen from diffusing upwards from the gate hydrogen diffusion pattern 2145 (e.g., a data storage pattern DSP or an upper wiring structure 2370).

[0269] Furthermore, the semiconductor device may also include a back-gate hydrogen diffusion barrier layer 2116 on the back-gate hydrogen diffusion pattern 2115. The back-gate hydrogen diffusion barrier layer 2116 may cover the back-gate hydrogen diffusion pattern 2115. The back-gate hydrogen diffusion barrier layer 2116 may be located below the storage contact BC, and it may be located between the back-gate hydrogen diffusion pattern 2115 and the storage contact BC.

[0270] For example, the back-gate hydrogen diffusion barrier layer 2116 may have a lower hydrogen diffusivity than the back-gate hydrogen diffusion pattern 2115. The back-gate hydrogen diffusion barrier layer 2116 may include silicon nitride with a low hydrogen diffusivity. The back-gate hydrogen diffusion barrier layer 2116 may have a lower hydrogen concentration than the back-gate hydrogen diffusion pattern 2115. In other words, a hydrogen source such as SiH4 or NH3 may not be used during the formation of the back-gate hydrogen diffusion barrier layer 2116. The back-gate hydrogen diffusion barrier layer 2116 may include 1 at% or less of hydrogen throughout the entire back-gate hydrogen diffusion barrier layer 2116, or it may not include hydrogen at all. The back-gate hydrogen diffusion barrier layer 2116 prevents hydrogen from diffusing upwards from the back-gate hydrogen diffusion pattern 2115 to, for example, a data storage pattern DSP or an on-wire structure 2370.

[0271] Figure 13 and Figure 14 Semiconductor devices according to some implementation methods and Figure 11 Corresponding cross-sectional view. For ease of explanation, the description will focus on its use. Figures 8 to 11 The differences in description.

[0272] Reference Figure 11 The diagram shows that the gate hydrogen diffusion pattern 2145 and the back gate hydrogen diffusion pattern 2115 include insulating material and hydrogen, representing a hydrogen-rich (H-rich) insulating layer.

[0273] Reference Figure 13The gate hydrogen diffusion pattern 2145 can be a hydrogen-rich (H-rich) insulating layer that includes insulating material and hydrogen, while the back gate hydrogen diffusion pattern 2115 can be a general insulating layer that includes insulating material but does not include hydrogen. Here, a general insulating layer that does not include hydrogen means that it does not contain any hydrogen or contains a small amount of hydrogen due to diffusion or other reasons.

[0274] Reference Figure 14 The back gate hydrogen diffusion pattern 2115 can be a hydrogen-rich (H-rich) insulating layer that includes insulating material and hydrogen, while the gate hydrogen diffusion pattern 2145 can be a general insulating layer that includes insulating material but does not include hydrogen.

[0275] While this specification includes numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features specific to particular implementations of a particular invention. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

[0276] The embodiments of this disclosure have been described in detail above, but the scope of this disclosure is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concept of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Substrate, comprising a cell active pattern, The cell gate structure, which is located on the cell active pattern, and Bitline structure, which is connected to the cell active pattern. The unit gate structure includes a unit gate insulating layer on the unit active pattern, a unit gate conductive layer on the unit gate insulating layer, and a unit gate capping layer on the unit gate conductive layer. The unit gate capping layer includes an insulating material and hydrogen.

2. The semiconductor device according to claim 1, wherein The insulating material of the unit gate capping layer includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate.

3. The semiconductor device according to claim 1, wherein The unit gate structure includes a unit gate hydrogen diffusion barrier layer on the unit gate capping layer. The unit gate hydrogen diffusion barrier layer comprises silicon nitride, and The hydrogen diffusion barrier layer of the unit gate has a lower hydrogen diffusivity than the unit gate capping layer.

4. The semiconductor device according to claim 1, wherein The cell gate capping layer includes an insulating material in which hydrogen is plasma-doped.

5. The semiconductor device according to claim 1, wherein The unit gate structure includes a second conductive layer on the unit gate conductive layer, and the second conductive layer includes polysilicon.

6. The semiconductor device according to claim 1, wherein The semiconductor device further includes: Data storage pattern, which is connected to the cell active pattern, and The upper wiring structure, which is on the data storage pattern, The upper wiring structure includes an upper wiring layer and an upper wiring hydrogen diffusion layer, wherein the upper wiring hydrogen diffusion layer covers the upper wiring layer, and wherein the upper wiring hydrogen diffusion layer comprises an insulating material and hydrogen. The insulating material of the upper wiring hydrogen diffusion layer includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate.

7. The semiconductor device according to claim 6, wherein The upper wiring structure includes an upper wiring hydrogen diffusion barrier layer on the upper wiring hydrogen diffusion layer. The upper wiring hydrogen diffusion barrier layer comprises silicon nitride, and The hydrogen diffusion barrier layer of the upper wiring has a lower hydrogen diffusivity than the hydrogen diffusion layer of the upper wiring.

8. The semiconductor device according to claim 6, wherein The hydrogen concentration in the cell gate capping layer is greater than the hydrogen concentration in the upper wiring hydrogen diffusion layer.

9. The semiconductor device according to claim 6, wherein The semiconductor device further includes: A peripheral gate structure, located in the peripheral region of the substrate; and A dielectric layer, located in the cell region of the substrate below the upper wiring structure. The substrate includes the cell region and the peripheral region, wherein the cell region includes the cell active pattern. The upper wiring structure is located on the peripheral gate structure. The dielectric layer comprises a first layer containing aluminum oxide, a second layer containing zirconium, or a composite layer, wherein the composite layer has alternating layers of the first and second layers, and Wherein, the semiconductor device does not have the dielectric layer in the peripheral region of the substrate between the peripheral gate structure and the upper wiring structure, wherein the semiconductor device does not have the first layer containing aluminum oxide, the second layer containing zirconium, or the composite layer in the peripheral region of the substrate.

10. The semiconductor device according to claim 9, wherein The data storage pattern includes a lower electrode connected to the unit active pattern, an upper electrode spaced apart from the lower electrode, and a data storage pattern dielectric layer between the lower electrode and the upper electrode, wherein the data storage pattern dielectric layer includes a first layer comprising aluminum oxide, a second layer comprising zirconium, or a composite layer in which the first layer and the second layer are alternately stacked.

11. A semiconductor device, comprising: Substrate, Bit lines, which are on the substrate and extend in a second direction different from the first direction, The first word line and the second word line on the bit line extend in the first direction and are alternately spaced apart from each other in the second direction. The first active pattern and the second active pattern on the bit line are spaced apart from each other in the first direction, wherein the first active pattern and the second active pattern are located between the first word line and the second word line, wherein the first active pattern is closer to the first word line than to the second word line, and wherein the second active pattern is closer to the second word line than to the first word line. A back gate electrode, extending in the first direction on the bit line and between the first active pattern and the second active pattern, The gate hydrogen diffusion pattern is located on the first word line and the second word line, and... A back-gate hydrogen diffusion pattern is present on the back-gate electrode. The gate hydrogen diffusion pattern and the back gate hydrogen diffusion pattern include insulating material and hydrogen.

12. The semiconductor device of claim 11, wherein, The insulating material of the gate hydrogen diffusion pattern and the back gate hydrogen diffusion pattern includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate.

13. The semiconductor device of claim 11, wherein, The semiconductor device further includes a first hydrogen diffusion barrier layer on the gate hydrogen diffusion pattern. Wherein, the first hydrogen diffusion barrier layer comprises silicon nitride, and The first hydrogen diffusion barrier layer has a lower hydrogen diffusivity than the gate hydrogen diffusion pattern. The semiconductor device further includes a second hydrogen diffusion barrier layer on the back gate hydrogen diffusion pattern. The second hydrogen diffusion barrier layer comprises silicon nitride, and The second hydrogen diffusion barrier layer has a lower hydrogen diffusivity than the back gate hydrogen diffusion pattern.

14. The semiconductor device of claim 11, wherein, The gate hydrogen diffusion pattern and the back gate hydrogen diffusion pattern include an insulating material in which the hydrogen is plasma-doped.

15. The semiconductor device of claim 11, wherein, The semiconductor device further includes data storage patterns on the first active pattern and the second active pattern, and The upper wiring structure, which is on the data storage pattern, The upper wiring structure includes: Upper wiring layer An upper wiring hydrogen diffusion layer, comprising an insulating material and hydrogen, and covering the upper wiring layer, and An upper wiring hydrogen diffusion barrier layer, which is located on the upper wiring hydrogen diffusion layer, The insulating material of the upper wiring hydrogen diffusion layer includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate. The upper wiring hydrogen diffusion barrier layer comprises silicon nitride, and The hydrogen diffusion barrier layer of the upper wiring has a lower hydrogen diffusivity than the hydrogen diffusion layer of the upper wiring.

16. A semiconductor device, comprising Substrate, Bit lines, which are on the substrate and extend in a second direction different from the first direction, The first word line and the second word line on the bit line extend in the first direction and are alternately spaced apart from each other in the second direction. The first active pattern and the second active pattern on the bit line are spaced apart in the first direction, wherein, The first active pattern and the second active pattern are located between the first character line and the second character line, wherein the first active pattern is closer to the first character line than to the second character line, and wherein the second active pattern is closer to the second character line than to the first character line. The gate hydrogen diffusion pattern is located on the first word line and the second word line, and... A hydrogen diffusion barrier layer is provided on the gate hydrogen diffusion pattern. The hydrogen diffusion barrier layer has a lower hydrogen diffusivity than the gate hydrogen diffusion pattern.

17. The semiconductor device of claim 16, wherein, The gate hydrogen diffusion pattern includes an insulating material, which includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate.

18. The semiconductor device of claim 16, wherein, The hydrogen diffusion barrier layer comprises silicon nitride.

19. The semiconductor device of claim 16, wherein the gate hydrogen diffusion pattern comprises an insulating material in which hydrogen is plasma-doped.

20. The semiconductor device of claim 16, wherein, The semiconductor device further includes data storage patterns on the first active pattern and the second active pattern, and The upper wiring structure, which is on the data storage pattern, The upper wiring structure includes: Upper wiring layer An upper wiring hydrogen diffusion layer, which covers the upper wiring layer and includes an insulating material and hydrogen, and An upper wiring hydrogen diffusion barrier layer, which is located on the upper wiring hydrogen diffusion layer, The insulating material of the upper wiring hydrogen diffusion layer includes at least one of silicon nitride, silicon oxide, and tetraethyl orthosilicate. The upper wiring hydrogen diffusion barrier layer comprises silicon nitride, and The hydrogen diffusion barrier layer of the upper wiring has a lower hydrogen diffusivity than the hydrogen diffusion layer of the upper wiring.

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