Semiconductor device and method for forming the same, electronic device

Abstract

The application discloses a semiconductor device and a forming method and an electronic device, word line structures are coupled on the same side of a vertical channel structure, the spacing between the word line structures of adjacent vertical transistors is controlled in the same range, the word line coupling effect can be improved, meanwhile, the word line structures are effectively isolated and the word line coupling effect is further inhibited through the design of a specific surrounding structure of a dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same, and an electronic device. Background Technology

[0002] With the development of semiconductor technology, the manufacturing process of DRAM (Dynamic Random Access Memory) has advanced to 10nm and below. In order to break through the area bottleneck of the traditional planar 1T1C (1 Transistor 1 Capacitor) structure of 6F² (6 times feature size squared) and achieve higher density and lower cost, the industry has turned to the VCT (Vertical Channel Transistor) architecture, whose theoretical cell area can be reduced to 4F².

[0003] Currently, VCT architectures often employ a face-to-face, back-to-back ring layout design. While this design is compact, it results in extremely small word line (WL) spacing between adjacent transistors, leading to a severe word line coupling effect. This effect causes signal crosstalk, increases noise, and consequently affects the read / write stability and electrical performance of DRAM.

[0004] Therefore, there is an urgent need for a new layout structure that can effectively improve the WL coupling effect without sacrificing integration. Summary of the Invention

[0005] This application provides a semiconductor device and a method for forming the same, to at least partially solve the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a semiconductor device is provided, comprising: a plurality of vertical channel structures extending in a first direction and spaced apart in a second direction and a third direction; word line structures extending in the second direction and coupled to the same side of the vertical channel structures; a dielectric layer covering the periphery of the word line structures in the first direction and the third direction; the second direction being perpendicular to the third direction, and the first direction being perpendicular to the second direction and the third direction; the dielectric layer comprising a first enclosure structure located on both sides of the word line structures in the first direction, a second enclosure structure located on both sides of the word line structures in the third direction, and a dielectric isolation layer located between the first enclosure structure and the second enclosure structure.

[0007] Optionally, the materials of the first enclosure structure and the second enclosure structure include the same dielectric material, and the materials of the first enclosure structure and the second enclosure structure are different from the dielectric material of the dielectric isolation layer.

[0008] Optionally, both the first and second enclosing structures are made of silicon oxide, and the dielectric isolation layer is made of a spin-coated dielectric material.

[0009] Optionally, in the first direction, the first enclosure structure includes a first substructure located at the top of the word line structure and a second substructure located at the bottom of the word line structure; wherein the second substructure extends upward from the third party and forms an L-shaped semi-enclosed structure, and the dielectric isolation layer is located on the semi-enclosed structure of the second substructure.

[0010] Optionally, in the third direction, the second surrounding structure includes a third substructure and a fourth substructure located on both sides of the word line structure, the third substructure being located between the word line structure and the vertical channel structure, and the dielectric isolation layer being located between the fourth substructure and the word line structure.

[0011] Optionally, in the third direction, the thickness of the dielectric isolation layer is greater than the thickness of the third substructure or the fourth substructure.

[0012] Optionally, in the first direction, the length of the dielectric isolation layer is greater than the length of the word line structure.

[0013] Optionally, the dielectric isolation layer has an air gap that extends in the second direction.

[0014] Optionally, in the first direction, the length of the air gap is greater than that of the character line structure.

[0015] Optionally, in the first direction, a conductive stacking structure is provided on the top of the vertical channel structure, the conductive stacking structure including a stacked polycrystalline silicon layer, a cobalt silicide layer and a tungsten layer.

[0016] According to a second aspect of this application, a method for forming a semiconductor device is provided, comprising forming a vertical channel structure extending in a first direction on a substrate, wherein a first trench is formed between two adjacent vertical channel structures, the first trench extending in a second direction; a word line structure and a dielectric layer are formed in the first trench, the dielectric layer comprising a first surrounding structure located on both sides of the word line structure in the first direction, a second surrounding structure located on both sides of the word line structure in a third direction, and a dielectric isolation layer located between the first surrounding structure and the second surrounding structure; the second direction is perpendicular to the third direction, and the first direction is perpendicular to the second direction and the third direction.

[0017] Optionally, forming the word line structure and dielectric layer in the first trench includes: forming a bottom dielectric layer located on the surface of the substrate and a side dielectric layer located on one side of the vertical channel structure in the first trench; filling the first trench with conductive material to form an initial word line and forming a top dielectric layer above the initial word line; etching a portion of the top dielectric layer, the initial word line, and the bottom dielectric layer to form a second trench, the remaining initial word line forming a word line structure extending along a second direction, the remaining top dielectric layer and the bottom dielectric layer forming a first surrounding structure, and the side dielectric layer forming a second surrounding structure; and forming a dielectric isolation layer in the second trench.

[0018] Optionally, after forming the dielectric isolation layer, the method further includes: forming a hard mask, the hard mask including a mask opening located above the vertical channel; the mask opening exposing the top of the vertical channel structure; and using the hard mask to form a conductive stack structure above the vertical channel, the conductive stack structure being located within the mask opening.

[0019] Optionally, the method of forming the conductive stacked structure includes: sequentially stacking a polycrystalline silicon layer, a cobalt silicide layer, and a tungsten layer within the mask opening.

[0020] Optionally, the method of forming a vertical channel structure extending in a first direction on a substrate further includes: providing a substrate; patterning the substrate to form a substrate and a plurality of initial channels located on the surface of the substrate, the plurality of initial channels extending in a third direction and spaced apart in a second direction; forming a stacked dielectric layer of oxide-nitride-oxide in a spacer region between adjacent initial channels; forming an etch barrier layer over the initial channels and the stacked dielectric layer; patterning the initial channels and the stacked dielectric layer to form a vertical channel structure, a stacked dielectric layer located within the vertical channel structure, and an etch barrier layer located on the surface of the vertical channel structure and the stacked dielectric layer.

[0021] Optionally, the method of forming a dielectric layer in the first trench, the dielectric layer including a bottom dielectric layer located on the surface of the substrate and a side dielectric layer located on one side of the vertical trench structure, further includes: forming a bottom dielectric layer in the first trench; forming a sacrificial layer on the surface of the bottom dielectric layer, the surface of the sacrificial layer being lower than the top surface of the vertical trench structure; forming a protective layer on the exposed side of the vertical trench structure, the protective layer being connected to the etching barrier layer to form a protective structure located at the top and part of the side of the vertical trench structure; and replacing the sacrificial layer with the side dielectric layer.

[0022] Optionally, the method of filling the first trench with conductive material to form an initial word line and forming a top dielectric layer above the initial word line includes: filling the first trench with conductive material to form an initial word line; etching back the initial word line so that the surface of the initial word line is lower than the opening of the first trench; and forming a top dielectric layer above the initial word line.

[0023] Optionally, after the patterning process, a second trench is formed in the first trench, and after the method of forming a dielectric isolation layer in the second trench, the method includes: forming a hard mask, the hard mask including a mask opening located above the vertical trench; and using the hard mask to form a conductive stack structure above the vertical trench, the conductive stack structure being located within the mask opening.

[0024] Optionally, the method of forming a hard mask, the hard mask including a mask opening located above the vertical channel, includes: forming a hard mask material layer above the substrate; forming a first etch stop material layer above the hard mask layer; patterning the first etch stop material layer to form first etch stop patterns spaced apart in three directions; forming an isolation layer above the hard mask layer, the isolation layer covering the first etch stop patterns and the gap region between two adjacent first etch stop patterns; forming a second etch stop material layer above the hard mask layer; patterning the second etch stop material layer and the isolation layer to form a second etch stop pattern spaced apart in two directions; the first etch stop patterns and the second etch stop patterns avoid the vertical channel structure, and a portion of the isolation layer is located above the vertical channel structure, forming an etch mask; using the etch mask to pattern the hard mask material layer, forming a mask opening on the hard mask material layer that exposes above the vertical channel, forming the hard mask.

[0025] Optionally, after forming the hard mask, the hard mask including a mask opening located above the vertical channel, the method further includes: using the hard mask to pattern the vertical channel structure to form a groove at the top of the vertical channel; and forming the conductive stack structure within the mask opening of the hard mask, the conductive stack structure being partially located within the groove.

[0026] According to a third aspect of this application, an electronic device is provided, comprising the semiconductor device described above, or a semiconductor device prepared according to the forming method described above.

[0027] In the semiconductor device and formation method of this application embodiment, the word line structure is coupled to the same side of the vertical channel structure, and the word line structure spacing of adjacent vertical transistors is controlled within the same range, which can improve the word line coupling effect. At the same time, through the design of a dielectric layer with a specific surrounding structure, the word line structure is effectively isolated and the word line coupling effect is further suppressed, ensuring the reliable operation of the semiconductor device.

[0028] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0030] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure provided in an exemplary embodiment of this disclosure.

[0031] Figure 3 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 1 ; Figure 4 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 1 The resulting semiconductor structure.

[0032] Figure 5 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 2 ; Figure 6 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 2 The resulting semiconductor structure.

[0033] Figure 7 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 3 ; Figure 8 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 3 The resulting semiconductor structure.

[0034] Figure 9 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 4 ; Figure 10 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 4 The resulting semiconductor structure.

[0035] Figure 11 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 5 ; Figure 12 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 5 The resulting semiconductor structure.

[0036] Figure 13 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 6 ; Figure 14 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 6 The resulting semiconductor structure.

[0037] Figure 15 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 7 ; Figure 16 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 7 The resulting semiconductor structure.

[0038] Figure 17 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 8 ; Figure 18 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 8 The resulting semiconductor structure.

[0039] Figure 19 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 9 ; Figure 20 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 9 The resulting semiconductor structure.

[0040] Figure 21 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 ; Figure 22 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 The resulting semiconductor structure.

[0041] Figure 23 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 one; Figure 24 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 A semiconductor structure is formed.

[0042] Figure 25 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 two; Figure 26 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 The resulting semiconductor structure.

[0043] Figure 27 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 three; Figure 28 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 The semiconductor structure formed by the three.

[0044] Figure 29 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 Four; Figure 30 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 The semiconductor structure formed by the four.

[0045] Figure 31 This is a schematic diagram of the semiconductor structure fabrication process provided in the exemplary embodiments of this disclosure. Figure 10 five; Figure 32 This is a schematic diagram of the preparation process in an exemplary embodiment of this disclosure. Figure 10 The semiconductor structure formed by five.

[0046] Explanation of reference numerals in the attached figures: W1 / W2 / W3, spacing between adjacent character lines; D1, First Direction; D2, Second Direction; D3, Third Direction; 101. Vertical channel structure; 102. Initial channel; 201. Character line structure; 202. Initial character line; 30. Dielectric layer; 301. First enclosure structure; 302. Second enclosure structure; 303. Third substructure; 304. Fourth substructure; 305. Second substructure / bottom dielectric layer; 306. Side dielectric layer; 307. First substructure / top dielectric layer; 308. Stacked dielectric layers; 401. Dielectric isolation layer; 402. Air gap; 50. Conductive stacked structure; 501. Polycrystalline silicon; 502. Cobalt silicide layer; 503. Tungsten layer; 504. Groove; 601, First trench; 602, Second trench; 70. Base; 80. Etching barrier layer; 801. Sacrificial layer; 802. Protective structure; 803. Hard mask; 804. Mask opening; 805. First etch barrier pattern; 806. Second etch barrier pattern; 807. Isolation layer. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0048] Traditional dynamic random access memory (DRAM) manufacturing processes using vertical channel transistor architectures often result in extremely small spacing between adjacent word lines (WLs) due to face-to-face or back-to-back ring layouts, leading to severe word line coupling. This effect causes signal crosstalk, increases noise, and consequently affects the read / write stability and electrical performance of DRAM. Therefore, a novel structure is urgently needed to improve coupling without sacrificing integration density.

[0049] Please see Figure 1 and Figure 2This application proposes a semiconductor device that effectively isolates word line structures 201 by designing a dielectric layer 30 with a multilayer surrounding structure, thereby significantly reducing capacitive coupling between adjacent word lines while maintaining high integration. The semiconductor device includes multiple vertical channel structures 101 extending in a first direction D1 and spaced apart in a second direction D2 and a third direction D3. The word line structures 201 extend in the second direction D2 and are coupled to the same side of the vertical channel structures 101. Crucially, the dielectric layer 30 is located between the word line structures 201 and the vertical channel structures 101, and covers the periphery of the word line structures 201 in the first direction D1 and the third direction D3. The dielectric layer 30 is further subdivided into first surrounding structures 301 located on both sides of the word line structures 201 in the first direction D1, second surrounding structures 302 located on both sides of the word line structures 201 in the third direction D3, and a dielectric isolation layer 401 located between the first surrounding structures 301 and the second surrounding structures 302. This layered surrounding and isolation design effectively blocks capacitive coupling paths.

[0050] The semiconductor device in this embodiment includes multiple vertical channel structures 101. The vertical channel structures 101 can be columnar structures, with their main bodies extending upwards along a first direction D1 (e.g., perpendicular to the surface of the substrate 70). These columnar structures can be arranged in a regular array on a second direction D2 and a third direction D3, forming multiple independent transistor channels. Alternatively, the vertical channel structures 101 can also be finned structures, extending along the first direction D1 and spaced apart along the second direction D2, while forming continuous fins along the third direction D3. This structure also provides multiple independent conductive channels.

[0051] The word line structure 201 extends in the second direction D2 and is coupled to the same side of the vertical channel structure 101. The word line structure 201 can be configured as an elongated conductive structure with its primary extension direction parallel to the second direction D2. The word line structure 201 is arranged to contact or couple through a specific side of each of the plurality of vertical channel structures 101. The word line structure 201 can be formed by filling a trench extending along the second direction D2 and adjacent to one side of the vertical channel structure 101 with a conductive material. The conductive material can include polysilicon 501, a metal, or a combination thereof.

[0052] A dielectric layer 30 is located between the word line structure 201 and the vertical channel structure 101, and covers the periphery of the word line structure 201 in the first direction D1 and the third direction D3. The second direction D2 and the third direction D3 are perpendicular to each other, and the first direction D1 is perpendicular to the second direction D2 and the third direction D3. The dielectric layer 30 can be made of a single dielectric material, such as an oxide or a nitride, and is formed in the space between the word line structure 201 and the vertical channel structure 101 by a deposition process. The dielectric layer 30 is designed to cover the top, bottom, and both sides (along the third direction D3) of the word line structure 201. The dielectric layer 30 can also be formed by multilayer deposition, for example, depositing a thin oxide layer first, followed by a nitride layer, to provide composite insulation properties. These layers together achieve the coverage of the periphery of the word line structure 201 in the first direction D1 and the third direction D3.

[0053] The dielectric layer 30 includes a first surrounding structure 301 located on both sides of the word line structure 201 in a first direction D1, a second surrounding structure 302 located on both sides of the word line structure 201 in a third direction D3, and a dielectric isolation layer 401 located between the first surrounding structure 301 and the second surrounding structure 302. The first surrounding structure 301 may be made of one or more layers of dielectric material and is disposed on the top and bottom surfaces of the word line structure 201. The second surrounding structure 302 may be made of dielectric material and is disposed on both sides of the word line structure 201 along the third direction D3.

[0054] The semiconductor device proposed in this application effectively achieves electrical insulation of the word line structure 201 in multiple directions by introducing a dielectric layer 30 with a multi-layered surrounding structure in a vertical channel transistor architecture. The first surrounding structure 301 and the second surrounding structure 302 provide basic coverage of the word line structure 201 from different directions, while the dielectric isolation layer 401 located between them provides an additional isolation barrier. This significantly increases the length of the effective capacitive coupling path between adjacent word lines and reduces the coupling strength. This helps to mitigate the word line coupling effect prevalent in dynamic random access memory, thereby improving signal crosstalk and noise, and ultimately enhancing the read / write stability and overall electrical performance of the device. Continue reading Figure 1 and Figure 2 This application further proposes that the materials of the first surrounding structure 301 and the second surrounding structure 302 include the same dielectric material, and the materials of the first surrounding structure 301 and the second surrounding structure 302 are different from the dielectric material of the dielectric isolation layer 401.

[0055] Specifically, the first surrounding structure 301 and the second surrounding structure 302 are made of the same dielectric material, meaning that the insulating structure surrounding the word line structure 201 in the first direction D1 and the third direction D3 uses a uniform dielectric material. For example, this uniform dielectric material can be silicon oxide (SiO2), which has good insulation properties and process compatibility; or it can be silicon nitride (Si3N4), which has a relatively high dielectric constant and provides stronger insulation. This uniform material selection helps simplify the manufacturing process and ensures the consistency and reliability of the insulating layer around the word line structure 201. Meanwhile, the materials of the first surrounding structure 301 and the second surrounding structure 302 are different from the dielectric material of the dielectric isolation layer 401, which introduces material differences within the dielectric layer 30. For example, when the first surrounding structure 301 and the second surrounding structure 302 use silicon oxide, the dielectric isolation layer 401 can use a spin-on dielectric (SOD) material, which typically has a lower dielectric constant, or it can be designed with an air gap 402 to further reduce the overall dielectric constant. Furthermore, the dielectric isolation layer 401 can also be made of porous dielectric materials or low dielectric constant materials such as SiCOH. This material difference can effectively optimize the electrical properties of the dielectric layer 30.

[0056] By employing the aforementioned technical solution, this application ensures the consistency and structural stability of the insulating layer surrounding the word line structure 201 by limiting the use of the same dielectric material for the first surrounding structure 301 and the second surrounding structure 302, while simplifying the manufacturing process. More importantly, by using different materials for the first surrounding structure 301 and the second surrounding structure 302 compared to the dielectric isolation layer 401, this application introduces a significant difference in dielectric constant within the dielectric layer 30. This difference allows the dielectric isolation layer 401 to more effectively block electrical signal interference, thereby significantly reducing coupling interference between adjacent word lines. Therefore, this solution effectively reduces signal crosstalk and noise, improves the read / write stability and overall electrical performance of semiconductor devices, especially in high-density DRAM applications, effectively improving word line coupling effects, thereby enhancing device reliability and performance without sacrificing integration density. This application further proposes that in the above-mentioned semiconductor device, the materials of the first enclosure structure 301 and the second enclosure structure 302 both include silicon oxide, and the material of the dielectric isolation layer 401 includes a spin-coated dielectric material.

[0057] Specifically, both the first enclosure structure 301 and the second enclosure structure 302 are made of silicon oxide. Silicon oxide (SiO2) is a dielectric material widely used in semiconductor manufacturing, characterized by excellent insulation properties, high dielectric strength, good thermal stability, and good compatibility with silicon-based processes. Silicon oxide can effectively block current leakage, providing reliable electrical isolation between the word line structure 201 and the vertical channel structure 101.

[0058] Meanwhile, the material of the dielectric isolation layer 401 includes a spin-on dielectric material. Spin-on dielectric (SOD) materials are a type of dielectric material that forms a thin film on the wafer surface through a spin-coating process. These materials typically exist in the form of a liquid precursor, which is uniformly spread under high-speed rotation and then forms a solid dielectric layer 30 through subsequent baking, curing, and other steps. Spin-on dielectric materials are widely used in semiconductor manufacturing due to their excellent planarization ability and ability to fill tiny gaps, and are especially suitable for filling and isolating complex three-dimensional structures.

[0059] Through the above technical solution, the materials of the first surrounding structure 301 and the second surrounding structure 302 are specified as silicon oxide. Utilizing the inherent high insulation and stability of silicon oxide, reliable electrical isolation between the word line structure 201 and the vertical channel structure 101 is ensured, effectively preventing leakage and electrical interference. The good process compatibility of silicon oxide also makes it easy to integrate in existing semiconductor processes, ensuring manufacturing reliability. Simultaneously, the material of the dielectric isolation layer 401 is specified as a spin-on dielectric material. Utilizing its excellent filling ability and planarization characteristics, it can efficiently fill the tiny gaps between the word line structures 201, forming a dense and continuous isolation layer. This dense isolation layer can significantly increase the capacitance distance between adjacent word line structures 201, thereby effectively reducing parasitic capacitance and suppressing word line coupling effects. This differentiated material selection allows each material to exert its optimal characteristics: silicon oxide provides robust interface isolation, while the spin-on dielectric material provides excellent gap filling and low dielectric constant characteristics. This combination not only optimizes the isolation between the word line structure 201 and the channel, but more importantly, it significantly reduces the coupling capacitance between adjacent word lines through the effective filling and low dielectric properties of the spin-coated dielectric material, thereby effectively suppressing the word line coupling effect. This application discloses a semiconductor device in which, in a first direction D1, a first enclosure structure 301 includes a first substructure 307 located at the top of a word line structure 201 and a second substructure 305 located at the bottom of the word line structure 201; wherein, the second substructure 305 extends in a third direction D3 and forms an L-shaped semi-enclosed structure, and a dielectric isolation layer 401 is located on the semi-enclosed structure of the second substructure 305. In the third direction D3, a second enclosure structure 302 includes a third substructure 303 and a fourth substructure 304 located on both sides of the word line structure 201, wherein the third substructure 303 is located between the word line structure 201 and the vertical channel structure 101, and the dielectric isolation layer 401 is located between the fourth substructure 304 and the word line structure 201.

[0060] Specifically, the first substructure 307 refers to the portion of the first enclosing structure 301 located in the top region of the word line structure 201. The main function of this first substructure 307 is to provide electrical isolation and structural support for the top of the word line structure 201. The second substructure 305 refers to the portion of the first enclosing structure 301 located in the bottom region of the word line structure 201. The key function of this second substructure 305 is to provide enhanced isolation and structural integrity for the lower part of the word line structure 201, especially in areas where strong coupling effects may occur.

[0061] The second substructure 305 extends along the third direction D3 to form an L-shaped semi-enclosed structure, defining the specific geometry and spatial arrangement of the second substructure 305. The L-shaped semi-enclosed structure means that the structure not only extends below the word line structure 201 but also partially surrounds one or more sides of the word line structure 201 along the third direction D3, thus providing more comprehensive coverage and isolation. This extension indicates its continuity along the third direction D3.

[0062] The third substructure 303 and the fourth substructure 304 refer to the portions of the second enclosure structure 302 located on both sides of the word line structure 201 along the third direction D3. The third substructure 303 is located between the word line structure 201 and the vertical channel structure 101, and is used to achieve electrical isolation between the word line structure 201 and the vertical channel structure 101; the fourth substructure 304 is located on the opposite side of the word line structure 201, and is used to enhance the electrical isolation between adjacent word line structures 201 and reduce the coupling effect.

[0063] The dielectric isolation layer 401 is located on the semi-enclosed structure of the second substructure 305, which clarifies the relative position of the dielectric isolation layer 401 with respect to the L-shaped semi-enclosed structure formed by the second substructure 305. This means that the dielectric isolation layer 401 is placed directly on or adjacent to the L-shaped structure, thereby utilizing the enhanced bottom isolation provided by the second substructure 305.

[0064] Through the above technical solution, the first surrounding structure 301 is refined into a first substructure 307 located at the top of the word line structure 201 and a second substructure 305 located at the bottom of the word line structure 201. The second substructure 305 forms an L-shaped semi-enclosed structure in the third direction D3. This application can significantly enhance the isolation effect in the bottom region of the word line structure 201. The second surrounding structure is refined into a third substructure 303 located between the word line structure 201 and the vertical channel structure 101. A dielectric isolation layer 401 is disposed between the fourth substructure 304 and the word line structure 201, ensuring electrical isolation between the word line structure 201 and the vertical channel structure 101 and reducing the coupling effect between adjacent word line structures 201. The dielectric isolation layer 401 is directly located on this L-shaped semi-enclosed structure, further ensuring sufficient and effective dielectric isolation in the critical region at the bottom of the word line structure 201, which is susceptible to coupling effects.

[0065] This application further proposes that, in the first direction D1, the length of the dielectric isolation layer 401 is greater than the length of the word line structure 201. Specifically, the dielectric isolation layer 401 is a material layer used to provide electrical insulation and isolation, and its main function is to reduce capacitive coupling between adjacent conductive structures, thereby suppressing signal crosstalk and noise. In semiconductor devices, the dielectric isolation layer 401 is typically made of a material with a low dielectric constant, such as silicon oxide, silicon nitride, or spin-coated dielectric materials. Its length in the first direction D1 refers to its dimension along the axis perpendicular to the second direction D2 and the third direction D3. The word line structure 201 is a control electrode in a semiconductor device, which controls the conduction and cutoff of the vertical channel structure 101 by applying a voltage. The word line structure 201 is typically made of a conductive material, and its length in the first direction D1 refers to its dimension along the axis perpendicular to the second direction D2 and the third direction D3.

[0066] The length of the dielectric isolation layer 401 is greater than the length of the word line structure 201, which means that the extension of the dielectric isolation layer 401 in the first direction D1 (i.e., in the vertical direction, considering that the word line structure 201 has a top and a bottom) exceeds the physical boundary of the word line structure 201.

[0067] Through the above technical solution, the dielectric isolation layer 401 extends beyond the physical boundary of the word line structure 201 in the first direction D1, especially in the top and bottom regions of the word line structure 201, providing a more comprehensive physical isolation barrier. Given that the word line structure 201 has a top and bottom in the first direction D1, this extending design ensures that the dielectric isolation layer 401 can effectively cover and isolate these critical regions of the word line structure 201, thereby significantly increasing the effective isolation distance and dielectric thickness between adjacent word line structures 201. The reduction in parasitic capacitance effectively suppresses capacitive coupling effects between word lines, reduces signal crosstalk and noise, and thus improves the electrical stability and reliability of the semiconductor device. This application further proposes that, on the third-direction D3, the thickness of the dielectric isolation layer 401 is greater than the thickness of the portion of the enclosure structure (third substructure 303 or fourth substructure 304) of the second enclosure structure 302 located on either side of the word line structure 201.

[0068] Specifically, the third direction D3 is a key spatial dimension in a semiconductor device, perpendicular to both the first direction D1 and the second direction D2. In the structure of a semiconductor device, the third direction D3 typically refers to the lateral dimension orthogonal to both the extension direction of the vertical channel structure 101 and the extension direction of the word line structure 201. This directional definition clarifies the spatial dimension targeted for thickness comparison and optimization, ensuring precise control over capacitive coupling in specific directions. The thickness of the dielectric isolation layer 401 refers to its physical dimension in the third direction D3. The dielectric isolation layer 401 is a structure made of dielectric material, and its main function is to provide electrical insulation between adjacent conductive structures. Its dimensions in a specific direction directly affect its electrical insulation capability and its suppression effect on electric field coupling.

[0069] Through the above technical solution, this application significantly enhances the dielectric isolation effect on the third-direction D3 by increasing the thickness of the dielectric isolation layer 401 to exceed the thickness of the portion of the second surrounding structure 302 surrounding the word line structure 201 located on either side. This design effectively strengthens the electrical insulation between the word line structure 201 and adjacent structures, significantly reduces word line capacitive coupling on the third-direction D3, and thus suppresses signal crosstalk and noise generation. Consequently, the read / write stability of the semiconductor device is significantly improved, and the electrical performance is optimized, effectively addressing the technical requirement to improve word line coupling effects without sacrificing integration density. This application further proposes a semiconductor device in which the dielectric isolation layer 401 has an air gap 402 extending in the second direction D2.

[0070] Air gap 402 refers to a cavity formed within the dielectric material or its structure that does not contain solid or liquid media; its interior is typically a vacuum or filled with air, inert gas, etc. The main purpose of introducing air gap 402 is to significantly reduce the overall effective dielectric constant of the dielectric isolation layer 401 by utilizing its extremely low dielectric constant (for example, the dielectric constant of air is approximately 1, far lower than the approximately 3.9 of commonly used solid dielectric materials such as silicon oxide). This is crucial for weakening electric field coupling effects.

[0071] The second direction D2 is the extension direction of the word line structure 201, and also the direction in which the multiple vertical channel structures 101 are spaced apart. The air gap 402 extends along the second direction D2, meaning that the length direction of the air gap 402 is parallel to the length direction of the word line structure 201, thereby ensuring that the air gap 402 can provide a continuous and uniform low-dielectric isolation region along the entire effective length of the word line structure 201. This directional extension is crucial for effectively isolating electric field coupling along the length direction of the word line structure 201.

[0072] In the first direction D1, the length of the air gap 402 is greater than the length of the word line structure 201. Similarly, as part of the dielectric isolation layer 401, the air gap 402 extends beyond the physical boundary of the word line structure 201 in the first direction D1, especially in the top and bottom regions of the word line structure 201, thus providing a more comprehensive physical isolation barrier.

[0073] By introducing an air gap 402 within the dielectric isolation layer 401 and extending the air gap 402 along the second direction D2, the effective dielectric constant of the dielectric isolation layer 401 is significantly reduced. Since the dielectric constant of a gas is much lower than that of a solid dielectric material, this structure effectively weakens the capacitive coupling effect between adjacent word line structures 201, thereby reducing signal crosstalk and noise. The uniform distribution of the air gap 402 along the second direction D2 (i.e., the extension direction of the word line structure 201) ensures comprehensive and consistent isolation along the length of the word line structure 201, further improving the electrical performance of the semiconductor device and the read / write stability of the DRAM. This design effectively solves the problem of insufficient isolation caused by the high dielectric constant of the dielectric isolation layer 401 in the prior art without increasing the device size, providing an effective solution for achieving higher density and more stable semiconductor devices. This application further proposes a semiconductor device in which a conductive stacked structure 50 is disposed on the top of a vertical channel structure 101 in a first direction D1. The conductive stacked structure 50 includes a polysilicon layer 501, a cobalt silicide layer 502, and a tungsten layer 503 stacked together.

[0074] Specifically, a conductive stack structure 50 is provided on top of the vertical channel structure 101, designed to provide an efficient and low-resistance electrical connection point for the vertical channel structure 101, typically used to connect upper-layer capacitor structures or interconnects. This arrangement ensures that current can be smoothly transmitted from the vertical channel structure 101 to the upper-layer circuitry and vice versa, thereby optimizing the signal transmission path. Its precise position in the first direction D1 is crucial for maintaining the electrical performance of the device, avoiding signal attenuation due to poor contact or excessively long paths.

[0075] The conductive stacked structure 50 is a composite structure composed of multiple conductive materials stacked layer by layer. Its design aims to comprehensively optimize electrical performance, such as reducing contact resistance, increasing conductivity, enhancing mechanical stability, or improving thermal management. By selecting different materials and stacking them appropriately, comprehensive performance that is difficult to achieve with a single material can be realized. In addition to the materials mentioned in this application, the conductive stacked structure 50 may also include a titanium silicide layer, a nickel silicide layer, an aluminum layer, a copper layer, or a combination thereof.

[0076] The polycrystalline silicon 501 layer, as one of the base layers of the conductive stacked structure 50, is typically in direct contact with the semiconductor vertical channel structure 101. Its main function is to provide an ohmic contact compatible with silicon-based materials and with good interface quality, thereby effectively reducing contact resistance. The doping concentration and grain size of the polycrystalline silicon 501 can be optimized to further improve its conductivity. Besides polycrystalline silicon 501, doped amorphous silicon or microcrystalline silicon can also be used as the bottom layer for contacting the channel to achieve a similar low-resistance contact effect.

[0077] The cobalt silicide layer 502 is typically located above the polycrystalline silicon layer 501. Its main function is to further reduce contact resistance and improve the interface characteristics between the polycrystalline silicon 501 and the upper metal layer. Cobalt silicides have low resistivity and good thermal stability, which can effectively improve current conduction efficiency and reduce energy loss. In addition to cobalt silicides, other metal silicides such as nickel silicides and titanium silicides can also be used as alternative materials, which also provide excellent low-resistance contact performance.

[0078] The tungsten layer 503, serving as the uppermost or main conductive layer of the conductive stack structure 50, provides highly conductive interconnect paths to ensure fast and stable signal transmission. Tungsten, with its high melting point, good electromigration resistance, and compatibility with silicon-based processes, is a commonly used metal material in integrated circuits. Its high conductivity helps reduce overall circuit resistance and RC delay. Besides tungsten, copper, aluminum, or their alloys can also be used as highly conductive metal layers, but their process compatibility and electromigration characteristics must be considered.

[0079] By employing the aforementioned technical solution, a conductive stacked structure 50, composed of a polysilicon 501 layer, a cobalt silicide layer 502, and a tungsten layer 503, is disposed on top of the vertical channel structure 101. This significantly optimizes the electrical connection between the vertical channel structure 101 and upper interconnects (such as capacitor structures). The polysilicon 501 layer ensures good interface contact with the semiconductor channel, effectively reducing the initial contact resistance; the cobalt silicide layer 502 further reduces the contact resistance to an extremely low level, improving current conduction efficiency; and the tungsten layer 503, as a highly conductive metal, provides an efficient signal transmission path, reducing the overall line resistance. Please see Figures 3-32 Based on the aforementioned semiconductor device structure, this application further proposes a method for forming a semiconductor device. By designing a multilayer dielectric surrounding structure and a dielectric isolation layer 401, the word line structure 201 is effectively isolated, thereby significantly reducing capacitive coupling between adjacent word lines while maintaining high integration. In this embodiment, the first surrounding structure 301 and the second surrounding structure 302 are combined in a layered surrounding manner, and a dielectric isolation layer 401 is introduced between them, thereby forming a continuous insulating barrier in multiple directions of the word line structure 201. This effectively blocks the capacitive coupling path between adjacent word line structures 201, achieving the effect of significantly reducing word line coupling effect and improving DRAM read / write stability and electrical performance.

[0080] See Figures 15 to 20 Specifically, the method for forming a semiconductor device according to embodiments of this application includes: forming a vertical channel structure 101 extending in a first direction D1 on a substrate 70, and forming a first trench 601 between two adjacent vertical channel structures 101; forming a dielectric layer 30 in the first trench 601, the dielectric layer 30 including a bottom dielectric layer 305 located on the surface of the substrate 70 and a side dielectric layer 306 located on one side of the vertical channel structure 101; filling the first trench 601 with conductive material to form an initial word line 202, and forming a top dielectric layer 307 above the initial word line 202; and etching a portion of the top dielectric layer. 307. The initial word line 202 and the bottom dielectric layer 305 form a second trench 602. The remaining initial word line 202 forms a word line structure 201. The remaining top dielectric layer 307 and the bottom dielectric layer 305 form a first surrounding structure 301. The first surrounding structure 301 is located on both sides of the word line structure 201 in the first direction D1. The side dielectric layer 306 forms a second surrounding structure 302. The second surrounding structure 302 is located on both sides of the word line structure 201 in the third direction D3. A second trench 602 is formed in the first trench 601. A dielectric isolation layer 401 is formed in the second trench 602.

[0081] Through the above technical solution, the bottom dielectric layer 305 isolates the word line structure 201 from the substrate 70 to reduce bottom parasitic capacitance, and the side dielectric layer 306 isolates the word line structure 201 from the vertical channel structure 101 to reduce lateral interference. The initial word line 202 serves as a prototype for the word line structure 201 for easier subsequent processing, and the top dielectric layer 307 provides upper isolation to initially reduce coupling risks. Patterning reduces the structural dimensions, while a second trench 602 is formed within the first trench 601, creating additional space for the introduction of the dielectric isolation layer 401. The first surrounding structure 301 is located on both sides of the word line structure 201 in the first direction D1, and the second surrounding structure 302 is located on both sides of the word line structure 201 in the third direction D3. These surrounding structures provide an all-around insulation barrier, enhancing the isolation of the word line structure 201. The dielectric isolation layer 401 fills the space formed after thinning, further blocking electrical signal crosstalk between adjacent word line structures 201, thereby significantly reducing word line coupling effects. Since the first enclosure structure 301 and the second enclosure structure 302 form a continuous insulating cover around the word line structure 201, and combined with the additional isolation effect of the dielectric isolation layer 401, the effective capacitive coupling path length between adjacent word lines is effectively increased, the coupling strength is reduced, and thus the read / write stability and overall electrical performance of the DRAM are improved. like Figure 3 , Figure 4 As shown, this application further proposes a method for forming a vertical channel structure 101 extending in a first direction D1 on a substrate 70. The method includes: providing a substrate 70; patterning the substrate 70 to form the substrate 70 and a plurality of initial channels 102 located on the surface of the substrate 70, wherein the plurality of initial channels 102 extend in a third direction D3 and are spaced apart in a second direction D2.

[0082] like Figure 5 , Figure 6 As shown, a stacked dielectric layer 308 of oxide-nitride-oxide is formed in the interval region between adjacent initial channels 102; an etch barrier layer 80 is formed above the initial channels 102 and the stacked dielectric layer 308; the initial channels 102 and the stacked dielectric layer 308 are patterned to form a vertical channel structure 101, a stacked dielectric layer 308 located in the vertical channel structure 101, and an etch barrier layer 80 located on the surface of the vertical channel structure 101 and the stacked dielectric layer 308.

[0083] Specifically, providing the substrate 70 is the initial step in semiconductor device fabrication, providing the physical carrier for all subsequent processes. The substrate 70 can be made of various materials; for example, it can be a P-type or N-type doped single-crystal silicon wafer, which has good electrical properties and mature processing technology. Alternatively, to achieve better device isolation and reduce parasitic capacitance, an SOI (Silicon-On-Insulator) substrate 70 can be used, where the upper silicon layer is used to form the device, and the lower insulating layer provides natural electrical isolation.

[0084] Subsequently, the substrate 70 is patterned to form the substrate 70 and a plurality of initial channels 102 located on the surface of the substrate 70. These initial channels 102 extend along a third direction D3 and are spaced apart in a second direction D2. Their function is to precisely define the position, shape, and spacing of the vertical channel structures 101, laying the foundation for the formation of subsequent devices. This patterning process can be achieved in various ways. For example, it can be achieved by combining photolithography with dry etching. First, photoresist is coated on the surface of the substrate 70, and the desired pattern is formed by exposure and development using a mask. Then, plasma etching technology is used to precisely etch the substrate 70 to form the initial channels 102.

[0085] Based on this, a stacked dielectric layer 308 of oxide-nitride-oxide is formed in the interval region between adjacent initial channels 102. The main function of this stacked dielectric layer 308 is to provide electrical insulation and mechanical support, effectively isolating adjacent initial channels 102, thereby significantly reducing capacitive coupling between them. The method of forming this stacked dielectric layer 308 may include, for example, using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques to sequentially and precisely deposit a silicon dioxide (SiO2) layer, a silicon nitride (Si3N4) layer, and another silicon dioxide (SiO2) layer. ALD technology is particularly suitable for providing excellent film uniformity and step coverage; or, plasma-enhanced chemical vapor deposition (PECVD) technology may be used to deposit these dielectric films at relatively low temperatures to reduce thermal damage to the substrate 70.

[0086] Furthermore, an etch barrier layer 80 is formed above the initial channel 102 and the stacked dielectric layer 308. The function of this etch barrier layer 80 is to protect the underlying structure from damage during subsequent etching steps, ensuring the accuracy and reliability of the patterning process. Various materials and processes can be used to form the etch barrier layer 80. For example, silicon nitride (Si3N4) can be used as the etch barrier layer 80, deposited via PECVD or low-pressure chemical vapor deposition (LPCVD), as silicon nitride exhibits good selectivity for various etching processes. Alternatively, alumina (Al2O3) can also be used as the etch barrier layer 80, deposited via ALD technology, as alumina has a high dielectric constant and good etching selectivity.

[0087] like Figure 7 and Figure 8 As shown, finally, the initial channel 102 and the stacked dielectric layer 308 are patterned to form a vertical channel structure 101, a stacked dielectric layer 308 within the vertical channel structure 101, and an etch stop layer 80 on the surface of the vertical channel structure 101 and the stacked dielectric layer 308. This step aims to precisely define the final vertical channel structure 101 and ensure that the stacked dielectric layer 308 and the etch stop layer 80 are precisely aligned with the vertical channel structure 101, thereby forming a functional device unit. This patterning process can employ a combination of photolithography and dry etching (such as reactive ion etching (RIE) or deep reactive ion etching (DRIE)). First, photoresist is coated and patterned over the etch stop layer 80. Then, using the patterned photoresist as a mask, the etch stop layer 80, the stacked dielectric layer 308, and the initial channel 102 are etched sequentially to finally form the desired vertical channel structure 101.

[0088] Through the above technical solution, this application provides a precise and controllable method for forming a vertical channel structure 101. By providing a stable substrate 70 and fine patterning processing, the position and spacing of the initial channels 102 can be ensured to be highly accurate, thereby effectively controlling the distance between adjacent structures. A stacked dielectric layer 308 of oxide-nitride-oxide layers is formed in the spacing region between adjacent initial channels 102. Utilizing the excellent insulation and mechanical support provided by this multilayer structure, adjacent channels can be effectively isolated, signal crosstalk can be significantly suppressed, thereby alleviating word line (WL) coupling effects. In addition, the introduction of the etching barrier layer 80 can protect critical structures from damage during subsequent complex patterning processes, ensuring the accuracy and reliability of the manufacturing process.

[0089] This application further proposes a method for forming a dielectric layer 30 within the first trench 601, the dielectric layer 30 including a bottom dielectric layer 305 located on the surface of the substrate 70 and a side dielectric layer 306 located on one side of the vertical channel structure 101, the method comprising the following steps: like Figure 9 and Figure 10As shown, firstly, a bottom dielectric layer 305 is formed within the first trench 601. This step aims to provide basic electrical isolation for the subsequent word line structure 201, preventing unnecessary conduction or leakage between the word line structure 201 and the substrate 70. Specifically, the bottom dielectric layer 305 can be formed using chemical vapor deposition (CVD) methods, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), and the deposition material can be silicon dioxide, silicon nitride, or silicon oxynitride, etc. Alternatively, atomic layer deposition (ALD) technology can be used to achieve better film uniformity and step coverage.

[0090] like Figure 11 , Figure 12 As shown, next, a sacrificial layer 801 is formed on the surface of the bottom dielectric layer 305, the surface of which is lower than the top surface of the vertical trench structure 101. This step, by forming a removable sacrificial material on the surface of the bottom dielectric layer 305 and precisely controlling its surface height to be lower than the top surface of the vertical trench structure 101, provides precise space for the formation of the subsequent protective layer. The sacrificial layer 801 can be a spin-coated polymer material, such as photoresist or an organic planarization layer, achieved through a spin-coating and baking process. Alternatively, a dielectric material that is easily selectively etchable, such as a sacrificial oxide layer or a sacrificial nitride layer, can be deposited, and its height can be precisely controlled through an etch-back process.

[0091] Next, a protective layer is formed on the exposed sides of the vertical channel structure 101. This protective layer is connected to the etch barrier layer 80, forming a protective structure 802 located on the top and part of the sides of the vertical channel structure 101. This step aims to provide effective physical and chemical protection to the exposed sides of the vertical channel structure 101, preventing damage or contamination in subsequent process steps. The protective layer can be formed using conformal deposition techniques, such as atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD), to ensure the formation of a uniform and dense film on the complex three-dimensional surface of the vertical channel structure 101. The protective layer material can be a dielectric material such as silicon dioxide, silicon nitride, or silicon oxynitride. This protective layer is connected to the etch barrier layer 80, forming a continuous protective structure 802, thereby effectively sealing the top and part of the sides of the vertical channel structure 101.

[0092] like Figure 13 , Figure 14As shown, finally, the sacrificial layer 801 is replaced with the side dielectric layer 306. This step completes the construction of the dielectric layer 30 without damaging the already protected vertical channel structure 101 by removing the temporary sacrificial layer 801 and filling its original position with the final side dielectric material. Specifically, the sacrificial layer 801 can be removed by selective wet etching or dry etching processes, which are highly selective for the formed protective layer and vertical channel structure 101. After the sacrificial layer 801 is removed, the side dielectric layer 306 can be filled by methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin-on dielectric (SOD), and the material used can be silicon dioxide, silicon nitride, or a low dielectric constant material.

[0093] This application effectively solves the problem of susceptibility to damage or contamination on the exposed sides of the vertical channel structure 101 during the formation of the dielectric layer 30. Specifically, a bottom dielectric layer 305 is first formed to provide basic isolation support for the entire dielectric layer 30. Subsequently, a height-controlled sacrificial layer 801 is formed, reserving precise space for the subsequent construction of the protective layer and avoiding interference with the top region of the channel during the formation of the protective layer. Crucially, a protective layer is formed on the exposed sides of the vertical channel structure 101 and connected to the etching barrier layer 80, thereby forming a complete, sealed protective structure 802 that directly shields the critical areas of the channel from the effects of subsequent etchants or contaminants. Finally, by safely replacing the sacrificial layer 801 with a side dielectric layer 306, the side dielectric layer 306 is ensured to be precisely formed while the vertical channel structure 101 is adequately protected.

[0094] See Figures 13 to 16 This application further proposes a method for filling a first trench 601 with conductive material to form an initial word line 202 and forming a top dielectric layer 307 above the initial word line 202. The specific steps include: filling a first trench 601 with conductive material to form an initial word line 202; etching back the initial word line 202 so that the surface of the initial word line 202 is lower than the opening of the first trench 601; and forming a top dielectric layer 307 above the initial word line 202.

[0095] The purpose of "filling the first trench 601 with conductive material to form the initial word line 202" is to construct the basic conductive structure of the word line structure 201, providing support for the subsequent realization of the functions of the word line structure 201. Specifically, conductive materials such as polycrystalline silicon 501, metals (such as tungsten, titanium, tantalum) or their alloys can be uniformly filled into the first trench 601 using techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Alternatively, conductive materials can be deposited in the trench using methods such as physical vapor deposition (PVD) or electroplating, followed by planarization to form the initial word line 202.

[0096] "Etching back the initial word line 202 so that its surface is lower than the opening of the first trench 601" is a crucial step in precisely controlling the height of the initial word line 202. This step aims to reserve sufficient space for the subsequent formation of the top dielectric layer 307 and effectively prevent the top of the initial word line 202 from being exposed. Specifically, dry etching (such as reactive ion etching, RIE) can be used. By precisely controlling process parameters such as etching time, etching gas ratio, and power, a portion of the initial word line 202 material can be uniformly etched away from the top until its surface reaches the preset height lower than the opening of the first trench 601. Alternatively, wet etching can be used, selectively etching the conductive material. By controlling the concentration, temperature, and etching time of the etching solution, precise etching back of the initial word line 202 height can be achieved.

[0097] The purpose of forming a top dielectric layer 307 above the initial word line 202 is to provide effective insulation coverage, thereby enhancing the isolation between the word line structure 201 and other components and significantly reducing electrical signal interference. Specifically, a layer of insulating material, such as silicon oxide, silicon nitride, or a high dielectric constant material (such as HfO2), can be deposited using CVD or ALD techniques to form the top dielectric layer 307. Alternatively, the top dielectric layer 307 can be formed by spin-on dielectric (SOD) materials, such as spin-on silicon oxide (Spin-on Glass, SOG) or spin-on polymers, followed by curing.

[0098] The above technical solution first involves filling the first trench 601 with conductive material to form an initial word line 202, laying the foundation for the function of the word line structure 201. Then, by precisely etching back the initial word line 202, ensuring its surface is below the opening of the first trench 601, the problem of improper height control of the initial word line 202 is effectively solved, creating the necessary space for the uniform and sufficient formation of the top dielectric layer 307. Based on this, the top dielectric layer 307 is formed above the initial word line 202, ensuring complete insulation coverage of the top of the word line structure 201. These steps work synergistically, enabling the dielectric layer 30 to completely cover the word line structure 201, thereby significantly enhancing the isolation effect between the word line structure 201 and other components, effectively reducing electrical signal crosstalk, mitigating word line coupling effects, and improving the stability and electrical performance of the semiconductor device. This application further proposes a method for forming a semiconductor device. After forming the dielectric isolation layer 401, the method further includes forming a hard mask 803. The hard mask 803 includes a mask opening 804 located above the vertical channel structure 101, with the mask opening 804 exposing the top of the vertical channel structure. Specifically, the hard mask 803 is a highly selective and highly etch-resistant material layer. Its function is to precisely protect specific areas and define patterns during subsequent etching or deposition processes, thereby ensuring the accurate position and size of subsequent structures (e.g., the groove 504 and the conductive stack structure 50). The hard mask 803 can be formed in various ways. For example, one or more layers of hard mask 803 material can be deposited first. The material can include, but is not limited to, silicon oxide, silicon nitride, or carbon materials, and then patterned using photolithography and etching processes to form the desired mask opening 804. Alternatively, a self-aligned technique can be used, utilizing an existing structure (such as the vertical channel structure 101) as a template, and a hard mask 803 can be indirectly formed through processes such as sidewall deposition and etch-back, so that the mask opening 804 is precisely located above the vertical channel structure 101.

[0099] Based on this, the vertical channel structure 101 is patterned using the hard mask 803 to form a groove 504 on the top of the vertical channel structure 101. This step aims to precisely create a recessed region on the top of the vertical channel structure 101, providing space for the subsequent embedding of the conductive stack structure 50, thereby enhancing the mechanical connection and electrical contact between the conductive stack structure 50 and the vertical channel structure 101. The groove 504 can be formed by using the hard mask 803 as an etching mask after its formation, selectively etching the exposed top of the vertical channel structure 101 using anisotropic dry etching (e.g., reactive ion etching, RIE) to form the groove 504. The etching depth can be achieved by precisely controlling the etching time or by using a termination layer. Alternatively, wet etching can be used to selectively remove the material at the top of the vertical channel structure 101, but it must be ensured that the wet etching is sufficiently selective for the hard mask 803 and can achieve the desired anisotropic or isotropic etching morphology.

[0100] Subsequently, a conductive stacked structure 50 is formed within the mask opening 804 of the hard mask 803, with a portion of the conductive stacked structure 50 located within the groove 504. This step involves forming a conductive stacked layer within a precisely defined area, establishing a good electrical connection with the vertical channel structure 101. The fact that the conductive stacked structure 50 is partially located within the groove 504 significantly enhances the stability of the connection and effectively reduces contact resistance. The formation of the conductive stacked structure 50 can be achieved through various techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), depositing multiple layers of conductive material within the mask opening 804 of the hard mask 803 and inside the groove 504. The conductive material may include, but is not limited to, polysilicon 501, metal silicides, or metals, thereby forming the conductive stacked structure 50. After deposition, an etch-back or chemical mechanical polishing (CMP) process may be required to remove excess material above the hard mask 803. Another approach is to first deposit a layer of conductive material on the entire surface, and then, through photolithography and etching processes, selectively retain the conductive material within the mask opening 804 in conjunction with the opening of the hard mask 803, ensuring that it partially fills the groove 504.

[0101] Through the above technical solution, after forming the dielectric isolation layer 401, a hard mask 803 is introduced for precise patterning, and a groove 504 is formed on the top of the vertical channel structure 101, allowing the conductive stacked structure 50 to be partially embedded in the groove 504 and precisely defined by the mask opening 804 of the hard mask 803. This significantly improves the positional accuracy of the conductive stacked structure 50 formation and effectively avoids misalignment problems that may be caused by direct deposition. See Figures 21 to 28 This application further proposes a method for forming a hard mask 803, which includes a mask opening 804 located above a vertical channel structure 101.

[0102] like Figure 21 and Figure 22 As shown, the specific steps include: forming a hard mask 803 material layer above the substrate 70; forming a first etch barrier material layer above the hard mask 803 material layer; patterning the first etch barrier material layer; and forming a first etch barrier pattern 805 spaced apart on the third direction D3.

[0103] like Figure 23 and Figure 24 As shown, an isolation layer 807 is formed above the material layer of the hard mask 803. The isolation layer 807 covers the first etch stop pattern 805 and the spaced area between two adjacent first etch stop patterns 805.

[0104] like Figure 25 , Figure 26 As shown, a second etch barrier material layer is formed above the hard mask 803 material layer. The second etch barrier material layer and the isolation layer 807 are patterned to form a second etch barrier pattern 806 spaced apart in the second direction D2. The first etch barrier pattern 805 and the second etch barrier pattern 806 avoid the vertical channel structure 101. Part of the isolation layer 807 is located above the vertical channel structure 101 to form an etch mask. The hard mask 803 material layer is patterned using the etch mask to form a mask opening 804 that exposes the vertical channel structure 101 on the hard mask 803 material layer, thus forming the hard mask 803.

[0105] Specifically, a hard mask 803 material layer is formed above the substrate 70. This hard mask 803 material layer is a protective layer for subsequent etching processes. Its material typically has a high etch selectivity to resist erosion by the etchant, thereby accurately transferring the pattern onto the underlying material. This hard mask 803 material layer serves as the main body of the final hard mask 803, carrying the subsequent patterning process. For example, a silicon dioxide (SiO2) layer or a silicon nitride (SiN) layer can be deposited using chemical vapor deposition (CVD) as the hard mask 803 material layer, or an aluminum oxide (Al2O3) layer or a hafnium oxide (HfO2) layer can be deposited using atomic layer deposition (ALD) to obtain a more uniform and dense film.

[0106] Subsequently, a first etch stop material layer is formed above the hard mask 803 material layer, and this first etch stop material layer is patterned to form a first etch stop pattern 805 spaced apart on the third direction D3. The first etch stop material layer is a material layer with high resistance to specific etching processes, used to protect the underlying hard mask 803 material layer during patterning or as an intermediate layer for pattern transfer. The first etch stop pattern 805 is a structure with a specific shape and spacing formed after the material layer has been patterned. This step, as a key layer in the multi-patterning or self-aligned patterning process, defines the size and position of subsequent structures, facilitating fine linewidth control.

[0107] Next, an isolation layer 807 is formed over the hard mask 803 material layer. This isolation layer 807 covers the first etch stop pattern 805 and the spacing region between two adjacent first etch stop patterns 805. The isolation layer 807 is a dielectric material layer used to fill the gaps between patterns and provide electrical insulation or serve as a mask for subsequent etching. In the process of multiple patterning, the isolation layer 807 can serve as a spacer or filler to reduce the pattern spacing or define new patterns. Covering the first etch stop pattern 805 and its spacing region provides a planar surface for the formation of the subsequent second etch stop pattern 806 or serves as an etch selector layer. For example, silicon dioxide (SiO2) or silicon nitride (SiN) can be deposited as the isolation layer 807 using chemical vapor deposition (CVD) followed by chemical mechanical polishing (CMP) to achieve planarization; or a spin-on dielectric (SOD) material, such as spin-on glass (SOG), can be used to fill and planarize the surface.

[0108] Based on this, a second etch barrier material layer is formed above the hard mask 803 material layer, and the second etch barrier material layer and the isolation layer 807 are patterned to form a second etch barrier pattern 806 spaced apart in the second direction D2. The second etch barrier material layer is similar to the first etch barrier material layer, but may be for different etching processes or used to define patterns in different directions.

[0109] Furthermore, the first etch barrier pattern 805 and the second etch barrier pattern 806 are designed to avoid the vertical channel structure 101, while a portion of the isolation layer 807 is located above the vertical channel structure 101, thereby forming an etch mask. This etch mask is a general term for the aforementioned multi-layer patterned structure, which precisely defines the areas to be etched and the areas to be protected. By precisely designing the positions of the first and second etch barrier patterns 806 to avoid the vertical channel structure 101, and simultaneously using the isolation layer 807 to cover the area above the vertical channel structure 101, a composite mask capable of precisely guiding subsequent etching is formed.

[0110] Finally, as Figure 27 , Figure 28 As shown, the etching mask is used to pattern the material layer of the hard mask 803, forming mask openings 804 on the hard mask 803 material layer that expose the vertical channel structure 101, thus forming the hard mask 803. The final hard mask 803 has precise mask openings 804 that correspond to the areas above the vertical channel structure 101 that need to be exposed.

[0111] Through the above technical solution, this application employs a precision hard mask 803 formation method, effectively solving the technical problem of how to accurately and efficiently form a hard mask 803 with specific openings in semiconductor device manufacturing to ensure the accurate deposition of subsequent conductive stacked structures 50 and avoid damage to the vertical channel structure 101. Specifically, this solution utilizes a step-by-step, multi-layer patterning approach, leveraging the synergistic effect of the first etch stop pattern 805, the isolation layer 807, and the second etch stop pattern 806 to construct a high-precision composite etch mask. This composite etch mask can precisely define the opening region above the vertical channel structure 101 and accurately transfer its pattern onto the hard mask 803 material layer, ultimately forming a hard mask 803 with precisely aligned and dimensionally controlled mask openings 804. This method significantly improves the alignment accuracy and dimensional control of the hard mask opening 804, providing a reliable template for the subsequent formation of the conductive stack structure 50 above the vertical channel structure 101. This ensures a good electrical connection between the conductive stack structure 50 and the vertical channel structure 101, thereby improving the overall manufacturing yield and performance stability of the semiconductor device. See also Figure 27 and Figure 28 This application proposes a method after forming a hard mask 803, which includes a mask opening 804 located above a vertical channel structure 101, comprising: patterning the vertical channel structure 101 using the hard mask 803 to form a groove 504 on the top of the vertical channel structure 101; and forming a conductive stack structure 50 within the mask opening 804 of the hard mask 803, wherein a portion of the conductive stack structure 50 is located within the groove 504.

[0112] Specifically, the step of patterning the vertical channel structure 101 using a hard mask 803 to form a groove 504 on top of the vertical channel aims to precisely create a groove 504 of predetermined shape and depth on the top of the vertical channel structure 101, providing precise positioning and accommodating space for the subsequent formation of the conductive stacked structure 50. Anisotropic etching techniques, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE), can be used, with the hard mask 803 acting as an etching barrier layer to precisely control the etching area and depth. By adjusting the etching gas formulation, RF power, and etching time, the verticality of the sidewalls and the flatness of the bottom of the groove 504 can be optimized. Alternatively, atomic layer etching (ALE) technology can be considered, which uses a cyclic adsorption-etching process to achieve atomic-level precise removal of the material on top of the vertical channel structure 101, thereby forming a groove 504 with high uniformity and controllable dimensions.

[0113] The step of forming a conductive stack structure 50 within the mask opening 804 of the hard mask 803, with a portion of the conductive stack structure 50 located within the groove 504, aims to precisely fill the space defined by the mask opening 804 of the hard mask 803 and the groove 504 at the top of the vertical channel with conductive material, thereby forming a conductive stack structure 50 that is electrically connected to the vertical channel structure 101. Conductive material can first be deposited across the entire wafer surface using methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) to fill the mask opening 804 and the groove 504. Subsequently, excess conductive material above the hard mask 803 is removed using chemical mechanical polishing (CMP) or an etch-back process, leaving the conductive stack structure 50 only within the mask opening 804 and the groove 504. Another approach is to use selective deposition techniques, such as selective tungsten deposition or selective polysilicon 501 deposition, so that the conductive material grows only on the exposed silicon surface (i.e., the bottom and sidewalls of the groove 504) and within the mask opening 804, thereby simplifying the subsequent planarization steps.

[0114] The above technical solution first uses a hard mask 803 to pattern the vertical channel structure 101, forming a groove 504 at the top of the vertical channel. This ensures that the groove 504 is precisely aligned with the vertical channel structure 101, providing a reliable positioning basis for the subsequent formation of the conductive stack structure 50. Subsequently, the conductive stack structure 50 is formed within the mask opening 804 of the hard mask 803, with a portion of it located within the pre-formed groove 504. This method of first forming the groove 504 and then embedding the conductive stack structure 50 allows the conductive stack structure 50 to be firmly and tightly bonded to the vertical channel structure 101, significantly reducing contact resistance and effectively lowering parasitic capacitance. Therefore, this technical solution effectively solves the problems of difficult precise embedding, poor contact, and increased parasitic capacitance that may result from directly forming the conductive stack structure 50. Please participate Figures 29-32 This application further proposes that the above-mentioned conductive stacked structure 50 includes a polycrystalline silicon 501 layer, a cobalt silicide layer 502, and a tungsten layer 503 formed by stacking.

[0115] Specifically, the polycrystalline silicon 501 layer is a silicon material composed of multiple tiny grains. As the first contact layer between the conductive stacked structure 50 and the vertical channel structure 101, it provides good semiconductor interface compatibility. The main function of this layer is to ensure the stability of the electrical connection and achieve low interface resistance. In actual fabrication, the polycrystalline silicon 501 layer can be formed using various methods. For example, it can be formed using low-pressure chemical vapor deposition (LPCVD) technology at a specific temperature by decomposing and depositing silane (SiH4) gas; or it can be deposited using plasma-enhanced chemical vapor deposition (PECVD) technology at a relatively low temperature.

[0116] Building upon this, the cobalt silicide layer 502 is a compound formed by the reaction of cobalt and silicon, characterized by low resistivity and excellent thermal stability. This layer plays a crucial intermediate connection role in the conductive stacked structure 50, significantly reducing the contact resistance with the polysilicon layer 501, thereby minimizing energy loss during signal transmission. Furthermore, the cobalt silicide layer 502 also serves as an effective diffusion barrier layer, preventing undesirable reactions between subsequently deposited metal layers and the underlying silicon layer.

[0117] Furthermore, the tungsten layer 503 is a high-melting-point, high-density, and highly conductive metal layer. It serves as the primary conductive path in the conductive stack structure 50, providing excellent electrical conductivity. The inherent high thermal stability of tungsten enhances the durability and thermal stress resistance of the entire conductive stack structure 50, ensuring reliable device operation at high temperatures or high current densities.

[0118] Through the above technical solution, the conductive stacked structure 50 adopts a stacked combination of a polysilicon 501 layer, a cobalt silicide layer 502, and a tungsten layer 503, effectively solving the problems of high contact resistance and poor thermal stability caused by improper selection of traditional materials. Specifically, the polysilicon 501 layer, as the interface layer in direct contact with the vertical channel structure 101, ensures good electrical compatibility and low interface resistance; the introduction of the cobalt silicide layer 502 significantly reduces interlayer contact resistance and optimizes charge transport efficiency; while the tungsten layer 503, with its high conductivity and excellent thermal stability, enhances the current carrying capacity and long-term reliability of the entire structure. This synergistic effect of multilayer materials not only improves signal transmission efficiency and reduces energy loss, but also significantly enhances the thermal stability and durability of the device in complex operating environments, thereby effectively improving the integration and electrical performance of DRAM devices and ensuring reliable operation in high-density integration environments.

[0119] This application provides an electronic device based on the aforementioned semiconductor device structure and semiconductor device formation method, comprising the aforementioned semiconductor device, or a semiconductor device prepared according to the aforementioned semiconductor device formation method. This electronic device possesses all the technical effects of the aforementioned semiconductor device, which will not be elaborated further here.

[0120] In the semiconductor device, formation method, and electronic device of this application embodiment, the word line structure 201 is coupled to the same side of the vertical channel structure 101, and the spacing between the word line structures 201 of adjacent vertical transistors is controlled within the same range, which can improve the word line coupling effect. At the same time, through the design of the dielectric layer 30 with a specific surrounding structure, the word line structure 201 is effectively isolated and the word line coupling effect is further suppressed, ensuring the reliable operation of the semiconductor device.

[0121] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0122] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0123] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0124] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple vertical channel structures, the vertical channel structures extending in a first direction and spaced apart in a second direction and a third direction; The word line structure extends in the second direction and is coupled to the same side of the vertical channel structure; A dielectric layer covers the periphery of the word line structure in a first direction and a third direction; the second direction is perpendicular to the third direction, and the first direction is perpendicular to the second direction and the third direction; The dielectric layer includes a first surrounding structure located on both sides of the word line structure in a first direction, a second surrounding structure located on both sides of the word line structure in a third direction, and a dielectric isolation layer located between the first surrounding structure and the second surrounding structure.

2. The semiconductor device according to claim 1, characterized in that, The first enclosure structure and the second enclosure structure are made of the same dielectric material, and the materials of the first enclosure structure and the second enclosure structure are different from the dielectric material of the dielectric isolation layer.

3. The semiconductor device according to claim 2, characterized in that, Both the first and second enclosing structures are made of silicon oxide, and the dielectric isolation layer is made of a spin-coated dielectric material.

4. The semiconductor device according to claim 1, characterized in that, In the first direction, the first surrounding structure includes a first substructure located at the top of the word line structure and a second substructure located at the bottom of the word line structure; The second substructure extends upward from the third party to form an L-shaped semi-enclosed structure, and the dielectric isolation layer is located on the semi-enclosed structure of the second substructure.

5. The semiconductor device according to claim 1, characterized in that, In the third direction, the second surrounding structure includes a third substructure and a fourth substructure located on both sides of the word line structure. The third substructure is located between the word line structure and the vertical channel structure, and the dielectric isolation layer is located between the fourth substructure and the word line structure.

6. The semiconductor device according to claim 5, characterized in that, In the third direction, the thickness of the dielectric isolation layer is greater than the thickness of the third substructure or the fourth substructure.

7. The semiconductor device according to claim 5, characterized in that, In the first direction, the length of the dielectric isolation layer is greater than the length of the word line structure.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The dielectric isolation layer has an air gap that extends in the second direction.

9. The semiconductor device according to claim 8, characterized in that, In the first direction, the length of the air gap is greater than that of the word line structure.

10. The semiconductor device according to any one of claims 1-7, characterized in that, In the first direction, a conductive stacking structure is provided on the top of the vertical channel structure, the conductive stacking structure including a stacked polycrystalline silicon layer, a cobalt silicide layer and a tungsten layer.

11. A method for forming a semiconductor device, characterized in that, A vertical channel structure extending in a first direction is formed on the substrate, and a first groove is formed between two adjacent vertical channel structures, the first groove extending in a second direction. A word line structure and a dielectric layer are formed within the first trench. The dielectric layer includes a first surrounding structure located on both sides of the word line structure in a first direction, a second surrounding structure located on both sides of the word line structure in a third direction, and a dielectric isolation layer located between the first surrounding structure and the second surrounding structure. The second direction is perpendicular to the third direction, and the first direction is perpendicular to the second direction and the third direction.

12. The method for forming a semiconductor device according to claim 11, characterized in that, The formation of the word line structure and dielectric layer within the first trench includes: A bottom dielectric layer located on the surface of the substrate and a side dielectric layer located on one side of the vertical channel structure are formed within the first trench. A conductive material is filled into the first trench to form an initial word line, and a top dielectric layer is formed above the initial word line; The top dielectric layer, the initial word line, and the bottom dielectric layer are etched to form a second trench. The remaining initial word line forms a word line structure extending along a second direction. The remaining top dielectric layer and the bottom dielectric layer form a first surrounding structure, and the side dielectric layer forms a second surrounding structure. A dielectric isolation layer is formed within the second trench.

13. The method for forming a semiconductor device according to claim 12, characterized in that, After forming the dielectric isolation layer, the method further includes: A hard mask is formed, the hard mask including a mask opening located above the vertical channel, the mask opening exposing the top of the vertical channel structure; The hard mask is used to form a conductive stack structure above the vertical channel, the conductive stack structure being located within the mask opening.

14. The method for forming a semiconductor device according to claim 13, characterized in that, Forming the conductive stacked structure includes: sequentially stacking a polycrystalline silicon layer, a cobalt silicide layer, and a tungsten layer within the mask opening.

15. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1-10, or the semiconductor device prepared by the forming method according to any one of claims 11-14.

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