Semiconductor device and method of forming the same

Abstract

This application discloses a semiconductor device and a method for forming the same. The semiconductor device includes a stacked structure, a transistor, and a capacitor structure. The stacked structure includes insulating layers stacked along a third direction. A transistor is located between two adjacent insulating layers, and a first groove is adjacent to the transistor in a first direction, with at least a portion of the first groove located between the two adjacent insulating layers. The capacitor structure includes a first electrode, a second electrode, and a dielectric layer located between the first and second electrodes. The first electrode fills the first groove to form a multi-faceted exposed three-dimensional solid structure, and the second electrode is located on the surface of the first electrode. The first electrode fills the first groove. The second electrode fully covers the exposed surface of the first electrode, significantly increasing the capacitor's energy storage capacity and thus improving storage density. Simultaneously, the interlayer insulating layer provides structural constraint support, improving overall structural stability, and the solid structure of the second electrode provides effective support for subsequent conformal coverage of the second electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] As the miniaturization of two-dimensional Dynamic Random Access Memory (DRAM) devices approaches physical limits, issues such as lithography precision, device leakage current, and edge electric field interference cannot be resolved through planar process optimization. Therefore, the industry is fully shifting towards three-dimensional stacked DRAM architectures. Three-dimensional (3D) DRAM constructs memory arrays through the vertical stacking of multiple thin films, overcoming the limitations of planar size miniaturization and significantly increasing memory integration density. In the core structure of 3D DRAM, the effective electrode area, capacitance, and structural stability of the capacitor structure directly determine the device's charge storage capacity, read / write sensing margin, data retention time, and overall array density.

[0003] Existing 3D DRAM capacitors suffer from drawbacks such as small effective electrode area, low capacitance, and large cell area, which severely restrict the development of high-density stacking processes. Summary of the Invention

[0004] This application provides a semiconductor device and a method for forming the same, to improve capacitance and thus increase storage density.

[0005] This application provides a semiconductor device, including: a stacked structure including insulating layers stacked along a third direction; a transistor located between two adjacent insulating layers, the transistor being adjacent to a first groove in a first direction, at least a portion of the first groove being located between two adjacent insulating layers; a capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; the first electrode filling the first groove and being connected to the transistor in the first direction, the first direction being perpendicular to the third direction; wherein, the two adjacent first electrodes and the insulating layers along the third direction form a second groove, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forming a third groove within the second groove, and the second electrode at least covering the inner wall of the third groove.

[0006] In some embodiments, the semiconductor device further includes: isolation structures extending along the third direction and spaced apart along the second direction, the second direction being perpendicular to the third direction and intersecting the first direction; the transistor being located between two adjacent isolation structures in the second direction; two first electrodes adjacent to each other in the same layer along the second direction forming a trench with the isolation structures, the dielectric layer contacting the inner wall of the trench, the dielectric layer forming a fourth groove in the trench, and the second electrode being located at least on the inner wall of the fourth groove.

[0007] In some embodiments, the semiconductor device further includes a connection structure connected to the second electrode, the connection structure including a main body and a branch, the main body extending along the third direction and the second direction, and the branch extending along the first direction.

[0008] In some embodiments, the second electrode and the branch portion sequentially fill the third groove and the fourth groove.

[0009] In some embodiments, the second electrode and the branch portion sequentially fill the third groove, and the second electrode fills the fourth groove.

[0010] In some embodiments, the second electrode fills the third groove, and the second electrode and the branch portion sequentially fill the fourth groove.

[0011] In some embodiments, the second electrode and the branch portion sequentially fill the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

[0012] In some embodiments, the second electrode and the second spacer structure sequentially fill the third groove, and the second electrode and the branch sequentially fill the fourth groove.

[0013] In some embodiments, the semiconductor device further includes a connection structure connected to the second electrode, the connection structure extending along the third direction and the second direction.

[0014] In some embodiments, the second electrode fills the third groove, and the second electrode fills the fourth groove.

[0015] In some embodiments, the second electrode fills the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

[0016] In some embodiments, the second electrode and the second spacer structure sequentially fill the third groove, and the second electrode fills the fourth groove.

[0017] In some embodiments, the second electrode and the second spacer structure sequentially fill the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

[0018] In some embodiments, both the first spacer structure and the second spacer structure include an insulating layer and / or an air gap.

[0019] In some embodiments, the transistor includes a channel layer and a gate layer, the gate layer surrounding a portion of the surface of the channel layer, and the gate layer exposing at least a portion of the sidewalls of the channel layer connected to the first electrode; the semiconductor device further includes a word line extending in a second direction and a bit line extending in a third direction, the word line being connected to the gate layers of a plurality of the transistors, and the channel layer being disposed around the surface of the bit line.

[0020] This application also provides a method for forming a semiconductor device, comprising: forming a stacked layer, the stacked layer including an insulating layer and a dielectric layer alternately stacked along a third direction; forming a transistor, the transistor being located between two adjacent insulating layers, the transistor being adjacent to a first groove in a first direction, at least a portion of the first groove being located between two adjacent insulating layers; forming a capacitor structure, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; the first electrode filling the first groove and being connected to the transistor in the first direction, the second electrode being located on the surface of the first electrode; wherein, two adjacent first electrodes and the insulating layer along the third direction form a second groove, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forming a third groove within the second groove, and the second electrode at least covering the inner wall of the third groove.

[0021] In some embodiments, forming a capacitor structure includes: forming a capacitor trench extending through the stacked layer along a third direction, the capacitor trench extending along a second direction, the third direction being the stacking direction of the stacked layer, and the second direction being perpendicular to the third direction; removing a portion of the dielectric layer through the capacitor trench to form a first groove; filling the first groove with a first electrode; removing a portion of the insulating layer through the capacitor trench to form a second groove; and sequentially forming a dielectric layer and a second electrode on the surface of the first electrode and the inner wall of the second groove.

[0022] In some embodiments, forming a transistor includes: forming a via through the stacked layer in a third direction, the via including a connected bit line via and a channel via, the channel via being disposed around the sidewall of the bit line via; sequentially forming a gate layer, a gate insulating layer, and a sacrificial layer within the via, the gate layer and the gate insulating layer being located on the inner wall of the channel via; removing a portion of the gate layer and a portion of the gate insulating layer through the capacitor trench to form a first groove exposing the sacrificial layer; removing the sacrificial layer; and forming a channel layer connected to the first electrode within the channel via.

[0023] In the semiconductor device of this application embodiment, a transistor has a first groove adjacent to it in a first direction. At least a portion of the first groove is located between two adjacent insulating layers. A first electrode fills the first groove to form a three-dimensional solid structure with multiple exposed surfaces. A second electrode completely covers the exposed surface of the first electrode. Without changing the lateral layout size of the cell and without occupying additional chip area, the effective area of ​​the first and second electrodes facing each other is increased, significantly improving the energy storage capacity of the capacitor and thus increasing the storage density. At the same time, at least a portion of the first electrode is located between adjacent insulating layers, and the interlayer insulating layer provides structural constraint support, improving the overall structural stability. Furthermore, the solid structure of the second electrode can provide effective support for the subsequent conformal coverage of the second electrode, reducing the risk of device collapse during the formation process.

[0024] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 1 ; Figure 2 yes Figure 1 A top view of the semiconductor device at point A-A1; Figure 3 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 2 ; Figure 4 yes Figure 3 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 5 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 3 ; Figure 6 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 4 ; Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure of the first partition structure at point B-B1; Figure 8 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 2 ; Figure 9 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 1 ; Figure 10 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 2 ; Figure 11 yes Figure 10 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 12 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 3 ; Figure 13 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 4 ; Figure 14 yes Figure 13 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 15 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 3 ; Figure 16 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 1 ; Figure 17 yes Figure 16 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 18 yes Figure 15Top view of the semiconductor device at point A-A1 Figure 2 ; Figure 19 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 3 ; Figure 20 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 4 ; Figure 21 yes Figure 20 A schematic cross-sectional view of the middle branch and the first spacer structure at point B-B1; Figure 22 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 4 ; Figure 23 yes Figure 22 A top view of the semiconductor device at point A-A1; Figure 24 yes Figure 23 A schematic diagram of the cross-sectional structure of the first and second spacers at point B-B1. Figure 25 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application; Figure 26 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 27 to 58 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0028] Explanation of reference numerals in the attached figures: 10. Stacked structure; 10a. Stacked layer; 11. Insulating layer; 12. Dielectric layer; 20. Transistor; 21. Channel layer; 22. Gate layer; 23. Gate insulating layer; 24. Sacrificial layer; 20a. Through-hole; 21a. Channel via; 30. Capacitor structure; 31. First electrode; 311. First surface; 312. Second surface; 313. Third surface; 32. Second electrode; 33. Dielectric layer; 31a. First groove; 32a. Second groove; 32b. Third groove; 40. Spacer Structure; 50, isolation structure; 50a, trench; 50b, fourth groove; 60, connection structure; 61, main body; 62, branch; 60a, capacitor groove; 70, word line; 70a, word line groove; 71, word line gap structure; 71a, word line gap; 80, bit line; 80a, bit line hole; 91, first spacing structure; 92, second spacing structure; 100, semiconductor device; 101, memory cell group; 102, substrate; X, first direction; Y, second direction; Z, third direction. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0030] Currently, 3D DRAM generally suffers from technical defects such as insufficient capacitor capacity, limited storage density, and poor structural stability.

[0031] Based on this, embodiments of this application provide a semiconductor device, including: a stacked structure including insulating layers stacked along a third direction; a transistor located between two adjacent insulating layers, the transistor being adjacent to a first groove in a first direction, at least a portion of the first groove being located between two adjacent insulating layers; a capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; the first electrode filling the first groove and being connected to the transistor in the first direction, the first direction being perpendicular to the third direction; wherein, the two adjacent first electrodes and the insulating layers along the third direction form a second groove, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forming a third groove within the second groove, and the second electrode at least covering the inner wall of the third groove.

[0032] In the semiconductor device of this application embodiment, a transistor has a first groove adjacent to it in a first direction. At least a portion of the first groove is located between two adjacent insulating layers. A first electrode fills the first groove to form a three-dimensional solid structure with multiple exposed surfaces. A second electrode completely covers the exposed surface of the first electrode. Without changing the lateral layout size of the cell and without occupying additional chip area, the effective area of ​​the first and second electrodes facing each other is increased, significantly improving the energy storage capacity of the capacitor and thus increasing the storage density. At the same time, at least a portion of the first electrode is located between adjacent insulating layers, and the interlayer insulating layer provides structural constraint support, improving the overall structural stability. Furthermore, the solid structure of the second electrode can provide effective support for the subsequent conformal coverage of the second electrode, reducing the risk of device collapse during the formation process.

[0033] The semiconductor devices provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0034] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 1, Figure 2 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 1 .

[0035] The semiconductor device 100 includes a stacked structure 10, a transistor 20, and a capacitor structure 30. The stacked structure 10 includes insulating layers 11 stacked along a third direction Z. The transistor 20 is located between two adjacent insulating layers 11, and the transistor 20 is adjacent to a first groove 31a in a first direction X, at least a portion of the first groove 31a being located between two adjacent insulating layers 11. The capacitor structure 30 includes a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 fills the first groove 31a and is connected to the transistor 20 in the first direction X, which is perpendicular to the third direction Z. A second groove 32a is formed between two adjacent layers of the first electrode 31 and the insulating layer 11. The dielectric layer 33 contacts the inner walls of the first groove 31a and the second groove 32a. The dielectric layer 33 forms a third groove 32b within the second groove 32a, and the second electrode 32 at least covers the inner wall of the third groove 32b.

[0036] The stacked structure 10 serves as both overall device support and interlayer isolation, consisting of multiple insulating layers 11 stacked at equal intervals along the third direction Z (stack direction). The insulating layers 11 can be made of highly dense, highly insulating dielectric materials (such as silicon oxide). Each insulating layer 11 has a uniform thickness and a smooth surface. After stacking, the multiple insulating layers 11 form multiple independent interlayer accommodating spaces, used to accommodate transistors 20 and capacitor structures 30, achieving three-dimensional integration of multi-layer memory cells while simultaneously providing electrical isolation between upper and lower layers, reducing interlayer crosstalk.

[0037] Transistor 20, serving as a switching control device for a single-layer memory cell, is entirely embedded and confined within the interlayer space between two adjacent insulating layers 11, and is fully integrated within the stacked structure 10. A first groove 31a is formed adjacent to the side of transistor 20 along the first direction X; the first groove 31a is a concave cavity structure. Since at least a portion of the first groove 31a is located between adjacent insulating layers 11, and the first electrode 31 fills the first groove 31a, at least a portion of the first electrode 31 is located between adjacent insulating layers 11.

[0038] Specifically, a small portion of the first electrode 31 is housed within the interlayer space between the two opposing insulating layers 11, while the majority of the first electrode 31 extends beyond the insulating layers 11 along the first direction X, forming an exposed surface. This allows the subsequently formed second electrode 32 to cover a large area of ​​the exposed surface of the first electrode 31, significantly increasing the energy storage area between the two electrodes. Simultaneously, the insulating layers 11 provide limiting support, balancing high capacity and structural stability. In other words, the dimension (i.e., lateral length) of the portion of the first electrode 31 covered by the second electrode 32 in the first direction X is greater than the dimension (i.e., lateral length) of the portion of the first electrode 31 covered by the insulating layers 11 in the first direction X.

[0039] The capacitor structure 30 is a metal-insulator-metal (MIM) energy storage structure, which is the charge energy storage core of the storage unit. It consists of three functional layers: the inner layer is the first electrode 31, the middle layer is the dielectric layer 33, and the outer layer is the second electrode 32. The first electrode 31 is formed by completely filling all the cavities of the first groove 31a using an integral full-fill process, resulting in a transverse columnar solid electrode. "Completely filled" means that subsequent materials cannot enter the first groove 31a, including both completely filling and situations where air gaps exist inside the filling structure (i.e., the first electrode 31) due to process limitations.

[0040] The first electrode 31 is directly attached to the inner end face of the transistor 20 along the first direction X to achieve electrical connection, realizing precise conduction between the transistor 20 switch and the capacitor structure. The second electrode 32 conformally covers all exposed surfaces of the first electrode 31, and the two electrodes are isolated by the dielectric layer 33 to form a closed energy storage cavity, maximizing the effective electrode energy storage area and improving the capacitor storage capacity.

[0041] In some examples, the first electrode 31 and the second electrode 32 are made of the same material, which can be a highly conductive and rigid metallic material, such as at least one of titanium (Ti), titanium nitride (TiN), tungsten (W), and molybdenum (Mo). In this embodiment, the first electrode 31 and the second electrode 32 are made of titanium nitride (TiN), which combines excellent conductivity, structural rigidity, and thin film stability. It is chemically inert, not easily oxidized, and can be stably formed into a solid columnar structure, which is not prone to deformation and collapse, making it suitable for long-term energy storage operation. The dielectric layer 33 can be made of a high dielectric constant (high k) dielectric material, including at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) or a multilayer composite stacked structure. It has strong insulation and withstand voltage and low leakage current, making it suitable for the energy storage requirements of MIM capacitors.

[0042] In some embodiments, the thickness of the first electrode 31 matches the spacing between two adjacent insulating layers 11. The thickness of the first electrode 31 refers to its dimension along the third direction Z, and the spacing between two adjacent insulating layers 11 is the vertical distance between the inner sidewalls of the upper and lower insulating layers 11. The two are precisely matched and have consistent dimensions. For example, the process matching tolerance of the two is controlled within ±5% film thickness deviation, which is a standard process tolerance allowed for semiconductor multilayer thin film stacking.

[0043] This dimensional matching ensures that the upper and lower surfaces of the first electrode 31 are completely fitted and in full contact with the lower wall of the upper insulating layer and the upper wall of the lower insulating layer, respectively, achieving full-fill positioning of the first electrode 31 within the interlayer space. This completely eliminates the gaps and offset spaces on the upper and lower sides of the first electrode 31, reducing defects such as warping, deformation, local collapse, and positional displacement that may occur during electrode fabrication, thin-film annealing, and device operation. It also ensures the regularity, flatness, and stress uniformity of each layer of transverse columnar electrodes, significantly improving the overall mechanical stability and structural consistency of the multilayer stacked array.

[0044] In some embodiments, the thickness of the first electrode 31 is greater than the thickness of the second electrode 32. The thicker first electrode 31 has high structural rigidity and overall flatness, which can reduce thin film deformation, depressions, and wrinkles. It can provide a stable and flat rigid support substrate for the subsequently conformally deposited dielectric layer 33 and thin-film second electrode 32, maximizing the preservation of the three-dimensionally aligned effective energy storage area of ​​the first electrode 31 and the second electrode 32. This avoids problems such as effective area reduction, capacitance decay, and poor capacitance consistency caused by thin-film electrode collapse distortion, ensuring stable device design capacitance. At the same time, the thin-film second electrode 32 can effectively reduce the parasitic resistance and parasitic capacitance of the electrode plate, reducing signal transmission loss and RC delay.

[0045] Since the dielectric layers 33 on both sides of the first electrode 31 and the second electrode 32 are both disposed in the same layer as the insulating layer 11, and the dielectric layer 33 is connected to the insulating layer 11, the thickness of the second electrode 32 is determined by matching the thickness of the insulating layer 11. For example, the sum of the thickness of the second electrode 32 and twice the thickness of the dielectric layer 33 is less than or equal to the single-layer thickness of the insulating layer 11.

[0046] This size limitation ensures that the thin film structure set in the same layer can be fully adapted to the vertical height of the single-layer insulating layer 11, avoiding process problems such as space compression, interface deformation, thin film wrinkles, and excessive interlayer stress caused by the excessive thickness of the double-sided thin film stacking. It ensures that the dielectric layer 33 and the second electrode 32 in the single-layer structure can form a uniform and flat conformal film, effectively guaranteeing the integrity, regularity and electrical consistency of the single-layer MIM energy storage interface.

[0047] In some embodiments, the first electrode 31 includes a first surface 311 connected to the transistor 20, a second surface 312 opposite to the first surface 311, and a third surface 313 connected to two adjacent insulating layers 11; the insulating layer 11 exposes at least a portion of the third surface 313, and the second electrode 32 is located on the second surface 312 and the portion of the third surface 313 exposed by the insulating layer 11.

[0048] The first surface 311 is the inner end face of the first electrode 31 along the first direction X, facing the sidewall of the transistor 20. It is a planar bonding structure used to achieve electrical connection and charge transfer between the first electrode 31 and the transistor 20, and serves as the conductive interface for capacitor charging and discharging. The second surface 312 is the outer end face of the first electrode 31 along the first direction X, completely facing and parallel to the first surface 311. The third surface 313 consists of the upper and lower end faces of the first electrode 31, respectively bonded to the inner sidewalls of the upper and lower insulating layers 11. The insulating layer 11 only covers a small portion of the third surface 313, selectively exposing most of the third surface 313.

[0049] Among them, the first surface 311, the second surface 312, and the exposed third surface 313 of the first electrode 31 are all energy storage interfaces, and can all cooperate with the dielectric layer 33 and the second electrode 32 to form an effective energy storage facing area. The facing area formed by the third surface 313 is the main effective energy storage facing area of ​​the capacitor, and is the core interface that ensures the basic storage capacity of the capacitor.

[0050] The dielectric layer 33 and the second electrode 32 simultaneously cover the second surface 312 and all exposed third surfaces 313, achieving complete coverage of all conductive exposed areas of the first electrode 31, completely blocking leakage channels caused by exposed electrodes, regulating the electric field distribution inside the capacitor, avoiding local field concentration, and improving the device's withstand voltage performance and data retention stability.

[0051] See Figure 2 The semiconductor device may further include isolation structures 50 extending along a third direction Z and spaced apart along a second direction Y, wherein the second direction Y is perpendicular to the third direction Z and intersects the first direction X. The transistor 20 is located between two adjacent isolation structures 50 in the second direction Y. A trench 50a is formed between adjacent first electrodes 31 and isolation structures 50 in the same layer along the second direction Y, the dielectric layer 33 is in contact with the inner wall of the trench 50a, the dielectric layer 33 forms a fourth groove 50b in the trench 50a, and the second electrode 32 is also located at least on the inner wall of the fourth groove 50b.

[0052] It should be noted that, Figure 1 The cross-sectional view only shows the first electrode 31 of the capacitor structure 30 being separated by the insulating layer 11 in the third direction Z. Figure 2 The top view shows that the first electrode 31 is separated by the isolation structure 50 in the second direction Y. The isolation structure 50 is a dielectric isolation wall that runs vertically through the third direction Z and is evenly spaced along the second direction Y to separate adjacent memory cells in the second direction Y. The transistor 20 and the first electrode 31 are both confined within the area between two adjacent isolation structures 50, achieving physical isolation in the second direction Y.

[0053] In some embodiments, the sidewalls of the isolation structure 50 may be aligned with the sidewalls of the insulating layer 11, except that the isolation structure 50 is a continuous through-structure in the third direction Z, while the insulating layer 11 is an interlayer structure.

[0054] In some embodiments, the semiconductor device further includes a connection structure 60 connected to the second electrode 32. The connection structure 60 includes a main body 61 and a branch 62. The main body 61 extends along the third direction Z and the second direction Y, and the branch 62 extends along the first direction X. In some examples, the material of the connection structure 60 may include at least one of tungsten (W), copper (Cu), aluminum (Al), and cobalt (Co). In this embodiment, the material of the connection structure 60 includes tungsten, which possesses excellent conductivity, filling capacity, and process stability.

[0055] It should be noted that since the second electrode 32 fills the second groove 32a, the material of the connecting structure 60 does not enter the second groove 32a, which can improve the material uniformity and electric field distribution regularity of the capacitor area.

[0056] exist Figure 1 In this embodiment, the second electrode 32 fills the third groove 32b and the fourth groove 50b. On one hand, this solid structure filling can offset the internal stress of multilayer thin film stacking, strengthen interlayer support, and effectively prevent process defects such as interlayer collapse, thin film warping, and structural cracking in high-layer stacking scenarios, thereby improving device yield. On the other hand, it can prevent other conductive materials from entering the second groove 32a. Utilizing the high work function, strong dielectric diffusion barrier properties, and excellent electrochemical stability of the second electrode 32 material, it improves the material uniformity and electric field distribution regularity of the capacitor region.

[0057] Please see Figure 3 and Figure 4 , Figure 3 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 2 , Figure 4 yes Figure 3 A schematic cross-sectional view of the branch section of the connecting structure at point B-B1. Figure 2The difference in this embodiment is that the second electrode 32 does not fill the fourth groove 50b.

[0058] The second electrode 32 fills the third groove 32b, and the second electrode 32 and the branch portion 62 sequentially fill the fourth groove 50b. The branch portion 62 extends along the third direction Z and is spaced apart along the second direction Y within the fourth groove 50b (the region corresponding to the isolation structure 50). In the region between the corresponding isolation structures 50, since the first electrode 31 fills the second groove 32a and the second electrode 32 fills the third groove 32b, there are no branch portions 62 in the second groove 32a and the third groove 32b.

[0059] Please see Figure 5 and Figure 6 , Figure 5 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 3 , Figure 6 yes Figure 1 Top view of the semiconductor device at point A-A1 Figure 4 These two embodiments are similar to... Figure 2 The difference in the embodiment is that the second electrode 32 does not fill the fourth groove 50b.

[0060] The second electrode 32 still fills the third groove 32b, and the second electrode 32 and the first spacer structure 90 sequentially fill the fourth groove 50b. In some embodiments, the first spacer structure 91 includes an insulating layer and / or an air gap. Figure 5 and Figure 6 The difference in the embodiments is that, Figure 5 The first spacer structure 91 includes an air gap, while Figure 6 The first spacer structure 91 includes an insulating layer.

[0061] Please see Figure 7 , Figure 7 yes Figure 6 A cross-sectional view of the first spacing structure at point B-B1. In the region corresponding to the isolation structure 50, the first spacing structure 91 extends in the third direction Z and is spaced out in the second direction Y.

[0062] In other examples, the first spacer structure 91 may include both an insulating layer and an air gap, the air gap being surrounded by the insulating layer.

[0063] Please see Figure 8 and Figure 9 , Figure 8 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 2 , Figure 9 yes Figure 8Top view of the semiconductor device at point A-A1 Figure 1 This embodiment is similar to... Figure 1 The difference in the embodiment is that the second electrode 32 does not completely fill the third groove 32b.

[0064] like Figure 8 As shown, the second electrode 32 and the second spacer structure 92 sequentially fill the third groove 32b; as Figure 9 As shown, the second electrode 32 and the first spacer structure 91 sequentially fill the fourth groove 50b. In some embodiments, the first spacer structure 91 includes an insulating layer and / or an air gap, and the second spacer structure 92 includes an insulating layer and / or an air gap. For example, Figure 9 In this embodiment, the first spacing structure 91 includes an air gap; Figure 8 In this embodiment, the second spacing structure 92 includes an air gap. The dielectric constant of the air gap is much smaller than that of solid insulating media such as silicon oxide and silicon nitride, thus exhibiting excellent electrical isolation performance.

[0065] Compared to Figure 1 and Figure 2 In this embodiment, the structure avoids the problems of large interlayer parasitic capacitance and severe coupling interference between upper and lower electrodes caused by the filling of fully conductive materials. By utilizing the insulating properties of the low dielectric constant of the hollow air gap, the electric field coupling and capacitance crosstalk between the upper and lower capacitor units are significantly weakened, effectively reducing interlayer parasitic parameters and adapting to the low-interference operation requirements of ultra-high density, high-layer stacked arrays. In addition, air gaps are formed in the third groove 32b and the fourth groove 50b, meaning that the second electrode 32 does not need to be completely filled, thus reducing the difficulty of filling the second electrode 32 and simplifying the process.

[0066] Please see Figure 10 and Figure 11 , Figure 10 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 2 , Figure 11 yes Figure 10 A schematic cross-sectional view of the branch section of the connecting structure at point B-B1. Figure 9 The difference in the embodiments is that the first spacer structure 91 includes an insulating layer.

[0067] like Figure 8 As shown, the second electrode 32 and the second spacer structure 92 sequentially fill the third groove 32b; as Figure 10 As shown, the second electrode 32 and the first spacer structure 91 sequentially fill the fourth groove 50b. The first spacer structure 91 includes an insulating layer, such as... Figure 11As shown, in the region corresponding to the isolation structure 50, the first spacing structure 91 extends in the third direction Z and is spaced out in the second direction Y.

[0068] Please see Figure 12 , Figure 12 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 3 This embodiment is similar to... Figure 9 The difference in this embodiment is that the second electrode 32 fills the fourth groove 50b. For example... Figure 8 As shown, the second electrode 32 and the second spacer structure 92 sequentially fill the third groove 32b; as Figure 12 As shown, the second electrode 32 fills the fourth groove 50b.

[0069] Please see Figure 13 and Figure 14 , Figure 13 yes Figure 8 Top view of the semiconductor device at point A-A1 Figure 4 , Figure 14 yes Figure 13 A schematic cross-sectional view of the branch section of the connecting structure at point B-B1. Figure 9 The difference in the embodiment is that the branch 62 is also located within the fourth groove 50b.

[0070] like Figure 8 As shown, the second electrode 32 and the second spacer structure 92 sequentially fill the third groove 32b; as Figure 13 As shown, the second electrode 32 and the branch portion 62 sequentially fill the fourth groove. Figure 14 As shown, the branch portion 62 extends along the third direction Z within the fourth groove 50b (the area corresponding to the isolation structure 50) and is spaced apart along the second direction Y. In the area between the corresponding isolation structures 50, since the first electrode 31 fills the second groove 32a and the second electrode 32 and the second spacing structure 92 sequentially fill the third groove 32b, there is no branch portion 62 in the second groove 32a and the third groove 32b.

[0071] Please see Figures 15 to 17 , Figure 15 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 3 , Figure 16 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 1 , Figure 17 yes Figure 16 A schematic cross-sectional view of the branch section of the connecting structure at point B-B1. Figure 15 Examples and Figure 8The difference in the embodiment is that a branch portion 62 is formed in the third groove 32b.

[0072] The second electrode 32 and the branch portion 62 sequentially fill the third groove 32b and the fourth groove 50b. In other words, the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b, and the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b and the fourth groove 50b. Alternatively, the second electrode 32 and the branch portion 62 together fill the third groove 32b and together fill the fourth groove 50b. Figure 16 and Figure 17 As shown, the branch 62 extends along the third direction Z in the fourth groove 50b (the area corresponding to the isolation structure 50); while in the area between the corresponding isolation structures 50, since the third groove 32b and the first groove 31a are arranged alternately along the third direction Z, the branch 62 in the third groove 32b and the branch 62 in the first groove 31a are arranged alternately along the third direction Z.

[0073] It should be noted that, Figure 17 Different patterns are used to distinguish the branch portions 62 in the third groove 32b and the first groove 31a, and the dimensions of the branch portions 62 in the third groove 32b and the first groove 31a along the third direction Z are not limited in this embodiment.

[0074] This embodiment maximizes the electrode contact area, effectively reduces contact resistance, and weakens signal loss. Simultaneously, the branch 62, embedded in the third groove 32b and the fourth groove 50b, forms a mechanical locking mechanism to prevent electrode misconnection, detachment, and open circuits, improving the long-term reliability of the array. The connection structure 60 uses a low-resistance conductive material, which further reduces the global electrode parasitic resistance, balances the electrode potential across the entire layer, and significantly improves the read / write consistency and operational stability of the three-dimensional storage array.

[0075] Please see Figure 18 , Figure 18 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 2 This embodiment is similar to Figure 16 The difference in this embodiment is that the second electrode 32 fills the fourth groove 50b. For example... Figure 15 As shown, the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b; as Figure 18 As shown, the second electrode fills the fourth groove.

[0076] Please see Figure 19 , Figure 19 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 3 This embodiment is similar to Figure 16 The difference in this embodiment is that the branch 62 is not formed within the fourth groove 50b. For example... Figure 15 As shown, the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b; as Figure 19 As shown, the second electrode 32 and the first spacing structure 91 sequentially fill the fourth groove 50b.

[0077] In some embodiments, the first spacing structure 91 may include an insulating layer and / or a gap. Figure 19 The first interval structure 91, including the gap, will be used as an example for explanation.

[0078] Please see Figure 20 and Figure 21 , Figure 20 yes Figure 15 Top view of the semiconductor device at point A-A1 Figure 4 , Figure 21 yes Figure 20 A schematic cross-sectional view of the middle branch and the first spacer structure at point B-B1. This embodiment is similar to... Figure 19 The difference in the embodiments is that the first spacer structure 91 includes an insulating layer.

[0079] like Figure 15 As shown, the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b; as Figure 20 As shown, the second electrode 32 and the first spacer structure 91 sequentially fill the fourth groove 50b. Figure 21 As shown, the first spacing structure 91 extends along the third direction Z within the fourth groove 50b (the area corresponding to the isolation structure 50) and is spaced apart along the second direction Y. Since the third groove 32b is spaced apart along the third direction Z, the branches 62 are also spaced apart along the third direction Z.

[0080] Please see Figures 22 to 24 , Figure 22 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 4 , Figure 23 yes Figure 22 A top view of the semiconductor device at point A-A1. Figure 24 yes Figure 23 A schematic cross-sectional view of the first and second spacer structures at point B-B1. This embodiment is similar to... Figure 8 The difference in the embodiment is that the second spacer structure 92 includes an insulating layer.

[0081] like Figure 22 As shown, the second electrode 32 and the second spacer structure 92 sequentially fill the third groove 32b; as Figure 23 As shown, the second electrode 32 and the first spacer structure 91 sequentially fill the fourth groove 50b. The first spacer structure 91 includes an insulating layer, and the second spacer structure 92 includes an insulating layer. Figure 24 As shown, in the region corresponding to the isolation structure 50, the first spacing structure 91 extends in the third direction Z and is spaced apart in the second direction Y. In the region between the corresponding isolation structures 50, since the third grooves 32b are spaced apart in the third direction Z, the second spacing structures 92 are also spaced apart in the third direction Z.

[0082] In some embodiments, the first spacer structure 91 may further include an insulating layer and a gap, or may only include a gap.

[0083] In other embodiments, the second electrode fills the fourth groove (see reference). Figure 12 Alternatively, the second electrode and the branch portion sequentially fill the fourth groove (refer to...). Figure 13 ).

[0084] In some embodiments, the transistor 20 includes a channel layer 21 and a gate layer 22. The gate layer 22 surrounds a portion of the surface of the channel layer 21, and the gate layer 22 exposes at least a portion of the sidewalls of the channel layer 21. The sidewalls are connected to the first electrode 31. The transistor 20 adopts a surround gate structure, which fully covers the channel layer 21, greatly improving the gate control capability. Only one sidewall is reserved as an electrical connection terminal, which is precisely connected to the first electrode 31.

[0085] The transistor 20 also includes a gate insulating layer 23 located between the gate layer 22 and the channel layer 21, the gate insulating layer 23 also exposing the portion of the sidewall of the channel layer 21.

[0086] In some embodiments, the semiconductor device further includes a spacer structure 40 located between the channel layer 21 and two adjacent insulating layers 11, and between the gate layer 22 and the first electrode 31.

[0087] By utilizing the space between the insulating layer 11 and the channel layer 21 to set the spacing structure 40, not only can the gate layer 22 and the first electrode 31 be effectively isolated, reducing the risk of short circuit failure between the gate layer 22 and the first electrode 31, but also the channel layer 21 can be protected, interface defects and leakage channels can be repaired, further reducing the leakage current of the transistor 20 and improving the stability and reliability of the device during long-term operation.

[0088] Please see Figure 25 , Figure 25This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application. The difference between this embodiment and the above embodiments is that this embodiment shows more array structures of the semiconductor device.

[0089] In the first direction X, two capacitor structures 30 are symmetrically distributed on both sides of the connecting structure 60, and the two capacitor structures 30 share a single connecting structure 60. Within one capacitor structure 30, multiple capacitors are also arranged at intervals along the second direction Y. The connecting structure 60 extends along the second direction Y to connect the multiple capacitors arranged along the second direction Y.

[0090] In some embodiments, the semiconductor device further includes a word line 70 extending along a second direction Y and a bit line 80 extending along a third direction Z. The word line 70 is connected to the gate layer 22 of the plurality of transistors 20. The channel layer 21 is disposed around the surface of the bit line 80. The third direction Z is the stacking direction of the insulating layer 11. The second direction Y is perpendicular to the third direction Z.

[0091] Each word line 70 is connected to multiple gate layers 22 located on the same side of the word line 70, and the word line 70 and the multiple gate layers 22 are connected in the same layer. A transistor 20 is disposed between the word line 70 and the capacitor structure 30. The word line 70 controls the conduction and turn-off of the transistor 20. The transistor 20, sandwiched between the word line 70 and the capacitor, acts as a dedicated switch for the capacitor. When on, the bit line 80 can quickly charge and discharge the capacitor to complete data reading and writing; when off, it completely cuts off the path between the capacitor and the external circuit, latching the charge and retaining the data.

[0092] In some examples, the channel layer 21 may be made of at least one of amorphous AOS oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), and indium zinc oxide (IZO). The gate insulating layer 23 may be made of single-layer or multi-layer composite dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide. The gate layer 22, word line 70, and bit line 80 are made of conductive materials, such as highly conductive and stable materials like tungsten, titanium, titanium nitride, cobalt, and polycrystalline silicon.

[0093] In the embodiments of this application, the semiconductor device adopts a vertical bit line (V-BL) architecture with word lines 70 and bit lines 80 arranged orthogonally. The addressing logic is clear and the array arrangement is regular, which can realize high-density cell precise addressing. It is perfectly adapted to the working mechanism of 3D DRAM vertical stacking and solves the defects of traditional planar transistors such as weak gate control, large leakage current and low array density.

[0094] In some embodiments, the semiconductor device further includes a word line slot structure 71 extending along the second direction Y, consistent with the extension direction of the word line 70. If a capacitor structure 30 and a plurality of transistors 20 on both sides are considered as a memory cell group 101, the word lines 70 between two adjacent memory cell groups 101 in the first direction X are separated by the word line slot structure 71 to avoid signal coupling between them.

[0095] Accordingly, embodiments of this application provide a method for forming a semiconductor device, used to form the aforementioned semiconductor device. Please refer to... Figure 26 , Figure 26 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: S1: Forming a stacked layer, the stacked layer comprising an insulating layer and a dielectric layer alternately stacked along a third direction; S2: Forming a transistor, the transistor being located between two adjacent insulating layers, the transistor having a first groove adjacent to it in a first direction, at least a portion of the first groove being located between two adjacent insulating layers; S3: Forming a capacitor structure, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; the first electrode fills the first groove and is connected to the transistor in the first direction, the second electrode is located on the surface of the first electrode; wherein, along the third direction, two adjacent layers of the first electrode and the insulating layer form a second groove, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forms a third groove in the second groove, and the second electrode at least covers the inner wall of the third groove.

[0096] In the semiconductor device formed in this application embodiment, a transistor has a first groove adjacent to it in a first direction. At least a portion of the first groove is located between two adjacent insulating layers. The first electrode fills the first groove to form a three-dimensional solid structure with multiple exposed surfaces. The second electrode completely covers the exposed surface of the first electrode. Without changing the lateral layout size of the cell and without occupying additional chip area, the effective area of ​​the first and second electrodes facing each other is increased, significantly improving the energy storage capacity and thus increasing the storage density. At the same time, at least a portion of the first electrode is located between adjacent insulating layers, and the interlayer insulating layer provides structural constraint support, improving the overall structural stability. Furthermore, the solid structure of the second electrode can provide effective support for the subsequent conformal coverage of the second electrode, reducing the risk of device collapse during the formation process.

[0097] The method for forming a semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0098] Please see Figures 27 to 58 , Figures 27 to 58 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0099] Step S1: Form a stacked layer 10a, the stacked layer 10a comprising an insulating layer 11 and a dielectric layer 12 alternately stacked.

[0100] See Figure 27 and Figure 28 , Figure 28 yes Figure 27 A top view of the structure at point A-A1.

[0101] A substrate 102 is provided, and a stacked layer 10a is formed on the substrate 102. The stacked layer 10a includes an insulating layer 11 and a dielectric layer 12 alternately stacked. An exemplary material for the insulating layer 11 is silicon oxide, and an exemplary material for the dielectric layer 12 is silicon nitride. The insulating layer 11 and the dielectric layer 12 have different etching selectivity. The deposition process for the insulating layer 11 and the dielectric layer 12 can employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0102] The method for forming the semiconductor device further includes: forming an isolation structure 50 extending through the stacked layer 10a along the third direction Z, wherein the isolation structure 50 is located between two adjacent transistors 20 in the second direction Y. The isolation structure 50 defines the formation space of the transistors 20 in the second direction Y.

[0103] For example, after the stacked layer 10a is formed, an isolation structure 50 is prepared vertically through the third direction Z by deep trench etching and dielectric filling processes. This structure is then arranged at equal intervals along the second direction Y to complete the partitioning and isolation of the memory cells in the second direction Y. The isolation structure 50 is mainly used to isolate the transistor 20 and the first electrode 31, and at least a portion of the isolation structure 50 can provide film-forming space for the dielectric layer 33 and the second electrode 32 of the subsequent capacitor structure 30, so as to form a continuous common outer electrode plate in the second direction Y.

[0104] S2: Forming a transistor 20, the transistor 20 being located between two adjacent insulating layers 11.

[0105] See Figures 29 to 58 It should be noted that the top view following each cross-sectional view is the top view of the corresponding semiconductor device at A-A1 (i.e., the layer where dielectric layer 12 is located), and will not be explained one by one.

[0106] The method for forming the transistor 20 includes the following steps.

[0107] See Figures 29 to 32 A through hole 20a is formed that penetrates the stacked layer 10a along the third direction Z. The through hole 20a includes a connected bit line hole 80a and a channel hole 21a. The channel hole 21a is disposed around the sidewall of the bit line hole 80a.

[0108] like Figure 29 and Figure 30 As shown, a bit line via 80a is first formed along the third direction Z, penetrating the stacked layer 10a. The bit line via 80a is located between two adjacent isolation structures 50 in the second direction Y. The formation process of the bit line via 80a may include anisotropic dry etching. For example... Figure 31 and Figure 32 As shown, a portion of the dielectric layer 12 is partially etched through the bit line hole 80a to form a channel hole 21a surrounding the sidewall of the bit line hole 80a. The etching process may include a wet etching process, in which the dielectric layer 12 has a higher etching selectivity than the insulating layer 11.

[0109] See Figures 33 to 36 A gate layer 22, a gate insulating layer 23, and a sacrificial layer 24 are sequentially formed within the through hole 20a, with the gate layer 22 and the gate insulating layer 23 located on the inner wall of the channel hole 21a.

[0110] like Figure 33 and Figure 34 As shown, the formation processes of the gate layer 22 and the gate insulating layer 23 can both include deposition processes and etch-back processes, so that the gate layer 22 and the gate insulating layer 23 are formed only within the channel via 21a, and are disconnected at the sidewall of the bit line via 80a. Figure 35 and Figure 36 As shown, the process of forming the sacrificial layer 24 may include a deposition process and a planarization process, so that the sacrificial layer 24 fills the remaining space of the channel hole 21a and the bit line hole 80a.

[0111] In some embodiments, see Figures 37 to 38 The formation of the semiconductor device also includes forming word lines 70 extending along the second direction Y.

[0112] Specifically, a word line slot 71a extending in the second direction Y is formed on the side of the transistor 20 away from the capacitor structure 30; a portion of the dielectric layer 12 is removed through the word line slot 71a to form a word line groove 70a.

[0113] See Figure 39 and Figure 40A character line 70 is formed in the character line groove 70a, and a character line gap structure 71 is formed in the character line gap 71a.

[0114] See Figure 43 and Figure 44 A portion of the gate layer 22 and a portion of the gate insulating layer 23 are removed to form the first groove 31a that exposes the sacrificial layer 24.

[0115] Specifically, the dielectric layer 12 can be removed first through the capacitor trench 60a to expose the gate layer 22 and the gate insulating layer 23; then, part of the gate layer 22 and part of the gate insulating layer 23 can be removed through an etching process.

[0116] The purpose of this step is to expose part of the sacrificial layer 24 so that when the sacrificial layer 24 is subsequently replaced with the channel layer 21, part of the sidewalls of the channel layer 21 can also be exposed so as to connect with the first electrode 31.

[0117] See Figures 55 to 58 The sacrificial layer 24 is removed, and a channel layer 21 connected to the first electrode 31 is formed within the channel hole 21a. For example... Figure 55 and Figure 56 As shown, the entire sacrificial layer 24 can be removed by etching after the entire capacitor structure 30 has been formed. Figure 57 and Figure 58 As shown, a channel layer 21 is deposited in the channel hole 21a to achieve precise electrical connection between the channel layer 21 and the first electrode 31.

[0118] In this embodiment, the sacrificial layer 24 is removed after the capacitor structure 30 is formed, and then the channel layer 21 is formed. By using the temporary protection technology of the sacrificial layer 24 and the post-channel forming process, the performance damage of the semiconductor channel material to the early high temperature and etching processes can be avoided, and the electrical performance of the transistor 20 can be stabilized.

[0119] In some embodiments, a single deposition process can be used to fill the channel hole 21a and cover the sidewall of the bit line hole 80a with the channel layer 21, and the bit line 80 is formed on the surface of the channel layer 21 and fills the bit line hole 80a.

[0120] In other embodiments, the channel layer 21 can be located only within the channel hole 21a by deposition and etch-back processes.

[0121] S3: Form a capacitor structure 30, the capacitor structure 30 including a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 is located between two adjacent insulating layers 11 and is connected to the transistor 20. The surface of the first electrode 31 facing away from the transistor 20 forms a first groove 31a. A second groove 32a is formed between two adjacent layers of the first electrode 31 and the insulating layer 11. The second electrode 32 is located on the inner wall of the first groove 31a and the inner wall of the second groove 32a. The second electrode 32 at least fills the second groove 32a.

[0122] See Figures 41 to 54 The method for forming the capacitor structure 30 includes the following steps.

[0123] See Figure 41 and Figure 42 A capacitor groove 60a is formed that penetrates the stacked layer 10a along a third direction Z. The capacitor groove 60a extends along a second direction Y. The third direction Z is the stacking direction of the stacked layer 10a. The second direction Y is perpendicular to the third direction Z.

[0124] A deep trench etching process is used to form a long strip capacitor trench 60a that penetrates the entire stacked layer 10a and extends along the second direction Y, forming a vertical third direction Z. This opens up the process window for capacitor fabrication in each layer. It should be noted that the capacitor trench 60a is filled at the end of the process to form the main body 61 of the connection structure 60.

[0125] See Figure 43 and Figure 44 A portion of the dielectric layer 12 is removed through the capacitor groove 60a to form a first groove 31a.

[0126] By utilizing the etching selectivity ratio between the dielectric layer 12 and the insulating layer 11, a portion of the dielectric layer 12 is selectively etched away through the capacitor trench 60a to form the first trench 31a. The partial removal of the gate layer 22 and the gate insulating layer 23, as described above, is also performed through this capacitor trench 60a.

[0127] In some embodiments, see Figure 45 and Figure 46 The method for forming the semiconductor device further includes forming a spacer structure 40 between the channel layer 21 and two adjacent insulating layers 11, and between the gate layer 22 and the first electrode 31. Similarly, the spacer structure 40 is also formed between the isolation structures 50 and on the exposed sidewalls of the gate layer 22.

[0128] The formation process of the spacer structure 40 includes a deposition process and an etch-back process, which enables the spacer structure 40 to isolate and protect the exposed gate layer 22.

[0129] See Figure 47 and Figure 48 The first electrode 31 is filled in the first groove 31a.

[0130] The method for forming the first electrode 31 may include a deposition process and an etch-back process, such that the first groove 31a is filled, while the layers of first electrodes 31 are disconnected from each other.

[0131] See Figure 49 and Figure 50 A portion of the insulating layer 11 is removed through the capacitor groove 60a to form a second groove 32a.

[0132] By selectively etching the interlayer local insulating layer 11 through the window of the reused capacitor trench 60a, a necked second groove 32a (i.e., recessed relative to the first groove 31a) is formed. It should be noted that after removing part of the insulating layer 11, the stacked layer 10a becomes the stacked structure 10. For example... Figure 50 As shown, the method for forming the semiconductor device further includes: in the process of forming the second groove 32a, removing a portion of the isolation structure 50 to form a trench 50a. The material of the isolation structure 50 is the same as the material of the insulating layer 11, and the trench 50a is connected to the multilayer second groove 32a.

[0133] See Figures 51 to 53 A dielectric layer 33 and a second electrode 32 are sequentially formed on the inner walls of the first groove 31a and the second groove 32a. Simultaneously, as... Figure 52 and Figure 54 As shown, the dielectric layer 33 and the second electrode 32 are also formed on the inner wall of the trench 50a. For example, using ALD atomic layer deposition process, the dielectric layer 33 and the second electrode 32 are conformally deposited sequentially on the inner wall of the entire double trench, completing the integrated molding of the three-layer structure of the MIM capacitor.

[0134] In some embodiments, a dielectric layer 33 is formed first, followed by the formation of a second electrode 32. The dielectric layer 33 forms a third groove 32b within the second groove 32a (e.g., ...). Figure 51 As shown), the dielectric layer 33 simultaneously forms a fourth groove 50b within the trench 50a (as shown). Figure 52 (As shown).

[0135] In other embodiments, the second electrode 32 can directly fill the second groove 32a and trench 50a, that is, the third groove 32b and the fourth groove 50b are not formed.

[0136] It should be noted that by adjusting the thickness of the insulating layer 11 and the thickness of the second electrode 32, common outer electrode plates with different structures can be formed. For example, in Figure 53 In the process, if the size of the second groove 32a matches the thickness of the second electrode 32, then the second electrode 32 can fill the second groove 32a, and the third groove 32b will not be formed, thus forming a... Figure 1 The corresponding structure.

[0137] Since the entire forming process of capacitor structure 30 reuses the same capacitor groove 60a process window, multiple alignments and groovings are unnecessary, greatly simplifying the process flow, reducing alignment deviations and process complexity, and effectively improving capacitor forming accuracy and array unit uniformity. In addition, the first electrode 31 directly fills the first groove 31a, effectively simplifying the process and reducing process difficulty.

[0138] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0139] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0140] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, including insulating layers stacked along a third direction; A transistor is located between two adjacent insulating layers, the transistor having a first groove adjacent to it in a first direction, at least a portion of the first groove being located between the two adjacent insulating layers; A capacitor structure includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; The first electrode fills the first groove and is connected to the transistor in the first direction, which is perpendicular to the third direction; Wherein, the first electrode and the insulating layer form a second groove between two adjacent layers along the third direction, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forms a third groove in the second groove, and the second electrode at least covers the inner wall of the third groove.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: an isolation structure extending along the third direction and spaced apart along the second direction, the second direction being perpendicular to the third direction and intersecting the first direction; The transistor is located between two adjacent isolation structures in the second direction; two adjacent first electrodes in the same layer along the second direction form a trench with the isolation structure, the dielectric layer is in contact with the inner wall of the trench, the dielectric layer forms a fourth groove in the trench, and the second electrode is also located at least on the inner wall of the fourth groove.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a connection structure connected to the second electrode, the connection structure including a main body and a branch, the main body extending along the third direction and the second direction, and the branch extending along the first direction.

4. The semiconductor device according to claim 3, characterized in that, The second electrode and the branch portion sequentially fill the third groove and the fourth groove.

5. The semiconductor device according to claim 3, characterized in that, The second electrode and the branch portion sequentially fill the third groove, and the second electrode fills the fourth groove.

6. The semiconductor device according to claim 3, characterized in that, The second electrode fills the third groove, and the second electrode and the branch successively fill the fourth groove.

7. The semiconductor device according to claim 3, characterized in that, The second electrode and the branch portion sequentially fill the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

8. The semiconductor device according to claim 3, characterized in that, The second electrode and the second spacer structure sequentially fill the third groove, and the second electrode and the branch sequentially fill the fourth groove.

9. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a connection structure connected to the second electrode, the connection structure extending along the third direction and the second direction.

10. The semiconductor device according to claim 9, characterized in that, The second electrode fills the third groove, and the second electrode fills the fourth groove.

11. The semiconductor device according to claim 9, characterized in that, The second electrode fills the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

12. The semiconductor device according to claim 9, characterized in that, The second electrode and the second spacer structure sequentially fill the third groove, and the second electrode fills the fourth groove.

13. The semiconductor device according to claim 9, characterized in that, The second electrode and the second spacer structure sequentially fill the third groove, and the second electrode and the first spacer structure sequentially fill the fourth groove.

14. The semiconductor device according to any one of claims 7, 10-13, characterized in that, Both the first spacer structure and the second spacer structure include an insulating layer and / or an air gap.

15. The semiconductor device according to any one of claims 2-13, characterized in that, The transistor includes a channel layer and a gate layer, the gate layer surrounding a portion of the surface of the channel layer, and the gate layer exposing at least a portion of the sidewalls of the channel layer, the portion of the sidewalls being connected to the first electrode; The semiconductor device further includes word lines extending in a second direction and bit lines extending in a third direction, the word lines being connected to the gate layers of the plurality of transistors, and the channel layers being disposed around the surface of the bit lines.

16. A method for forming a semiconductor device, characterized in that, include: A stacked layer is formed, the stacked layer comprising an insulating layer and a dielectric layer alternately stacked along a third direction; A transistor is formed, the transistor being located between two adjacent insulating layers, the transistor having a first groove adjacent to it in a first direction, at least a portion of the first groove being located between two adjacent insulating layers; A capacitor structure is formed, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode; The first electrode fills the first groove and is connected to the transistor in the first direction, and the second electrode is located on the surface of the first electrode; Wherein, the first electrode and the insulating layer form a second groove between two adjacent layers along the third direction, the dielectric layer is in contact with the surface of the first electrode and the inner wall of the second groove, the dielectric layer forms a third groove in the second groove, and the second electrode at least covers the inner wall of the third groove.

17. The method for forming a semiconductor device according to claim 16, characterized in that, The formation of the capacitor structure includes: A capacitor groove is formed that penetrates the stacked layer along the third direction, the capacitor groove extends along the second direction, the third direction is the stacking direction of the stacked layer, and the second direction is perpendicular to the third direction; A portion of the dielectric layer is removed through the capacitor trench to form a first groove; The first electrode is filled into the first groove; A second groove is formed by removing part of the insulating layer through the capacitor groove; A dielectric layer and a second electrode are sequentially formed on the surface of the first electrode and the inner wall of the second groove.

18. The method for forming a semiconductor device according to claim 17, characterized in that, The formation of the transistor includes: A through hole is formed along the third direction through the stacked layer. The through hole includes a connected bit line hole and a channel hole, and the channel hole is disposed around the sidewall of the bit line hole. A gate layer, a gate insulating layer, and a sacrificial layer are sequentially formed within the through-hole, wherein the gate layer and the gate insulating layer are located on the inner wall of the channel hole; The capacitor trench removes a portion of the gate layer and a portion of the gate insulating layer to form the first groove that exposes the sacrificial layer; Remove the sacrificial layer and form a channel layer connected to the first electrode within the channel hole.

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