Split-gate flash memory and method of manufacturing the same

Abstract

The present application provides a split-gate flash memory and a manufacturing method thereof. The memory includes a semiconductor substrate having an active region and isolation structures, part of the isolation structure surface is lower than the active region surface to expose part of the active region sidewall; a first dielectric layer covers the top of the active region and the exposed sidewall; a floating gate is located on the surface of the first dielectric layer, surrounds the top of the active region and the exposed sidewall, and has a pointed end structure; an inter-electrode dielectric layer is located on the surface of the floating gate; a control gate is located on the surface of the inter-electrode dielectric layer; a second dielectric layer is located on the sidewall of the floating gate, the inter-electrode dielectric layer and the control gate; and a word line is located on the sidewall of the second dielectric layer. The present application increases the control of the channel by the floating gate surrounding the channel, reduces the risk of punch-through, improves the erase efficiency by the discharge effect of the pointed end of the floating gate, has a simple process and is compatible with the existing process, and improves the product yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a gate-divided flash memory and its manufacturing method. Background Technology

[0002] Flash memory, as a type of non-volatile memory, is widely used in various electronic devices because it retains data even when power is off and has electrically erasable and rewritable characteristics. With the continuous miniaturization of semiconductor process nodes, the industry has placed higher demands on the integration density, power consumption, erasure and write efficiency, and reliability of flash memory.

[0003] Currently, the mainstream split-gate flash memory cell structures each have their own advantages and disadvantages. Please refer to... Figure 1 The second-generation ESF2 (Extra Flash Memory) structure not only has a larger device area, but also higher dynamic power consumption during read operations, making it difficult to meet the requirements of low-power applications. Please refer to [reference needed]. Figure 2 While the third-generation ESF3 flash memory structure has a relatively small device area, its manufacturing process is complex, and the excessively high source line (SL) resistance affects device performance. Please refer to [reference needed]. Figure 3 Although the fourth-generation ultra-fast flash memory (ESF4, similar to a low threshold voltage cell) has a relatively simple process, its device area is large, and it also suffers from the problem of excessive source line resistance.

[0004] Furthermore, as memory cell sizes continue to shrink, the lateral diffusion effect of the source / drain junction (S / D junction) becomes increasingly significant. This not only easily leads to severe punch-through risks but also causes a shift in the floating gate threshold voltage (Vtfg shift), thus severely compressing the operating window of the memory cell and reducing product yield and reliability. Meanwhile, the erase efficiency of traditional floating gate structures is often limited by the structure itself, making further improvements difficult.

[0005] Therefore, the industry urgently needs a new flash memory storage structure and its manufacturing process to simplify the process, be compatible with existing processes, effectively improve the floating gate's control over the channel, reduce the risk of punch-through, and improve erasure efficiency and product reliability. Summary of the Invention

[0006] The technical problem this invention aims to solve is that existing segmented flash memories are prone to severe punch-through risks as their size continues to shrink, and lateral diffusion of the source-drain junction can lead to a shift in the floating gate threshold voltage, compressing the operating window of the memory cell. Simultaneously, the erase efficiency of existing structures is limited, and some structures have complex manufacturing processes, high power consumption, or large device area. To address these problems, this invention provides a novel segmented flash memory and its fabrication method.

[0007] This invention provides a gate-divided flash memory, comprising:

[0008] A semiconductor substrate having an active region and an isolation structure, wherein a portion of the surface of the isolation structure is lower than the surface of the active region to expose a portion of the sidewalls of the active region and a groove is formed between adjacent active regions;

[0009] A first dielectric layer covers the top of the active region and the exposed sidewalls of the active region;

[0010] A floating gate is located on the surface of the first dielectric layer. The floating gate surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove. The floating gate has a pointed structure.

[0011] An inter-electrode dielectric layer is located on the surface of the floating gate;

[0012] The control gate is located on the surface of the inter-electrode dielectric layer;

[0013] The second dielectric layer is located on the sidewall of the floating gate, the inter-electrode dielectric layer, and the control gate;

[0014] The word line is located on the sidewall of the second dielectric layer;

[0015] The source and drain doped regions are located within the semiconductor substrate on both sides of the word line and the floating gate.

[0016] Preferably, the floating gate, the control gate, and the word line are made of polycrystalline silicon.

[0017] Preferably, the materials of the first dielectric layer and the second dielectric layer include silicon oxide.

[0018] Preferably, the inter-electrode dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

[0019] Preferably, it further includes a floating grid sidewall, which is located on the control grid sidewall.

[0020] Preferably, it further includes a source / drain sidewall located on the sidewall of the floating gate and the control gate away from the word line.

[0021] The present invention also provides a method for manufacturing a gate-divided flash memory, comprising:

[0022] Step 1: Provide a semiconductor substrate, wherein an active region and an isolation structure are formed within the semiconductor substrate;

[0023] Step 2: Etch part of the isolation structure so that the surface of part of the isolation structure is lower than the surface of the active region, exposing part of the sidewall of the active region, and forming a groove between adjacent active regions;

[0024] Step 3: Form a first dielectric layer on the top of the active region and the exposed sidewalls of the active region;

[0025] Step 4: Form a first conductive layer on the surface of the first dielectric layer. The first conductive layer surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove.

[0026] Step 5: Sequentially form an inter-electrode dielectric layer and a second conductive layer on the surface of the first conductive layer;

[0027] Step 6: Pattern the second conductive layer, the inter-electrode dielectric layer, and the first conductive layer to form a control gate and a floating gate, and make the floating gate form a tip structure;

[0028] Step 7: Form a second dielectric layer on the sidewalls of the floating gate, the inter-electrode dielectric layer, and the control gate, and form a third conductive layer as a word line on the sidewalls of the second dielectric layer;

[0029] Step 8: Form source / drain doped regions in the semiconductor substrate on both sides of the word line and the floating gate.

[0030] Preferably, in step one, forming the active region and the isolation structure includes: sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate; patterning the second mask layer, the first mask layer and the semiconductor substrate to form a trench; filling the trench with an isolation medium and performing planarization treatment to expose the second mask layer to form the isolation structure.

[0031] Preferably, the first mask layer includes a base oxide layer, and the second mask layer includes a base silicon nitride layer.

[0032] Preferably, in step two, before etching the isolation structure, the second mask layer is removed.

[0033] Preferably, in step four, forming the first conductive layer includes: depositing a first conductive material, the first conductive material covering the first dielectric layer and the isolation structure, and completely filling the groove; and planarizing the first conductive material.

[0034] Preferably, in step five, after forming the second conductive layer, a third mask layer is formed on the surface of the second conductive layer.

[0035] Preferably, in step six, the patterning process includes: etching the third mask layer and the second conductive layer to form the control gate; forming a floating gate sidewall on the sidewall of the control gate; using the floating gate sidewall as a mask, etching the inter-electrode dielectric layer and the first conductive layer to form the floating gate, and using an etching process to form the tip structure of the floating gate.

[0036] Preferably, in step seven, forming the word line includes: depositing a second dielectric material and a third conductive material; planarizing the third conductive material; and patterning the third conductive material to form the word line.

[0037] Preferably, in step eight, before forming the source / drain doped regions, the method further includes: depositing a sidewall dielectric layer and etching it to form source / drain sidewalls on the sidewalls of the floating gate and the control gate away from the word line.

[0038] As described above, the gate-divided flash memory and its manufacturing method of the present invention have the following beneficial effects:

[0039] The novel gate-based flash memory structure and its formation method provided by this invention are simple to manufacture and highly compatible with existing embedded flash memory processes, reducing the need for four high-temperature furnace tube processes. By enabling the floating gate to surround the channel in three dimensions from the top and sides, the control capability of the floating gate over the channel is significantly increased, greatly reducing the punch-through risk caused by the miniaturization of memory cells. The pointed structure formed on the top of the floating gate can greatly improve the erasure efficiency by utilizing the tip discharge effect. In addition, this structure effectively reduces the floating gate threshold voltage offset caused by the lateral diffusion of the source-drain junction, greatly increasing the operating window of the memory cell compared with traditional memory cells, thereby improving product yield and long-term reliability. Attached Figure Description

[0040] Figure 1 The diagram shows a cross-sectional view of the existing second-generation super flash memory (ESF2) structure;

[0041] Figure 2 The diagram shows a cross-sectional view of the existing third-generation ultra-flash memory (ESF3) structure.

[0042] Figure 3 The diagram shows a cross-sectional view of the fourth-generation ESF4 (Extra Flash Memory) structure in the prior art.

[0043] Figure 4 The diagram shows a process flow diagram of a method for forming a gated flash memory provided in an embodiment of the present invention;

[0044] Figure 5 The diagram shows a cross-sectional view after the formation of the first mask layer and the second mask layer in an embodiment of the present invention;

[0045] Figure 6 The diagram shows a cross-sectional view of the trench formed in an embodiment of the present invention.

[0046] Figure 7 The diagram shows a cross-sectional view of the isolation structure formed in an embodiment of the present invention.

[0047] Figure 8 The diagram shows a cross-sectional view after the second mask layer has been removed in an embodiment of the present invention.

[0048] Figure 9 The diagram shown is a cross-sectional view of the etched isolation structure in an embodiment of the present invention.

[0049] Figure 10 The diagram shown is a cross-sectional view after the formation of the first dielectric layer in an embodiment of the present invention.

[0050] Figure 11 The diagram shows a cross-sectional view in the X direction after the formation of the first conductive layer in an embodiment of the present invention.

[0051] Figure 12 The diagram shows a cross-sectional view in the Y direction after the formation of the first conductive layer in an embodiment of the present invention.

[0052] Figure 13 The diagram shows a cross-sectional view after the formation of the inter-electrode dielectric layer, the second conductive layer, and the third mask layer in an embodiment of the present invention.

[0053] Figure 14 The diagram shown is a cross-sectional view of the control gate formed in an embodiment of the present invention.

[0054] Figure 15 The diagram shown is a cross-sectional view of the floating grid sidewall after it has been formed in an embodiment of the present invention.

[0055] Figure 16 The diagram shows a cross-sectional view of the etching process of the inter-electrode dielectric layer and the first conductive layer in an embodiment of the present invention.

[0056] Figure 17 The diagram shown is a cross-sectional view of the floating gate and tip structure formed in an embodiment of the present invention.

[0057] Figure 18 The diagram shows a cross-sectional view after the deposition of the second dielectric material and the third conductive material in an embodiment of the present invention.

[0058] Figure 19 The diagram shows a cross-sectional view of the character lines formed in an embodiment of the present invention.

[0059] Figure 20 The diagram shown is a cross-sectional view of the source / drain sidewalls and source / drain doped regions formed in an embodiment of the present invention. Detailed Implementation

[0060] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] Please refer to Figure 20 A gate-splitter flash memory includes a semiconductor substrate 101 having an active region and an isolation structure 104, wherein a portion of the surface of the isolation structure 104 is lower than the surface of the active region to expose a portion of the active region sidewalls and to form a groove between adjacent active regions.

[0062] In some embodiments, the semiconductor substrate 101 may be a silicon substrate, and may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. The semiconductor substrate 101 may have a P-type doped well region or an N-type doped well region pre-formed within it, depending on the conductivity type of the device, and may even include a deep well region for providing deep electrical isolation. The isolation structure 104 is typically configured as a shallow trench isolation structure. Its main function is to provide reliable physical and electrical isolation between adjacent active regions in a high-density memory array, preventing leakage or crosstalk between adjacent memory cells. This specific recessed topography design exposes the top and part of the sidewalls of the active region in three-dimensional space, allowing the subsequently formed gate material to wrap around the active region from multiple directions. This three-dimensional wrapping structure increases the physical contact area between the gate and the channel region, enhancing the gate's electric field coupling capability and control over the channel carriers.

[0063] The first dielectric layer 105 covers the top of the active region and the exposed sidewalls of the active region.

[0064] In some embodiments, the material of the first dielectric layer 105 includes silicon oxide.

[0065] In other embodiments, the material of the first dielectric layer 105 may also include silicon oxynitride, fluorine-doped silicon oxynitride, carbon-doped silicon oxynitride, or dielectric materials with high dielectric constants, such as hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, or silicates and aluminates of these materials. The first dielectric layer 105 acts as a tunnel dielectric layer in a gate-divided flash memory. As a channel for charge transfer, the quality of the first dielectric layer 105 directly affects the programming and erasing efficiency of the memory cells and their data retention capability. Using high-quality thermal silicon oxynitride or high-dielectric-constant materials can effectively suppress direct tunneling leakage current in the data retention state while ensuring smooth Fowler-Nordheim tunneling or hot electron injection during programming and erasing operations, thereby extending the data retention lifetime of the memory.

[0066] The floating gate 106 is located on the surface of the first dielectric layer 105. The floating gate 106 surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove. The floating gate 106 has a pointed structure.

[0067] In some embodiments, the floating gate 106 is made of polycrystalline silicon.

[0068] In other embodiments, the material of the floating gate 106 may also include amorphous silicon, doped polycrystalline silicon, polycrystalline silicon-germanium alloy, or composite materials containing metal nanocrystals. In some advanced process nodes, the floating gate 106 may also employ a work function metal material, such as titanium nitride, tantalum nitride, tantalum carbide, tungsten, cobalt, or ruthenium, to further modulate the threshold voltage of the device and reduce the gate resistance. The structural features of the floating gate 106 surrounding the top and sidewalls of the active region form a three-dimensional enveloping configuration. This configuration significantly increases the electrostatic control capability of the floating gate 106 over the underlying channel region, greatly reducing the increasingly severe short-channel effect and punch-through risk as memory cell sizes continue to shrink. During erase operations, the tip structure can generate a strong electric field concentration effect in its local area. Utilizing this tip discharge principle, a higher charge release rate can be achieved at a lower erase voltage, thereby greatly improving erase efficiency, shortening erase time, and reducing damage to the tunnel dielectric layer caused by high-voltage operations.

[0069] The inter-electrode dielectric layer 107 is located on the surface of the floating gate 106.

[0070] In some embodiments, the inter-electrode dielectric layer 107 includes a silicon oxide-silicon nitride-silicon oxide composite layer.

[0071] In other embodiments, the inter-electrode dielectric layer 107 may also employ other multilayer stacked structures, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide composite layer, or a composite layer containing a high dielectric constant material, such as a silicon oxide-hafnium oxide-silicon oxide stack. The primary function of the inter-electrode dielectric layer 107 is to provide high capacitive coupling between the floating gate 106 and the control gate 108, allowing the voltage applied to the control gate 108 to be more effectively transferred to the floating gate 106. Simultaneously, the inter-electrode dielectric layer 107 needs to possess excellent insulation properties to prevent undesirable leakage of charge stored in the floating gate 106 to the control gate 108.

[0072] The control gate 108 is located on the surface of the inter-electrode dielectric layer 107.

[0073] In some embodiments, the control gate 108 is made of polysilicon.

[0074] In other embodiments, the material of the control gate 108 may also include doped polysilicon, metal silicides such as nickel silicide, cobalt silicide, titanium silicide, or low-resistivity metallic materials such as tungsten, aluminum, copper, or alloys thereof. The control gate 108 is used to receive a bias voltage applied by an external memory controller. Through the capacitive coupling of the inter-electrode dielectric layer 107, the control gate 108 can adjust the potential of the floating gate 106, thereby enabling programming, erasing, and reading operations on the memory cells. Using a low-resistivity material can effectively reduce signal transmission delay in the word line direction and improve the overall operating speed of the memory array.

[0075] In some embodiments, the partitioned flash memory further includes a floating gate sidewall 110 located on the sidewall of the control gate 108.

[0076] The material of the floating gate sidewall 110 may include one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride. During manufacturing, the floating gate sidewall 110 primarily functions as a hard mask to protect the underlying floating gate 106 material from damage during subsequent etching processes. Simultaneously, the bottom width and sidewall morphology of the floating gate sidewall 110 directly determine the specific shape and angle of the tip structure formed by the floating gate 106 after etching.

[0077] The second dielectric layer 111 is located on the sidewalls of the floating gate 106, the inter-electrode dielectric layer 107, and the control gate 108.

[0078] In some embodiments, the material of the second dielectric layer 111 includes silicon oxide.

[0079] In other embodiments, the material of the second dielectric layer 111 may also include high-temperature silicon oxide, free radical silicon oxide, or a high-dielectric-constant dielectric material formed by atomic layer deposition. The second dielectric layer 111 serves as a coupling and isolation medium between the word line 112 and the floating gate 106 and control gate 108. In embodiments including the floating gate sidewall 110, the second dielectric layer 111 also conformally covers the sidewall of the floating gate sidewall 110 and extends to the surface of the semiconductor substrate 101. The second dielectric layer 111 needs to have a sufficiently high breakdown voltage and a low defect density to prevent high-voltage breakdown or leakage between the word line 112 and the floating gate 106 or control gate 108 during programming or erasing operations.

[0080] The character line 112 is located on the side wall of the second dielectric layer 111.

[0081] In some embodiments, the word line 112 is made of polycrystalline silicon.

[0082] In other embodiments, the word line 112 may also be made of doped polysilicon, metal silicide, or a metallic material. The word line 112 acts as a select gate in the split-gate structure, controlling the on / off state of the select transistor within the memory cell. By independently positioning the word line 112 on the sidewall of the floating gate 106, the read current of the memory cell is jointly controlled by the word line 112 and the floating gate 106. This split-gate design effectively suppresses the over-erasure problem common in traditional stacked gate structures. Even if the floating gate 106 is over-erased, causing the channel beneath it to be depleted, the channel beneath the word line 112 remains closed, thus avoiding leakage across the entire memory column and improving the accuracy of read operations and the reliability of the array.

[0083] In some embodiments, the split-gate flash memory further includes a source-drain sidewall 113 located on the sidewall of the floating gate 106 and the control gate 108 away from the word line 112.

[0084] The source / drain sidewall 113 can be a single-layer structure or an L-type or D-type multilayer composite structure containing silicon oxide and silicon nitride. The main function of the source / drain sidewall 113 is to provide self-aligned physical masking in the subsequent source / drain ion implantation process, precisely control the lateral distance between the heavily doped region and the gate edge, thereby optimizing the short-channel performance and hot carrier injection efficiency of the device.

[0085] The source / drain doped regions 114 are located within the semiconductor substrate 101 on both sides of the word line 112 and the floating gate 106.

[0086] The conductivity type of the source / drain doped region 114 is opposite to that of the well region of the semiconductor substrate 101. For example, for an N-type memory cell, the source / drain doped region 114 may include N-type dopants such as phosphorus, arsenic, or antimony; for a P-type memory cell, the source / drain doped region 114 may include P-type dopants such as boron, boron difluoride, or indium. The source / drain doped region 114 may include a lightly doped drain region near the channel and a heavily doped region away from the channel. By optimizing the size of the source / drain sidewalls 113 and the ion implantation process parameters, the floating gate threshold voltage offset caused by lateral diffusion of the source / drain junction can be effectively reduced. Compared with traditional memory cell architectures, the structure provided in this embodiment can significantly increase the operating window of the memory cell, improve the overall yield of the memory array, and enhance the reliability of the product during long-term use.

[0087] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the process flow for a method of forming a gate-divided flash memory provided in an embodiment of the present invention.

[0088] A method for forming a gate-divided flash memory includes:

[0089] Step 1: Provide a semiconductor substrate 101, in which an active region and an isolation structure 104 are formed.

[0090] In some embodiments, step one, forming the active region and isolation structure 104 includes (see reference) Figure 5 A first mask layer 102 and a second mask layer 103 are sequentially formed on the surface of the semiconductor substrate 101; please refer to Figure 6 The second mask layer 103, the first mask layer 102, and the semiconductor substrate 101 are patterned to form trenches; please refer to Figure 7 The trench is filled with an isolation medium and planarized until the second mask layer 103 is exposed, forming an isolation structure 104.

[0091] In some embodiments, the first mask layer 102 includes a base oxide layer, and the second mask layer 103 includes a base silicon nitride layer.

[0092] Semiconductor manufacturing equipment can perform the above-described process steps. Specifically, the first mask layer 102 can be formed by performing a dry oxygen or wet oxygen thermal oxidation process in a high-temperature furnace tube. The first mask layer 102 mainly serves to buffer the lattice stress between the semiconductor substrate 101 and subsequent deposited layers, and to protect the surface of the semiconductor substrate 101 from contamination. The second mask layer 103 can be formed by a low-pressure chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process. The second mask layer 103 has high hardness and etching resistance, and serves as a reliable stop layer in the subsequent chemical mechanical polishing process. The patterning process includes coating the surface of the second mask layer 103 with photoresist, defining the pattern of the active region through exposure and development processes, and then using an anisotropic dry etching process containing fluorine-based or chlorine-based gases in an etching chamber to sequentially penetrate the second mask layer 103, the first mask layer 102, and penetrate deep into the semiconductor substrate 101 to form trenches with a certain depth and sidewall angle. The filling of the isolation medium can be accomplished through high-density plasma chemical vapor deposition (PDCVD), flowable PDCVD, or spin-coating processes to ensure that the high aspect ratio trenches are filled without voids. After filling, a high-temperature annealing process is typically performed to densify the isolation medium, and finally, a chemical mechanical polishing (CMP) process is used to remove excess isolation medium from the outside of the trenches, achieving global surface planarization.

[0093] Step 2: Etch part of the isolation structure 104 so that the surface of part of the isolation structure 104 is lower than the surface of the active region, exposing part of the active region sidewall, and forming a groove between adjacent active regions.

[0094] In some embodiments, step two, before etching the partial isolation structure 104, includes [refer to...]. Figure 8 Remove the second mask layer 103.

[0095] Removing the second mask layer 103 typically employs a wet etching process, such as immersing the semiconductor substrate 101 in a heated phosphoric acid solution. This solution has extremely high etching selectivity for silicon nitride, enabling complete removal of the second mask layer 103 without damaging the isolation dielectric and the first mask layer 102. Please refer to [reference needed]. Figure 9 , Figure 9 The cross-sectional structure along the Y direction, spanning multiple active regions, is shown. Subsequently, an etch-back process is performed on the isolation structure 104. This etch-back process can employ a wet etching process using a solution containing dilute hydrofluoric acid or buffered oxide, or a dry chemical etching process based on the reaction of hydrogen fluoride and ammonia. By precisely controlling the etching time, solution concentration, or gas flow rate, the etch-back depth of the isolation structure 104 can be accurately controlled. This crucial step causes the top and part of the sidewalls of the active regions to protrude from the surrounding surface of the isolation structure 104, providing the necessary physical space and structural foundation for the subsequent formation of a three-dimensional enveloping floating gate.

[0096] Step 3: Form a first dielectric layer 105 on the top of the active region and the exposed sidewalls of the active region.

[0097] Please refer to Figure 10 Before forming the first dielectric layer 105, semiconductor manufacturing equipment typically performs a pre-cleaning process, such as using RCA cleaning fluid to remove particles, organic matter, metal ions, and residual first mask layer 102 and native oxides from the surface of the semiconductor substrate 101, exposing the semiconductor lattice surface. Subsequently, the first dielectric layer 105 is formed through in-situ vapor-generated thermal oxidation, rapid thermal oxidation, or plasma oxidation. These advanced oxidation processes can grow a uniform, dense silicon oxide layer with extremely low interface state density on the top of the active region and the exposed sidewalls. A high-quality first dielectric layer 105 plays a crucial role in ensuring the erase / write lifetime and data retention characteristics of the memory cells.

[0098] Step 4: A first conductive layer 106 is formed on the surface of the first dielectric layer 105. The first conductive layer 106 surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove.

[0099] In some embodiments, step four, forming the first conductive layer 106 includes (see reference) Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the cross-section in the X direction. Figure 12 This is a schematic diagram of the cross-section in the Y direction. A first conductive material is deposited, which covers the first dielectric layer 105 and the isolation structure 104; the first conductive material is then planarized.

[0100] The first conductive material can be deposited using a low-pressure chemical vapor deposition (LPCVD) process. During deposition, silane or disilane can be introduced as a precursor gas, and phosphine or diborane can be introduced simultaneously for in-situ doping to adjust the conductivity of the first conductive material. It is important to emphasize that, as shown in the Y-direction cross-section... Figure 12 As shown, the deposited first conductive material completely fills the groove formed between adjacent active regions by the etched partial isolation structure 104 and covers the entire surface of the semiconductor substrate 101. Subsequently, the first conductive material is planarized using a chemical mechanical polishing process. The planarization process can be stopped at a specific thickness above the surface of the first dielectric layer 105 by controlling the polishing time, or by using a pre-deposited stop layer as the polishing endpoint, thereby forming mutually isolated and flat-topped first conductive layers 106. At this time, in the Y direction, the first conductive layer 106 not only completely fills the aforementioned groove, but also completely wraps around the protruding portions of the active regions from the top and sides, achieving three-dimensional enclosure of the channel.

[0101] Step 5: Sequentially form an inter-electrode dielectric layer 107 and a second conductive layer 108 on the surface of the first conductive layer 106.

[0102] In some embodiments, step five, after forming the second conductive layer 108, further includes (see reference...) Figure 13 A third mask layer 109 is formed on the surface of the second conductive layer 108.

[0103] The interpolar dielectric layer 107 can be formed using a multi-step deposition process. For example, a bottom layer of silicon oxide, an intermediate layer of silicon nitride, and a top layer of silicon oxide can be deposited sequentially using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). ALD provides atomic-level thickness control and excellent step coverage, ensuring that the interpolar dielectric layer 107 forms a uniform conformal coverage on the surface of the first conductive layer 106. The second conductive layer 108 can also be formed by depositing doped polycrystalline silicon or a metallic material using a chemical vapor deposition process. The third mask layer 109 can be formed by depositing silicon nitride, silicon oxynitride, or amorphous carbon material using a plasma-enhanced chemical vapor deposition (PECVD) process. The third mask layer 109 serves as a hard mask in subsequent complex etching processes, used to precisely transfer the pattern of the control gate 108 and protect the underlying second conductive layer 108 from etching gases.

[0104] Step 6: Pattern the second conductive layer 108, the inter-electrode dielectric layer 107 and the first conductive layer 106 to form the control gate 108 and the floating gate 106, and make the floating gate 106 form a tip structure.

[0105] In some embodiments, step six, the patterning process includes (see reference) Figure 14 The third mask layer 109 and the second conductive layer 108 are etched to form the control gate 108; please refer to Figure 15 A floating gate sidewall 110 is formed on the sidewall of the control gate 108; please refer to Figure 16 and Figure 17 Using the floating gate sidewall 110 as a mask, the inter-electrode dielectric layer 107 and the first conductive layer 106 are etched to form the floating gate 106, and the floating gate 106 is formed into a tip structure by using the etching process.

[0106] This patterning process is a core step in forming the specific structure of this embodiment. First, a photoresist pattern is formed on the surface of the third mask layer 109 using photolithography. Then, an anisotropic dry etching process is used in the etching chamber to sequentially penetrate the third mask layer 109 and the second conductive layer 108. This etching process typically has a high selectivity for the inter-electrode dielectric layer 107, so the etching stops precisely on the surface of the inter-electrode dielectric layer 107, thereby forming the control gate 108. Next, a sidewall dielectric material is conformally deposited over the entire surface using chemical vapor deposition. Subsequently, an anisotropic etch-back process is performed to remove the dielectric material on the horizontal surface, leaving the dielectric material on the sidewalls of the control gate 108 to form the floating gate sidewall 110. Then, using the floating gate sidewall 110 and the third mask layer 109 as a combined mask, the inter-electrode dielectric layer 107 and the first conductive layer 106 are etched downwards. During the etching of the first conductive layer 106, the balance between physical bombardment and chemical polymer deposition rate can be controlled by finely adjusting the mixing ratio of etching gases, such as the ratio of hydrogen bromide, chlorine, and oxygen, the radio frequency bias power, and the chamber pressure. This dynamic balance ensures that while the first conductive layer 106 is being etched downwards, its top edge region is protected by the polymer or exhibits a specific lateral drilling effect, thereby self-aligning and forming an upwardly protruding tip structure at the top edge of the final floating gate 106.

[0107] Step 7: A second dielectric layer 111 is formed on the sidewalls of the floating gate 106, the inter-electrode dielectric layer 107 and the control gate 108, and a third conductive layer is formed on the sidewalls of the second dielectric layer 111 as a word line 112.

[0108] In some embodiments, step seven, forming the word line 112 includes (see reference) Figure 18 Deposit the second dielectric material 111 and the third conductive material 112; perform planarization treatment on the third conductive material 112; please refer to Figure 19 The third conductive material 112 is patterned to form the character lines 112.

[0109] The second dielectric material 111 can be formed by high-temperature oxidation, in-situ vapor generation, or chemical vapor deposition. High-temperature oxidation consumes some of the silicon material on the sidewalls of the floating gate 106, forming a dense silicon oxide layer with excellent interface quality. The third conductive material 112 can be formed by depositing doped polysilicon using chemical vapor deposition, with a deposition thickness sufficient to cover the sidewalls of the entire gate stack structure. Subsequently, the third conductive material 112 is planarized using chemical mechanical polishing or isotropic etching back, removing excess conductive material from the top of the control gate 108, making its top surface substantially flush with the top of the control gate 108 or the third mask layer 109. Finally, the unwanted areas of the third conductive material 112 are removed using photolithography and anisotropic dry etching, leaving the conductive material on the sidewalls of the second dielectric layer 111 to form the word line 112. This word line 112 manufacturing method, similar to a sidewall formation process, enables self-alignment control of the word line 112 width, reducing the impact of photolithographic alignment deviations.

[0110] Step 8: Form source / drain doped regions 114 in the semiconductor substrate 101 on both sides of word line 112 and floating gate 106.

[0111] In some embodiments, step eight, before forming the source / drain doped regions 114, also includes (see reference...) Figure 20 A sidewall dielectric layer is deposited and etched to form a source / drain sidewall 113 on the sidewall of the floating gate 106 and the control gate 108 away from the word line 112.

[0112] The formation process of the source / drain sidewall 113 is similar to that of the aforementioned floating gate sidewall 110, including conformal deposition of dielectric material and anisotropic etch-back. Before forming the source / drain sidewall 113, a low-dose ion implantation process can be performed to form a lightly doped drain region within the semiconductor substrate 101 to alleviate the electric field concentration effect at the drain edge. After forming the source / drain sidewall 113, a high-dose ion implantation process is performed to form a heavily doped source / drain doped region 114. The implanted impurity ions may include arsenic, phosphorus, or boron. After implantation, the semiconductor manufacturing equipment performs a rapid thermal annealing process, a spike annealing process, or a laser annealing process. These short-duration high-temperature treatments can effectively limit the lateral diffusion of impurity ions while activating the implanted impurities and repairing semiconductor lattice damage. The formation method provided in this embodiment has a simple process flow and good compatibility with existing embedded flash memory processes. By optimizing process steps and structural design, this method can reduce four high-temperature furnace tube processes, which not only significantly reduces manufacturing costs and production cycle, but also reduces the adverse impact of overall thermal budget on device performance, providing an optimal solution for manufacturing high-density, high-performance, and high-reliability gate-division flash memory.

[0113] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A grid-splitting flash memory, characterized in that, include: A semiconductor substrate having an active region and an isolation structure, wherein a portion of the surface of the isolation structure is lower than the surface of the active region to expose a portion of the sidewalls of the active region and a groove is formed between adjacent active regions; A first dielectric layer covers the top of the active region and the exposed sidewalls of the active region; A floating gate is located on the surface of the first dielectric layer. The floating gate surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove. The floating gate has a pointed structure. An inter-electrode dielectric layer is located on the surface of the floating gate; The control gate is located on the surface of the inter-electrode dielectric layer; The second dielectric layer is located on the sidewall of the floating gate, the inter-electrode dielectric layer, and the control gate; The word line is located on the sidewall of the second dielectric layer; The source and drain doped regions are located within the semiconductor substrate on both sides of the word line and the floating gate.

2. The gate-division flash memory according to claim 1, characterized in that: The floating gate, the control gate, and the word line are made of polycrystalline silicon.

3. The gate-division flash memory according to claim 1, characterized in that: The materials of the first dielectric layer and the second dielectric layer include silicon oxide.

4. The gate-division flash memory according to claim 1, characterized in that: The inter-electrode dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

5. The gate-division flash memory according to claim 1, characterized in that: It also includes a floating grid sidewall, which is located on the control grid sidewall and on top of the floating grid.

6. The gate-divided flash memory according to claim 1, characterized in that: It also includes a source / drain sidewall, which is located on the sidewall of the floating grid and the control grid away from the word line.

7. A method for manufacturing a segmented gate flash memory, characterized in that, include: Step 1: Provide a semiconductor substrate, wherein an active region and an isolation structure are formed within the semiconductor substrate; Step 2: Etch part of the isolation structure so that the surface of part of the isolation structure is lower than the surface of the active region, exposing part of the sidewall of the active region, and forming a groove between adjacent active regions; Step 3: Form a first dielectric layer on the top of the active region and the exposed sidewalls of the active region; Step 4: Form a first conductive layer on the surface of the first dielectric layer. The first conductive layer surrounds the top of the active region and the exposed sidewalls of the active region, and completely fills the groove. Step 5: Sequentially form an inter-electrode dielectric layer and a second conductive layer on the surface of the first conductive layer; Step 6: Pattern the second conductive layer, the inter-electrode dielectric layer, and the first conductive layer to form a control gate and a floating gate, and make the floating gate form a tip structure; Step 7: Form a second dielectric layer on the sidewalls of the floating gate, the inter-electrode dielectric layer, and the control gate, and form a third conductive layer as a word line on the sidewalls of the second dielectric layer; Step 8: Form source / drain doped regions in the semiconductor substrate on both sides of the word line and the floating gate.

8. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step one, forming the active region and the isolation structure includes: sequentially forming a first mask layer and a second mask layer on the surface of the semiconductor substrate; patterning the second mask layer, the first mask layer and the semiconductor substrate to form a trench; filling the trench with an isolation medium and performing planarization treatment to expose the second mask layer to form the isolation structure.

9. The method for manufacturing a segmented flash memory according to claim 8, characterized in that: The first mask layer includes a base oxide layer, and the second mask layer includes a base silicon nitride layer.

10. The method for manufacturing a grid-splitter flash memory according to claim 8, characterized in that: In step two, before etching the isolation structure, the second mask layer is removed.

11. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step four, forming the first conductive layer includes: depositing a first conductive material, the first conductive material covering the first dielectric layer and the isolation structure, and completely filling the groove; and planarizing the first conductive material.

12. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step five, after forming the second conductive layer, a third mask layer is also formed on the surface of the second conductive layer.

13. The method for manufacturing a grid-splitter flash memory according to claim 12, characterized in that: In step six, the patterning process includes: etching the third mask layer and the second conductive layer to form the control gate; forming a floating gate sidewall on the sidewall of the control gate; using the floating gate sidewall as a mask, etching the inter-electrode dielectric layer and the first conductive layer to form the floating gate, and using an etching process to form the tip structure of the floating gate.

14. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step seven, forming the word lines includes: depositing a second dielectric material and a third conductive material; planarizing the third conductive material; and patterning the third conductive material to form the word lines.

15. The method for manufacturing a grid-splitter flash memory according to claim 7, characterized in that: In step eight, prior to forming the source / drain doped regions, the method further includes: depositing a sidewall dielectric layer and etching it to form source / drain sidewalls on the sidewalls of the floating gate and the control gate away from the word line.

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