Non-self-aligned nord flash memory structure and method of manufacturing the same

Abstract

The present application provides a non-self-aligned NORD flash memory structure and a manufacturing method thereof. The structure comprises a substrate, a coupling medium layer, a floating gate conductive layer, an isolation medium layer and a control gate conductive layer. In a single memory cell, the floating gate conductive layer comprises two floating gates arranged at intervals, each floating gate having a groove with a concave cross-section. The control gate conductive layer, as a word line, comprises a main body and two downwardly extending lower protrusions, the lower protrusions being filled in the grooves respectively. The main body has a width greater than that of the groove, so that the control gate conductive layer and the floating gate form a mutually embedded wrap structure. The present application breaks the traditional planar stacking limit, greatly increases the lateral coupling area between the control gate and the floating gate by vertical extension, improves the coupling ratio, shortens the programming and erasing time, improves the read-write speed and reduces the power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a non-self-aligned NORD flash memory structure and its manufacturing method. Background Technology

[0002] In the NORD flash memory structure, the basic working principle is to apply voltage to the control gate (CG) and inject or remove electrons into the floating gate (FG) through capacitive coupling, thereby realizing the programming, reading and erasing operations of the flash memory.

[0003] In the above operation process, the coupling area between the control gate and the floating gate plays a crucial role. A higher control gate / floating gate (CG / FG) coupling area means that the voltage applied to the control gate can be more effectively transferred to the floating gate, thereby directly shortening the programming and erasing time, improving the operating speed of the device, and significantly reducing dynamic power consumption.

[0004] However, as semiconductor process nodes continue to shrink, the cell pitch becomes increasingly smaller. Due to the physical limitations of device size, the lateral coupling area between the control gate and the floating gate is significantly reduced, leading to a substantial decrease in the coupling ratio. This not only severely restricts the improvement of device operating speed but also results in increased power consumption, failing to meet the demands for high-performance, low-power flash memory devices under advanced processes.

[0005] Therefore, there is an urgent need for a new flash memory structure and its manufacturing method to significantly increase the coupling area and achieve high coupling between the control gate and the floating gate while the memory cell size is constantly shrinking. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a non-self-aligned NORD flash memory structure and its manufacturing method, in order to solve the problem that as semiconductor process nodes continue to shrink, the lateral coupling area between the control gate and the floating gate in the traditional non-self-aligned NORD flash memory structure is greatly reduced, resulting in a significant decrease in the coupling ratio, which seriously restricts the improvement of device operating speed and increases power consumption.

[0007] To achieve the above and other related objectives, the present invention provides a non-self-aligned NORD flash memory structure, comprising:

[0008] Substrate;

[0009] A coupling dielectric layer located on the substrate;

[0010] The floating gate conductive layer located on the coupling dielectric layer includes two floating gates spaced apart in a single memory cell. Each floating gate has a groove so that the cross-section of the floating gate is concave.

[0011] An isolation dielectric layer is located on the floating gate conductive layer, and the isolation dielectric layer conformally covers the surface of the floating gate.

[0012] A control gate conductive layer is located on the isolation dielectric layer. The control gate conductive layer serves as a word line. The control gate conductive layer includes a main body and two downward protrusions extending from the main body. The two floating gates are located on both sides below the main body of the word line. The two downward protrusions are respectively filled in the grooves of the two floating gates.

[0013] The width of the main body is greater than the width of the groove, so that the control gate conductive layer and the floating gate form a mutually interlocking encapsulating structure.

[0014] Preferably, the coupling dielectric layer material comprises oxide, the floating gate conductive layer material comprises polysilicon, the isolation dielectric layer comprises a polysilicon isolation dielectric layer, and the control gate conductive layer material comprises polysilicon.

[0015] The present invention also provides a method for manufacturing a non-self-aligned NORD flash memory structure, comprising:

[0016] Step 1: Provide a substrate, and sequentially form a coupling dielectric layer and a floating gate conductive layer on the substrate;

[0017] Step 2: Etch the floating gate conductive layer to form two grooves in the region corresponding to a single memory cell;

[0018] Step 3: Form an isolation dielectric layer on the floating gate conductive layer with the grooves formed;

[0019] Step 4: Form a control gate conductive layer on the isolation dielectric layer, and fill the two grooves with the control gate conductive layer;

[0020] Step 5: Planarize the control gate conductive layer;

[0021] Step 6: Etch the control gate conductive layer so that the width of the retained control gate conductive layer is greater than the width of the groove.

[0022] Preferably, in step one, the coupling dielectric layer material comprises oxide, and the floating gate conductive layer material comprises polysilicon.

[0023] Preferably, in step two, the floating gate conductive layer is partially etched so that the cross-section of the subsequently formed floating gate is concave.

[0024] Preferably, in step three, the isolation dielectric layer comprises a polycrystalline silicon isolation dielectric layer.

[0025] Preferably, in step four, the control gate conductive layer material comprises polycrystalline silicon.

[0026] Preferably, in step five, the control gate conductive layer is planarized using a chemical mechanical polishing process.

[0027] Preferably, in step six, a hard mask layer is formed on the planarized control gate conductive layer, and the hard mask layer is etched to form an opening.

[0028] Preferably, in step six, the opening exposes the control gate conductive layer located on both sides of the groove; after etching the exposed control gate conductive layer, the width of the retained control gate conductive layer is greater than the width of the groove.

[0029] Preferably, after step six, the method further includes: step seven, forming a sidewall material layer; step eight, integrally etching the sidewall material layer and the floating gate conductive layer, and performing a retraction process on the sidewall material layer; and step nine, forming a tunneling dielectric layer and a word line conductive layer.

[0030] Preferably, in step seven, a rapid thermal oxidation process is performed first, followed by the deposition of a silicon nitride layer to form the sidewall material layer.

[0031] Preferably, after step nine, the method further includes: step ten, forming a protective layer on the word line conductive layer; step eleven, etching the stacked layers to form a memory cell structure; and step twelve, forming cell sidewalls on the sidewalls of the memory cell structure.

[0032] As described above, the non-self-aligned NORD flash memory structure and its manufacturing method of the present invention have the following beneficial effects:

[0033] This invention designs a dual floating gate and dual groove structure on both sides of the word line within a single memory cell, and makes the width of the main body of the control gate conductive layer greater than the groove width, thereby forming a complementary, interlocking structure in three-dimensional space. This geometric design breaks the physical limitations of traditional planar stacked structures, significantly increasing the lateral coupling area between the control gate conductive layer and the floating gate by extending vertically. The higher coupling area means that the voltage applied to the control gate conductive layer can be more effectively transferred to the floating gate, directly shortening the programming and erasing time of the flash memory device, improving the overall read and write operation speed, and significantly reducing the dynamic power consumption of the device in operation, meeting the stringent requirements of advanced process nodes for high-performance, low-power non-volatile memory devices. Attached Figure Description

[0034] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0035] Figure 2 The diagram shows the structure of the present invention after the formation of the coupling dielectric layer and the floating gate conductive layer;

[0036] Figure 3 The diagram shows the structure of the present invention after etching the floating gate conductive layer to form a groove.

[0037] Figure 4 The diagram shown is a structural schematic of the present invention after the formation of the isolation medium layer;

[0038] Figure 5 The diagram shown is a structural schematic of the present invention after the formation of the control gate conductive layer;

[0039] Figure 6 The diagram shown is a schematic representation of the structure of the control gate conductive layer after planarization processing according to the present invention.

[0040] Figure 7 The diagram shows the structure of the present invention after forming a hard mask layer and etching out an opening;

[0041] Figure 8 The diagram shows the structure of the control gate conductive layer after etching according to the present invention.

[0042] Figure 9 The diagram shown is a structural schematic of the present invention after the formation of the sidewall material layer;

[0043] Figure 10 The diagram shows the structure after the integrated etching and sidewall material layer retraction treatment of the present invention.

[0044] Figure 11 The diagram shown is a structural schematic of the present invention after the formation of the tunneling medium layer;

[0045] Figure 12 The diagram shows the structure after the formation of the word line conductive layer and the protective layer of the present invention.

[0046] Figure 13 The diagram shown is a schematic representation of the structure of the memory cell after etching according to the present invention.

[0047] Figure 14 The diagram shown is a schematic representation of the final structure after the sidewalls of the forming unit are formed according to the present invention. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] A non-self-aligned NORD flash memory structure, comprising:

[0050] Substrate 101; coupling dielectric layer 102 located on substrate 101;

[0051] The floating gate conductive layer 103 located on the coupling dielectric layer 102 includes two floating gates 103 spaced apart in a single memory cell. Each floating gate 103 has a groove so that the cross section of the floating gate 103 is concave.

[0052] In some embodiments, the coupling dielectric layer 102 is made of oxide, and the floating gate conductive layer 103 is made of polysilicon.

[0053] In some embodiments, substrate 101 may be a silicon substrate, a bulk semiconductor substrate, or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor in the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0054] The coupling dielectric layer 102 is configured to provide a physical path for charge tunneling or hot electron injection when a programming or erasing voltage is applied to the control gate conductive layer 105. In addition to conventional thermal silicon oxide materials, the coupling dielectric layer 102 may also be made of silicon oxynitride, or, in order to reduce leakage current while maintaining the same equivalent oxide thickness, may be made of a high dielectric constant material, such as hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0055] The floating gate conductive layer 103 serves as a charge storage node. Besides using conventional undoped polysilicon, it can also employ N-type or P-type in-situ doped polysilicon to adjust the work function. In advanced process nodes pursuing lower word line resistance and smaller RC delay, the floating gate conductive layer 103 can also be replaced with a metal or metal alloy material, such as tungsten, titanium, tantalum, titanium nitride, tantalum nitride, aluminum, or copper.

[0056] An isolation dielectric layer 104 is located on the floating gate conductive layer 103, and the isolation dielectric layer 104 conformally covers the surface of the floating gate 103.

[0057] In some embodiments, the isolation dielectric layer 104 includes a polysilicon isolation dielectric layer.

[0058] The isolation dielectric layer 104 is used to physically and electrically isolate the floating gate conductive layer 103 and the control gate conductive layer 105 to prevent the loss of stored charge. The isolation dielectric layer 104 can be a single silicon oxide layer or a composite stack structure of silicon oxide-silicon nitride-silicon oxide, which can utilize the trap energy levels of silicon nitride to improve charge retention capability.

[0059] The control gate conductive layer 105 is located on the isolation dielectric layer 104. The control gate conductive layer 105 serves as a word line. The control gate conductive layer 105 includes a main body and two downward protrusions extending from the main body. Two floating gates 103 are located on both sides below the main body of the word line. The two downward protrusions are respectively filled in the grooves of the two floating gates 103.

[0060] The width of the main body is greater than the width of the groove, so that the control gate conductive layer 105 and the floating gate 103 form a mutually interlocking encapsulated structure.

[0061] In some embodiments, the control gate conductive layer 105 material includes polycrystalline silicon.

[0062] The control gate conductive layer 105, serving as the application node for the operating voltage, can also be made of doped polysilicon or metal. By giving the floating gate 103 a groove and the control gate conductive layer 105 a downward protrusion, the two form a complementary, interlocking structure in three-dimensional space. This geometric design breaks the physical limitations of traditional planar stacked structures, increasing the lateral coupling area between the control gate conductive layer 105 and the floating gate 103 through vertical extension. A higher coupling area means that the voltage applied to the control gate conductive layer 105 can be more effectively transferred to the floating gate 103 through a larger capacitive coupling network, thereby shortening the programming and erasing time of the flash memory device, improving the overall read / write speed, and reducing the dynamic power consumption of the device in operation. This interlocking structural design allows the coupling ratio of the device to be maintained or even improved even as semiconductor process nodes continue to shrink and memory cell spacing continues to decrease. According to actual device measurements and evaluations, when the memory cell area is 0.1 square micrometers, the coupling ratio between the control gate conductive layer 105 and the floating gate 103 can reach 0.813. Compared to traditional non-enclosed planar structures, the structure in this embodiment improves the capacitive coupling ratio within the same physical dimensions, meeting the requirements of advanced process nodes for high-performance, low-power non-volatile memory devices.

[0063] In some embodiments, the non-self-aligned NORD flash memory structure further includes a hard mask layer 106 located above the control gate conductive layer 105, and a sidewall material layer 107 located on the sidewalls of the hard mask layer 106 and the control gate conductive layer 105. The hard mask layer 106 may be made of an oxide material; the sidewall material layer 107 may be a composite dielectric layer, for example, including an inner silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

[0064] In some embodiments, a gap is formed between the two floating gates 103 and the control gate conductive layer 105 above them in a single memory cell. The non-self-aligned NORD flash memory structure also includes a tunneling dielectric layer 108 and a word line conductive layer 109 located within the gap. The tunneling dielectric layer 108 conformally covers the sidewalls and bottom of the gap (i.e., the exposed surface of the coupling dielectric layer 102), and the word line conductive layer 109 is located on the tunneling dielectric layer 108 and fills the gap. The material of the word line conductive layer 109 may include doped polysilicon or tungsten.

[0065] In some embodiments, the non-self-aligned NORD flash memory structure further includes a protective layer 110 located above the word line conductive layer 109, and cell sidewalls 111 located on the outer sidewalls of the entire memory cell structure. The protective layer 110 may be an oxide layer; the cell sidewalls 111 are tightly wrapped around the sidewalls of the memory cell structure and may employ a composite sidewall structure of silicon oxide-silicon nitride-silicon oxide, configured as a sealed memory cell to block the intrusion of external moisture, mobile ions, or other contaminants, and to provide physical protection.

[0066] like Figure 1 As shown, a method for manufacturing a non-self-aligned NORD flash memory structure includes:

[0067] like Figure 2 As shown, in step one, a substrate 101 is provided, and a coupling dielectric layer 102 and a floating gate conductive layer 103 are sequentially formed on the substrate 101.

[0068] In some embodiments, in step one, the coupling dielectric layer 102 is made of oxide and the floating gate conductive layer 103 is made of polysilicon.

[0069] In a specific manufacturing process, semiconductor manufacturing equipment, such as a thermal oxidation furnace, can be configured to chemically react silicon atoms on the surface of substrate 101 with oxygen or water vapor in a high-temperature, oxygen-containing environment, thereby growing a dense coupling dielectric layer 102 with low defect density. Alternatively, a rapid thermal oxidation process can be used to control the thermal budget of the oxide layer thickness. Subsequently, substrate 101 is transferred to a chemical vapor deposition chamber, such as a low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (PECVD) apparatus. By introducing a silicon-containing precursor gas, such as silane or dichlorosilane, into the chamber, under specific temperature and pressure conditions, the precursor gas undergoes thermal decomposition or plasma-assisted decomposition on the surface of coupling dielectric layer 102, thereby uniformly depositing a floating gate conductive layer 103. If it is necessary to form doped polycrystalline silicon, phosphorus- or boron-containing doping gases can be simultaneously introduced during the deposition process to achieve in-situ doping.

[0070] like Figure 3 As shown, in step two, the floating gate conductive layer 103 is etched to form two grooves in the region corresponding to a single memory cell.

[0071] In some embodiments, in step two, the floating gate conductive layer 103 is partially etched so that the cross-section of the subsequently formed floating gate 103 is concave.

[0072] Specifically, this step involves the coordinated operation of photolithography and etching. First, a layer of photoresist is spin-coated over the floating gate conductive layer 103. The photoresist is selectively exposed using a photolithography mask, followed by developer treatment to remove the photoresist from the exposed or unexposed areas, thus forming a photoresist mask layer with a specific opening pattern. Next, the substrate 101 with the photoresist mask is fed into a dry etching chamber, such as a reactive ion etching (RIE) or inductively coupled plasma (ICP) etching apparatus. A fluorine- or chlorine-containing etching gas is introduced into the chamber, generating high-energy plasma under the excitation of a radio frequency power supply. The physical bombardment and chemical reactions in the plasma work together on the exposed floating gate conductive layer 103, achieving anisotropic etching. To form non-penetrating grooves, the fabrication equipment is equipped with an endpoint detection system such as optical emission spectroscopy, or the etching rate and time are calculated to stop the etching process before reaching the bottom of the floating gate conductive layer 103. This partial etching process retains a bottom wall within the floating gate conductive layer 103 and forms sidewalls on both sides, creating physical space for the subsequent filling of the control gate conductive layer 105 and the formation of the mutually enclosing structure. During the etching process, the width of the groove can be controlled to 70 nanometers. This process dimension can be referenced to the top-level wiring rules of the 40-nanometer low-power process node to meet manufacturing requirements.

[0073] like Figure 4 As shown, in step three, an isolation dielectric layer 104 is formed on the floating gate conductive layer 103 with grooves.

[0074] In some embodiments, in step three, the isolation dielectric layer 104 includes a polysilicon isolation dielectric layer.

[0075] Considering the complex three-dimensional morphology inside the groove, the deposition of the isolation dielectric layer 104 requires good step coverage. Therefore, atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD) can be used. ALD, by alternately introducing different precursor gases into the chamber and utilizing the self-limiting chemical reaction on the surface, can grow the isolation dielectric layer 104 layer by layer with atomic precision. This process ensures that the isolation dielectric layer 104 has a consistent thickness on the bottom wall, sidewalls of the groove, and the top surface of the floating gate conductive layer 103, avoiding electric field concentration and leakage problems caused by thinning at corners, thus providing stable electrical isolation.

[0076] Step 4: Form a control gate conductive layer 105 on the isolation dielectric layer 104, and fill two grooves in the control gate conductive layer 105.

[0077] In some embodiments, in step four, the material of the control gate conductive layer 105 includes polycrystalline silicon.

[0078] like Figure 5As shown, a chemical vapor deposition process with good via-filling capability is used when forming the control gate conductive layer 105. By optimizing the deposition temperature, chamber pressure, and precursor gas flow rate ratio, the conductive material can fill the trench from bottom to top. The deposition thickness of the control gate conductive layer 105 is set to be large enough to ensure that it not only completely fills the inside of the trench but also covers the isolation dielectric layer 104 outside the trench. A good via-filling process can avoid the generation of gaps or voids inside the trench. If these physical defects exist, they will affect the conductivity and structural stability of the device. The device structure at this time includes, from bottom to top, a substrate 101, a coupling dielectric layer 102, a floating gate conductive layer 103 with trenches, a conformally covered isolation dielectric layer 104, and a control gate conductive layer 105 filling the trenches.

[0079] Step 5: Planarize the control gate conductive layer 105;

[0080] like Figure 6 As shown, in some embodiments, step five involves planarizing the control gate conductive layer 105 using a chemical mechanical polishing (CMP) process. CMP is a global planarization technique that combines mechanical abrasion and chemical etching. The substrate 101 is inverted and pressed onto a rotating polishing pad, while a polishing slurry containing abrasive particles and a chemical etchant is supplied to the polishing interface. The chemical etchant first softens the surface of the control gate conductive layer 105, and then the abrasive particles remove the softened layer through mechanical friction. By adjusting the polishing pressure, rotation speed, and chemical composition of the polishing slurry, excess control gate conductive layer 105 material outside the groove can be removed, eliminating surface morphology undulations. The planarization process provides a flat surface, which is beneficial for subsequent photolithography processes, solving the problem of insufficient depth of focus caused by uneven surfaces and improving the transfer accuracy of the photolithographic pattern.

[0081] Step 6: Etch the control gate conductive layer 105 so that the width of the remaining control gate conductive layer 105 is greater than the trench width.

[0082] like Figure 7 and Figure 8As shown, in some embodiments, in step six, a hard mask layer 106 is formed on the planarized control gate conductive layer 105, and the hard mask layer 106 is etched to form openings. The openings expose the control gate conductive layers 105 located on both sides of the groove; after etching the exposed control gate conductive layers 105, the width of the remaining control gate conductive layer 105 is greater than the groove width. Considering the depth and selectivity requirements of subsequent etching processes, ordinary photoresist may not withstand prolonged plasma bombardment; therefore, a hard mask layer 106 is used. The hard mask layer 106 can be made of oxide material and formed by chemical vapor deposition. Openings are then formed in the hard mask layer 106 through photolithography and etching processes. The opening width is designed to be greater than the groove width to provide sufficient overlap margin during manufacturing. In actual photolithography alignment, the projection position of the mask pattern may shift slightly due to mechanical vibration or optical distortion. Based on the overlay error data of the 40nm low-power polysilicon process, the overlay window is 14nm. This window size is sufficient to tolerate photolithography alignment deviations, ensuring that the opening can always expose the groove and the area on both sides, thereby improving the yield of wafer manufacturing.

[0083] In some embodiments, after step six, the method further includes: step seven, forming a sidewall material layer 107 (e.g., Figure 9 (As shown); Step 8: Perform integrated etching on the sidewall material layer 107 and the floating gate conductive layer 103, and perform a retraction process on the sidewall material layer 107 (as shown). Figure 10 (As shown); Step 9: Form the tunneling dielectric layer 108 and the word line conductive layer 109 (as shown). Figure 11 and Figure 12 (As shown).

[0084] like Figure 10 As shown, in step eight, an integrated etching process is employed. Within the same etching chamber, by switching the gas composition or adjusting the bias parameters, using the hard mask layer 106 and the sidewall material layer 107 as masks, the exposed isolation dielectric layer 104 and the underlying floating gate conductive layer 103 are continuously etched until the bottom coupling dielectric layer 102 is exposed. This integrated etching process simplifies the manufacturing process, reduces the number of wafer transfers between different devices, and thus reduces the probability of defect generation. Subsequently, a retraction process is performed on the sidewall material layer 107. The retraction process can employ isotropic wet etching or a slight dry retraction. By precisely controlling the etching time, the sidewall material layer 107 is retracted to a certain extent in the vertical or horizontal direction. This retraction step further optimizes the exposed area of ​​the floating gate 103, providing a better surface morphology for the subsequent growth of the tunneling dielectric layer 108, and helps to adjust the effective channel length of the final memory cell. Figure 11As shown, in step nine, the tunneling dielectric layer 108 can be deposited conformally inside the groove and on the surface of each layer through high-temperature thermal oxidation or atomic layer deposition processes. Its quality directly determines the erase / write life and data retention capability of the flash memory device. Figure 12 As shown, a word line conductive layer 109 is then deposited, for example, doped polycrystalline silicon or tungsten metal. The word line conductive layer 109 fills the interior of the groove and is then chemically and mechanically polished again to achieve surface planarization.

[0085] In some embodiments, in step seven, a rapid thermal oxidation process is performed first, followed by the deposition of a silicon nitride layer to form the sidewall material layer 107. The sidewall material layer 107 is formed using a composite dielectric process. First, a rapid thermal oxidation process is performed on the wafer. In a controlled high-temperature oxygen-containing environment, the exposed surface of the control gate conductive layer 105 is slightly oxidized to form a thin and dense silicon oxide layer. This rapid thermal oxidation step can repair plasma damage and lattice defects that may be caused on the conductive layer surface by the preceding etching process, and also serves as a stress buffer layer for the subsequent silicon nitride layer, reducing the interface state density. Next, the wafer is transferred to a deposition chamber, and a silicon nitride material is deposited conformally on the silicon oxide layer using a low-pressure chemical vapor deposition or atomic layer deposition process. The silicon nitride material has excellent physical barrier properties and a high selectivity for subsequent etching processes.

[0086] In some embodiments, after step nine, the method further includes: step ten, forming a protective layer 110 on the word line conductive layer 109 (e.g., ...). Figure 12 (As shown); Step 11: Etch the stacked layers to form the memory cell structure (e.g., Figure 13 (As shown); Step 12, form cell sidewalls 111 on the sidewalls of the storage cell structure (as shown). Figure 14 (As shown).

[0087] like Figure 12 As shown, in step ten, the word line conductive layer 109 is oxidized to repair surface defects and form an oxide layer. This oxide layer serves as a protective layer 110. Simultaneously, corresponding protective materials can be deposited in the peripheral logic region to prevent subsequent memory area processes from affecting the peripheral logic devices. For example... Figure 13 As shown, in step eleven, after completing the relevant processes for the logic region, the peripheral protective material and part of the sacrificial layer such as the hard mask layer 106 are removed by photolithography and etching. Finally, selective etching is performed to cut off the connections between adjacent cells, remove excess floating gate conductive layer 103 and coupling dielectric layer 102, and ultimately define the independent memory cell structure in the array. In a single memory cell structure, the floating gate conductive layer 103 is etched to form two floating gates 103 located on both sides of the word line, each floating gate 103 having a groove. Figure 14As shown, in step twelfth, the cell sidewall 111 can be formed using a composite sidewall process of silicon oxide-silicon nitride-silicon oxide. Through deposition and etch-back steps, the cell sidewall 111 tightly wraps around the sidewalls of the entire memory cell structure. The cell sidewall 111 is configured to enclose the memory cell, preventing the intrusion of external moisture, mobile ions, or other contaminants, while providing physical protection in subsequent interlayer dielectric deposition and contact via etching processes, thereby improving the long-term reliability and lifespan of the flash memory device.

[0088] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A non-self-aligned NORD flash memory structure, characterized in that, include: Substrate; A coupling dielectric layer located on the substrate; The floating gate conductive layer located on the coupling dielectric layer includes two floating gates spaced apart in a single memory cell. Each floating gate has a groove so that the cross-section of the floating gate is concave. An isolation dielectric layer is located on the floating gate conductive layer, and the isolation dielectric layer conformally covers the surface of the floating gate. A control gate conductive layer is located on the isolation dielectric layer. The control gate conductive layer serves as a word line. The control gate conductive layer includes a main body and two downward protrusions extending from the main body. The two floating gates are located on both sides below the main body of the word line. The two downward protrusions are respectively filled in the grooves of the two floating gates. The width of the main body is greater than the width of the groove, so that the control gate conductive layer and the floating gate form a mutually interlocking encapsulating structure.

2. The non-self-aligned NORD flash memory structure according to claim 1, characterized in that: The coupling dielectric layer material includes oxide, the floating gate conductive layer material includes polysilicon, the isolation dielectric layer includes a polysilicon isolation dielectric layer, and the control gate conductive layer material includes polysilicon.

3. A method for manufacturing a non-self-aligned NORD flash memory structure, characterized in that, include: Step 1: Provide a substrate, and sequentially form a coupling dielectric layer and a floating gate conductive layer on the substrate; Step 2: Etch the floating gate conductive layer to form two grooves in the region corresponding to a single memory cell; Step 3: Form an isolation dielectric layer on the floating gate conductive layer with the grooves formed; Step 4: Form a control gate conductive layer on the isolation dielectric layer, and fill the two grooves with the control gate conductive layer; Step 5: Planarize the control gate conductive layer; Step 6: Etch the control gate conductive layer so that the width of the retained control gate conductive layer is greater than the width of the groove.

4. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step one, the coupling dielectric layer material includes oxide, and the floating gate conductive layer material includes polysilicon.

5. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step two, the floating gate conductive layer is partially etched so that the cross-section of the subsequently formed floating gate is concave.

6. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step three, the isolation dielectric layer includes a polycrystalline silicon isolation dielectric layer.

7. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step four, the control gate conductive layer material includes polycrystalline silicon.

8. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step five, the control gate conductive layer is planarized using a chemical mechanical polishing process.

9. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: In step six, a hard mask layer is formed on the planarized control gate conductive layer, and the hard mask layer is etched to form an opening.

10. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 9, characterized in that: In step six, the opening exposes the control gate conductive layer located on both sides of the groove; after etching the exposed control gate conductive layer, the width of the retained control gate conductive layer is greater than the width of the groove.

11. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 3, characterized in that: Following step six, the process further includes: step seven, forming a sidewall material layer; step eight, integrally etching the sidewall material layer and the floating gate conductive layer, and performing a retraction process on the sidewall material layer; and step nine, forming a tunneling dielectric layer and a word line conductive layer.

12. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 11, characterized in that: In step seven, a rapid thermal oxidation process is first performed, followed by the deposition of a silicon nitride layer to form the sidewall material layer.

13. The method for manufacturing a non-self-aligned NORD flash memory structure according to claim 11, characterized in that: After step nine, the method further includes: step ten, forming a protective layer on the word line conductive layer; step eleven, etching the stacked layers to form a memory cell structure; and step twelve, forming cell sidewalls on the sidewalls of the memory cell structure.

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