Semiconductor device

Abstract

A semiconductor device is provided to improve operating speed and reliability. The semiconductor device includes: a source electrode; an insulator disposed above the source electrode; a first conductive layer in contact with the insulator in a first region; a second conductive layer disposed between the source electrode and the first conductive layer, in contact with the insulator in a second region, the second region being lower than the height of the first region from the source electrode; a first insulating layer disposed between the first and second conductive layers, in contact with the insulator in a third region, the third region connecting the first and second regions in a first direction; and a first columnar conductive portion disposed at the boundary between the first and third regions, extending along a second direction orthogonal to the first direction, and connected to the first conductive layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices. Background Technology

[0002] Semiconductor packages using NAND flash memory as a semiconductor device are known. To increase the capacity of such NAND flash memory, three-dimensional NAND flash memory, which consists of multiple stacked memory cells, has been put into practical use. In this type of stacked three-dimensional NAND flash memory, improving operating speed and reliability has become a challenge. Existing technical documents Patent documents

[0003] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0286912 Patent Document 2: U.S. Patent Application Publication No. 2017 / 0338240 Patent Document 3: U.S. Patent Application Publication No. 2019 / 0214267 Summary of the Invention The technical problem that the invention aims to solve

[0004] The embodiments disclosed herein provide a semiconductor device that improves operating speed and reliability. Means for solving technical problems

[0005] One embodiment of the semiconductor device includes: a source electrode; an insulator disposed above the source electrode; a first conductive layer in contact with the insulator in a first region; a second conductive layer disposed between the source electrode and the first conductive layer, in contact with the insulator in a second region, wherein the second region is at a lower height from the source electrode than the first region is at a lower height from the source electrode; a first insulating layer disposed between the first conductive layer and the second conductive layer, in contact with the insulator in a third region, wherein the third region connects the first region and the second region in a first direction; and a first columnar conductive portion disposed at the boundary between the first region and the third region, extending along a second direction orthogonal to the first direction, and connected to the first conductive layer. Attached Figure Description

[0006] Figure 1 This is a top view showing the overall configuration of a semiconductor device according to one embodiment. Figure 2 This is a perspective view showing the configuration near the contact region HUR of the semiconductor device according to this embodiment. Figure 3This is a perspective view showing the configuration of the memory cell region MCR and the contact region HUR of a semiconductor device according to one embodiment. Figure 4 This is a top view showing the configuration of the contact region HUR of a semiconductor device according to one embodiment. Figure 5 This is a cross-sectional view showing the configuration of the contact plug of a semiconductor device according to one embodiment. Figure 6 This is a cross-sectional view showing the configuration of the contact plug of a semiconductor device according to one embodiment. Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 9 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 12 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 13 This is a cross-sectional view showing the configuration of the contact plug of a semiconductor device according to one embodiment. Figure 14 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 15 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 16 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Figure 17 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. Detailed Implementation

[0007] Hereinafter, the semiconductor device according to this embodiment will be specifically described with reference to the accompanying drawings. In the following description, elements having substantially the same function and structure will be given the same reference numerals or reference numerals followed by letters, and will be described repeatedly only where necessary. The embodiments shown below illustrate apparatus and methods for embodying the technical concept of the embodiments. Various modifications may be made to the embodiments without departing from the spirit of the invention. These embodiments and their modifications are included within the scope of the invention as set forth in the claims and its equivalents.

[0008] To further clarify, the accompanying drawings may sometimes schematically represent the width, thickness, shape, etc., of various parts compared to the actual embodiment; however, these are merely examples and do not limit the interpretation of the invention. In this specification and the accompanying drawings, elements having the same function as those described in the accompanying drawings are given the same reference numerals, and sometimes repeated descriptions are omitted.

[0009] Unless otherwise specified, the statement "α includes A, B, or C" in this specification does not exclude the possibility that α includes a combination of multiple A through C. Furthermore, these statements do not exclude the possibility that α includes other elements.

[0010] The following implementation methods can be combined with each other as long as they do not create technical contradictions.

[0011] In various embodiments of the present invention, the direction from the source to the memory cell is referred to as "upward." Conversely, the direction from the memory cell to the source is referred to as "downward." Thus, for ease of explanation, terms such as "upward" or "downward" are used in the description, but for example, the vertical relationship between the source and the memory cell can also be configured in a manner opposite to that shown in the figures. Furthermore, in the following description, the term "memory cell on the source" is merely used to illustrate the vertical relationship between the source and the memory cell as described above; other components may also be configured between the source and the memory cell.

[0012] [First Implementation Method] [Overall Structure of a Semiconductor Device] use Figure 1 and Figure 2 The overall configuration of the semiconductor device involved in this embodiment will be described. Figure 1 This is a top view showing the overall configuration of the semiconductor device 10 according to this embodiment. Figure 2 This is a perspective view showing the structure near the contact region HUR of a certain block BLK involved in this embodiment. Figure 1 and Figure 2In this context, the two directions that are parallel and orthogonal to each other relative to the principal surface of source electrode 11 are called the X direction and the Y direction, and the surface that is parallel to the principal surface of source electrode 11 is called the XY surface. The direction that is orthogonal to both the X and Y directions is called the Z direction (stack direction).

[0013] Semiconductor device 10 is, for example, a NAND flash memory device. Semiconductor device 10 includes a source 11. Two memory cell regions (MCRs) and a contact region (HUR) are defined on the source 11. A memory cell array 16, comprising a plurality of memory cells stacked in three dimensions, is formed in the memory cell regions (MCRs). Specifically, source-side gate select transistors, a plurality of (e.g., 64) memory cell transistors, and drain-side gate select transistors are connected in series in a direction perpendicular to the main plane (XY plane) of the source 11 (Z direction) to form a memory string. Alternatively, dummy cell transistors may be included at both ends of the series-connected plurality of memory cell transistors or in a portion between the plurality of memory cell transistors. The memory cell array 16 includes a stack of multiple conductive layers that form source-side gate select lines, word lines, and drain-side gate select lines connected to each transistor, each separated by an insulating layer. The multiple conductive layers of the memory cell array 16 extend to the contact region (HUR), forming a stacked wiring structure 17 and a bridging portion 18.

[0014] A contact region HUR is disposed between two memory cell regions MCR. The contact region HUR is positioned approximately at the center of the semiconductor device 10 in the X direction (the extension direction of the slit ST). The memory cell array 16, separated in the X direction, is electrically connected in the contact region HUR via a bridging portion 18 adjacent to the stacked wiring structure 17 in the Y direction. The bridging portion 18 comprises a stack of multiple conductive layers, each separated by an insulating layer, corresponding to wirings extending from source-side gate select lines, word lines, and drain-side gate select lines connected to each transistor of the memory cell array 16. The bridging portion 18 extends along the X direction (the extension direction of the slit ST) and electrically connects the memory cell array 16 separated in the X direction for each of the multiple conductive layers.

[0015] A slit ST is formed in the semiconductor device 10. The slit ST extends along the stacking direction (Z direction) of the memory cell array 16, penetrating the memory cell array 16 and reaching the source 11. The slit ST extends along the X direction, separating the memory cell array 16 into multiple blocks BLK in the Y direction. An insulating layer is formed in the slit ST.

[0016] [The composition of the memory cell region MCR and the contact region HUR] Figure 3This is a perspective view showing the configuration of the memory cell region MCR and the contact region HUR of the semiconductor device according to this embodiment. To avoid complexity in the diagram, conductive components are shown, while insulating components are omitted. Figure 3 The parts of the component not shown are insulated with insulating materials such as silicon dioxide.

[0017] In the memory cell region MCR, a memory cell array 16 is formed on the source electrode 11. The source electrode 11 may be, for example, a semiconductor substrate using a single crystal silicon, a semiconductor layer using polycrystalline silicon, or a conductive layer using a metal such as tungsten. The memory cell array 16 has conductive layers 71, 72, 73, and 74 (referred to as conductive layer 70 when conductive layers 71 to 74 are not distinguished) extending substantially parallel to the surface of the source electrode 11. The memory cell array 16 has a stack of these multiple conductive layers 70, each separated by an insulating layer. Here, the material of the conductive layer 70 may be, for example, tungsten or molybdenum. The material of the insulating layer may be, for example, a silicon dioxide film (SiO2) or an oxygen-containing silicon such as TEOS (Tetra Ethyl OrthoSilicate). Only four conductive layers 70 are shown in the figure, but more layers may be stacked, such as 33 or 65 layers. These conductive layers 70 correspond to source-side select gate lines, word lines, or drain-side select gate lines connected to transistors.

[0018] A memory pillar 60 is formed in the memory cell region MCR, through which multiple conductive layers 70 and multiple insulating layers are formed. The memory pillar 60 is cylindrical in shape, and from the outer periphery to the center side are stacked a barrier insulating film containing a silicon dioxide film, a charge storage film containing a silicon nitride film, a tunnel insulating film containing a silicon dioxide film, a semiconductor channel containing an amorphous or polycrystalline silicon film, and a silicon dioxide film. A portion of the charge storage film located between the conductive layers 71, 72, 73, 74 corresponding to the select gate line or word line and the semiconductor channel functions as part of a non-volatile memory cell that traps charge carriers.

[0019] The upper end of the semiconductor channel of the memory pillar 60 is connected to a bit line BL (not shown). A plurality of memory pillars 60, each selected from one of the blocks BLK separated in the Y direction by the slit ST, are connected to a common bit line BL extending in the Y direction.

[0020] In the contact region HUR, a stacked wiring structure 17 is formed on the source 11. Multiple insulating layers and multiple conductive layers 70 extending from the memory cell region MCR are also formed in the contact region HUR. The stacked wiring structure 17 has conductive layers 71, 72, 73, and 74 extending substantially parallel to the surface of the source 11. The stacked wiring structure 17 is a stack formed by stacking these multiple conductive layers 70 with insulating layers in between. Only four conductive layers 70 are shown in the figure, but as mentioned above, more layers, such as 33 or 65 layers, are stacked. Furthermore, these multiple conductive layers 70 correspond in the contact region HUR to wiring led out from the source-side gate selection line, word line, or drain-side gate selection line.

[0021] In the contact region HUR, conductive layers 71, 72, 73, and 74 corresponding to wiring led out from the selected gate line or word line form a stepped structure in the X direction such that a portion of the underlying conductive layer is exposed.

[0022] A contact plug 50 is formed in the contact region HUR, through which multiple conductive layers 70 and multiple insulating layers are formed. The contact plug 50 is generally cylindrical in shape, and its details will be described later. The material of the contact plug 50 may be, for example, tungsten.

[0023] Conductive layers 71, 72, 73, and 74 are connected to contact plugs 51, 52, 53, and 54 (here, contact plugs 51 to 54 are referred to as contact plugs 50 without distinguishing between them) respectively in the stepped areas exposed in the stepped structure. Here, conductive layer 71 is connected to contact plug 51, conductive layer 72 is connected to contact plug 52, conductive layer 73 is connected to contact plug 53, and conductive layer 74 is connected to contact plug 54. Only four contact plugs 50 are shown in the figure, but for example, the same number as multiple conductive layers could be configured. Each contact plug 50 is insulated from the underlying conductive layer 70 (excluding the connected conductive layer 70) via an insulating layer (not shown). Each contact plug 50 is led out onto the stacked wiring structure 17 via contact holes (not shown) penetrating the insulator.

[0024] [The structure of the multilayer wiring structure and contact plugs] use Figures 4 to 6 This describes the configuration of the stacked wiring structure and contact plug involved in this embodiment. Figure 4 This is a top view showing an outline of the contact area HUR of a certain block BLK involved in this embodiment. Figure 5 and Figure 6 This is a cross-sectional view showing the configuration of the contact plug of the semiconductor device according to this embodiment. Figure 5 It is cut at A-A'. Figure 4 The cross-sectional view of the contact area HUR shown is as follows. Figure 6 This is equivalent to cutting at B-B'. Figure 4 The cross-sectional view of the contact area HUR shown is obtained.

[0025] like Figure 4 As shown, in the contact region HUR, a stacked wiring structure 17 is provided for connecting contact plugs 50 to each of the plurality of conductive layers 70. In the stacked wiring structure 17, the plurality of contact plugs 50 are arranged in a square grid along the X and Y directions. In the stacked wiring structure 17, the plurality of conductive layers 70 are each formed in a stepped structure such that the conductive layer 70 is exposed from the upper section (the side opposite to the source 11). Furthermore, an insulator 30 is disposed on top of the stacked wiring structure 17 (in the opening region). However, for ease of explanation, in… Figure 4 It was omitted in the text.

[0026] The plurality of contact plugs 50 includes: a plurality of contact plugs 51a, 52a, 53a, 54a, and 55a arranged along the X direction (here, contact plugs 51a to 55a are referred to as contact plugs 50a without distinguishing between them) and a plurality of contact plugs 51b, 52b, 53b, 54b, and 55b (here, contact plugs 51b to 55b are referred to as contact plugs 50b without distinguishing between them). The plurality of contact plugs 50a are disposed in the Y direction on the side opposite to the bridging portion 18 and are connected to a plurality of conductive layers 70a. The plurality of contact plugs 50b are disposed in the Y direction between the bridging portion 18 and the contact plugs 50a and are connected to a plurality of conductive layers 70b (here, conductive layers 70a and 70b are referred to as conductive layers 70 without distinguishing between them).

[0027] like Figure 5 As shown, adjacent contact plugs 50a in the X direction are arranged for each conductive layer 70a. Here, the conductive layer 71a disposed above the insulating layer 41a is connected to the contact plug 51a, the conductive layer 72a disposed above the insulating layer 42a is connected to the contact plug 52a, the conductive layer 73a disposed above the insulating layer 43a is connected to the contact plug 53a, the conductive layer 74a disposed above the insulating layer 44a is connected to the contact plug 54a, and the conductive layer 75a disposed above the insulating layer 45a is connected to the contact plug 55a (here, when not distinguishing between insulating layers 41a to 45a, it is referred to as insulating layer 40a, and when not distinguishing between conductive layers 71a to 75a, it is referred to as conductive layer 70a).

[0028] like Figure 6 As shown, the contact plug 50b adjacent to the contact plug 50a in the Y direction is configured for each of the plurality of conductive layers 70b. Figure 6The diagram shows an example where a contact plug 54b adjacent to contact plug 54a in the Y direction is connected to a conductive layer 77b on a multilayer, but this is not a limitation. Multiple contact plugs 50b may also be arranged in the Y direction between the bridging portion 18 and the contact plug 50a. Here, the conductive layer 77b disposed on the insulating layer 47b is connected to the contact plug 54b.

[0029] like Figure 6 As shown, the stacked wiring structure 17 includes a first region 1, a second region 2, and a third region 3 in the Y direction. The bridging portion 18 includes a fourth region 4 and a fifth region 5 in the Y direction. The first region 1, the second region 2, and the fourth region 4 are stepped regions of a stepped structure, with the conductive layer 70 exposed corresponding to the upper surface of the stack and approximately parallel to the source electrode 11. The conductive layer 70 exposed on the upper surface of the stack is in contact with the insulator 30. The height of the first region 1 from the source electrode 11 is lower than that of the fourth region 4, and the height of the second region 2 from the source electrode 11 is lower than that of the first region 1. For example, the conductive layer 77b is exposed in the first region 1, the conductive layer 74a, which is lower than the conductive layer 77b (on the source electrode 11 side), is exposed in the second region 2, and the conductive layer 79b, which is higher than the conductive layer 77b (on the side opposite to the source electrode 11), is exposed in the fourth region 4. The step difference of the stepped regions of the stepped structure is not particularly limited (when conductive layers 77b...79b are not distinguished, it is called conductive layer 70b).

[0030] Region 3 and Region 5 are conical regions that connect the stepped regions of the stepped structure in the Y direction, exposing the insulating layer 40 (referred to as insulating layer 40 when not distinguishing between insulating layers 44a…47b…49b). Region 3 connects Region 1 and Region 2, and Region 5 connects Region 1 and Region 4. For example, the insulating layer 47b, which is lower than the conductive layer 77b (on the source 11 side), is exposed in Region 3, and the insulating layer 49b, which is lower than the conductive layer 79b (on the source 11 side), is exposed in Region 5 (referred to as insulating layer 40b when not distinguishing between insulating layers 47b…49b).

[0031] The conductive layer 77b exposed in the first region 1, the conductive layer 74a exposed in the second region 2, and the conductive layer 79b exposed in the fourth region 4 are all thicker in the Z-direction (stack direction) than the underlying conductive layer 70. Furthermore, the conductive layer 77b exposed in the first region 1 is thicker than the conductive layer 77b in the fourth region 4, and the conductive layer 74a exposed in the second region 2 is thicker than the conductive layer 74a in the first region 1. An insulator 30 with an embedded stepped structure is disposed on top of the stack of the insulating layer 40 and the conductive layer 70.

[0032] Contact plugs 50a and 50b (referred to as contact plug 50 when not distinguishing between them) extend along the stacking direction (Z direction) of the laminate, penetrating the laminate of insulator 30, insulating layer 40, and conductive layer 70 to reach source 11. Contact plug 50a is disposed in the second region 2. Contact plug 50b is disposed in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the widths of the first region 1 and the third region 3 in the Y direction. Therefore, contact plug 50b is disposed at the boundary (dashed arrow) between the first region 1 and the third region 3.

[0033] The contact plug 50a has a widened portion A protruding in the connection direction to connect with the conductive layer 70a. For example, the contact plug 54a has a disk-shaped widened portion A in the stepped region of the stepped structure opposite the conductive layer 74a, with a diameter (width in the XY direction) larger than the portion opposite the insulating layer 44a of the lower layer. The widened portion A of the contact plug 54a is connected to the conductive layer 74a in the XY direction in the second region 2.

[0034] The contact plug 50b has a widened portion B protruding in the connection direction to connect with the conductive layer 70b. For example, the contact plug 54b has a fan-shaped widened portion B in the stepped region of the stepped structure, opposite the conductive layer 77b, whose diameter (width in the Y direction) is larger than the portion opposite the insulating layer 47b of the lower layer. The widened portion B of the contact plug 54b is connected to the conductive layer 77b in the Y direction in the first region 1.

[0035] An insulating film 31 is disposed between the contact plug 50 and the lower conductive layer 70, excluding the conductive layer 70 connected via the widened portion A or the widened portion B. The contact plug 50 and the lower conductive layer 70, excluding the conductive layer 70 connected via the widened portion A or the widened portion B, are insulated by the insulating film 31.

[0036] As described above, according to the stacked wiring structure of this embodiment, even if the contact plug 54b is disposed in the conical region of the stepped structure, since an insulating film 31 is disposed between the conductive layer 70b, which is lower than the conductive layer 77b, and the side of the contact plug 54b, the contact plug 54b can be reliably connected to the conductive layer 77b, thus providing a semiconductor device 10 with improved reliability.

[0037] The width of the second region 2 forming the contact plug 54a in the Y direction can be designed to be approximately the same as the sum of the widths of the first region 1 forming the contact plug 54b and the third region 3 in the Y direction, thereby reducing the width of the stacked wiring structure 17 in the Y direction. Therefore, the width of the bridging portion 18 in the Y direction can be increased, and the rise in resistance of the bridging portion 18 can be suppressed, thus providing a semiconductor device with improved operating speed (read and program operation speed).

[0038] [Manufacturing Method of Layered Wiring Structures] Reference Figures 7 to 12 The manufacturing method of the stacked wiring structure 17 involved in this embodiment will be described.

[0039] First, on a semiconductor substrate Y, insulating layers 40 and sacrificial layers 20 (referred to as sacrificial layers 20 without distinguishing between sacrificial layers 24a…27b…29b) are alternately deposited to form a laminate. These insulating layers 40 and sacrificial layers 20 are deposited, for example, using a CVD apparatus. The alternately stacked insulating layers 40 and sacrificial layers 20 are formed in contact with each other. The insulating layers 40 and sacrificial layers 20 are periodically stacked in a direction perpendicular to the main surface of the semiconductor substrate Y. In this embodiment, the material of the insulating layer 40 can be a silicon dioxide film (SiO2). The material of the sacrificial layer 20 can be a silicon nitride film (SiN). However, the material of the sacrificial layer 20 is not limited to these; for example, it can be silicon or a metal such as tungsten.

[0040] like Figure 7 As shown, the stack of insulating layer 40 and sacrificial layer 20 is formed in a stepped structure such that the lower sacrificial layer 20 is exposed. The region forming the stacked wiring structure 17 includes a first region 1, a second region 2, and a third region 3 in the Y direction. The region that subsequently becomes the bridging portion 18 includes a fourth region 4 and a fifth region 5 in the Y direction. The first region 1, the second region 2, and the fourth region 4 are step regions of the stepped structure, with the sacrificial layer 20 exposed and formed substantially parallel to the semiconductor substrate Y. The height of the first region 1 from the semiconductor substrate Y is lower than that of the fourth region 4, and the height of the second region 2 from the semiconductor substrate Y is lower than that of the first region 1. For example, the sacrificial layer 27b is exposed in the first region 1, the sacrificial layer 24a, which is lower than the sacrificial layer 27b (on the semiconductor substrate Y side), is exposed in the second region 2, and the sacrificial layer 29b, which is higher than the sacrificial layer 27b (on the side opposite to the semiconductor substrate Y), is exposed in the fourth region 4. The step difference of the step regions of the stepped structure is not particularly limited. For example, it is preferable to arrange a sacrificial layer 20 with 6 or more layers and 24 or fewer layers between the sacrificial layer 24a and the sacrificial layer 27b.

[0041] Regions 3 and 5 are tapered regions that connect the stepped regions of the stepped structure in the Y direction, exposing the insulating layer 40. Region 3 connects Region 1 and Region 2, and Region 5 connects Region 1 and Region 4. For example, the insulating layer 47b, which is lower than the sacrificial layer 27b (on the Y side of the semiconductor substrate), is exposed in Region 3, and the insulating layer 49b, which is lower than the sacrificial layer 29b (on the Y side of the semiconductor substrate), is exposed in Region 5. The stepped structure of the laminate of insulating layer 40 and sacrificial layer 20 is formed using RIE (Reactive Ion Etching) with a mask having a pattern formed by photolithography. However, the method for forming the stepped structure is not particularly limited.

[0042] The sacrificial layer 27b exposed in the first region 1, the sacrificial layer 24a exposed in the second region 2, and the sacrificial layer 29b exposed in the fourth region 4 are thickened in the Z-direction (stack direction) by depositing silicon nitride (SiN) using a CVD apparatus. Thus, the thickness of the sacrificial layer 27b exposed in the first region 1 is greater than that of the sacrificial layer 27b in the fourth region 4, and the thickness of the sacrificial layer 24a exposed in the second region 2 is greater than that of the sacrificial layer 24a in the first region 1. An insulator 30 with an embedded stepped structure is formed on the stack of the insulating layer 40 and the sacrificial layer 20.

[0043] like Figure 8 As shown, contact holes Ha and Hb (referred to as contact holes H when not distinguishing between them) are formed in a stepped laminate. Contact hole H is formed such that it extends along the lamination direction (Z direction) of the laminate and penetrates the laminate of insulator 30, insulating layer 40, and sacrificial layer 20 to reach the semiconductor substrate Y. Contact hole Ha is formed in the second region 2. Contact hole Hb is formed in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the widths of the first region 1 and the third region 3 in the Y direction. Therefore, contact hole Hb can also be formed at the boundary (dashed arrow) between the first region 1 and the third region 3. Contact hole H is formed using a RIE (Relative Earth Interchange) mask with a pattern formed by photolithography. The mask pattern has openings in the region where contact hole H is formed, exposing the insulator 30. However, the method for forming contact hole H is not particularly limited.

[0044] like Figure 9As shown, the sacrificial layer 20 exposed on the inner side of the contact hole H is etched. Regarding the etching of the sacrificial layer 20 exposed on the inner side of the contact hole H, selective etching of the silicon nitride film (SiN) is preferred; for example, wet etching using phosphoric acid may be used. By etching the sacrificial layer 20, a groove protruding outward from the contact hole H is formed on the inner side of the contact hole H. Here, by thickening the sacrificial layer 27b exposed on the inner side of the contact hole Hb and the sacrificial layer 24a exposed on the inner side of the contact hole Ha in the Z direction (stack direction), a groove larger than the respective lower sacrificial layer 20 in the Z direction (stack direction) is formed.

[0045] like Figure 10 As shown, an insulating film 31 is formed in a laminate having contact holes H. The material of the insulating film 31 can be, for example, a silicon dioxide film (SiO2). The silicon dioxide film (SiO2) is deposited, for example, using a CVD apparatus. By forming the insulating film 31 on the inner side of the contact hole H, most of the trenches formed by etching the sacrificial layer 20 exposed on the inner side of the contact hole H are filled by the insulating film 31. On the other hand, since the trench b formed on the inner side of the contact hole Hb by etching of the sacrificial layer 27b and the trench a formed on the inner side of the contact hole Ha by etching of the sacrificial layer 24a are larger in the Z direction (laminar direction), trenches a and b will remain on the inner sides of the contact holes Ha and Hb.

[0046] like Figure 11 As shown, the insulating film 31 exposed on the surface of the laminate having contact holes H is etched. Regarding the etching of the insulating film 31 exposed on the surface of the laminate, selective etching of the silicon dioxide film (SiO2) is preferred, for example, wet etching using DHF or BHF. By etching the insulating film 31 exposed on the surface of the laminate, the diameter of the contact hole H, the groove b formed on the inner side of the contact hole Hb by the etching of the sacrificial layer 27b, and the groove a formed on the inner side of the contact hole Ha by the etching of the sacrificial layer 24a become larger. On the other hand, since the grooves of the sacrificial layer 20, which are lower than the sacrificial layer 27b and exposed on the inner side of the contact hole Hb, and lower than the sacrificial layer 24a, which are filled by the insulating film 31, are smaller in the Z direction (laminar direction), the insulating film 31 is not etched and remains as a spacer between the inner sides of the contact holes Ha and Hb and the sacrificial layer 20.

[0047] like Figure 12 As shown, an insulator 32 is formed inside the contact hole H. The material of the insulator 32 can be, for example, a dual structure of silicon dioxide (SiO2) and amorphous silicon film. The silicon dioxide (SiO2) and amorphous silicon film are deposited, for example, using a CVD apparatus.

[0048] A conductive layer 70 is formed in the region where the sacrificial layer 20 is disposed. A slit (not shown) is excavated in a predetermined region of the laminate, through which the sacrificial layer 20 contained in the laminate is removed. As a result, a cavity is created in the area where the sacrificial layer 20 was previously present. The conductive layer 70 is then formed by filling the cavity with a metal such as tungsten.

[0049] Next, the insulator 32 inside the contact hole H is removed by anisotropic etching such as RIE. Regarding the etching of the insulator 32, selective etching of the amorphous silicon film is preferred; for example, RIE using CF4 and oxygen can be employed. By removing the insulator 32, the conductive layer 77b is exposed by the groove b formed on the inner side of the contact hole Hb by the etching of the sacrificial layer 27b, and the conductive layer 74a is exposed by the groove a formed on the inner side of the contact hole Ha by the etching of the sacrificial layer 24a.

[0050] By filling the inside of contact holes Ha and Hb with a metal such as tungsten, a structure is formed. Figure 6 The contact plugs 54a and 54b are shown. Widened portions A of contact plug 54a and B of contact plug 54b are formed in groove b (etched from sacrificial layer 27b) on the inner side of contact hole Hb and groove a (etched from sacrificial layer 24a) on the inner side of contact hole Ha. Therefore, widened portion A of contact plug 54a is connected to conductive layer 74a, and widened portion B of contact plug 54b is connected to conductive layer 77b.

[0051] As described above, according to the manufacturing method of the stacked wiring structure according to this embodiment, even if the contact hole Hb is formed in the tapered region of the stepped structure, since there is a spacer remaining between the conductive layer 70, which is lower than the conductive layer 77b, and the inner side of the contact hole Hb, the contact plug 54b can be reliably connected to the conductive layer 77b, thus providing a semiconductor device 10 with improved reliability.

[0052] The width of the second region 2 forming the contact plug 54a in the Y direction can be designed to be approximately the same as the sum of the widths of the first region 1 forming the contact plug 54b and the third region 3 in the Y direction, thereby reducing the width of the stacked wiring structure 17 in the Y direction. Therefore, the width of the bridging portion 18 in the Y direction can be increased, and the rise in resistance of the bridging portion 18 can be suppressed, thus providing a semiconductor device with improved operating speed (read and program operation speed).

[0053] [Second Implementation] [Overall Structure of a Semiconductor Device] The overall configuration of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment. The configuration of the multilayer wiring structure according to the second embodiment is the same as that of the multilayer wiring structure according to the first embodiment, except for the configuration of the contact plugs. Descriptions identical to those in the first embodiment are omitted; instead, descriptions will focus on the differences in the configuration of the contact plugs compared to those in the first embodiment.

[0054] [Construction of the contact plug] use Figure 13 The configuration of the contact plug involved in this embodiment will be described. Figure 13 This is equivalent to cutting at B-B'. Figure 4 The cross-sectional view of the contact area HUR shown is obtained.

[0055] like Figure 13 As shown, contact plug 50c (corresponding to Figure 4 The contact plug 50a. Here, without distinguishing between contact plugs 51c to 55c, they are referred to as contact plug 50c) and contact plug 50d (corresponding to Figure 4 The contact plug 50b. Here, it is referred to as contact plug 50d when contact plugs 51d to 55d are not distinguished, and contact plugs 50c and 50d are referred to as contact plug 50. It extends along the stacking direction (Z direction) of the laminate and is connected to the conductive layer 70 exposed in the step region of the stepped structure.

[0056] Contact plug 50c is disposed in the second region 2. Contact plug 50d is disposed in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the widths of the first region 1 and the third region 3 in the Y direction. Therefore, contact plug 50d is disposed at the boundary between the first region 1 and the third region 3 (dashed arrow).

[0057] Contact plug 50c is connected to the upper surface of conductive layer 70 exposed in the stepped region of the stepped structure in the second region 2. For example, contact plug 54c is connected to the upper surface of conductive layer 74a in the Z direction in the second region 2.

[0058] Contact plug 50d is connected to the end of conductive layer 70 exposed in the stepped area of ​​the stepped structure at the boundary (dashed arrow) between the first region 1 and the third region 3. For example, contact plug 54d is connected to the end of conductive layer 77b in the Y direction at the boundary between the first region 1 and the third region 3.

[0059] An insulating film 31 is disposed between the contact plug 50 and the lower conductive layer 70 other than the conductive layer 70 connected to the contact plug 50. The contact plug 50 and the lower conductive layer 70 other than the conductive layer 70 connected to the contact plug 50 are insulated from each other by the insulating film 31.

[0060] As described above, according to the stacked wiring structure of this embodiment, even if the contact plug 54d is disposed in the conical region of the stepped structure, since it is insulated from the conductive layer 70 which is lower than the conductive layer 77b, the contact plug 54d can be reliably connected to the conductive layer 77b, thus providing a semiconductor device 10 with improved reliability.

[0061] The width of the second region 2 forming the contact plug 54c in the Y direction can be designed to be approximately the same as the sum of the widths of the first region 1 forming the contact plug 54d in the Y direction and the width of the third region 3 in the Y direction, thereby reducing the width of the stacked wiring structure 17 in the Y direction. Therefore, the width of the bridging portion 18 in the Y direction can be increased, and the rise in resistance of the bridging portion 18 can be suppressed, thus providing a semiconductor device with improved operating speed (read and program operation speed).

[0062] [Manufacturing Method of Layered Wiring Structures] Reference Figure 7 , Figure 8 as well as Figures 14 to 17 The manufacturing method of the stacked wiring structure 17 involved in this embodiment will be described.

[0063] like Figure 7 As shown, the laminate of insulating layer 40 and sacrificial layer 20 is formed in a stepped structure such that the lower sacrificial layer 20 is exposed. Figure 8 Similarly, contact holes Hc and Hd (referred to as contact holes H when not distinguishing between them) are formed in the stepped laminate. Contact hole Hc is formed in the second region 2, and contact hole Hd is formed in the first region 1 and the third region 3.

[0064] like Figure 14 As shown, the insulating layer 40 exposed on the inner side of the contact hole H is etched. Regarding the etching of the insulating layer 40 exposed on the inner side of the contact hole H, selective etching of the silicon dioxide film is preferred; for example, wet etching using DHF or BHF may be employed. By etching the insulating layer 40, the sacrificial layer 20 protrudes inward from the inner side of the contact hole H.

[0065] like Figure 15As shown, an insulating film 31 is formed in a laminate having contact holes H. The material of the insulating film 31 can be, for example, a silicon dioxide film (SiO2). The silicon dioxide film (SiO2) is deposited, for example, using a CVD apparatus. By forming the insulating film 31 on the inner side of the contact holes H, the protrusions of the sacrificial layer 20 formed by etching the insulating layer 40 exposed on the inner side of the contact holes H are filled by the insulating film 31.

[0066] like Figure 16 As shown, the insulating film 31 exposed on the surface of the laminate having contact holes H is etched. Regarding the etching of the insulating film 31 exposed on the surface of the laminate, selective etching of the silicon dioxide film (SiO2) is preferred, for example, wet etching using DHF or BHF. By etching the insulating film 31 exposed on the surface of the laminate, the upper part of the contact hole H, the protrusion d of the sacrificial layer 27 formed on the inner side of the contact hole Hd, and the protrusion c of the sacrificial layer 24 formed on the inner side of the contact hole Hc are exposed. On the other hand, in the lower parts of the contact holes Hd and Hc, which are filled with the insulating film 31, the insulating film 31 is not etched and remains as a spacer.

[0067] like Figure 17 As shown, an insulator 32 is formed inside the contact hole H. The material of the insulator 32 can be, for example, a dual structure of silicon dioxide (SiO2) and amorphous silicon film. The silicon dioxide (SiO2) and amorphous silicon film are deposited, for example, using a CVD apparatus.

[0068] A conductive layer 70 is formed in the region where the sacrificial layer 20 is disposed. A slit (not shown) is excavated in a predetermined region of the laminate, through which the sacrificial layer 20 contained in the laminate is removed. As a result, a cavity is created in the area where the sacrificial layer 20 was previously present. The conductive layer 70 is then formed by filling the cavity with a metal such as tungsten.

[0069] Next, the insulator 32 inside the contact hole H is removed by anisotropic etching such as RIE. Regarding the etching of the insulator 32, selective etching of the amorphous silicon film is preferred; for example, RIE using CF4 and oxygen can be employed. Removing the insulator 32 exposes the conductive layer 77b protruding from the inner surface of the contact hole Hd and the conductive layer 74a protruding from the inner surface of the contact hole Hc.

[0070] By filling the inside of contact holes Hc and Hd with a metal such as tungsten, a structure is formed. Figure 13 The contact plugs 54c and 54d are shown. Therefore, contact plug 54c is connected to conductive layer 74a, and contact plug 54d is connected to conductive layer 77b.

[0071] As described above, according to the manufacturing method of the stacked wiring structure according to this embodiment, even if the contact hole Hd is formed in the tapered region of the stepped structure, since there is a spacer between the conductive layer 70, which is lower than the conductive layer 77b, and the contact plug 54d, the contact plug 54d can be reliably connected to the conductive layer 77b, thus providing a semiconductor device 10 with improved reliability.

[0072] The width of the second region 2 forming the contact plug 54c in the Y direction can be designed to be approximately the same as the sum of the widths of the first region 1 forming the contact plug 54d in the Y direction and the width of the third region 3 in the Y direction, thereby reducing the width of the stacked wiring structure 17 in the Y direction. Therefore, the width of the bridging portion 18 in the Y direction can be increased, and the rise in resistance of the bridging portion 18 can be suppressed, thus providing a semiconductor device with improved operating speed (read and program operation speed).

[0073] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. [Explanation of reference numerals in the attached figures]

[0074] 1 First region, 2 Second region, 3 Third region, 4 Fourth region, 5 Fifth region, 7 Conductive layer, 10 Semiconductor device, 11 Source, 16 Memory cell array, 17 Stacked wiring structure, 18 Bridging section, 50 Contact plug, 70 Conductive layer, Trenches a, b, Protrusion c, Protrusion d

Claims

1. A semiconductor device comprising: Source pole; An insulator is disposed above the source electrode; A first conductive layer is in contact with the insulator in a first region; A second conductive layer is disposed between the source electrode and the first conductive layer, and is in contact with the insulator in a second region, wherein the height of the second region from the source electrode is lower than the height of the first region from the source electrode. A first insulating layer is disposed between the first conductive layer and the second conductive layer, and is in contact with the insulator in a third region, the third region connecting the first region and the second region in a first direction; as well as A first columnar conductive portion is disposed at the boundary between the first region and the third region, extends along a second direction orthogonal to the first direction, and is connected to the first conductive layer.

2. The semiconductor device according to claim 1, wherein, It also includes a second columnar conductive portion disposed in the second region, extending along the second direction, and connected to the second conductive layer.

3. The semiconductor device according to claim 2, wherein, The width of the second region in the first direction is the sum of the width of the first region in the first direction and the width of the third region in the first direction.

4. The semiconductor device according to claim 1, wherein, Also includes: A third conductive layer is disposed on the side of the first conductive layer opposite to the source electrode, and is in contact with the insulator in a fourth region, wherein the fourth region is at a higher height from the source electrode than the first region is at a higher height from the source electrode. as well as A second insulating layer is disposed between the first conductive layer and the third conductive layer, and is in contact with the insulator in a fifth region, the fifth region connecting the first region and the fourth region in a first direction.

5. The semiconductor device according to claim 1, wherein, The first columnar conductive portion has a first widened portion on a first portion opposite to the first conductive layer, and the width of the first widened portion in the first direction is larger than that of the second portion opposite to the first insulating layer.

6. The semiconductor device according to claim 5, wherein, The first widened portion of the first columnar conductor is connected to the first conductive layer.

7. The semiconductor device according to claim 4, wherein, The thickness of the first conductive layer in the first region is greater than the thickness in the fourth region.

8. The semiconductor device according to claim 2, wherein, It also includes a third insulating layer disposed between the source electrode and the second conductive layer. The second columnar conductive portion has a second widened portion on the third portion opposite to the second conductive layer, and the width of the second widened portion in the first direction is larger than that of the fourth portion opposite to the third insulating layer.

9. The semiconductor device according to claim 8, wherein, The second widened portion of the second columnar conductor is connected to the second conductive layer.

10. The semiconductor device according to claim 1, wherein, The second conductive layer is thicker in the second region than it is thicker in the first region.

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