Semiconductor package

Abstract

A semiconductor package includes a base substrate and a first chip, a second chip, and a mediator layer electrically connected to the base substrate. The first chip, the second chip, and the mediator layer overlap each other. The mediator layer is disposed between the first chip and the second chip. The mediator layer includes a capacitor structure electrically connected to the first chip.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package having an interposer layer between logic chips, the interposer layer including a capacitor. Background Technology

[0002] Semiconductor packaging is a structure that includes an integrated circuit chip suitable for use in electronic devices. Typically, a semiconductor package includes a semiconductor chip on a printed circuit board (PCB), and the PCB and semiconductor chip are electrically connected using bonding wires or bumps. Various studies have been conducted to improve the reliability of semiconductor packages. Summary of the Invention

[0003] According to some embodiments, this disclosure relates to a semiconductor package including: a substrate; and a first chip, a second chip, and an interposer electrically connected to the substrate. The first chip, the second chip, and the interposer overlap each other. The interposer is disposed between the first chip and the second chip. The interposer includes a capacitor structure electrically connected to the first chip.

[0004] According to some embodiments, this disclosure relates to a semiconductor package, including: a substrate; and a first chip, a second chip, and an interposer electrically connected to the substrate. The first chip, the second chip, and the interposer overlap each other. The interposer is disposed between the first chip and the second chip. The second chip is disposed between the substrate and the interposer. The interposer includes the first substrate and a first capacitor structure. The first capacitor structure is disposed between the first substrate and the first chip.

[0005] According to some embodiments, this disclosure relates to a semiconductor package, including: a package substrate; a base substrate electrically connected to the package substrate; and a first chip, a second chip, an interposer, a plurality of first memory chips, and a plurality of second memory chips electrically connected to the base substrate. The first chip, the second chip, and the interposer overlap each other. The plurality of first memory chips overlap each other. The plurality of second memory chips overlap each other. The interposer is disposed between the first chip and the second chip. The first chip, the second chip, and the interposer are disposed between the first memory chips and the second memory chips. The interposer includes a substrate and a through-path penetrating the substrate. The first chip includes a first logic unit structure. The second chip includes a second logic unit structure. The through-path electrically connects the first chip and the second chip.

[0006] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor package, the method comprising: forming a first chip on a carrier substrate; electrically connecting an interposer to the first chip; electrically connecting a second chip to the interposer; and mounting the first chip, the second chip, and the interposer to a substrate. The interposer includes a capacitor structure electrically connected to the first chip.

[0007] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor package, the method comprising hybrid bonding of a first chip and an interposer.

[0008] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor package, the method comprising a hybrid bonding interposer and a second chip.

[0009] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor package, the method comprising mounting a substrate onto a package substrate.

[0010] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor package, the method comprising mounting a memory chip on a substrate. Attached Figure Description

[0011] The exemplary embodiments will be more clearly understood from the following description in conjunction with the accompanying drawings.

[0012] Figure 1A This is a cross-sectional view of an example of a semiconductor package according to some implementation methods.

[0013] Figure 1B It is based on some implementation methods Figure 1A A magnified view of an example of the Q1 region.

[0014] Figure 1C It is based on some implementation methods Figure 1A A magnified view of an example of the Q2 region.

[0015] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to some embodiments.

[0016] Figure 10 This is an enlarged view of an example of a semiconductor package according to some implementation methods. Detailed Implementation

[0017] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0018] In some embodiments, this disclosure relates to a capacitor structure disposed within an interposer, wherein power can be supplied from the capacitor structure within the interposer to the logic cell structure. Therefore, the power path can be relatively short, and voltage (IR) drop can be reduced.

[0019] In some embodiments, this disclosure relates to a capacitor structure disposed in a substrate, such that power is supplied from the capacitor structure in the substrate to a logic cell structure. Therefore, the power path can be relatively short, and IR drop can be reduced.

[0020] Figure 1A This is a cross-sectional view of an example of a semiconductor package according to some implementation methods. Figure 1B yes Figure 1A A magnified view of the Q1 region. Figure 1C yes Figure 1A A magnified view of the Q2 region.

[0021] exist Figure 1A In this semiconductor package, a terminal 10, a package substrate 1, a first bump 20, a second bump 30, a third bump 40, a base substrate 100, a memory chip 200, a first chip 300, a second chip 400, an interposer 500, a first underfill layer 50, a second underfill layer 61, a third underfill layer 62, a molding layer 63, and a heat slug 70 may be included.

[0022] The packaging substrate 1 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. As an example, the first direction D1 and the second direction D2 may be horizontal directions that are orthogonal to each other. The packaging substrate 1 may be, for example, a printed circuit board (PCB) or a redistribution substrate.

[0023] Terminal 10 can be connected to the package substrate 1. Terminal 10 may include conductive material.

[0024] The substrate 100 can be mounted on the package substrate 1. The substrate 100 can be electrically connected to the package substrate 1. A first bump 20 can be provided between the substrate 100 and the package substrate 1. The first bump 20 may include a conductive material. A first underfill layer 50 can be provided between the substrate 100 and the package substrate 1. The first underfill layer 50 may include a polymer material.

[0025] The substrate 100 may include a redistribution pattern 120, a photosensitive insulating layer 110, and a bump connection pattern 130. The photosensitive insulating layer 110 may be stacked sequentially along a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. As an example, the third direction D3 may be a perpendicular direction orthogonal to the first direction D1 and the second direction D2.

[0026] The photosensitive insulating layer 110 may include a photoimageable dielectric (PID) material. The photoimageable dielectric material may include at least one of, for example, photosensitive polyimide, polybenzoxazole, phenol-based polymers, and benzocyclobutene-based polymers.

[0027] The redistribution pattern 120 may be surrounded by the photosensitive insulating layer 110. The redistribution pattern 120 may be disposed within the photosensitive insulating layer 110. At least some of the redistribution patterns 120 may include a base portion and a via portion on the base portion. The width of the base portion may be greater than the width of the via portion. The base portion may have a line or strip shape, and the via portion may have a column shape.

[0028] The redistribution pattern 120 may include a conductive material. In one example, the redistribution pattern 120 may include copper.

[0029] The bump connection pattern 130 can be connected to the redistribution pattern 120. The bump connection pattern 130 can be disposed on the outer side of the photosensitive insulating layer 110. The bump connection pattern 130 can include a conductive material. In one example, the bump connection pattern 130 can include copper.

[0030] In some embodiments, the substrate 100 may be an interlayer comprising a semiconductor substrate and a through-path penetrating the semiconductor substrate. In some embodiments, the substrate 100 may be a printed circuit board.

[0031] The memory chip 200, the first chip 300, the second chip 400, and the interposer 500 can be electrically connected to the substrate 100. The memory chip 200, the first chip 300, the second chip 400, and the interposer 500 can overlap with the substrate 100 on a third-direction D3. The first chip 300, the second chip 400, and the interposer 500 can overlap with each other on a third-direction D3.

[0032] Intermediate layer 500 can be disposed between first chip 300 and second chip 400. Intermediate layer 500 can be disposed at a lower level than first chip 300 and at a higher level than second chip 400.

[0033] The second chip 400 and the interposer 500 can be disposed between the first chip 300 and the substrate 100. The second chip 400 can be disposed between the interposer 500 and the substrate 100. The second chip 400 can be disposed at a level higher than the substrate 100.

[0034] The first chip 300 and the second chip 400 can be logic chips. For example, the first chip 300 and the second chip 400 can be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

[0035] The first chip 300 may include a first substrate 320, a first insulating structure 330, a first conductive structure 340, a first lower insulating layer 350, a first lower pad 360, and a first logic unit structure 310.

[0036] The first substrate 320 may be a semiconductor substrate, an insulator substrate, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include, for example, silicon, germanium, silicon-germanium, GaP, or GaAs.

[0037] The first logic unit structure 310 can be disposed on the lower surface of the first substrate 320.

[0038] The first conductive structure 340 may be electrically connected to the first logic unit structure 310. The first conductive structure 340 may include at least one of a conductive path, a conductive line, and a conductive pad. The first conductive structure 340 may include a conductive material.

[0039] A first insulating structure 330 may surround a first conductive structure 340. The first conductive structure 340 may be disposed within the first insulating structure 330. The first insulating structure 330 may be disposed on the lower surface of the first substrate 320. The first insulating structure 330 may include an insulating material. In some embodiments, the first insulating structure 330 may be a multilayer comprising multiple insulating layers.

[0040] The first lower pad 360 can be electrically connected to the first conductive structure 340. The first lower pad 360 can contact the first conductive structure 340. The first logic unit structure 310 can be electrically connected to the first lower pad 360 through the first conductive structure 340. The first lower pad 360 may include conductive material.

[0041] A first lower insulating layer 350 may surround a first lower pad 360. The first lower pad 360 may be disposed within the first lower insulating layer 350. The first lower insulating layer 350 may include an insulating material. In some embodiments, the first lower insulating layer 350 may be a multilayer comprising multiple insulating layers.

[0042] The second chip 400 may include a second substrate 420, a second insulating structure 430, a second conductive structure 440, a first upper insulating layer 450, a first upper pad 460, a first through-path 470, a second lower pad 480, a second lower insulating layer 490, and a second logic unit structure 410.

[0043] The second substrate 420 may be a semiconductor substrate, an insulator substrate, or a semiconductor-on-insulator (SOI) substrate.

[0044] The second logic unit structure 410 can be disposed on the lower surface of the second substrate 420.

[0045] The second conductive structure 440 can be electrically connected to the second logic unit structure 410. The second conductive structure 440 may include at least one of a conductive path, a conductive line, and a conductive pad. The second conductive structure 440 may include a conductive material.

[0046] The second insulating structure 430 may surround the second conductive structure 440. The second conductive structure 440 may be disposed within the second insulating structure 430. The second insulating structure 430 may be disposed on the lower surface of the second substrate 420. The second insulating structure 430 may include an insulating material. In some embodiments, the second insulating structure 430 may be a multilayer comprising multiple insulating layers.

[0047] The second lower pad 480 can be electrically connected to the second conductive structure 440. The second lower pad 480 can contact the second conductive structure 440. The second logic unit structure 410 can be electrically connected to the second lower pad 480 through the second conductive structure 440. The second lower pad 480 may include conductive material.

[0048] The second lower insulating layer 490 may surround the second lower pad 480. The second lower pad 480 may be disposed within the second lower insulating layer 490. The second lower insulating layer 490 may include an insulating material. In some embodiments, the second lower insulating layer 490 may be a multilayer comprising multiple insulating layers.

[0049] The first through-path 470 can be electrically connected to the second conductive structure 440. The first through-path 470 can contact the second conductive structure 440. The first through-path 470 can penetrate the second substrate 420 in the third direction D3. The first through-path 470 can include conductive material.

[0050] The first upper pad 460 can be electrically connected to the first through-path 470. The first upper pad 460 can contact the first through-path 470. The second logic cell structure 410 can be electrically connected to the first upper pad 460 through the second conductive structure 440 and the first through-path 470. The first upper pad 460 may include conductive material.

[0051] A first upper insulating layer 450 may surround a first upper pad 460. The first upper pad 460 may be disposed within the first upper insulating layer 450. The first upper insulating layer 450 may include an insulating material. In some embodiments, the first upper insulating layer 450 may be a multilayer comprising multiple insulating layers.

[0052] Intermediate layer 500 may include a third substrate 520, a third insulating structure 530, a third conductive structure 540, a second upper insulating layer 550, a second upper pad 560, a second through-path 570, a third lower pad 580, a third lower insulating layer 590, and a first capacitor structure 510. Intermediate layer 500 may not include transistors.

[0053] The third substrate 520 may be a semiconductor substrate, an insulator substrate, or a semiconductor-on-insulator (SOI) substrate.

[0054] The third conductive structure 540 can be electrically connected to the first capacitor structure 510. The third conductive structure 540 may include at least one of a conductive path, a conductive line, and a conductive pad. The third conductive structure 540 may include a conductive material.

[0055] The third insulating structure 530 may surround the third conductive structure 540. The third conductive structure 540 may be disposed within the third insulating structure 530. The third insulating structure 530 may be disposed on the upper surface of the third substrate 520. The third insulating structure 530 may include an insulating material. In some embodiments, the third insulating structure 530 may be a multilayer comprising multiple insulating layers.

[0056] The second upper pad 560 can be electrically connected to the third conductive structure 540. The second upper pad 560 can contact the third conductive structure 540. The first capacitor structure 510 can be electrically connected to the second upper pad 560 through the third conductive structure 540. The second upper pad 560 may include conductive material.

[0057] The second upper insulating layer 550 may surround the second upper pad 560. The second upper pad 560 may be disposed within the second upper insulating layer 550. The second upper insulating layer 550 may include an insulating material. In some embodiments, the second upper insulating layer 550 may be a multilayer comprising multiple insulating layers.

[0058] The second through-path 570 can be electrically connected to the third conductive structure 540. The second through-path 570 can contact the third conductive structure 540. The second through-path 570 can penetrate the third substrate 520 in the third direction D3. The second through-path 570 can include conductive material.

[0059] The third lower pad 580 can be electrically connected to the second through-path 570. The third lower pad 580 can contact the second through-path 570. The first capacitor structure 510 can be electrically connected to the third lower pad 580 through the third conductive structure 540 and the second through-path 570. The third lower pad 580 may include conductive material.

[0060] A third lower insulating layer 590 may surround a third lower pad 580. The third lower pad 580 may be disposed within the third lower insulating layer 590. The third lower insulating layer 590 may include an insulating material. In some embodiments, the third lower insulating layer 590 may be a multilayer comprising multiple insulating layers.

[0061] The first logic unit structure 310, the first insulating structure 330, the first conductive structure 340, the first lower insulating layer 350, the first lower pad 360, the second upper pad 560, the second upper insulating layer 550, the third conductive structure 540, the third insulating structure 530 and the first capacitor structure 510 can be disposed between the first substrate 320 and the third substrate 520.

[0062] The first logic unit structure 310, the first insulating structure 330, the first conductive structure 340, the first lower insulating layer 350, the first lower pad 360, the second upper pad 560, the second upper insulating layer 550, the third conductive structure 540, the third insulating structure 530, and the first capacitor structure 510 can be disposed at a level lower than the first substrate 320 and at a level higher than the third substrate 520.

[0063] The first logic unit structure 310, the first insulating structure 330, the first conductive structure 340, the first lower insulating layer 350, and the first lower pad 360 can be disposed between the first substrate 320 and the interposer layer 500.

[0064] The second upper pad 560, the second upper insulating layer 550, the third conductive structure 540, the third insulating structure 530 and the first capacitor structure 510 can be disposed between the first chip 300 and the third substrate 520.

[0065] The first lower pad 360 can contact the second upper pad 560. The first logic unit structure 310 can be electrically connected to the first capacitor structure 510 through the first conductive structure 340, the first lower pad 360, the second upper pad 560, and the third conductive structure 540. The first capacitor structure 510 can be electrically connected to the first chip 300 through the second upper pad 560 and the third conductive structure 540.

[0066] The third lower pad 580 can contact the first upper pad 460. The first lower insulating layer 350 can contact the second upper insulating layer 550. The third lower insulating layer 590 can contact the first upper insulating layer 450.

[0067] The lower surface of the first chip 300 can be co-bonded to the upper surface of the interposer 500. The upper surface of the second chip 400 can be co-bonded to the lower surface of the interposer 500.

[0068] A second bump 30 may be provided between the second chip 400 and the substrate 100. The second bump 30 may include a conductive material. A second underfill layer 61 may be provided between the second chip 400 and the substrate 100. The second underfill layer 61 may include a polymer material.

[0069] The substrate 100 may further include a second capacitor structure 140. The second capacitor structure 140 may be electrically connected to the redistribution pattern 120. The second capacitor structure 140 may be electrically connected to the second bump 30 via the redistribution pattern 120. The second capacitor structure 140 may be disposed in the photosensitive insulating layer 110. The second capacitor structure 140 may be surrounded by the photosensitive insulating layer 110.

[0070] The second logic unit structure 410, the second lower pad 480, the second insulating structure 430, the second conductive structure 440, the second lower insulating layer 490, and the second bump 30 can be disposed between the second substrate 420 and the base substrate 100.

[0071] The second logic unit structure 410, the second lower pad 480, the second insulating structure 430, the second conductive structure 440, the second lower insulating layer 490, and the second bump 30 can be disposed at a level lower than the second substrate 420 and at a level higher than the base substrate 100.

[0072] The second bump 30 can contact the second lower pad 480 and the redistribution pattern 120. The second logic cell structure 410 can be electrically connected to the second capacitor structure 140 through the second conductive structure 440, the second lower pad 480, the second bump 30, and the redistribution pattern 120. The second capacitor structure 140 can be electrically connected to the second chip 400 through the redistribution pattern 120 and the second bump 30.

[0073] The memory chip 200 may include a first memory chip overlapping each other on a third-direction D3 and a second memory chip overlapping each other on a third-direction D3. The first chip 300, the second chip 400, and the interposer layer 500 may be disposed between the first memory chip and the second memory chip.

[0074] The memory chip 200 can be a volatile memory chip or a non-volatile memory chip. Volatile memory chips can be, for example, dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero-capacitor RAM (ZRAM), or dual-transistor RAM (TTRAM). Non-volatile memory chips can be, for example, flash memory, magnetic RAM (MRAM), spin-torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), resistive RAM (RRAM), polymer RAM, or insulator resistance-changing memory.

[0075] Each of the memory chips 200 may include a memory substrate 220, a memory insulating structure 230, a memory conductive structure 240, a memory upper insulating layer 250, a memory upper pad 260, a memory through-path 270, a memory lower pad 280, a memory lower insulating layer 290, and a memory cell structure 210. The uppermost memory chip in the memory chip 200 may not include the memory upper insulating layer 250, the memory upper pad 260, and the memory through-path 270.

[0076] The memory substrate 220 may be a semiconductor substrate, an insulator substrate, or a semiconductor-on-insulator (SOI) substrate.

[0077] The memory cell structure 210 can be disposed on the lower surface of the memory substrate 220.

[0078] The memory conductive structure 240 can be electrically connected to the memory cell structure 210. The memory conductive structure 240 may include at least one of a conductive path, a conductive line, and a conductive pad. The memory conductive structure 240 may include a conductive material.

[0079] The memory insulating structure 230 may surround the memory conductive structure 240. The memory conductive structure 240 may be disposed within the memory insulating structure 230. The memory insulating structure 230 may be disposed on the lower surface of the memory substrate 220. The memory insulating structure 230 may include an insulating material. In some embodiments, the memory insulating structure 230 may be a multilayer comprising multiple insulating layers.

[0080] The memory under pad 280 may include a conductive material. A memory under insulating layer 290 may surround the memory under pad 280. The memory under insulating layer 290 may include an insulating material.

[0081] The memory through-path 270 may pass through the memory substrate 220 (or extend into the memory substrate 220) in the third direction D3. The memory through-path 270 may include a conductive material.

[0082] The memory pad 260 may include a conductive material. An insulating layer 250 may surround the memory pad 260. The insulating layer 250 may include an insulating material.

[0083] The upper pad 260 and the lower pad 280 of the memory can contact each other. The upper insulating layer 250 and the lower insulating layer 290 of the memory can contact each other. The memory chips 200 can be mixed and bonded together.

[0084] A third bump 40 may be disposed between the memory chip 200 and the substrate 100. The third bump 40 may include a conductive material. A third underfill layer 62 may be provided between the memory chip 200 and the substrate 100. The third underfill layer 62 may include a polymer material.

[0085] A molding layer 63 may be provided surrounding the memory chip 200, the first chip 300, the second chip 400, and the interposer 500. The molding layer 63 may include a polymer material.

[0086] A heat sink 70 may be provided on the packaging substrate 1. In some embodiments, the heat sink 70 may have a ring shape surrounding the substrate 100, memory chip 200, first chip 300, second chip 400, and interposer 500. The heat sink 70 can release heat generated in the substrate 100, memory chip 200, first chip 300, second chip 400, and interposer 500 to the outside.

[0087] exist Figure 1B In the first logic unit structure 310, a fin pattern FP, a semiconductor pattern SP, a source / drain pattern SD, a gate electrode GE, a gate spacer GS, a gate insulating layer GI, a gate cap pattern GP, ​​and an active contact AC may be included.

[0088] The fin pattern FP, semiconductor pattern SP, source / drain pattern SD, gate electrode GE, gate spacer GS, gate insulating layer GI, gate cap pattern GP, ​​and active contact AC of the first logic unit structure 310 may be surrounded by the first insulating structure 330.

[0089] The fin pattern FP can be a part of the first substrate 320. The portion of the first substrate 320 that protrudes in the direction opposite to the third direction D3 can be defined as the fin pattern FP.

[0090] The source / drain pattern SD can be connected to the fin pattern FP. The source / drain pattern SD can be an epitaxial pattern formed using a selective epitaxial growth (SEG) process. The source / drain pattern SD can include a semiconductor material. As an example, the source / drain pattern SD can include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The source / drain pattern SD can be doped with a dopant.

[0091] Semiconductor patterns SP can be connected to source / drain patterns SD. Semiconductor patterns SP between adjacent source / drain patterns SD can overlap each other on a third-direction D3. In some embodiments, semiconductor patterns SP can include silicon (Si). For example, semiconductor patterns SP can include crystalline silicon. In some embodiments, semiconductor patterns SP can include silicon germanium (SiGe).

[0092] The gate electrode GE may overlap with the semiconductor pattern SP on a third-direction D3. The gate electrode GE may include portions provided between the semiconductor patterns SP. The gate electrode GE and the semiconductor pattern SP may constitute a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET). The gate electrode GE may include a conductive material.

[0093] A gate insulating layer GI can be provided. The gate insulating layer GI can contact the gate electrode GE, the semiconductor pattern SP, and the source / drain pattern SD. The gate insulating layer GI can separate the gate electrode GE from the semiconductor pattern SP and the source / drain pattern SD. The gate insulating layer GI can include an insulating material. As an example, the gate insulating layer GI can include silicon oxide.

[0094] Gate spacers GS can be provided. A pair of gate spacers GS can be disposed on both sides of the gate electrode GE. The gate spacers GS may include insulating material.

[0095] A gate cap pattern GP can be provided. A gate electrode GE can be provided on the gate cap pattern GP. The gate cap pattern GP may include insulating material.

[0096] The active contact AC can be electrically connected to the source / drain pattern SD. The source / drain pattern SD can be electrically connected to the first conductive structure 340 via the active contact AC. The active contact AC may include a conductive material.

[0097] The first capacitor structure 510 may include a first electrode EL1, a second electrode EL2, and a first capacitor insulating layer CI1. The first electrode EL1 and the second electrode EL2 may be spaced apart from each other. The first capacitor insulating layer CI1 may be inserted between the first electrode EL1 and the second electrode EL2. The first electrode EL1, the second electrode EL2, and the first capacitor insulating layer CI1 of the first capacitor structure 510 may be surrounded by a third insulating structure 530.

[0098] The second electrode EL2 of the first capacitor structure 510 can be electrically connected to the source / drain pattern SD through the third conductive structure 540, the second upper pad 560, the first lower pad 360, the first conductive structure 340, and the active contact AC. The first electrode EL1 of the first capacitor structure 510 can be electrically connected to the third conductive structure 540.

[0099] The first capacitor structure 510 can store electrical energy and can supply power voltage (e.g., VDD or VSS) to the first logic unit structure 310.

[0100] refer to Figure 1C The second logic unit structure 410 may include a fin pattern FP, a semiconductor pattern SP, a source / drain pattern SD, a gate electrode GE, a gate spacer GS, a gate insulating layer GI, a gate cap pattern GP, ​​and an active contact AC.

[0101] The structure of the fin pattern FP, semiconductor pattern SP, source / drain pattern SD, gate electrode GE, gate spacer GS, gate insulating layer GI, gate cap pattern GP, ​​and active contact AC of the second logic unit structure 410 can be similar to the structure of the fin pattern FP, semiconductor pattern SP, source / drain pattern SD, gate electrode GE, gate spacer GS, gate insulating layer GI, gate cap pattern GP, ​​and active contact AC of the first logic unit structure 310.

[0102] The fin pattern FP, semiconductor pattern SP, source / drain pattern SD, gate electrode GE, gate spacer GS, gate insulating layer GI, gate cap pattern GP, ​​and active contact AC of the second logic unit structure 410 may be surrounded by the second insulating structure 430.

[0103] The second capacitor structure 140 may include a third electrode EL3, a fourth electrode EL4, and a second capacitor insulating layer CI2. The third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other. The second capacitor insulating layer CI2 may be inserted between the third electrode EL3 and the fourth electrode EL4. The third electrode EL3, the fourth electrode EL4, and the second capacitor insulating layer CI2 between the third electrode EL3 and the fourth electrode EL4 may be surrounded by a photosensitive insulating layer 110.

[0104] The fourth electrode EL4 of the second capacitor structure 140 can be electrically connected to the source / drain pattern SD through the redistribution pattern 120, the second bump 30, the second lower pad 480, the second conductive structure 440, and the active contact AC. The third electrode EL3 of the second capacitor structure 140 can be electrically connected to the redistribution pattern 120.

[0105] The second capacitor structure 140 can store electrical energy and can supply power supply voltage (e.g., VDD or VSS) to the second logic unit structure 410.

[0106] In some implementations, when the first capacitor structure 510 is disposed within the interposer layer 500, power is supplied from the first capacitor structure 510 to the first logic cell structure 310. Therefore, the power supply path can be relatively short, and IR drop can be reduced.

[0107] In some embodiments, when the second capacitor structure 140 is disposed in the substrate 100, power can be supplied from the second capacitor structure 140 to the second logic cell structure 410. Therefore, the power path can be relatively short, and the IR drop can be reduced. Since the first capacitor structure 510 is disposed in the interposer 500 and the second capacitor structure 140 is disposed in the substrate 100, the semiconductor package according to some embodiments does not require mounting the capacitor structure on the lower surface of the package substrate 1. Therefore, space for forming the terminals 10 can be ensured, allowing the size of the semiconductor package to be minimized. Furthermore, cracks generated during the process of mounting the capacitor structure on the package substrate 1 can be reduced.

[0108] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor package according to some embodiments.

[0109] exist Figure 2 In this process, a first chip 300 may be formed on a first carrier substrate 610. Forming the first chip 300 on the first carrier substrate 610 may include forming the first chip 300 and attaching the first chip 300 to the first carrier substrate 610.

[0110] Surface treatment of the first chip 300 can be performed. For example, the first chip 300 can be ground or etched. The surface treatment of the first chip 300 can be a pretreatment for performing a hybrid bonding process on the first chip 300.

[0111] exist Figure 3 In this process, an interposer layer 500 may be disposed on the first chip 300. Disposing of the interposer layer 500 on the first chip 300 may include forming the interposer layer 500 and bonding the interposer layer 500 to the first chip 300.

[0112] The second upper pad 560 of the interposer 500 and the first lower pad 360 of the first chip 300 can be bonded, and the second upper insulating layer 550 of the interposer 500 and the first lower insulating layer 350 of the first chip 300 can be bonded.

[0113] In some implementations, bumps can be used to electrically connect the interposer 500 to the first chip 300.

[0114] exist Figure 4 In this process, a second chip 400 may be disposed on the interposer layer 500. Disposing of the second chip 400 on the interposer layer 500 may include forming the second chip 400 and hybrid bonding the interposer layer 500 and the second chip 400.

[0115] The third lower pad 580 of the interposer 500 and the first upper pad 460 of the second chip 400 can be bonded, and the third lower insulating layer 590 of the interposer 500 and the first upper insulating layer 450 of the second chip 400 can be bonded.

[0116] In some implementations, bumps can be used to electrically connect the second chip 400 to the interposer layer 500.

[0117] exist Figure 5 In the middle, a second bump 30 can be formed. The first carrier substrate 610 can be flipped.

[0118] exist Figure 6 In this process, a substrate 100 can be formed on a second carrier substrate 620. A first chip 300, a second chip 400, and an interposer 500 can be mounted on the substrate 100. Mounting the first chip 300, the second chip 400, and the interposer 500 on the substrate 100 may include attaching a second bump 30 to a redistribution pattern 120 and forming a second bottom fill layer 61.

[0119] The first carrier substrate 610 and the first chip 300 can be separated.

[0120] exist Figure 7 In this process, a memory chip 200 can be mounted on the substrate 100. The memory chip 200 and a third bump 40 can be formed, and the third bump 40 can be attached to the redistribution pattern 120. A third bottom fill layer 62 can be formed.

[0121] A molding layer 63 can be formed around the memory chip 200, the first chip 300, the second chip 400, and the interposer layer 500.

[0122] exist Figure 8 In this process, the second carrier substrate 620 and the base substrate 100 can be separated. A bump connection pattern 130 connected to the redistribution pattern 120 can be formed. A first bump 20 connected to the bump connection pattern 130 can be formed.

[0123] exist Figure 9 In this process, a base substrate 100 can be mounted on the packaging substrate 1. A first bump 20 can be attached to the packaging substrate 1. A first bottom fill layer 50 can be formed.

[0124] refer to Figure 1A A heat sink 70 can be formed on the packaging substrate 1.

[0125] Figure 10 This is an enlarged view of a semiconductor package according to some embodiments. In addition to the following description, according to... Figure 10 Semiconductor packaging can be similar to that based on Figures 1A to 1C Semiconductor packaging.

[0126] exist Figure 10 In the process, the second chip 400a may include a second substrate 420a, a second insulating structure 430a, a second conductive structure 440a, a first upper insulating layer 450a, a first upper pad 460a, a first through-path 470a, and a second lower pad 480a. Figure 1C ), second lower insulation layer 490 ( Figure 1C ) and the second logic unit structure 410a.

[0127] The second logic unit structure 410a may be disposed on the upper surface of the second substrate 420a. The second insulating structure 430a may be disposed on the upper surface of the second substrate 420a.

[0128] The first upper pad 460a can be electrically connected to the second conductive structure 440a. The first upper pad 460a can contact the second conductive structure 440a. The second logic unit structure 410a can be electrically connected to the first upper pad 460a through the second conductive structure 440a.

[0129] The second logic unit structure 410a may include a fin pattern FPa, a semiconductor pattern SPa, a source / drain pattern SDa, a gate electrode GEa, a gate spacer GSa, a gate insulating layer GIa, a gate cap pattern GPa, and an active contact ACa.

[0130] The fin pattern FPa, semiconductor pattern SPa, source / drain pattern SDa, gate electrode GEa, gate spacer GSa, gate insulating layer GIa, gate cap pattern GPa, and active contact ACa of the second logic cell structure 410a can be disposed on the upper surface of the second substrate 420a. The fin pattern FP, semiconductor pattern SP, source / drain pattern SD, gate electrode GE, gate spacer GS, gate insulating layer GI, gate cap pattern GP, ​​and active contact AC of the first logic cell structure 310 can be disposed on the lower surface of the first substrate 320.

[0131] A first connection bump 630 and a first adhesive layer 640 may be provided between the first chip 300 and the interposer 500. The first connection bump 630 may contact a first lower pad 360 of the first chip 300 and a second upper pad 560 of the interposer 500. The first connection bump 630 may include a conductive material. The first adhesive layer 640 may surround the first connection bump 630. The first adhesive layer 640 may include a polymer material.

[0132] A second connection bump 650 and a second adhesive layer 660 may be provided between the second chip 400 and the interposer 500. The second connection bump 650 may contact a first upper pad 460a of the second chip 400 and a third lower pad 580 of the interposer 500. The second connection bump 650 may include a conductive material. The second adhesive layer 660 may surround the second connection bump 650. The second adhesive layer 660 may include a polymer material.

[0133] The first logic unit structure 310 can be electrically connected to the first capacitor structure 510 through the first conductive structure 340, the first lower pad 360, the first connecting bump 630, the second upper pad 560 and the third conductive structure 540.

[0134] The second logic unit structure 410a can be electrically connected to the first capacitor structure 510 through the second conductive structure 440a, the first upper pad 460a, the second connecting bump 650, the third lower pad 580, the second through path 570 and the third conductive structure 540.

[0135] The second logic unit structure 410a, the second insulating structure 430a, the second conductive structure 440a, the first upper insulating layer 450a, and the first upper pad 460a can be disposed between the second substrate 420a and the interposer layer 500.

[0136] Power supply voltage can be supplied from the first capacitor structure 510 to the first logic unit structure 310 and the second logic unit structure 410a.

[0137] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims, their equivalents, or the claims themselves. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0138] This patent application claims priority to Korean Patent Application No. 10-2025-0020903, filed on February 18, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, comprising: Substrate; as well as The first chip, the second chip, and the interposer are electrically connected to the substrate. The first chip, the second chip, and the interposer layer overlap each other. The intermediate layer is disposed between the first chip and the second chip, and The interposer layer includes a capacitor structure electrically connected to the first chip.

2. The semiconductor package according to claim 1, The first chip includes a first substrate and a logic unit structure. The interposer layer includes a second substrate, and The capacitor structure and the logic unit structure are located between the first substrate and the second substrate.

3. The semiconductor package of claim 2, wherein the interposer includes a through-path extending into the second substrate.

4. The semiconductor package according to claim 2, wherein the logic unit structure comprises: Source / drain patterns; Semiconductor patterns are connected to source / drain patterns; as well as The gate electrode overlaps with the semiconductor pattern.

5. The semiconductor package according to claim 2, The first chip includes a first insulating structure surrounding the logic unit structure. The intermediate layer includes a second insulating structure surrounding the capacitor structure, and The first insulating structure and the second insulating structure are located between the first substrate and the second substrate.

6. The semiconductor package according to claim 5, The first chip includes: A lower insulating layer is located between the first insulating structure and the second insulating structure; as well as The lower pad is surrounded by the lower insulating layer. The intermediary layer includes: An upper insulating layer is located between the second insulating structure and the lower insulating layer; as well as The upper pads are surrounded by the upper insulating layer. The upper pad and the lower pad are in contact with each other, and The upper insulating layer and the lower insulating layer are in contact with each other.

7. The semiconductor package according to claim 2, The first chip includes: The first conductive structure is electrically connected to the logic unit structure; as well as The lower pad is electrically connected to the first conductive structure. The intermediary layer includes: A second conductive structure is electrically connected to the capacitor structure; as well as The upper pad is electrically connected to the second conductive structure, and The lower pad and the upper pad are located between the first conductive structure and the second conductive structure.

8. A semiconductor package, comprising: Substrate; as well as The first chip, the second chip, and the interposer are electrically connected to the substrate. The first chip, the second chip, and the interposer layer overlap each other. The intermediary layer is located between the first chip and the second chip. The second chip is located between the substrate and the interposer layer. The interposer layer includes a first substrate and a first capacitor structure, and The first capacitor structure is located between the first substrate and the first chip.

9. The semiconductor package of claim 8, wherein the substrate includes a second capacitor structure electrically connected to the second chip.

10. The semiconductor package according to claim 9, The second chip includes a second substrate and a logic unit structure, and The logic unit structure is located between the second substrate and the second capacitor structure.

11. The semiconductor package according to claim 10, The second chip includes a through-path extending into the second substrate, and The logic unit structure is electrically connected to the intermediary layer through the through-path.

12. The semiconductor package of claim 9, wherein the substrate comprises: A photosensitive insulating layer surrounds the second capacitor structure; as well as The redistribution pattern is in the photosensitive insulating layer.

13. The semiconductor package according to claim 8, The first chip includes a second substrate and a first logic unit structure. The second chip includes a third substrate and a second logic unit structure. The first logic unit structure is located between the second substrate and the interposer layer, and The second logic unit structure is located between the third substrate and the base substrate.

14. The semiconductor package of claim 13, wherein the first logic unit structure and the second logic unit structure are electrically connected to the first capacitor structure.

15. The semiconductor package according to claim 13, The interposer layer includes a through-path extending into the first substrate, and The second logic unit structure is electrically connected to the first capacitor structure through the through-path.

16. A semiconductor package, comprising: Packaging substrate; A substrate electrically connected to the packaging substrate; as well as A first chip, a second chip, an interposer, a plurality of first memory chips, and a plurality of second memory chips are electrically connected to the substrate. The first chip, the second chip, and the interposer layer overlap each other. The plurality of first memory chips overlap each other. The plurality of second memory chips overlap each other. The intermediary layer is located between the first chip and the second chip. The first chip, the second chip, and the interposer are located between the first memory chip and the second memory chip. The interposer layer includes a substrate and a through-path extending into the substrate. The first chip includes a first logic unit structure. The second chip includes a second logic unit structure, and The through-path electrically connects the first chip and the second chip.

17. The semiconductor package of claim 16, wherein the interposer includes a capacitor structure electrically connected to the first logic cell structure.

18. The semiconductor package according to claim 16, The first chip includes a first lower pad. The interposer layer includes a first upper pad. Wherein the first lower pad contacts the first upper pad, and The first logic unit structure is electrically connected to the capacitor structure via the first lower pad and the first upper pad.

19. The semiconductor package according to claim 18, The interposer layer includes a second lower pad. The second chip includes a second upper pad, and The second lower pad contacts the second upper pad.

20. The semiconductor package of claim 17, wherein the second logic unit structure is electrically connected to the capacitor structure.

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