Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a first magnetic layer, a first dielectric layer over the first magnetic layer, a conductive feature over the first dielectric layer, a second dielectric layer over the conductive feature, and a second magnetic layer over the second dielectric layer. The conductive feature is embedded in the second dielectric layer. In a top view, the first magnetic layer extends beyond a boundary of the second magnetic layer. Embodiments of the present application also provide a method of fabricating a semiconductor structure.

Description

Technical Field

[0001] This application relates to semiconductor structures and their manufacturing methods. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned multiple generations of ICs, each featuring smaller and more complex circuits than the previous one. Throughout IC development, functional density (the number of interconnect devices per unit chip area) has generally increased, while geometry (the smallest component (or line) that can be created through manufacturing processes) has continuously shrunk. This miniaturization typically provides advantages by increasing production efficiency and reducing associated costs.

[0003] This scaling down also increases the complexity of IC processing and manufacturing. To achieve these technological advancements, corresponding progress is needed in IC processing and manufacturing. For example, for inductors, electromagnetic interference (EMI) effects and inductance become more challenging during scaling down. While existing structures and methods generally meet the intended use, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] One aspect of this application provides a semiconductor structure, including: a substrate; a multilayer interconnect (MLI) structure above the substrate; a passivation layer above the MLI structure; a first magnetic layer above the passivation layer; a first dielectric layer above the first magnetic layer and the passivation layer; a conductive line on the first dielectric layer, the conductive line extending longitudinally along a first direction above the first magnetic layer; a second dielectric layer surrounding the conductive line and above the conductive line; and a second magnetic layer surrounding the second dielectric layer and located above the second dielectric layer, wherein the first magnetic layer extends a first width along a second direction different from the first direction, and wherein the second magnetic layer extends a second width along the second direction that is smaller than the first width.

[0005] Another aspect of this application provides a method for manufacturing a semiconductor structure, comprising: forming a first magnetic layer over a first dielectric layer; depositing a second dielectric layer over the first magnetic layer and the first dielectric layer; forming a first conductive component and a second conductive component over the second dielectric layer and the first magnetic layer; forming a third dielectric layer around and over the first conductive component and the second conductive component; and forming a second magnetic layer over the third dielectric layer, wherein, in a top view, the first magnetic layer extends beyond the boundary of the second magnetic layer.

[0006] Another aspect of this application provides a method for manufacturing a semiconductor structure, comprising: providing a structure including a device layer and an interconnect structure located above the device layer; forming a first magnetic layer above the interconnect structure; forming a first dielectric layer above the first magnetic layer and the interconnect structure; forming conductive lines above the first dielectric layer and above the first magnetic layer; forming a second dielectric layer above the conductive lines to fill the space between the conductive lines; depositing a second magnetic layer above the second dielectric layer; and patterning the second magnetic layer, wherein after patterning the second magnetic layer, the edge of the second magnetic layer is located above the first magnetic layer, wherein the interconnect structure includes a plurality of intermetallic dielectric layers interleaved by a plurality of etch stop layers, and wherein the dielectric constant of at least one of the plurality of etch stop layers is greater than the dielectric constant of at least one of the plurality of intermetallic dielectric layers. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure is achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to various aspects of this disclosure is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The following are shown in relation to various aspects of this disclosure. Figure 1 The method is associated with exemplary partial cross-sectional views of the structure at different manufacturing stages.

[0010] Figure 10 The following are shown in relation to various aspects of this disclosure. Figure 1 The method is associated with exemplary partial top views of structures at different manufacturing stages.

[0011] Figure 11 The following are shown in accordance with various aspects of this disclosure: Figure 1 A schematic diagram of the magnetic field inside and around an exemplary structure manufactured by the method.

[0012] Figure 12 , Figure 13 and Figure 14 The following are shown in accordance with various aspects of this disclosure: Figure 1 A partial schematic cross-sectional view of an exemplary structure manufactured by the method described above. Detailed Implementation

[0013] The following disclosure provides various embodiments or examples of different features for implementing embodiments of this disclosure. Specific examples of components and arrangements described below are intended to simplify this disclosure. Of course, these are merely examples and do not constitute limitation. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact.

[0014] Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This is for the purpose of brevity and clarity and does not in itself indicate any association between the various embodiments and / or configurations. Moreover, in this disclosure, the formation of a feature located on, connected to, and / or coupled to another feature may include embodiments where the features are in direct contact, or embodiments where additional intercalation features are formed between the features, such that the features may not be in direct contact. Additionally, spatial relative terms used herein (e.g., “lower,” “upper,” “horizontal,” “vertical,” “above,” “on,” “below,” “below,” “upward,” “downward,” “top,” “bottom,” etc.) and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate the description of the spatial relationship between one feature and another. These spatial relative terms are intended to cover different orientations of the device containing the feature. Furthermore, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., the term is intended to cover numerical values ​​within a reasonable range that takes into account variations inherent in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing features with characteristics associated with that value, the value or range of values ​​covers a reasonable range including the value, such as ±10% of the value. For example, a material layer with a thickness of "about 5 nm" can cover a size range of 4.25 nm to 5.75 nm (when the manufacturing tolerance for depositing the material layer is ±15% as known to those skilled in the art). Other ranges known to those skilled in the art may also apply and may depend on the process.

[0015] Inductors or inductive structures can be used in a variety of electronic applications, such as radio frequency filters, alternating current (AC) blockers, voltage regulators, transformers, and / or similar devices. Inductive structures may include magnetic components, such as magnetic layers or films. Inductive structures can be formed on one or more passivation layers and other layers, as well as on the device itself. Electromagnetic interference (EMI) effects between the underlying components and the inductive structure can cause a decrease in inductance and / or an increase in resistance, and may affect the overall performance of the semiconductor structure. While the prior art generally meets the intended use, it is not entirely satisfactory in every aspect.

[0016] This disclosure generally relates to semiconductor structures and methods of manufacturing the same. More specifically, this disclosure relates to semiconductor structures including inductors. In some embodiments, the semiconductor structure includes a substrate, a circuit structure above the substrate, a passivation layer above the circuit structure, and an inductor above the passivation layer. In some embodiments, the inductor includes a first magnetic layer, a conductive line above the first magnetic layer, a second magnetic layer above and around the conductive line, and an isolation layer isolating the first magnetic layer, the second magnetic layer, and the conductive line. In this disclosure, the first magnetic layer is wider than the second magnetic layer such that the first magnetic layer extends laterally beyond the outer wall of the second magnetic layer. Advantages may include reduced electromagnetic interference (EMI) effects between the inductor and the circuit structure, increased inductance of the inductor, and reduced resistance of the inductor.

[0017] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. For this purpose, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is in conjunction with… Figures 2 to 10 Description method 100. Figures 2 to 9 It is structure 200 according to Figure 1 Partial cross-sectional views of different manufacturing stages of an embodiment of method 100. Figure 10 It is structure 200 according to Figure 1 Partial top view of different manufacturing stages of an embodiment of method 100. Figure 11 This is a magnetic field diagram of the interior and surrounding area of ​​structure 200. Figure 12 This is a partial schematic cross-sectional view of structure 200. Figure 13 It is based on Figure 1 A partial schematic cross-sectional view of the structure 300 manufactured according to an embodiment of method 100. Figure 14 It is based on Figure 1A partial schematic cross-sectional view of structure 400 manufactured according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or moved for additional embodiments of method 100. For the sake of brevity, not all steps are described in detail herein. Since structure 200 (or 300, 400) will be manufactured as a semiconductor structure, structure 200 (or 300, 400) may be referred to herein as semiconductor structure 200 (or 300, 400) or semiconductor device 200 (or 300, 400), depending on the context. To avoid ambiguity, Figures 2 to 14 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, the same reference numerals denote the same parts unless otherwise stated. That is, the material properties of various reference numerals and their comparisons described in connection with a method or drawing shall apply to parts with the same reference numerals described in connection with different methods or different drawings.

[0018] refer to Figures 1 to 2 Method 100 includes block 102, in which structure 200 is formed or provided. In some embodiments, structure 200 includes substrate 202, circuit structure 204 above substrate 202, and passivation structure 206 above circuit structure 204.

[0019] In one embodiment, substrate 202 may be a silicon (Si) substrate. In other embodiments, substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Example group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to form a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure. In some embodiments, substrate 202 may include one or more well regions, such as n-type well regions doped with n-type dopants (i.e., phosphorus (P) or arsenic (As)) or p-type well regions doped with p-type dopants (i.e., boron (B)), for forming different types of devices. The n-type and p-type traps can be formed using ion implantation or thermal diffusion.

[0020] In some embodiments, circuit structure 204 includes a structure formed by front-end process (FEOL) and back-end process (BEOL). In some embodiments, circuit structure 204 includes device layer 208 and multilayer interconnect (MLI) structure 210 disposed above device layer 208. In some embodiments, circuit structure 204 includes a logic structure and may also be referred to as logic structure 204.

[0021] Device layer 208 can be fabricated on and / or above substrate 202 using a front-end process (FEOL) technology. Such FEOL processes can form various transistors and / or other types of devices on substrate 202 to provide different functions. For example, these various transistors can form access transistors for central processing units (CPUs), graphics processing units (GPUs), memory devices, or image signal processing (ISP) circuitry. Transistors can be planar transistors or multi-gate transistors. A planar device refers to a device having a gate structure on a planar surface that joins the active regions of a semiconductor. A multi-gate device generally refers to a device having a gate structure or portion of a gate structure disposed above more than one side of a channel region. FinFETs and gate all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels surrounded by gates on more than one side (e.g., gates surrounding the top and sidewalls of a semiconductor material "fin" extending from the substrate). A gate-all-around (GAA) transistor has a gate structure that extends partially or completely around the channel region to provide access to the channel region on one or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be called a gate-all-around (SGT) transistor. The channel region of a GAA transistor can be formed from nanowires, nanosheets, or other nanostructures, so a GAA transistor can also be called a nanowire transistor or a nanosheet transistor.

[0022] Device layer 208 may include passive and / or active microelectronic devices, such as resistors, capacitors, inductors, diodes, P-type field-effect transistors (PFETs), N-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other devices, or combinations thereof. Various microelectronic devices may be configured to provide different functional regions of the integrated circuit, such as logic regions (i.e., core regions), memory regions, analog regions, peripheral regions (e.g., input / output regions), pseudo-regions, other suitable regions, or combinations thereof.

[0023] In some embodiments, device layer 208 includes one or more dielectric layers. The one or more dielectric layers may comprise silicon oxide or a silicon oxide-containing material. In some cases, the one or more dielectric layers may comprise undoped silicate glass (USG). In various examples, the one or more dielectric layers may be deposited by plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), subatmospheric pressure CVD (SACVD), ALD, PVD, or combinations thereof.

[0024] In some embodiments, device layer 208 includes an interlayer dielectric (ILD) layer. The ILD layer may include silicon oxide, a silicon oxide-containing material, or a low-k dielectric layer, such as TEOS oxide, undoped silicate glass (USG), or doped silicon oxide (e.g., BPSG, FSG, PSG, BSG), and / or other suitable low-k dielectric materials. In various examples, the ILD layer may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0025] In some embodiments, device layer 208 includes an etch stop layer (ESL). In some cases, the etch stop layer (ESL) includes a nitrogen-containing material and / or a carbon-containing material. For example, the etch stop layer (ESL) may include silicon carbonitride (SiCN), silicon carbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), or combinations thereof. In various examples, the etch stop layer (ESL) may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof.

[0026] The multilayer interconnect (MLI) structure 210 can be fabricated on and / or above device layer 208 using mid-stage (MEOL) and / or back-end (BEOL) processes. In some embodiments, the multilayer interconnect (MLI) structure 210 is fabricated using a back-end (BEOL) process. The multilayer interconnect (MLI) structure 210 provides interconnections (e.g., wiring) between the components formed within device layer 208 and upper conductive components (e.g., conductive pads in a passivation structure, to be described).

[0027] In some embodiments, the multilayer interconnect (MLI) structure 210 includes about five (5) to about nineteen (19) metal layers (or metallization layers). In some embodiments, each metal layer of the multilayer interconnect (MLI) structure 210 includes an inter-metal dielectric (IMD) layer and a plurality of vias and / or metal lines embedded in the IMD layer. The thickness of the IMD layers may decrease from top to bottom. For example, the thickness of the bottommost IMD layer may be less than the thickness of at least one of the IMD layers located above the bottommost IMD layer. The vias and metal lines may be formed of one or more of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). In some embodiments, the metal lines and vias comprise a barrier layer and a body metal layer above the barrier layer. The intermetallic dielectric (IMD) layer may comprise silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass (such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)) and / or other suitable dielectric materials. In some embodiments, the intermetallic dielectric (IMD) layer comprises a low-k dielectric material (e.g., a dielectric constant having a lower dielectric constant than that of silicon oxide (e.g., k < 3.9)). In some embodiments, the intermetallic dielectric (IMD) layer comprises silicon oxide.

[0028] In some embodiments, each metal layer of the multilayer interconnect (MLI) structure 210 further includes an etch stop layer (ESL) (e.g., below an inter-metal dielectric (IMD) layer within the metal layer), and multiple vias and / or metal lines in the metal layers may also be embedded within the etch stop layers (ESLs). In some embodiments, the inter-metal dielectric (IMD) layers are staggered by multiple etch stop layers (ESLs). The etch stop layers (ESLs) may contain a material different from that of the inter-metal dielectric (IMD) layers, such as a dielectric material different from the dielectric material of the inter-metal dielectric (IMD) layers. In some embodiments, the IMD layer comprises silicon oxide, and the ESL comprises silicon and nitrogen (e.g., silicon nitride or silicon oxynitride). In some embodiments, the dielectric constant of at least one of the multiple etch stop layers (ESLs) is greater than the dielectric constant of at least one of the multiple inter-metal dielectric (IMD) layers.

[0029] In some embodiments, a passivation structure 206 is formed over a multilayer interconnect (MLI) structure 210. The multilayer interconnect (MLI) structure 210 and the passivation structure 206 may be collectively referred to as interconnect structure 217. In some embodiments, the passivation structure 206 includes a plurality of passivation layers. These plurality of passivation layers may include protective layers (e.g., 212-1, 212-2) comprising nitrogen-containing and / or carbon-containing materials. For example, the protective layers may include silicon carbonitride (SiCN), silicon carbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), or combinations thereof. In various examples, the protective layers may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. In some embodiments, the protective layers may protect the top metal lines in the multilayer interconnect (MLI) structure 210 from oxidation.

[0030] Multiple passivation layers may also include a plasma-enhanced oxide (PEOX) layer (e.g., 214-1, 214-2) formed over the protective layer. In some embodiments, the plasma-enhanced oxide (PEOX) layer may comprise silicon oxide or a silicon oxide-containing material. In some cases, the plasma-enhanced oxide (PEOX) layer may comprise undoped silicate glass (USG). The plasma-enhanced oxide (PEOX) layer may be deposited by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), subatmospheric pressure chemical vapor deposition (SACVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof.

[0031] In some embodiments, the plurality of passivation layers further include a polymer layer 216. The polymer layer 216 may be formed over the protective layer. In some embodiments, the polymer layer 216 is the top layer of the passivation structure 206. In some embodiments, the polymer layer 216 comprises an epoxy resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or a combination thereof. In some embodiments, the polymer layer 216 comprises PI and is referred to as a PI layer. The polymer layer 216 may be deposited over the protective layer using a suitable deposition technique, such as spin coating or vapor deposition (VDP) process.

[0032] In some embodiments, the passivation structure 206 further includes conductive pads embedded in a plurality of passivation layers. In some embodiments, the conductive pads are not located directly beneath the inductor (to be formed and described). For example, in a top view, the conductive pads are arranged outside the boundary of the magnetic layer of the inductor (to be described). The conductive pads may include a conductive material, including copper, cobalt, nickel, aluminum, tungsten, titanium, silver, or combinations thereof. In some embodiments, the conductive pads include copper and silver. The conductive pads may have any suitable shape and may be formed using any suitable method. For example, openings may be formed in the plurality of passivation layers using patterning and etching processes (e.g., dry etching processes, wet etching processes, or combinations thereof), and conductive material may be deposited into the openings using a suitable deposition technique (e.g., ALD, PVD, or CVD). In the illustrated embodiment, a chemical mechanical polishing (CMP) process may be performed to remove excess material. The conductive pads may be exposed or covered by at least one of the plurality of passivation layers.

[0033] Still referencing Figures 1 to 2 Method 100 includes block 104, wherein a first isolation layer 218 is deposited over a passivation structure 206, and a first magnetic layer 220 is deposited over the first isolation layer 218.

[0034] The first isolation layer 218 may have a multilayer structure and, as shown, may include one or more dielectric layers. In some embodiments, one or more dielectric layers of the first isolation layer 218 may include an etch stop layer (ESL). The etch stop layer (ESL) may be made of or include tantalum oxide, zirconium oxide, tantalum nitride, titanium, one or more other suitable materials, or combinations thereof. In some embodiments, the etch stop layer (ESL) may include the topmost layer of the first isolation layer 218. In some embodiments, one or more dielectric layers of the first isolation layer 218 may include polyimide, silicon nitride (SiN), silicon carbide (SiC), alumina (Al2O3), silicon oxide (e.g., SiO2), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass (such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. In one embodiment, one or more dielectric layers of the first isolation layer 218 may include silicon oxide. One or more dielectric layers of the first isolation layer 218 may be sequentially deposited over the passivated structure 206 using any suitable method (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), flowable CVD (FCVD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ambient pressure CVD (APCVD), plasma-enhanced ALD (PEALD), other applicable methods, or combinations thereof). In some embodiments, the first isolation layer 218 is deposited by CVD.

[0035] Still referencing Figures 1 to 2A first magnetic layer 220 is deposited over a first insulating layer 218. The first magnetic layer 220 extends horizontally along the top surface of the first insulating layer 218. The first magnetic layer 220 may include a multilayer structure. In some embodiments, the first magnetic layer 220 includes a stacked film. The first magnetic layer 220 may include one or more sublayers. In some embodiments, the first magnetic layer 220 includes one or more magnetic materials, such as cobalt (Co), iron (Fe), boron (B), another magnetic material, or a combination thereof. In some embodiments, the first magnetic layer 220 includes a cobalt alloy (e.g., cobalt-zirconium-tantalum (CoZrTa, also known as CZT), CoZr, and / or the like), an iron alloy, a nickel alloy (e.g., nickel-iron (NiFe), and / or the like), or a combination thereof. In some embodiments, the first magnetic layer 220 includes cobalt, zirconium, tantalum, iron, nickel, or a combination thereof. In some embodiments, the first magnetic layer 220 includes CoZrTa. The first magnetic layer 220 may be deposited by any suitable method, such as a PVD process, a CVD process, an ALD process, one or more other suitable processes, or a combination thereof.

[0036] refer to Figure 1 and Figure 3Method 100 includes block 106, in which a first magnetic layer 220 is patterned. A patterned mask layer (not explicitly shown) may be formed over the first magnetic layer 220 to assist subsequent patterning processes of the first magnetic layer 220. In some embodiments, patterning at block 106 includes a combination of photolithography and etching steps. For example, at least one hard mask is deposited over the first magnetic layer 220 using chemical vapor deposition (CVD), flowable CVD (FCVD), or a suitable process. A photoresist layer is then deposited over the at least one hard mask layer using spin coating. The deposited photoresist layer may undergo a pre-exposure baking process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure baking process, and a development process to form a patterned photoresist. The at least one hard mask layer is then etched using the patterned photoresist as an etch mask to form a patterned hard mask. The patterned hard mask is then applied as an etch mask to etch the first magnetic layer 220. In some embodiments, in a top view, the patterned first magnetic layer 220 may have a square shape, a rectangular shape, or another suitable shape. In some embodiments, etching the first magnetic layer 220 includes a wet etching process. The etchant used in the wet etching process may include nitric acid, hydrochloric acid, hydrofluoric acid, one or more other suitable etchants, or combinations thereof. For example, a mixture of nitric acid, hydrochloric acid, and hydrofluoric acid may be used in a wet etching process. The first isolation layer 218 may be included in and / or used as an etch stop layer in this etching process, and protects the underlying component (e.g., passivation structure 206) from damage during the wet etching process used to pattern the first magnetic layer 220. In some embodiments, the etch stop layer may be removed from a portion of the first isolation layer 218 located laterally outside the patterned first magnetic layer 220. After the etching process, the sidewalls of the first magnetic layer 220 may be vertical or inclined. In some embodiments, the first magnetic layer 220 has, in a cross-sectional view, as shown... Figure 3 The trapezoidal shape is shown. In some embodiments, the lower layer of one or more sublayers in the first magnetic layer 220 is wider than the upper layer of the one or more sublayers in the X direction. For example, the width of one or more sublayers in the X direction gradually decreases from bottom to top.

[0037] In some embodiments, structure 200 includes a lower conductive member 219 in circuit structure 204, the lower conductive member 219 extending longitudinally along the Y direction. The lower conductive member 219 may be located directly beneath a patterned first magnetic layer 220. The lower conductive member 219 may be a portion of a metal line in a multilayer interconnect (MLI) structure 210. In some embodiments, the lower conductive member 219 is located in the highest metal layer of the multilayer interconnect (MLI) structure 210. In other embodiments, structure 200 does not include the lower conductive member 219. Although not shown in all of the following figures, it should be understood that circuit structure 204 may include the lower conductive member 219.

[0038] refer to Figure 1 and Figure 4 Method 100 includes block 108, wherein a patterned first magnetic layer 220 and / or a patterned mask layer are used as a mask-patterned first isolation layer 218. A suitable etching process at block 108 may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process at block 108 may be a dry etching process (e.g., reactive ion etching (RIE) process), which includes the use of an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). The polymer layer 216 may act as an etch stop layer in the etching process and protect the underlying structure of the passivation structure 206 from damage during the etching process.

[0039] refer to Figure 1 and Figure 5 Method 100 includes block 110, wherein a second isolation layer 222 is formed over a first magnetic layer 220, a first isolation layer 218, and a passivation structure 206. The second isolation layer 222 may comprise a suitable dielectric material, such as polyimide, silicon nitride (SiN), silicon carbide (SiC), alumina (Al2O3), silicon oxide (e.g., SiO2), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass (such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. In some embodiments, the second isolation layer 222 comprises polyimide. The second isolation layer 222 may be deposited using suitable methods such as those described in the deposition of the first isolation layer 218. The second isolation layer 222 on the sidewall of the first magnetic layer 220 and the second isolation layer 218 may be thicker than the second isolation layer 222 on the top surface of the first magnetic layer 220 and the passivation structure 206.

[0040] refer to Figure 1 and Figure 6Method 100 includes block 112, wherein conductive lines 224 are formed over a second isolation layer 222. Conductive lines 224 may also be referred to as post-passivated interconnects (PPIs) 224. In some embodiments, two conductive lines 224 are formed. The two conductive lines 224 may correspond to the input terminal (e.g., Vin) and the output terminal (e.g., Vout) of an inductor. In some embodiments, conductive lines 224 comprise copper (Cu), cobalt, nickel, aluminum, tungsten, titanium, or combinations thereof. In some embodiments, conductive lines 224 comprise copper. Conductive lines 224 can be formed using any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, stripping, seed etching, sputtering, evaporation, electroplating, printing, or combinations thereof.

[0041] The height H1 of the conductive wire 224 along the Z direction can be from approximately 20 µm to approximately 100 µm. The height H1 can be adjusted to meet design parameters (e.g., the resistance and modulus of the conductive wire 224). If H1 is too small, the resistance of the conductive wire 224 may be too high, which could increase energy waste during operation of the structure 200. If H1 is too large, it may unnecessarily increase the material and associated costs of the conductive wire 224. In some embodiments, the width W1 of the conductive wire 224 along the X direction is from approximately 20 µm to approximately 100 µm. If W1 is too small, the conductive wire 224 may lack the ability to maintain stress. If W1 is too large, it may unnecessarily increase the footprint and associated costs of the conductive wire 224.

[0042] refer to Figure 1 and Figure 7 Method 100 includes block 114, wherein a third isolation layer 226 is formed over conductive lines 224 and a second isolation layer 222. The third isolation layer 226 fills the space between the conductive lines 224. In some embodiments, the third isolation layer 226 is disposed on the top surface and sidewalls of the conductive lines 224 such that the conductive lines 224 are embedded in the third isolation layer 226. In some embodiments, as shown, the top surface of the third isolation layer 226 has a hilly profile with grooves (e.g., grooves located in the middle of the profile). The third isolation layer 226 isolates the conductive lines 224 from the second magnetic layer (to be described) and provides support for the second magnetic layer. In some embodiments, the third isolation layer 226 comprises one or more insulating and / or dielectric materials, such as silicon nitride (SiN), silicon dioxide (SiO), polymers (e.g., epoxy resin, PI, BCB, PBO), and / or combinations thereof. In some embodiments, the third isolation layer 226 comprises PI. The third isolation layer 226 can be deposited using any suitable method, such as the method described in depositing the first isolation layer 218.

[0043] refer to Figure 1 and Figure 8Method 100 includes block 116, wherein a fourth isolation layer 228 is deposited over a third isolation layer 226 and a second isolation layer 222. The fourth isolation layer 228 may include a dielectric material and may have a multilayer structure. In the illustrated embodiment, the fourth isolation layer 228 includes a first sublayer 228-1 and a second sublayer 228-2 located above the first sublayer 228-1. In some embodiments, the first sublayer 228-1 includes silicon nitride. The second sublayer 228-2 may be an etch stop layer (ESL) and may include a material similar to the ESL in the first isolation layer 218 described above. The fourth isolation layer 228 may be deposited over the third isolation layer 226 and the second isolation layer 222. The fourth isolation layer 228 may follow the contour of the third isolation layer 226 and the exposed surface of the second isolation layer 222, and thus may have a stepped profile. In various examples, any suitable method (e.g., the method described in the deposition of the first isolation layer 218) may be used to deposit the fourth isolation layer 228.

[0044] Still referencing Figure 1 and Figure 8 Method 100 includes frame 118, wherein a second magnetic layer 230 is deposited over a fourth insulating layer 228. The second magnetic layer 230 may include a multilayer structure. In some embodiments, the second magnetic layer 230 includes a stacked film. In some embodiments, the second magnetic layer 230 may follow the contour of the fourth insulating layer 228 and have a hilly shape with grooves 230g. The bottom surface of the second magnetic layer 230 over the first magnetic layer 220 is separated from the first magnetic layer 220 by the second insulating layer 222 and the fourth insulating layer 228. In some embodiments, the second magnetic layer 230 includes one or more magnetic materials, such as those of the first magnetic layer 220 described above. In some embodiments, the second magnetic layer 230 includes CoZrTa. In some embodiments, the fourth insulating layer 228 extends laterally beyond the relatively outermost edge of the second magnetic layer 230.

[0045] refer to Figure 1 as well as Figures 9 to 10 Method 100 includes a frame 120, wherein a second magnetic layer 230 is patterned. Figure 10 A partial top view of structure 200 is shown. Figure 9 It is along Figure 10 A partial cross-sectional view of structure 200 taken by line A-A' in the diagram. The second magnetic layer 230 can be patterned using a method similar to that used at box 106. The fourth isolation layer 228 can act as an etch stop layer in the etching process. In some embodiments, after patterning, the width W2 of the first magnetic layer 220 along the X direction is greater than the width W3 of the second magnetic layer 230 along the X direction. For example, the sidewalls of the first magnetic layer 220 extend laterally beyond the outer sidewalls of the second magnetic layer 230. In some embodiments, after patterning, as... Figure 9As shown, the second magnetic layer 230 does not include a horizontal portion extending longitudinally along the top surface of the fourth insulating layer 228. In some other embodiments, the second magnetic layer 230 includes this horizontal portion, and the first magnetic layer 220 extends laterally beyond this horizontal portion.

[0046] refer to Figure 10 In some embodiments, the first magnetic layer 220 and the second magnetic layer 230 each have a rectangular berth area. In some embodiments, along the Y direction, the width W4 of the first magnetic layer 220 is greater than the width W5 of the second magnetic layer 230. In some embodiments, in a top view, the end of the conductive line 224 is located outside the boundary of the first magnetic layer 220. This end may be electrically connected to the conductive pad 234. As previously mentioned, the conductive pad 234 may be arranged outside the boundary of the first magnetic layer 220 and embedded in the passivation structure 206.

[0047] refer to Figure 1 and Figure 9 Method 100 includes block 122, in which a fourth isolation layer 228 is patterned. In some embodiments, the patterning at block 122 includes a combination of photolithography and etching steps. Etching may include a dry etching process, a wet etching process, or a combination thereof, similar to the etching at block 108. The second isolation layer 222 may be used as an etch stop layer.

[0048] After patterning, the first magnetic layer 220, the conductive line 224, the second magnetic layer 230, the first isolation layer 218, the third isolation layer 226, the fourth isolation layer 228, and a portion of the second isolation layer 222 below the fourth isolation layer 228 together form an inductor 232 or an inductor structure 232.

[0049] Still referencing Figure 1 and Figure 9 Method 100 includes frame 124, wherein a fifth insulating layer 236 is formed over an exposed surface of structure 200 (e.g., the second magnetic layer 230). The fifth insulating layer 236 may include a dielectric material, such as silicon nitride (SiN), silicon dioxide (SiO), a polymer (e.g., epoxy resin, PI, BCB, PBO), and / or combinations thereof. In some embodiments, the fifth insulating layer 236 includes PI. The fifth insulating layer 236 may isolate and protect underlying components from environmental factors (e.g., moisture).

[0050] Figure 11 An example diagram of the magnetic field inside and around structure 200 during operation of structure 200 is shown. Figure 11This can be derived from measurement and / or simulation. During operation, a magnetic field may be present (e.g., generated) within and around structure 200. By providing the first magnetic layer 220 and the second magnetic layer 230 disclosed herein, a reverse magnetic field can be generated, and most of the magnetic field leaking from inductor 232 is located in the space above inductor 232, thereby reducing EMI effects between the inductor and components below the first magnetic layer 220. The lower conductive component 219 can further reduce EMI effects between the inductor and components below the lower conductive component 219. Therefore, EMI between inductor 232 and devices and components located below inductor 232 in circuit structure 204 can be reduced. The reduced EMI effects can lower the resistance of inductor 232 (e.g., by a reduction of about 5% to about 15%, a reduction of about 10%, a reduction of about 10.7%, or other similar values) and increase the inductance of inductor 232 (e.g., by an increase of about 1% to about 5%, an increase of about 3%, an increase of about 2.6%, or other similar values).

[0051] On average, the magnetic field inside inductor 232 can be larger (or stronger) than the magnetic field outside inductor 232. In some embodiments, the average magnetic field inside inductor 232 is stronger than the magnetic field above inductor 232 (e.g., at recess 230g). The magnetic field above inductor 232 can be stronger than the magnetic field below inductor 232 (e.g., in circuit structure 204). In some embodiments, the magnetic field of inductor 232 leaks from the opening S1 between the edge 230e of the second magnetic layer 230 and the edge 220e of the first magnetic layer 220, and enters the space near the edge (e.g., in region B shown in the figure). Most of region B is located above rather than below the opening S1. This may be because the first magnetic layer 220 is wider than the second magnetic layer 230, thus providing the opposite magnetic field distribution. In some embodiments, the magnetic field above edge 230e is stronger than the magnetic field below edge 220e. For example, point C is located at a distance H2 above the bottom surface of edge 230e, while point D is located at the same distance H2 below the top surface of edge 220e. In the illustrated embodiment, the first magnetic field at point C is stronger than the second magnetic field at point D. The first and second magnetic fields are less than or weaker than the third magnetic field at point E between edges 230e and 220e. The fourth magnetic field in region F below the lower conductive member 219 is weaker than the second magnetic field at point D.

[0052] refer to Figure 12 A schematic partial cross-sectional view of structure 200 is shown. The combined structure 205 includes a circuit structure 204 and a passivation structure 206. In some embodiments, edge 230e and edge 220e have a horizontal distance D1 of approximately 20 μm to approximately 100 μm. D1 is independent of... Figure 9 and Figure 10The width W2 or W3 in the first magnetic layer. If D1 is too small, it may not be able to reduce or adequately reduce EMI effects. If D1 is too large, it may unnecessarily increase the material and related costs of the first magnetic layer 220.

[0053] refer to Figure 13 A schematic partial cross-sectional view of structure 300 is shown. Structure 300 can be manufactured by method 100. Structure 300 includes a substrate 202, a combined structure 205 above the substrate 202, and two inductors 238 similar to the inductor 232 described above. A second isolation layer 222 extends continuously from one inductor 238 to the other inductor 238. In some embodiments, the distance between the first magnetic layers 220 of the two inductors 238 is D2, as shown. D2 can be in the range of about 20 μm to about 1000 μm. D2 is independent of width W2 or width W3. If D2 is too small, the EMI effect between the two inductors 238 may be too large. If D2 is too large, the footprint of structure 300 may be too large, and the associated cost and time may be excessive. Structure 300 may include a lower conductive member 219 as described above in the combined structure 205 and located directly below the two inductors 238.

[0054] refer to Figure 14 A schematic partial cross-sectional view of structure 400 is shown. Structure 400 may be manufactured by method 100. Structure 400 includes a substrate 202, a combined structure 205 above the substrate 202, and two inductors 240. The differences from structure 300 include the following. In some embodiments, the two inductors 240 share a first isolation layer 218', a first magnetic layer 220', a second isolation layer 222', and a fourth isolation layer 228', compared to inductor 238. The first isolation layer 218', the first magnetic layer 220', the second isolation layer 222', and the fourth isolation layer 228' each extend continuously from one inductor 240 to the other. The first isolation layer 218', the first magnetic layer 220', the second isolation layer 222', and the fourth isolation layer 228' may each have a similar composition to the first isolation layer 218, the first magnetic layer 220, the second isolation layer 222', and the fourth isolation layer 228' described above, and may be manufactured using similar methods. The distance D3 between the second magnetic layers 230 of the two inductors 240 is in the range of about 20 μm to about 100 μm. D3 is independent of the width W2 or the width W3. If D3 is too small, the EMI effect between the two inductors 240 may be too large. If D3 is too large, the material and related costs of the first magnetic layer 220' may be excessive. Structure 400 may include a lower conductive member 219 as described above, located in the combined structure 205 and directly below the two inductors 240.

[0055] Although the aforementioned inductor is arranged above the combined structure 205 or the passivation structure 206, the inductor can be applied above other semiconductor structures.

[0056] While not intended to be limiting, one or more embodiments of this disclosure offer numerous advantages for semiconductor structures. For example, this disclosure provides semiconductor structures with less EMI effects, reduced inductor resistance, and increased inductance. For instance, by making the first magnetic layer wider than the second magnetic layer and / or the underlying conductive component, opposite magnetic field distributions can be generated, thereby reducing EMI effects between the inductor and the underlying component (e.g., the underlying conductive component, device). Therefore, the overall performance of the semiconductor structure can be improved.

[0057] In one exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a multilayer interconnect (MLI) structure above the substrate, a passivation layer above the MLI structure, a first magnetic layer above the passivation layer, a first dielectric layer above the first magnetic layer and the passivation layer, and conductive lines on the first dielectric layer, the conductive lines being located above the first magnetic layer and extending longitudinally along a first direction. The semiconductor structure includes a second dielectric layer surrounding and above the conductive lines, and a second magnetic layer surrounding and above the second dielectric layer. The first magnetic layer extends a first width along a second direction different from the first direction, and the second magnetic layer extends a second width along the second direction that is smaller than the first width.

[0058] In some embodiments, at the edge of the first magnetic layer, a first magnetic field above the first magnetic layer is greater than a second magnetic field below the first magnetic layer. In some embodiments, the multilayer interconnect (MLI) structure includes a plurality of intermetallic dielectric (IMD) layers interleaved with a plurality of etch stop layers (ESLs), wherein the dielectric constant of at least one of the plurality of etch stop layers (ESLs) is greater than the dielectric constant of at least one of the plurality of intermetallic dielectric (IMD) layers, and the semiconductor structure also includes a plurality of conductive components in the multilayer interconnect (MLI) structure. In some embodiments, the sidewall of the first magnetic layer extends beyond the outer sidewall of the second magnetic layer by a distance of about 20 µm to about 100 µm. In some embodiments, the conductive line is a first conductive line, and the semiconductor structure also includes a third magnetic layer above the passivation layer, a third dielectric layer above the third magnetic layer, a second conductive line on the third dielectric layer, the second conductive line being located above the third magnetic layer and extending longitudinally along a first direction, and the semiconductor structure also includes a fourth dielectric layer surrounding and above the second conductive line, and a fourth magnetic layer surrounding and above the fourth dielectric layer. The distance between the first magnetic layer and the third magnetic layer is from about 20 µm to about 1,000 µm. In some embodiments, the sidewall of the third magnetic layer extends beyond the outer sidewall of the fourth magnetic layer by about 20 µm to about 100 µm. In some embodiments, the conductive line is a first conductive line, and the semiconductor structure further includes a second conductive line on the first dielectric layer, the second conductive line being located above the first magnetic layer and extending longitudinally along a first direction. The semiconductor structure also includes a third dielectric layer surrounding and above the second conductive line, and a third magnetic layer surrounding and above the third dielectric layer. The third magnetic layer is spaced from the second magnetic layer by about 20 µm to about 100 µm. In some embodiments, the semiconductor structure further includes a fourth dielectric layer disposed between the second dielectric layer and the second magnetic layer, and between the third dielectric layer and the third magnetic layer.

[0059] In another exemplary aspect, this disclosure relates to a method. The method includes forming a first magnetic layer over a first dielectric layer, depositing a second dielectric layer over the first magnetic layer and the first dielectric layer, forming a first conductive component and a second conductive component over the second dielectric layer and the first magnetic layer, forming a third dielectric layer around and over the first and second conductive components, and forming a second magnetic layer over the third dielectric layer. In a top view, the first magnetic layer extends beyond the boundary of the second magnetic layer.

[0060] In some embodiments, the method further includes forming a fourth dielectric layer over the second magnetic layer and the second dielectric layer. In some embodiments, before forming the second magnetic layer and after forming the third dielectric layer, the method further includes forming a fourth dielectric layer over the second and third dielectric layers. The second magnetic layer is formed over the fourth dielectric layer, and in a top view, the fourth dielectric layer extends beyond the boundary of the first magnetic layer. In some embodiments, the method further includes forming a plurality of metal lines in the first dielectric layer, wherein at least a portion of the metal lines is located directly below the first magnetic layer. In some embodiments, in a top view, the first conductive member and the second conductive member include ends located outside the boundary of the first magnetic layer, the ends being connected to conductive pads in the first dielectric layer. In some embodiments, in a top view, the second magnetic layer is located within the boundary of the first magnetic layer. In some embodiments, the method further includes forming a third conductive member and a fourth conductive member over the second dielectric layer and the first magnetic layer, forming a fourth dielectric layer around and over the third and fourth conductive members, and forming a third magnetic layer over the fourth dielectric layer. In a top view, the first magnetic layer extends beyond the boundary of the third magnetic layer, and the third magnetic layer is spaced apart from the second magnetic layer. In some embodiments, the method further includes forming a third magnetic layer over a first dielectric layer, with a second dielectric layer also deposited over the third magnetic layer, and further includes forming a third conductive component and a fourth conductive component over the second dielectric layer and the third magnetic layer, forming a fourth dielectric layer around and over the third and fourth conductive components, and forming a fourth magnetic layer over the fourth dielectric layer. In a top view, the third magnetic layer extends beyond the boundary of the fourth magnetic layer, and the third magnetic layer is spaced apart from the first magnetic layer.

[0061] In another exemplary aspect, this disclosure relates to a method. The method includes providing a structure including a device layer and an interconnect structure above the device layer, forming a first magnetic layer above the interconnect structure, forming a first dielectric layer above the first magnetic layer and the interconnect structure, forming conductive lines above the first dielectric layer and the first magnetic layer, forming a second dielectric layer above the conductive lines to fill the spaces between the conductive lines, depositing a second magnetic layer above the second dielectric layer, and patterning the second magnetic layer. After patterning the second magnetic layer, the edge of the second magnetic layer is located above the first magnetic layer. The interconnect structure includes a plurality of intermetallic dielectric layers interleaved by a plurality of etch stop layers, at least one of the plurality of etch stop layers having a dielectric constant greater than that of at least one of the plurality of intermetallic dielectric layers.

[0062] In some embodiments, before forming the first magnetic layer, the method further includes forming a third dielectric layer over an interconnect structure, with the first magnetic layer formed over the third dielectric layer. In some embodiments, after patterning the second magnetic layer, the method further includes forming a third dielectric layer over the second magnetic layer and the first dielectric layer. In some embodiments, the method further includes forming a third dielectric layer over the second dielectric layer before depositing the second magnetic layer, and patterning the third dielectric layer after patterning the second magnetic layer.

[0063] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: Substrate; A multilayer interconnect structure is located above the substrate; A passivation layer is placed above the multilayer interconnect structure; A first magnetic layer is located above the passivation layer; A first dielectric layer is located above the first magnetic layer and the passivation layer; A conductive line, the conductive line being on the first dielectric layer, the conductive line being above the first magnetic layer and extending longitudinally along a first direction; A second dielectric layer surrounds and is above the conductive line; as well as A second magnetic layer surrounds the second dielectric layer and is located above the second dielectric layer. The first magnetic layer extends a first width along a second direction different from the first direction. The second magnetic layer extends along the second direction with a second width smaller than the first width.

2. The semiconductor structure according to claim 1, wherein at the edge of the first magnetic layer, the first magnetic field above the first magnetic layer is greater than the second magnetic field below the first magnetic layer.

3. The semiconductor structure according to claim 1, wherein the multilayer interconnect structure comprises a plurality of intermetallic dielectric layers interleaved by a plurality of etch stop layers. The dielectric constant of at least one of the plurality of etch stop layers is greater than the dielectric constant of at least one of the plurality of inter-metal dielectric layers. The semiconductor structure further includes multiple conductive components in the multilayer interconnect structure.

4. The semiconductor structure of claim 1, wherein the sidewall of the first magnetic layer extends beyond the outer sidewall of the second magnetic layer by a distance of about 20 µm to about 100 µm.

5. The semiconductor structure according to claim 1, wherein the conductive line is a first conductive line; The semiconductor structure further includes: A third magnetic layer is located above the passivation layer; A third dielectric layer is located above the third magnetic layer; The second conductive line is on the third dielectric layer and extends longitudinally along the first direction above the third magnetic layer. A fourth dielectric layer surrounds the second conductive line and is located above the second conductive line; and A fourth magnetic layer, surrounding and above the fourth dielectric layer; and The distance between the first magnetic layer and the third magnetic layer is approximately 20 µm to approximately 1000 µm.

6. The semiconductor structure of claim 5, wherein the sidewall of the third magnetic layer extends beyond the outer sidewall of the fourth magnetic layer by a distance of about 20 µm to about 100 µm.

7. The semiconductor structure according to claim 1, wherein the conductive line is a first conductive line; The semiconductor structure further includes: The second conductive line is located on the first dielectric layer and is located above the first magnetic layer and extends longitudinally along the first direction. A third dielectric layer surrounds and is located above the second conductive line; and A third magnetic layer surrounds the third dielectric layer and is located above the third dielectric layer; and The third magnetic layer is spaced from the second magnetic layer by a distance of approximately 20 µm to approximately 100 µm.

8. The semiconductor structure of claim 7 further includes a fourth dielectric layer disposed between the second dielectric layer and the second magnetic layer, and disposed between the third dielectric layer and the third magnetic layer.

9. A method for manufacturing a semiconductor structure, comprising: A first magnetic layer is formed above the first dielectric layer; A second dielectric layer is deposited over the first magnetic layer and the first dielectric layer; A first conductive component and a second conductive component are formed above the second dielectric layer and the first magnetic layer; A third dielectric layer is formed around and above the first conductive component and the second conductive component; and A second magnetic layer is formed above the third dielectric layer. In the top view, the first magnetic layer extends beyond the boundary of the second magnetic layer.

10. A method for manufacturing a semiconductor structure, comprising: A structure including a device layer and an interconnect structure located above the device layer is provided; A first magnetic layer is formed above the interconnect structure; A first dielectric layer is formed above the first magnetic layer and the interconnect structure; Conductive lines are formed above the first dielectric layer and above the first magnetic layer; A second dielectric layer is formed above the conductive lines to fill the space between the conductive lines; A second magnetic layer is deposited above the second dielectric layer; as well as Pattern the second magnetic layer, After the second magnetic layer is patterned, the edge of the second magnetic layer lies above the first magnetic layer. The interconnect structure includes multiple intermetallic dielectric layers interleaved with multiple etch stop layers, and The dielectric constant of at least one of the plurality of etch stop layers is greater than the dielectric constant of at least one of the plurality of intermetallic dielectric layers.

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