Pairs of capacitors and methods of making the same

Abstract

A pair of capacitors and a manufacturing method thereof are disclosed. The capacitor structure includes a substrate, a left region, a middle region and a right region defined on the substrate, the middle region is between the left region and the right region, a first capacitor structure includes a first lower electrode pattern and a first upper electrode pattern, the first lower electrode pattern and the first upper electrode pattern are in different regions and different layers in a vertical direction, and a second capacitor structure includes a second lower electrode pattern and a second upper electrode pattern, the second lower electrode pattern and the second upper electrode pattern are in different regions and different layers in the vertical direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a paired capacitor with an alternating layered pattern composed of MOM capacitors, which can reduce the problem of inconsistent capacitance values ​​on both sides due to manufacturing process errors. Background Technology

[0002] In integrated circuit design, capacitor structures play an indispensable role. Among them, MOM (Metal-Oxide-Metal) capacitors and MIM (Metal-Insulator-Metal) capacitors are two common capacitor structures. Although both are composed of metal and insulating layers, they differ significantly in structure, manufacturing process, and performance. These differences directly influence their selection in different application scenarios.

[0003] MOM capacitors primarily utilize the oxide layer between the same or adjacent metal layers as the dielectric, forming an interdigital electrode structure. The advantage of this structure lies in its simple fabrication process, eliminating the need for additional mask layers and fully utilizing existing metal interconnect layers. However, due to the relatively low dielectric constant of the oxide layer and its large parasitic capacitance, MOM capacitors typically have small capacitance values ​​and relatively limited frequency characteristics. Nevertheless, MOM capacitors remain widely used in digital circuits as coupling capacitors, bypass capacitors, and so on.

[0004] MIM capacitors use different layers of metal with a high-dielectric-constant insulating layer sandwiched in between. The advantages of this structure are a large capacitance, excellent frequency response, and relatively stable capacitance. However, the manufacturing process of MIM capacitors is relatively complex, requiring additional mask layers and fabrication steps. Furthermore, the high-dielectric-constant insulating layer may introduce significant leakage current, affecting the capacitor's performance. MIM capacitors are typically used in analog circuits, radio frequency circuits, and other applications where high capacitance accuracy is required. Summary of the Invention

[0005] The present invention provides a capacitor structure comprising a substrate on which a left region, a middle region, and a right region are defined, wherein the middle region is located between the left region and the right region; a first capacitor structure comprising a first lower electrode pattern and a first upper electrode pattern, wherein the first lower electrode pattern and the first upper electrode pattern are located within different regions and in different layers in a vertical direction; and a second capacitor structure comprising a second lower electrode pattern and a second upper electrode pattern, wherein the second lower electrode pattern and the second upper electrode pattern are located within different regions and in different layers in the vertical direction.

[0006] The present invention also provides a method for manufacturing a capacitor structure, comprising providing a substrate, defining a left region, a middle region and a right region on the substrate, wherein the middle region is located between the left region and the right region, forming a first capacitor structure including a first lower electrode pattern and a first upper electrode pattern, wherein the first lower electrode pattern and the first upper electrode pattern are located in different regions and in different layers in a vertical direction, and forming a second capacitor structure including a second lower electrode pattern and a second upper electrode pattern, wherein the second lower electrode pattern and the second upper electrode pattern are located in different regions and in different layers in the vertical direction.

[0007] The present invention is characterized by providing a paired capacitor and a method for manufacturing the same. The paired capacitor comprises two capacitor structures, each containing multiple layers of MOM electrode patterns. Along a vertical direction, the MOM electrode patterns of the two capacitor structures are alternately stacked in different regions, and the MOM electrode patterns are connected to each other via contact plugs. Therefore, the capacitance difference between electrode patterns in different regions can be effectively reduced, improving the quality of the paired capacitor. Attached Figure Description

[0008] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0009] Figure 1 This is a top view schematic diagram of the two electrode patterns of the paired capacitor according to the first embodiment of the present invention;

[0010] Figure 2 This is a three-dimensional schematic diagram of paired capacitors according to the second embodiment of the present invention;

[0011] Figure 3 This is a top view schematic diagram of the lower electrode pattern of the paired capacitors according to the third embodiment of the present invention;

[0012] Figure 4 This is a top view schematic diagram of the upper electrode pattern of the paired capacitors according to the third embodiment of the present invention;

[0013] Figure 5 This is a three-dimensional schematic diagram of paired capacitors according to the third embodiment of the present invention;

[0014] Figure 6 This is a three-dimensional schematic diagram of paired capacitors according to the fourth embodiment of the present invention.

[0015] Symbol Explanation

[0016] 1: Paired capacitors

[0017] 2: Paired capacitors

[0018] 3: Paired capacitors

[0019] 4: Paired capacitors

[0020] 10: Left capacitor structure

[0021] 11: First electrode pattern

[0022] 11A: Spindle electrode

[0023] 11B: Spindle electrode

[0024] 11C: Branch electrode

[0025] 11D: Branch electrode

[0026] 12: Second electrode pattern

[0027] 12A: Spindle electrode

[0028] 12B: Spindle electrode

[0029] 12C: Branch electrode

[0030] 12D: Branch electrode

[0031] 20: Right capacitor structure

[0032] 31: First lower layer electrode pattern

[0033] 31A: Spindle electrode

[0034] 31B: Spindle electrode

[0035] 31C: Branch electrode

[0036] 31D: Branch electrode

[0037] 31E: Connecting electrode

[0038] 32: Second lower layer electrode pattern

[0039] 32A: Spindle electrode

[0040] 32B: Spindle electrode

[0041] 32C: Branch electrode

[0042] 32D: Branch electrode

[0043] 32E: Connecting electrode

[0044] 41: First upper electrode pattern

[0045] 41': First middle layer electrode pattern

[0046] 41A: Spindle electrode

[0047] 41B: Spindle electrode

[0048] 41C: Branch electrode

[0049] 41D: Branch electrode

[0050] 41E: Connecting electrode

[0051] 42: Second upper electrode pattern

[0052] 42': Second middle layer electrode pattern

[0053] 42A: Spindle electrode

[0054] 42B: Spindle electrode

[0055] 42C: Branch electrode

[0056] 42D: Branch electrode

[0057] 42E: Connecting electrode

[0058] C1: First capacitor structure

[0059] C2: Second capacitor structure

[0060] LR: Left region

[0061] MR: Central Region

[0062] RR: Right region

[0063] S: Substrate

[0064] V: Contact plug

[0065] V1: Contact plug

[0066] V2: Contact plug

[0067] V3: Contact plug

[0068] V4: Contact plug Detailed Implementation

[0069] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0070] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0071] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a complex combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0072] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0073] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0074] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0075] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0076] As described in existing technology, capacitor structures are widely used in integrated circuit design. Among them, MOM (Metal-Oxide-Metal) capacitors are frequently used as the primary capacitor structure in smaller electronic components because they can be fabricated together with the conductive layers of the electronic component. Additionally, a paired capacitor is a circuit element containing two capacitor structures. Ideally, the two capacitor structures in a paired capacitor have the same capacitance value, and therefore, the output signal magnitudes of the two capacitor structures are also the same. Paired capacitors can be used in various electronic products, such as in headphones (to ensure that the sound output from the left and right sides of the headphones is the same), or in other circuits, such as differential circuits, filtering circuits, and coupling circuits.

[0077] In order to ensure that the two capacitor structures in a pair of capacitors have the most similar capacitance values, two identical capacitor patterns are usually made to serve as the two capacitor structures in the pair of capacitors. Figure 1 A top view schematic diagram illustrating the electrode patterns of a paired capacitor according to a first embodiment of the present invention is shown. Figure 1 As shown, the paired capacitor 1 includes a first electrode pattern 11 and a second electrode pattern 12. The first electrode pattern 11 is located on the left side of the figure, and the second electrode pattern 12 is located on the right side of the figure. The first electrode pattern 11 and the second electrode pattern 12, together with the surrounding dielectric layer (not shown), can each form a capacitor structure. That is, the paired capacitor 1 is composed of one capacitor structure on each side. In some embodiments of the present invention, the first electrode pattern 11 and the second electrode pattern 12 are preferably the same or similar patterns. Taking this embodiment as an example, the first electrode pattern 11 includes two main axis electrodes 11A and 11B and a plurality of parallel branch electrodes 11C and 11D. The main axis electrodes 11A and 11B are arranged along a first direction (e.g., the X direction) and are respectively located on the left side of the figure. Figure 1 Near the upper and lower positions, multiple branch electrodes 11C and multiple branch electrodes 11D are arranged along a second direction (e.g., the Y direction), wherein each branch electrode 11C is connected to the main shaft electrode 11A located near the upper position, and each branch electrode 11D is connected to the main shaft electrode 11D located near the lower position. Furthermore, viewed along the X direction, the branch electrodes 11C and 11D are arranged alternately, for example, in the order of branch electrode 11C, branch electrode 11D, branch electrode 11C, branch electrode 11D… The lengths of the branch electrodes 11C and 11D in the Y direction are preferably the same. The two main shaft electrodes 11A and 11B and the branch electrodes 11C and 11D are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the first electrode pattern 11 includes two main shaft electrodes 11A and 11B and branch electrodes 11C and 11D made of conductive material, and forms an interdigital electrode pattern. The interdigitated electrode pattern is located in a dielectric layer (not shown in the figure). The interdigitated electrode pattern serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0078] Similarly, the second electrode pattern 12 has a structure similar to the first electrode pattern 11, wherein the second electrode pattern 12 includes two main axis electrodes 12A and 12B and a plurality of parallel branch electrodes 12C and 12D, wherein the main axis electrodes 12A and 12B are arranged along a first direction (e.g., the X direction) and are respectively located at Figure 1Near the upper and lower positions, multiple branch electrodes 12C and multiple branch electrodes 12D are arranged along a second direction (e.g., the Y direction), wherein each branch electrode 12C is connected to the main shaft electrode 12A located near the upper position, and each branch electrode 12D is connected to the main shaft electrode 12D located near the lower position. Furthermore, viewed along the X direction, the branch electrodes 12C and branch electrodes 12D are arranged alternately, for example, from left to right in the order of branch electrode 12C, branch electrode 12D, branch electrode 12C, branch electrode 12D… The lengths of the branch electrodes 12C and branch electrodes 12D in the Y direction are preferably the same. The two main shaft electrodes 12A and 12B and the branch electrodes 12C and 12D are all made of a highly conductive material (e.g., metal) to form an electrode pattern. Therefore, the second electrode pattern 12 includes the two main shaft electrodes 12A and 12B and the branch electrodes 12C and 12D made of conductive material, forming an interdigitated electrode pattern. The interdigitated electrode pattern is located in a dielectric layer (not shown in the figure). The interdigitated electrode pattern serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0079] The paired capacitor 1 is composed of the first electrode pattern 11 and the second electrode pattern 12 described above, and can be applied to various circuits as previously mentioned. It is worth noting that one way to increase the capacitance value of the capacitor structure is to increase the area of ​​the electrode pattern. Since the capacitance value is proportional to the area of ​​the electrode pattern, that is, the larger the area of ​​the electrode pattern, the higher the capacitance value of the capacitor structure.

[0080] However, as electronic products become increasingly miniaturized, the components are often limited by space, preventing excessive increases in area. In such cases, electrode patterns can be stacked, and different layers of electrode patterns can be electrically connected to each other to increase the overall capacitance of the capacitor structure. Figure 2 A three-dimensional schematic diagram of paired capacitors according to a second embodiment of the present invention is shown. Figure 2 As shown, the paired capacitor 2 includes a left capacitor structure 10 and a right capacitor structure 20. The left capacitor structure 10 includes multiple layers of electrode patterns stacked on top of each other. For example, the first electrode pattern 11 described above is repeatedly formed and disposed in different layers in the Z-axis direction, and the first electrode patterns 11 in each layer are electrically connected to each other by multiple contact plugs V. Similarly, the right capacitor pattern 20 also includes multiple layers of electrodes stacked on top of each other. For example, the second electrode pattern 12 described above is repeatedly formed and disposed in different layers in the Z-axis direction, and the second electrode patterns 12 in each layer are electrically connected to each other by multiple contact plugs V. In this way, the total capacitance value of the left capacitor structure 10 and the right capacitor pattern 20 is equal to the sum of the capacitance values ​​of each layer of electrodes included, thus effectively increasing the capacitance value and making it applicable to electronic products that require higher capacitance values. It is worth noting that, although Figure 2 Only two layers of first electrode pattern 11 and two layers of second electrode pattern 12 are shown in the figure. However, it is understood that the present invention can add more layers of electrode pattern according to actual needs to form a capacitor structure with a higher capacitance value, which is also within the scope of the present invention.

[0081] In the above embodiments, a pair of capacitors 2 with high capacitance values ​​are formed. Ideally, the left capacitor structure 10 and the right capacitor structure 20 should have the same capacitance value. However, in actual manufacturing processes, various errors, such as manufacturing conditions, can cause slight differences in the capacitance values ​​of the left capacitor structure 10 and the right capacitor structure 20. That is, the capacitance value of the left capacitor structure 10 is not exactly the same as the capacitance value of the right capacitor structure 20, and there is a capacitance difference between them. This situation, where the capacitance values ​​of the left capacitor structure 10 and the right capacitor structure 20 are not exactly the same, is defined as capacitance mismatch. The cause of capacitance mismatch may be errors in the manufacturing process, resulting in differences in various conditions (such as area, thickness, distance, etc.) between the first electrode pattern 11 and the second electrode pattern 12, thus causing different capacitance values ​​for the corresponding electrode patterns. For example, if, due to manufacturing process errors, the area of ​​the first electrode pattern 11 is slightly larger than the area of ​​the second electrode pattern 12, the capacitance value of the first electrode pattern 11 will be slightly larger than the capacitance value of the second electrode pattern 12. Especially when... Figure 2 As shown, when multiple layers of first electrode pattern 11 and second electrode pattern 12 are stacked to form left capacitor structure 10 and right capacitor structure 20 respectively, the difference in capacitance value between the left and right capacitor structures will gradually increase, so the above-mentioned capacitance mismatch will become more obvious.

[0082] To mitigate the aforementioned capacitor mismatch, the present invention proposes several other embodiments of paired capacitors in the following examples. Compared to the embodiments described above, the following paired capacitors have a more specialized structure and can effectively reduce the capacitor mismatch problem. Details are described in the following paragraphs.

[0083] Figure 3 A top view schematic diagram illustrating the lower electrode pattern of a paired capacitor according to a third embodiment of the present invention is shown. Figure 4 A top view schematic diagram illustrating the upper electrode pattern of a paired capacitor according to a third embodiment of the present invention is shown. Figures 3-4As shown, the paired capacitor includes a substrate S, on which a first lower electrode pattern 31, a second lower electrode pattern 32, a first upper electrode pattern 41, and a second upper electrode pattern 42 are mounted. The first lower electrode pattern 31 and the second lower electrode pattern 32 described herein have a structure similar to the first electrode pattern 11 or the second electrode pattern 12 in the first embodiment described above. More specifically, the first lower electrode pattern 31 includes two main axis electrodes 31A and 31B, a plurality of parallel branch electrodes 31C and 31D, and a connecting electrode 31E. The main axis electrodes 31A, 31B, and the connecting electrode 31E are arranged along a first direction (e.g., the X direction), while the plurality of branch electrodes 31C and 31D are arranged along a second direction (e.g., the Y direction). Each branch electrode 31C is connected to the main axis electrode 31A, and each branch electrode 31D is connected to the main axis electrode 31B. Furthermore, viewed along the X direction, the branch electrodes 31C and 31D are arranged alternately. The branch electrodes 31C and 31D preferably have the same length in the Y direction. The two main axis electrodes 31A and 31B, the branch electrodes 31C and 31D, and the connecting electrode 31E are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the first lower electrode pattern 31 includes two main axis electrodes 31A and 31B, branch electrodes 31C and 31D, and the connecting electrode 31E, all made of conductive material, forming an interdigital electrode pattern. The interdigital electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure. It is worth noting that in this embodiment, the length of the main axis electrode 31A is greater than the length of the main axis electrode 31B, and the connecting electrode 31E connects to the end of the branch electrode 31D closest to the second lower electrode pattern 32. In addition, it also includes a contact plug V1, which in this embodiment is located on the spindle electrode 31A and the connecting electrode 31E, and is used to connect the first lower electrode pattern 31 to the first upper electrode pattern 41 of other layers (which will be described in a later paragraph).

[0084] Similarly, the second lower electrode pattern 32 includes two main axis electrodes 32A and 32B, multiple parallel branch electrodes 32C and 32D, and a connecting electrode 32E. The main axis electrodes 32A, 32B, and connecting electrode 32E are arranged along a first direction (e.g., the X direction), while the multiple branch electrodes 32C and 32D are arranged along a second direction (e.g., the Y direction). Each branch electrode 32C is connected to a main axis electrode 32A, and each branch electrode 32D is connected to a main axis electrode 32B. Furthermore, viewed along the X direction, the branch electrodes 32C and 32D are arranged alternately. The lengths of the branch electrodes 32C and 32D in the Y direction are preferably the same. Here, the two main axis electrodes 32A and 32B, the branch electrodes 32C and 32D, and the connecting electrode 32E are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the first lower electrode pattern 32 includes two main axis electrodes 32A and 32B, branch electrodes 32C and 32D, and a connecting electrode 32E, all made of conductive material, forming an interdigital electrode pattern. The interdigital electrode pattern is located within a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure. It is worth noting that in this embodiment, the length of the main axis electrode 32A is greater than the length of the main axis electrode 32B, and the connecting electrode 32E connects to the end of the branch electrode 32D closest to the first lower electrode pattern 31. Furthermore, a contact plug V2 is included. In this embodiment, the contact plug V2 is located on the main axis electrode 32A and the connecting electrode 32E, and is used to connect the second lower electrode pattern 32 to the second upper electrode pattern 42 of other layers (which will be further described in a later paragraph).

[0085] It is worth noting that... Figure 3 The diagram defines a left region LR, a middle region MR, and a right region RR. The left region LR includes branch electrodes 31C and 31C of the first lower electrode pattern 31, as well as a portion of the main spindle electrode 31A and a portion of the main spindle electrode 31B. The right region RR includes branch electrodes 32C and 32C of the second lower electrode pattern 32, as well as a portion of the main spindle electrode 32A and a portion of the main spindle electrode 32B. The middle region MR includes a portion of the main spindle electrode 31A, a connecting electrode 31E, a portion of the main spindle electrode 32A, a connecting electrode 32E, and multiple contact plugs V1 and V2. It is worth noting that in this embodiment, the contact plugs V1 and V2 are located within the middle region MR, and not within the left region LR or the right region RR.

[0086] Then as Figure 4As shown, the paired capacitors also include a first upper electrode pattern 41 and a second upper electrode pattern 32. The first upper electrode pattern 41 has a structure similar to the second lower electrode pattern 32 described above, and along the Z-axis direction, both the first upper electrode pattern 41 and the second lower electrode pattern 32 are located in the right region RR, with the first upper electrode pattern 41 located above the second lower electrode pattern 32. More specifically, the first upper electrode pattern 41 includes two main shaft electrodes 41A and 41B, multiple parallel branch electrodes 41C and 41D, and a connecting electrode 41E. The main shaft electrodes 41A, 41B, and the connecting electrode 41E are arranged along a first direction (e.g., the X direction), while the multiple branch electrodes 41C and 41D are arranged along a second direction (e.g., the Y direction). Each branch electrode 41C is connected to the main shaft electrode 41A, and each branch electrode 41D is connected to the main shaft electrode 41B. Furthermore, along the X-axis, the branch electrodes 41C and 41D are arranged alternately. The branch electrodes 41C and 41D preferably have the same length in the Y direction. The two main axis electrodes 41A and 41B, the branch electrodes 41C and 41D, and the connecting electrode 41E are all made of a highly conductive material (e.g., metal) forming the electrode pattern. Therefore, the first upper electrode pattern 41 includes two main axis electrodes 41A and 41B, the branch electrodes 41C and 41D, and the connecting electrode 41E, all made of conductive material, forming an interdigital electrode pattern. The interdigital electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure. It is worth noting that in this embodiment, the length of the main axis electrode 41A is greater than the length of the main axis electrode 41B, and the connecting electrode 41E connects to the end of the branch electrode 41D closest to the second upper electrode pattern 42. In addition, it also includes a contact plug V1, which in this embodiment is located on the spindle electrode 41A and the connecting electrode 41E, and is used to connect the first upper electrode pattern 41 to the first lower electrode pattern 31.

[0087] Similarly, the second upper electrode pattern 42 has a structure similar to the first lower electrode pattern 31 described above, and along the Z-axis direction, both the second upper electrode pattern 42 and the first lower electrode pattern 32 are located in the left region LR, with the second upper electrode pattern 42 positioned above the first lower electrode pattern 32. More specifically, the second upper electrode pattern 42 includes two main shaft electrodes 42A and 42B, multiple parallel branch electrodes 42C and 42D, and a connecting electrode 42E. The main shaft electrodes 42A, 42B, and connecting electrode 42E are arranged along a first direction (e.g., the X direction), while the multiple branch electrodes 42C and 42D are arranged along a second direction (e.g., the Y direction). Each branch electrode 42C is connected to a main shaft electrode 42A, and each branch electrode 42D is connected to a main shaft electrode 42B. Furthermore, viewed along the X-axis, the branch electrodes 42C and 42D are arranged alternately. The lengths of the branch electrodes 42C and 42D in the Y-axis direction are preferably the same. The two main spindle electrodes 42A and 42B, the branch electrodes 42C and 42D, and the connecting electrode 42E are all made of a highly conductive material (e.g., metal) forming the electrode pattern. Therefore, the second upper electrode pattern 42 includes the two main spindle electrodes 42A and 42B, the branch electrodes 42C and 42D, and the connecting electrode 42E, all made of conductive material, forming an interdigital electrode pattern. The interdigital electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure. It is worth noting that in this embodiment, the length of the main spindle electrode 42A is greater than the length of the main spindle electrode 42B, and the connecting electrode 42E is connected to the end of the branch electrode 42D closest to the first upper electrode pattern 41. Furthermore, a contact plug V2 is included. In this embodiment, the contact plug V2 is located on the main spindle electrode 42A and the connecting electrode 42E, and is used to connect the second upper electrode pattern 42 to the second lower electrode pattern 32.

[0088] It is worth noting that in the above electrode pattern connection structure, although the first lower electrode pattern 31 is connected to the first upper electrode pattern 41, when viewed along the Z-axis, the first upper electrode pattern 41 is not directly above the first lower electrode pattern 31, but rather directly above the second lower electrode pattern 32. On the other hand, when viewed along the Z-axis, the second upper electrode pattern 42 is directly above the first lower electrode pattern 31. This can be referred to in conjunction with the above. Figure 5 , Figure 5 A three-dimensional schematic diagram of paired capacitors according to a third embodiment of the present invention is shown. Figure 5As shown, the paired capacitor 3 includes a first lower electrode pattern 31, a second lower electrode pattern 32, a first upper electrode pattern 41, a second upper electrode pattern 42, contact plugs V1 and V2, and a surrounding dielectric layer. The first lower electrode pattern 31 and the second upper electrode pattern 42 are both located in the left region LR, while the second lower electrode pattern 32 and the first upper electrode pattern 41 are both located in the right region RR. Furthermore, the first lower electrode pattern 31 and the first upper electrode pattern 41 are electrically connected to each other through contact plug V1 in the middle region MR, and the second lower electrode pattern 32 and the second upper electrode pattern 42 are electrically connected to each other through contact plug V2 in the middle region MR. In other words, the paired capacitor 3 comprises two capacitor structures, defined as a first capacitor structure C1 and a second capacitor structure C2. The first capacitor structure C1 comprises a first lower electrode pattern 31, a first upper electrode pattern 41, and a surrounding dielectric layer. The second capacitor structure C2 comprises a second lower electrode pattern 32, a second upper electrode pattern 42, and a surrounding dielectric layer. The first lower electrode pattern 31 of the first capacitor structure C1 is located in the left region LR, and the first upper electrode pattern 41 is located in the right region RR. On the other hand, the second lower electrode pattern 32 of the second capacitor structure C2 is located in the right region RR, while the second upper electrode pattern 42 is located in the left region LR.

[0089] Therefore, based on the above structure, for either the first capacitor structure C1 or the second capacitor structure C2, the lower electrode pattern and the upper electrode pattern are located in different regions (left region LR or right region RR), and then the lower electrode pattern and the upper electrode pattern are electrically connected to each other through contact plugs V1 and V2 in the middle region MR. As mentioned earlier, during the manufacturing process of paired capacitors, due to errors in the manufacturing process, the capacitance values ​​of the left and right capacitor structures may be slightly different, resulting in capacitance mismatch. For example, if the capacitance value of the electrode pattern formed in the left region is X1, and the capacitance value of the electrode pattern formed in the right region is X2, where X1 is slightly larger than X2. If the above... Figure 2 The structure shown, where multiple electrode patterns in the left region LR and the right region RR are stacked separately, will cause the capacitance difference between the capacitor structures in the left and right regions to gradually increase (because the capacitance value X1 of each layer is slightly larger than the capacitance value X2, theoretically, after stacking N layers, the capacitance difference will be N×(X1-X2)). However, if... Figure 5The structure shown involves overlapping electrode patterns in different regions. Specifically, in the left region, the second upper electrode pattern 42 is positioned above the first lower electrode pattern 31, while in the right region RR, the first upper electrode pattern 41 is positioned above the second lower electrode pattern 32. As described above, assuming the capacitance value of the electrode pattern formed in the left region is X1 and the capacitance value of the electrode pattern formed in the right region is X2, then for either the first capacitor structure C1 or the second capacitor structure C2, the capacitance value is X1 + X2. Therefore, the capacitance values ​​of the two capacitor structures will approach consistency, reducing capacitance mismatch between the two structures and improving the quality of the paired capacitors.

[0090] It is worth noting that, although in the third embodiment above ( Figures 3-5 The diagram only shows the top and bottom electrode patterns. However, in other embodiments of the present invention, more electrode patterns can be stacked to form paired capacitors with higher capacitance values. Figure 6 A three-dimensional schematic diagram of paired capacitors according to a fourth embodiment of the present invention is shown. Figure 5 Electrode patterns continue to be stacked on the paired capacitors shown to form a structure as described above. Figure 6 The paired capacitors are shown. More specifically, Figure 6The paired capacitor 4 shown includes a first capacitor structure C1 and a second capacitor structure C2. The first capacitor structure C1 includes a first lower electrode pattern 31, a first middle electrode pattern 41', a first upper electrode pattern 51, and a surrounding dielectric layer. The electrode patterns in the first capacitor structure C1 are electrically connected to each other through contact plugs V1 and V3. The second capacitor structure C2 includes a second lower electrode pattern 32, a second middle electrode pattern 42', a second upper electrode pattern 52, and a surrounding dielectric layer. The electrode patterns in the second capacitor structure C2 are electrically connected to each other through contact plugs V2 and V4. The first lower electrode pattern 31, the second lower electrode pattern 32, the first middle electrode pattern 41', and the second middle electrode pattern 42' described here are the same as those in the previous embodiment, and will not be repeated here. The first upper electrode pattern 51 has a shape similar to or the same as the first lower electrode pattern 31 and is located in the left region LR. The second upper electrode pattern 52 has a shape similar to or the same as the second lower electrode pattern 32 and is located in the right region RR. That is, in the left region LR, the first lower electrode pattern 31, the second middle electrode pattern 42', and the first upper electrode pattern 51 are sequentially included along the Z-axis direction. In the right region RR, the second lower electrode pattern 32, the first middle electrode pattern 41', and the second upper electrode pattern 52 are sequentially included along the Z-axis direction. More specifically, in the left region LR and the right region RR, the electrode patterns included in the first capacitor structure C1 and the electrode patterns included in the second capacitor structure C2 are alternately stacked. It is understood that in other embodiments of the present invention, it can be based on Figure 6 The paired capacitors shown continue to form more layers of electrode patterns stacked on top of them, and their arrangement follows the pattern described above. For example, in the left region, from bottom to top, there are first electrode patterns, second electrode patterns, first electrode patterns, second electrode patterns, and so on, while in the right region, from bottom to top, there are second electrode patterns, first electrode patterns, second electrode patterns, first electrode patterns, and so on.

[0091] Based on the above description and accompanying drawings, the present invention provides a paired capacitor comprising a substrate S, on which a left region LR, a middle region MR, and a right region RR are defined, wherein the middle region MR is located between the left region LR and the right region RR; a first capacitor structure C1 comprising a first lower electrode pattern 31 and a first upper electrode pattern 41, wherein the first lower electrode pattern 31 and the first upper electrode pattern 41 are located in different regions and in different layers in a vertical direction (Z-axis direction); and a second capacitor structure C2 comprising a second lower electrode pattern 32 and a second upper electrode pattern 42, wherein the second lower electrode pattern 32 and the second upper electrode pattern 42 are located in different regions and in different layers in a vertical direction (Z-axis direction).

[0092] In some embodiments of the present invention, the first lower electrode pattern 31 is located in the left region LR, the first upper electrode pattern 41 is located in the right region RR, the second lower electrode pattern 32 is located in the right region, and the second upper electrode pattern 42 is located in the left region.

[0093] In some embodiments of the present invention, the first lower electrode pattern 31, the first upper electrode pattern 41, the second lower electrode pattern 32, and the second upper electrode pattern 42 each include a plurality of main shaft electrodes and a plurality of branch electrodes (including main shaft electrodes 31A, 31B, 32A, 32B, 41A, 41B, 42A, 42B, and branch electrodes 31C, 31D, 32C, 32D, 41C, 41D, 42C, 42D), wherein the plurality of branch electrodes included in the first lower electrode pattern 31, the first upper electrode pattern 41, the second lower electrode pattern 32, and the second upper electrode pattern 42 are all arranged along the same direction (X direction).

[0094] In some embodiments of the present invention, a plurality of first contact plugs V1 and a plurality of second contact plugs V2 are located in the middle region MR. The first contact plugs V1 are electrically connected to the first lower electrode pattern 31 and the first upper electrode pattern 41, and the second contact plugs V2 are electrically connected to the second lower electrode pattern 32 and the second upper electrode pattern 42.

[0095] In some embodiments of the present invention, some of the first contact plugs V1 and some of the second contact plugs V2 are not located within the left region LR and the right region RR.

[0096] In some embodiments of the present invention, a plurality of first contact plugs V1 are electrically connected to the spindle electrode 31A of the first lower electrode pattern 31 and the spindle electrode of the first upper electrode pattern 41, and a plurality of second contact plugs V2 are electrically connected to the spindle electrode 32A of the second lower electrode pattern 32 and the spindle electrode 42A of the second upper electrode pattern 42.

[0097] In some embodiments of the present invention, when viewed from a top view, the first lower electrode pattern 31 and the second upper electrode pattern 42 partially overlap (that is, the two partially overlap in the Z-axis direction).

[0098] In some embodiments of the present invention, the first capacitor structure C1 further includes a third electrode pattern 51, which is located above the second upper electrode pattern 42.

[0099] In some embodiments of the present invention, the third capacitor pattern 51, the second upper electrode pattern 42, and the first lower electrode pattern 31 of the first capacitor structure C1 partially overlap each other along the vertical direction.

[0100] In some embodiments of the present invention, it further includes a plurality of third contact plugs V3, a third capacitor pattern 51 electrically connected to the first capacitor structure C1, and a first upper electrode pattern 41.

[0101] The present invention also provides a method for manufacturing a paired capacitor, comprising providing a substrate S, defining a left region LR, a middle region MR and a right region RR on the substrate S, wherein the middle region MR is located between the left region LR and the right region RR, forming a first capacitor structure C1, comprising a first lower electrode pattern 31 and a first upper electrode pattern 41, wherein the first lower electrode pattern 31 and the first upper electrode pattern 41 are located in different regions and in different layers in a vertical direction (Z-axis direction), and forming a second capacitor structure C2, comprising a second lower electrode pattern 32 and a second upper electrode pattern 42, wherein the second lower electrode pattern 32 and the second upper electrode pattern 42 are located in different regions and in different layers in a vertical direction (Z-axis direction).

[0102] The present invention is characterized by providing a paired capacitor and a method for manufacturing the same. The paired capacitor comprises two capacitor structures, each containing multiple layers of MOM electrode patterns. Along a vertical direction, the MOM electrode patterns of the two capacitor structures are alternately stacked in different regions, and the MOM electrode patterns are connected to each other via contact plugs. Therefore, the capacitance difference between electrode patterns in different regions can be effectively reduced, improving the quality of the paired capacitor.

[0103] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A pair of capacitors, comprising: A base on which a left region, a middle region and a right region are defined, wherein the middle region is located between the left region and the right region; A first capacitor structure includes a first lower electrode pattern and a first upper electrode pattern, wherein the first lower electrode pattern and the first upper electrode pattern are located in different regions and in different layers in the vertical direction; and The second capacitor structure includes a second lower electrode pattern and a second upper electrode pattern, wherein the second lower electrode pattern and the second upper electrode pattern are located in different regions and in different layers in the vertical direction.

2. The paired capacitor as claimed in claim 1, wherein the first lower electrode pattern is located in the left region, the first upper electrode pattern is located in the right region, the second lower electrode pattern is located in the right region, and the second upper electrode pattern is located in the left region.

3. The paired capacitor as claimed in claim 1, wherein the first lower electrode pattern, the first upper electrode pattern, the second lower electrode pattern, and the second upper electrode pattern each include a plurality of main axis electrodes and a plurality of branch electrodes, wherein the plurality of branch electrodes included in the first lower electrode pattern, the first upper electrode pattern, the second lower electrode pattern, and the second upper electrode pattern are all arranged along the same direction.

4. The paired capacitor as claimed in claim 3, further comprising a plurality of first contact plugs and a plurality of second contact plugs located in the central region, wherein the first contact plugs are electrically connected to the first lower electrode pattern and the first upper electrode pattern, and the second contact plugs are electrically connected to the second lower electrode pattern and the second upper electrode pattern.

5. The paired capacitors of claim 4, wherein the first contact plugs and the second contact plugs are not located in the left region and the right region.

6. The paired capacitor of claim 4, wherein the plurality of first contact plugs are electrically connected to the spindle electrode of the first lower electrode pattern and the spindle electrode of the first upper electrode pattern, and the plurality of second contact plugs are electrically connected to the spindle electrode of the second lower electrode pattern and the spindle electrode of the second upper electrode pattern.

7. The paired capacitor as claimed in claim 1, wherein, viewed from a top view, the first lower electrode pattern partially overlaps with the second upper electrode pattern, and the second lower electrode pattern partially overlaps with the first upper electrode pattern.

8. The paired capacitor as claimed in claim 1, wherein the first capacitor structure further includes a third electrode pattern located above the second upper electrode pattern.

9. The paired capacitors of claim 8, wherein along the vertical direction, the third capacitor pattern of the first capacitor structure, the second upper electrode pattern, and the first lower electrode pattern partially overlap each other.

10. The paired capacitor of claim 8, further comprising a plurality of third contact plugs electrically connecting the third capacitor pattern of the first capacitor structure and the first upper electrode pattern.

11. A method for manufacturing a pair of capacitors, comprising: Provide a base on which a left region, a middle region, and a right region are defined, wherein the middle region is located between the left region and the right region; A first capacitor structure is formed, comprising a first lower electrode pattern and a first upper electrode pattern, wherein the first lower electrode pattern and the first upper electrode pattern are located in different regions and in different layers in the vertical direction. as well as A second capacitor structure is formed, comprising a second lower electrode pattern and a second upper electrode pattern, wherein the second lower electrode pattern and the second upper electrode pattern are located in different regions and in different layers in the vertical direction.

12. The method for manufacturing a paired capacitor as claimed in claim 11, wherein the first lower electrode pattern is located in the left region, the first upper electrode pattern is located in the right region, the second lower electrode pattern is located in the right region, and the second upper electrode pattern is located in the left region.

13. The method for manufacturing paired capacitors as described in claim 11, wherein the first lower electrode pattern, the first upper electrode pattern, the second lower electrode pattern, and the second upper electrode pattern each include a plurality of main axis electrodes and a plurality of branch electrodes, wherein the plurality of branch electrodes included in the first lower electrode pattern, the first upper electrode pattern, the second lower electrode pattern, and the second upper electrode pattern are all arranged along the same direction.

14. The method of manufacturing a paired capacitor as claimed in claim 13, further comprising forming a plurality of first contact plugs and a plurality of second contact plugs located in the region, the first contact plugs being electrically connected to the first lower electrode pattern and the first upper electrode pattern, and the second contact plugs being electrically connected to the second lower electrode pattern and the second upper electrode pattern.

15. The method of manufacturing paired capacitors as claimed in claim 14, wherein the first contact plugs and the second contact plugs are not located in the left region and the right region.

16. The method for manufacturing a paired capacitor as claimed in claim 14, wherein the plurality of first contact plugs are electrically connected to the spindle electrode of the first lower electrode pattern and the spindle electrode of the first upper electrode pattern, and the plurality of second contact plugs are electrically connected to the spindle electrode of the second lower electrode pattern and the spindle electrode of the second upper electrode pattern.

17. The method for manufacturing paired capacitors as claimed in claim 11, wherein, viewed from a top view, the first lower electrode pattern partially overlaps with the second upper electrode pattern, and the second lower electrode pattern partially overlaps with the first upper electrode pattern.

18. The method for manufacturing a paired capacitor as claimed in claim 11, wherein the first capacitor structure further includes forming a third electrode pattern, the third electrode pattern being located above the second upper electrode pattern.

19. The method of manufacturing a pair of capacitors as claimed in claim 18, wherein along the vertical direction, the third capacitor pattern of the first capacitor structure, the second upper electrode pattern, and the first lower electrode pattern partially overlap each other.

20. The method for manufacturing a paired capacitor as claimed in claim 18, further comprising forming a plurality of third contact plugs, the third capacitor pattern electrically connecting the first capacitor structure, and the first upper electrode pattern.

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