Method for manufacturing a capacitor device using a self-alignment process and capacitor device

Abstract

The application provides a method for manufacturing a capacitor device by using a self-alignment process and the capacitor device. The method comprises the following steps: forming a first dielectric layer and a first conductive layer on a substrate; patterning to form an active region and an isolation trench and filling an isolation medium; forming a second dielectric layer and a second conductive layer; etching the second conductive layer and the second dielectric layer by using a flash memory process mask to expose part of the first conductive layer to lead out a lower plate and use the second conductive layer as an upper plate. The application synchronously forms PIP and PPS capacitors without increasing additional masks by reusing the mask and material layer in the flash memory process. The scheme reduces the manufacturing cost, avoids alignment errors, improves the consistency of integration efficiency and device performance, and is suitable for embedded flash memory chip manufacturing with a multi-layer polysilicon structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for fabricating capacitors using a self-aligned process, and the capacitor itself. Background Technology

[0002] In modern semiconductor integrated circuits, capacitors are indispensable passive components. Among them, polysilicon-insulator-polysilicon (PIP) capacitors and polysilicon-polysilicon-substrate (PPS) capacitors play a crucial role in noise control and frequency modulation in analog circuits.

[0003] With the continuous evolution of semiconductor technology, embedded flash memory technology is widely used in various microcontrollers and smart chips. In embedded flash memory processes with multi-layer polysilicon structures, PIP or PPS capacitors are typically integrated. Because these capacitors have a large capacitance per unit area, they can effectively reduce the overall footprint of the chip, thereby improving integration efficiency.

[0004] However, in existing manufacturing processes, to simultaneously fabricate the aforementioned capacitors on flash memory chips, it is typically necessary to introduce additional photomasks and separate process steps to define the upper and lower electrode structures of the capacitors. This approach not only disrupts the continuity of the original flash memory process, increasing the complexity of the process flow and production cycle, but also significantly increases manufacturing costs.

[0005] Especially in self-aligned flash memory technology, how to achieve seamless integration of capacitors and flash memory cells and avoid additional photomask costs has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The technical problem to be solved by this invention is that in the existing self-aligned flash memory process, the fabrication of polysilicon-dielectric-polysilicon (PIP) or polysilicon-polysilicon-substrate (PPS) capacitors usually requires the introduction of additional photomasks and independent process steps. This not only increases the complexity of the manufacturing process and the production cycle, but also significantly increases the manufacturing cost. At the same time, the alignment error between the multilayer masks may also have an adverse effect on the consistency of the electrical performance of the capacitor.

[0007] This invention provides a method for fabricating capacitors using a self-aligned process, wherein the capacitors are formed simultaneously with the self-aligned flash memory process. The method includes:

[0008] Step 1: Provide a substrate, and sequentially form a first dielectric layer and a first conductive layer on the substrate;

[0009] Step 2: Pattern the first conductive layer, the first dielectric layer and the substrate to form an active region and an isolation trench, and fill the isolation trench with an isolation medium;

[0010] Step 3: Sequentially form a second dielectric layer and a second conductive layer on the first conductive layer and the isolation medium;

[0011] Step 4: Using a mask in flash memory technology, etch the second conductive layer and the second dielectric layer to expose a portion of the first conductive layer, so that the first conductive layer is used as the lower electrode of the capacitor and the second conductive layer is used as the upper electrode of the capacitor to form the capacitor.

[0012] Preferably, in step one, the first conductive layer comprises polycrystalline silicon.

[0013] Preferably, in step one, the first conductive layer serves as a floating gate in a self-aligned flash memory.

[0014] Preferably, in step one, the first dielectric layer comprises silicon oxide.

[0015] Preferably, in step one, the first dielectric layer serves as the tunneling dielectric layer in the self-aligned flash memory.

[0016] Preferably, in step three, the second dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

[0017] Preferably, in step three, the second conductive layer comprises polycrystalline silicon.

[0018] Preferably, in step three, the second conductive layer serves as a control gate in the self-aligned flash memory.

[0019] Preferably, in step four, the capacitor device includes a polysilicon-dielectric layer-polysilicon capacitor, wherein the upper electrode of the polysilicon-dielectric layer-polysilicon capacitor is the second conductive layer, the lower electrode is the first conductive layer, and the dielectric layer is the second dielectric layer.

[0020] Preferably, in step four, the capacitor device includes a polysilicon-polysilicon-substrate capacitor, wherein the upper electrode of the polysilicon-polysilicon-substrate capacitor is the first conductive layer, the lower electrode is the active region in the substrate, and the dielectric layer is the first dielectric layer.

[0021] Preferably, the method further includes: step five, forming an interlayer dielectric layer on the second conductive layer and the exposed first conductive layer, and etching the interlayer dielectric layer to form contact holes that are electrically connected to the upper electrode plate and the lower electrode plate, respectively.

[0022] The present invention also provides a capacitor device fabricated using a self-aligned process, which is prepared by the aforementioned method. The capacitor device and the self-aligned flash memory cell are co-located on a substrate. The capacitor device includes:

[0023] The substrate;

[0024] The first dielectric layer located on the substrate;

[0025] A first conductive layer is located on the first dielectric layer, and the first conductive layer serves as the lower electrode of the capacitor.

[0026] The second dielectric layer is located on the first conductive layer;

[0027] A second conductive layer is located on the first dielectric layer, and the second conductive layer serves as the upper electrode of the capacitor.

[0028] The second conductive layer and the second dielectric layer have openings that expose a portion of the first conductive layer, which is used to lead out the lower electrode plate.

[0029] Preferably, the capacitor device includes a polysilicon-dielectric layer-polysilicon capacitor, wherein the upper electrode of the polysilicon-dielectric layer-polysilicon capacitor is a control gate polysilicon, the lower electrode is a floating gate polysilicon, and the dielectric layer is a silicon oxide-silicon nitride-silicon oxide composite layer located between the control gate polysilicon and the floating gate polysilicon.

[0030] Preferably, the capacitor device includes a polysilicon-polysilicon-substrate capacitor, wherein the upper electrode of the polysilicon-polysilicon-substrate capacitor is a floating gate polysilicon, the lower electrode is an active region in the substrate, and the dielectric layer is a silicon oxide layer located between the floating gate polysilicon and the active region.

[0031] As described above, the method for fabricating capacitors using a self-aligned process and the capacitors of the present invention have the following beneficial effects:

[0032] By deeply integrating the self-aligned flash memory process, PIP and PPS capacitor structures are simultaneously formed using existing masks in the flash memory process, eliminating the need for additional photolithography masks. This significantly reduces manufacturing costs and shortens the production cycle. Since the capacitors share the same material layers and process environment as the flash memory cells, precise alignment of the capacitor electrode edges is ensured, eliminating alignment error risks and improving device performance consistency and yield. Simultaneously, this approach allows for the flexible integration of multiple types of capacitors on the same chip, increasing design freedom and integration efficiency, and providing effective technical support for the optimization of embedded flash memory products. Attached Figure Description

[0033] Figure 1The diagram shows a process flow diagram of a method for fabricating capacitors using a self-aligned process according to the present invention.

[0034] Figure 2 The diagram shows a cross-sectional view of the formation of the first dielectric layer and the first conductive layer in a method for fabricating a capacitor using a self-aligned process according to the present invention.

[0035] Figure 3 The diagram shows a cross-sectional view of the formation of an active region and an isolation trench in a method for fabricating a capacitor using a self-aligned process according to the present invention.

[0036] Figure 4 The diagram shows a cross-sectional view of the formation of the second dielectric layer and the second conductive layer in a method for fabricating a capacitor using a self-aligned process according to the present invention.

[0037] Figure 5 The diagram shows a planar structure of a polycrystalline silicon-dielectric layer-polycrystalline silicon capacitor device fabricated using a self-aligned process according to the present invention.

[0038] Figure 6 This invention illustrates a polycrystalline silicon-dielectric-polycrystalline silicon capacitor fabricated using a self-aligned process. Figure 5 A schematic diagram of a cross section where line AA' is tangent to the mask opening;

[0039] Figure 7 This invention illustrates a polycrystalline silicon-dielectric-polycrystalline silicon capacitor fabricated using a self-aligned process. Figure 5 A schematic diagram of a cross section where line AA' is tangent to the middle of two mask lines;

[0040] Figure 8 This invention illustrates a polycrystalline silicon-dielectric-polycrystalline silicon capacitor fabricated using a self-aligned process. Figure 5 Schematic diagram of the cross section of line BB' in the middle;

[0041] Figure 9 The diagram shows a planar structure of a polycrystalline silicon-substrate capacitor device fabricated using a self-aligned process according to the present invention.

[0042] Figure 10 This invention illustrates a polycrystalline silicon-polycrystalline silicon-substrate capacitor device fabricated using a self-aligned process. Figure 9 A schematic diagram of the cross section of line AA'. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Figure 1 A schematic diagram of a process flow for fabricating a capacitor device using a self-aligned process is shown. The capacitor device is formed simultaneously with a self-aligned flash memory process, and the method includes the following steps.

[0045] Step 1, refer to Figure 2 A substrate 101 is provided, on which a first dielectric layer 102 and a first conductive layer 103 are sequentially formed. The substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In some embodiments, various doped regions can be pre-formed in the substrate 101, such as deep N-type wells, P-type wells, or N-type wells formed by ion implantation processes, to achieve electrical isolation between different devices or to adjust the bottom electrode characteristics of capacitors. By flexibly configuring the doping concentration in the substrate 101, the voltage linearity of the capacitors can be effectively adjusted.

[0046] In some embodiments, in step one, the first conductive layer 103 comprises polycrystalline silicon. The first conductive layer 103 can be formed using a low-pressure chemical vapor deposition (LPD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a physical vapor deposition (PVD) process. During deposition, in-situ doping can be performed, or dopant elements such as phosphorus, arsenic, or boron can be introduced after deposition using an ion implantation process to reduce the resistivity of the first conductive layer 103 to a preset range. Besides polycrystalline silicon, the first conductive layer 103 can also be made of amorphous silicon, a silicon-germanium alloy, or metallic materials such as titanium nitride, tantalum nitride, tungsten, aluminum, or combinations thereof. The thickness of the first conductive layer 103 can be set according to the charge storage requirements of the floating gate in the flash memory cell. Using polycrystalline silicon as the first conductive layer 103 ensures perfect compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes.

[0047] In some embodiments, in step one, the first conductive layer 103 serves as a floating gate in a self-aligned flash memory. By directly reusing the floating gate layer in the flash memory process as the electrode of a capacitor, the fabrication process of the capacitor can be highly integrated with the fabrication process of the memory cell, reducing the switching of process steps and ensuring the flatness consistency of the capacitor and the memory cell in the height direction. This reuse strategy significantly reduces the complexity of process development.

[0048] In some embodiments, in step one, the first dielectric layer 102 comprises silicon oxide. The first dielectric layer 102 can be formed by a thermal oxidation process, such as growing in a high-temperature environment containing oxygen or water vapor. In-situ vapor growth or free radical oxidation processes can also be used to obtain a dielectric film with higher density and lower defect density. In some alternative embodiments, the first dielectric layer 102 can be formed by an atomic layer deposition process using a high dielectric constant material, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, or silicates thereof, to increase the equivalent capacitance while maintaining the physical thickness.

[0049] In some embodiments, in step one, the first dielectric layer 102 serves as a tunneling dielectric layer in a self-aligned flash memory. When the first dielectric layer 102 serves as the dielectric layer of a capacitor, its thickness uniformity can be strictly controlled, thereby ensuring that the capacitor has a stable capacitance value and breakdown voltage. Since tunneling dielectric layers typically have extremely high quality requirements, using them as capacitor dielectrics can significantly improve the reliability and lifespan of the capacitor. The thickness of the first dielectric layer 102 can be optimized according to the requirements of the tunneling effect.

[0050] Step Two, Refer to Figure 3The first conductive layer 103, the first dielectric layer 102, and the substrate 101 are patterned to form active regions and isolation trenches, and the isolation trenches are filled with an isolation dielectric 104. Patterning typically involves photolithography, including photoresist coating, exposure, and development, to define the locations of the active regions. Subsequently, an anisotropic dry etching process, such as reactive ion etching, is used to penetrate the first conductive layer 103 and the first dielectric layer 102 and reach a certain depth in the substrate 101, thereby forming a shallow trench isolation structure. Fluorine- or chlorine-containing plasmas can be used during etching. After trench formation, a thin pad oxide layer can be grown to repair etching damage. The isolation dielectric 104 can be silicon dioxide formed by high-density plasma chemical vapor deposition, or a dielectric material formed by a high aspect ratio, flowable chemical vapor deposition process. After filling, high-temperature annealing is typically performed to densify the isolation dielectric 104. Subsequently, planarization is performed using a chemical mechanical polishing (CMP) process. This process uses either the first conductive layer 103 as a stop layer or a hard mask layer covering the first conductive layer 103 as a stop layer, ensuring that the top surface of the insulating medium 104 is at the same level as the top surface of the first conductive layer 103. This planarization process provides an excellent surface foundation for subsequent thin film deposition.

[0051] Step 3, refer to Figure 4 A second dielectric layer 105 and a second conductive layer 106 are sequentially formed on the first conductive layer 103 and the isolation medium 104. Before forming the second dielectric layer 105, the surface of the first conductive layer 103 can be pretreated, for example, by removing surface oxides with diluted hydrofluoric acid, or by plasma treatment to enhance interface properties.

[0052] In some embodiments, in step three, the second dielectric layer 105 includes a silicon oxide-silicon nitride-silicon oxide composite layer. This composite structure can be formed by thermal oxidation, chemical vapor deposition, or a combination thereof. For example, a bottom oxide layer is first formed by thermal oxidation, then an intermediate nitride layer is formed by low-pressure chemical vapor deposition, and finally a top oxide layer is formed by high-temperature oxidation or deposition. This composite structure combines the high breakdown field strength of silicon oxide and the high dielectric constant of silicon nitride, effectively suppressing leakage current. In other embodiments, the second dielectric layer 105 can also adopt a single-layer structure or a multi-layer stacked structure, and the material can be selected from silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, etc. The equivalent oxide layer thickness of the second dielectric layer 105 can be designed according to the coupling ratio between the control gate and the floating gate.

[0053] In some embodiments, in step three, the second conductive layer 106 comprises polycrystalline silicon. The second conductive layer 106 can be formed by chemical vapor deposition and heavily doped to reduce gate resistance. In some advanced processes, the second conductive layer 106 can also employ a metal gate structure, including a work function adjustment layer and a metal filler layer.

[0054] In some embodiments, in step three, the second conductive layer 106 serves as a control gate in the self-aligned flash memory. By reusing the control gate layer as the upper plate of the capacitor, structural simplification is achieved, and the electrical characteristics of the capacitor can be matched with the logic control levels of the flash memory cell.

[0055] Step 4, Refer to Figures 5 to 10 The second conductive layer 106 and the second dielectric layer 105 are etched using a mask in the flash memory process to expose part of the first conductive layer 103, so that the first conductive layer 103 is used as the lower electrode of the capacitor and the second conductive layer 106 is used as the upper electrode of the capacitor to form a capacitor.

[0056] This step utilizes existing masks in flash memory manufacturing processes, such as... Figure 5 and Figure 9 The second flash gate mask FLGT2 is shown in the diagram. This mask is used to define the topography of the control gate in the memory array region and to create the lead-out windows in the capacitor region. The etching process typically employs a multi-step dry etching method. First, the second conductive layer 106 is etched, stopping at the surface of the second dielectric layer 105. Then, the etching gas is switched to etch the second dielectric layer 105, ultimately exposing the first conductive layer 103. This self-aligned method eliminates the need for additional photomasks, significantly reducing manufacturing costs and avoiding the alignment error risks associated with stacking multiple photomasks.

[0057] In some embodiments, in step four, the capacitor device includes a polysilicon-dielectric-polysilicon capacitor. (See reference...) Figure 5 floor plan and Figure 6 , Figure 7 , Figure 8 The cross-sectional view shows that the upper electrode of the polysilicon-dielectric-polysilicon capacitor is the second conductive layer 106, the lower electrode is the first conductive layer 103, and the dielectric layer is the second dielectric layer 105. This PIP structure utilizes the second dielectric layer 105 between the two polysilicon layers as the energy storage medium. Because the second dielectric layer 105 typically has excellent linearity and a low temperature coefficient, this capacitor is well-suited for precision analog signal processing, filtering circuits, and frequency modulation circuits. The effective area of ​​the upper electrode can be precisely defined through the opening design of the FLGT2 mask. Specifically, as shown... Figure 6As shown, within the region defined by the second flash gate mask FLGT2, the second conductive layer 106 and the second dielectric layer 105 are completely removed, forming an opening through both layers that exposes the top surface of the first conductive layer 103. The floating gate contact via FG CT falls directly onto the exposed first conductive layer 103, enabling electrical lead-out to the lower electrode. Figure 7 The non-opening region shown, i.e., the area between the two FLGT2 mask lines, maintains a complete stacked structure of the second conductive layer 106, the second dielectric layer 105, and the first conductive layer 103. The control gate contact hole CG CT 107 falls on the second conductive layer 106 in this region to lead out the upper electrode. Figure 8 As shown, in a cross section perpendicular to the gate length direction, the sidewall of the first conductive layer 103 is in contact with the sidewall of the isolation medium 104, and the second conductive layer 106 is retained thereon.

[0058] In some embodiments, in step four, the capacitor device includes a polysilicon-polysilicon-substrate capacitor. (Refer to...) Figure 9 floor plan and Figure 10 The cross-sectional view shows that the upper electrode of the polysilicon-polysilicon-substrate capacitor is the first conductive layer 103, the lower electrode is the active region in the substrate 101, and the dielectric layer is the first dielectric layer 102. This PPS structure utilizes the first dielectric layer 102 between the first conductive layer 103 and the active region of the substrate 101 as the energy storage medium. Since the first dielectric layer 102, as a tunneling dielectric layer, is typically very thin, the PPS capacitor can provide a very large capacitance per unit area. This structure can fully utilize the substrate space and significantly increase the total capacitance of the system without increasing the additional chip area. Figure 10 As shown, in the PPS capacitor structure, the second conductive layer 106 and the second dielectric layer 105 are removed in the core region of the capacitor, leaving the first conductive layer 103 directly exposed as the top electrode. A floating gate contact hole (FG CT) is disposed above the first conductive layer 103. To achieve effective biasing of the bottom electrode, an active region contact hole (AA CT) is disposed on the surface of the substrate 101 outside the first conductive layer 103. The active region in the substrate 101 can undergo additional heavy doping treatment to form a low-resistivity conductive layer, thereby reducing plate losses. The first dielectric layer 102 is sandwiched between the first conductive layer 103 and the substrate 101, and its thickness uniformity is precisely ensured by a thermal oxidation process. This configuration allows the PPS capacitor to form a good topological connection with the surrounding isolation dielectric 104, providing high capacitance density while maintaining excellent breakdown characteristics and reliability.

[0059] In some embodiments, the method further includes step five: forming an interlayer dielectric layer on the second conductive layer 106 and the exposed first conductive layer 103, and etching the interlayer dielectric layer to form contact holes that are electrically connected to the upper electrode plate and the lower electrode plate, respectively.

[0060] Reference Figure 6 , Figure 7 , Figure 8 and Figure 10 The contact holes include active region contact holes AA CT connected to the active region, control gate contact holes CG CT (107) connected to the control gate, and floating gate contact holes FG CT connected to the floating gate. Before forming the interlayer dielectric layer, a contact hole etch stop layer can be deposited on the exposed surface. This etch stop layer can be made of silicon nitride, silicon carbide, silicon nitride, silicon oxynitride, or other etch-selective dielectric materials. The deposition process can be plasma-enhanced chemical vapor deposition or atomic layer deposition to ensure good coverage on complex step morphologies. The interlayer dielectric layer can be a single-layer or multi-layer stacked structure, and its material can be selected from undoped silicon glass, borosilicate glass, phosphosilicate glass, fluorinated silicon glass, carbon-doped silicon oxide, organosilicon glass, or other low dielectric constant materials.

[0061] The formation of the interlayer dielectric layer can employ various deposition techniques, such as high aspect ratio processes, flow-through chemical vapor deposition (CVD), subatmospheric pressure CVD, or plasma-enhanced CVD. After deposition, thermal annealing is typically performed to densify the dielectric material, followed by chemical mechanical polishing (CMP) to planarize the interlayer dielectric layer, eliminating topographic undulations caused by the underlying structure and providing a flat depth-of-focus plane for subsequent high-resolution photolithography. Contact hole formation involves precise photolithography and etching steps. First, a photoresist system is coated onto the surface of the interlayer dielectric layer. This system may include an underlayer anti-reflective coating, a hard mask layer, and the photoresist layer. The contact hole pattern is defined by photolithography exposure and development. Subsequently, an anisotropic dry etching process, such as reactive ion etching (RIE), is used to penetrate the interlayer dielectric layer. The etching process typically employs fluorinated chemicals, such as carbon tetrafluoride, trifluoromethane, hexafluoroethane, or octafluorocyclobutane, along with oxygen, nitrogen, or argon as auxiliary gases. The sidewall profile of the contact hole is controlled by adjusting the bias voltage and plasma density. The etching process stops at the surface of the contact hole etching stop layer. The etching conditions are then switched to penetrate the stop layer and expose the underlying conductive region. After contact hole etching, a plasma ashing process is typically performed to remove residual photoresist, followed by wet cleaning to remove etching byproducts and polymers. The contact hole filling process usually involves forming a continuous and uniform barrier layer, which can be made of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or a combination thereof, using physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. This barrier layer prevents interdiffusion between the subsequent filler metal and the dielectric material and enhances interfacial adhesion. A seed layer can be further formed on the barrier layer. Subsequently, a metal material, selected from tungsten, cobalt, ruthenium, copper, aluminum, or alloys thereof, is filled into the contact hole using chemical vapor deposition, physical vapor deposition, or electroplating processes. Finally, chemical mechanical polishing is used again to remove excess metal and barrier material from the top surface of the interlayer dielectric layer, thereby forming electrically isolated conductive plugs in the contact holes to achieve reliable electrical connection between the capacitor plates and the upper metal interconnects.

[0062] A capacitor device fabricated using a self-aligned process, prepared by the aforementioned method, is located on a substrate 101 along with a self-aligned flash memory cell. The capacitor device includes: a substrate 101; a first dielectric layer 102 on the substrate 101; a first conductive layer 103 on the first dielectric layer 102, serving as the lower electrode of the capacitor device; a second dielectric layer 105 on the first conductive layer 103; and a second conductive layer 106 on the first conductive layer 103, serving as the upper electrode of the capacitor device. The second conductive layer 106 and the second dielectric layer 105 have openings that expose a portion of the first conductive layer 103, which is used to lead out the lower electrode. This structure, by stacking multiple conductive and dielectric layers vertically, enables the simultaneous integration of multiple types of capacitor devices in the same process flow, improving process flexibility and integration density. This vertical integration method significantly saves silicon wafer area in the horizontal direction, providing higher functional density for system-on-a-chip (SoC).

[0063] In some embodiments, the capacitor includes a polysilicon-dielectric-layer-polysilicon capacitor, wherein the upper electrode of the polysilicon-dielectric-layer-polysilicon capacitor is a control gate polysilicon, the lower electrode is a floating gate polysilicon, and the dielectric layer is a silicon oxide-silicon nitride-silicon oxide composite layer located between the control gate polysilicon and the floating gate polysilicon. This structure effectively reduces parasitic resistance and improves the quality factor of the capacitor in high-frequency applications by reusing the interlayer dielectric of the flash memory cell as the capacitor dielectric. Due to the excellent breakdown resistance of the composite dielectric layer, the capacitor also exhibits excellent stability in power management circuits.

[0064] In some embodiments, the capacitor includes a polysilicon-polysilicon-substrate capacitor, wherein the upper electrode of the polysilicon-polysilicon-substrate capacitor is a floating-gate polysilicon, the lower electrode is an active region in the substrate 101, and the dielectric layer is a silicon oxide layer located between the floating-gate polysilicon and the active region. This structure achieves extremely high charge storage capacity by utilizing an ultrathin tunneling dielectric layer as the capacitor dielectric. In some embodiments, the active region can be further heavily doped to further reduce the depletion effect of the lower electrode, thereby improving the voltage linearity of the capacitor. This PPS capacitor has a significant competitive advantage in scenarios requiring large-capacity decoupling capacitors.

[0065] This invention achieves simultaneous manufacturing of PIP and PPS capacitors by deeply integrating self-aligned flash memory process flows and redefining existing photomask logic without altering the performance of the original memory cells. This integrated approach completely eliminates the additional photolithography steps required in traditional processes to form capacitor plates, thereby eliminating the impact of photoresist contamination and alignment misalignment on device performance. Since the capacitors share the exact same material growth and deposition environment as the flash memory cells, key parameters such as dielectric constant and sheet resistance of the capacitors are highly synchronized and predictable with flash memory process parameters, providing extremely high accuracy support for circuit simulation. Furthermore, this method allows designers to flexibly combine PIP and PPS capacitors on the same chip according to the different needs of analog and digital circuits, achieving an optimal balance between performance, area, and cost. This highly compatible manufacturing strategy not only improves the utilization rate of wafer fabs but also provides effective technical support for the rapid iteration and cost optimization of embedded flash memory products.

[0066] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating capacitor components using a self-aligned process, characterized in that, The capacitor element is formed simultaneously with the self-aligned flash memory process and includes at least: Step 1: Provide a substrate, and sequentially form a first dielectric layer and a first conductive layer on the substrate; Step 2: Pattern the first conductive layer, the first dielectric layer and the substrate to form an active region and an isolation trench, and fill the isolation trench with an isolation medium; Step 3: Sequentially form a second dielectric layer and a second conductive layer on the first conductive layer and the isolation medium; Step 4: Using a mask in flash memory technology, etch the second conductive layer and the second dielectric layer to expose a portion of the first conductive layer, so that the first conductive layer is used as the lower electrode of the capacitor and the second conductive layer is used as the upper electrode of the capacitor to form the capacitor.

2. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step one, the first conductive layer comprises polycrystalline silicon.

3. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step one, the first conductive layer serves as a floating gate in the self-aligned flash memory.

4. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step one, the first dielectric layer comprises silicon oxide.

5. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step one, the first dielectric layer serves as the tunneling dielectric layer in the self-aligned flash memory.

6. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step three, the second dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide composite layer.

7. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step three, the second conductive layer comprises polycrystalline silicon.

8. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step three, the second conductive layer serves as a control gate in the self-aligned flash memory.

9. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step four, the capacitor device includes a polysilicon-dielectric layer-polysilicon capacitor, wherein the upper electrode of the polysilicon-dielectric layer-polysilicon capacitor is the second conductive layer, the lower electrode is the first conductive layer, and the dielectric layer is the second dielectric layer.

10. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: In step four, the capacitor device includes a polysilicon-polysilicon-substrate capacitor, wherein the upper electrode of the polysilicon-polysilicon-substrate capacitor is the first conductive layer, the lower electrode is the active region in the substrate, and the dielectric layer is the first dielectric layer.

11. The method for fabricating capacitor components using a self-aligned process according to claim 1, characterized in that: The method further includes: step five, forming an interlayer dielectric layer on the second conductive layer and the exposed first conductive layer, and etching the interlayer dielectric layer to form contact holes that are electrically connected to the upper electrode plate and the lower electrode plate, respectively.

12. A capacitor device manufactured using a self-aligned process, characterized in that, The capacitor element is fabricated using the method described in any one of claims 1 to 11, wherein the capacitor element and the self-aligned flash memory cell are co-located on the substrate, and the capacitor element comprises: The substrate; The first dielectric layer located on the substrate; A first conductive layer is located on the first dielectric layer, and the first conductive layer serves as the lower electrode of the capacitor. The second dielectric layer is located on the first conductive layer; A second conductive layer is located on the first dielectric layer, and the second conductive layer serves as the upper electrode of the capacitor. The second conductive layer and the second dielectric layer have openings that expose a portion of the first conductive layer, which is used to lead out the lower electrode plate.

13. The capacitor element according to claim 12, characterized in that: The capacitor device includes a polysilicon-dielectric layer-polysilicon capacitor, wherein the upper electrode of the polysilicon-dielectric layer-polysilicon capacitor is a control gate polysilicon, the lower electrode is a floating gate polysilicon, and the dielectric layer is a silicon oxide-silicon nitride-silicon oxide composite layer located between the control gate polysilicon and the floating gate polysilicon.

14. The capacitor element according to claim 12, characterized in that: The capacitor device includes a polysilicon-polysilicon-substrate capacitor, wherein the upper electrode of the polysilicon-polysilicon-substrate capacitor is a floating gate polysilicon, the lower electrode is an active region in the substrate, and the dielectric layer is a silicon oxide layer located between the floating gate polysilicon and the active region.

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