Mim capacitor structure and method of forming the same

Abstract

The application provides a MIM capacitor structure, a plurality of grooves are formed on a substrate, and the top corner and the bottom corner of each groove are rounded; a plurality of electrode layers and a plurality of insulating layers in a multilayer stacked MIM capacitor structure are sequentially overlapped and formed by conformal deposition and are located in the grooves and extend to a dielectric layer; the projection patterns of the electrode layers are coincident; each electrode layer is electrically connected with a pad, and the pads of odd layers and the pads of even layers are located on different sides of the electrode layers in a second direction, and the projections of the pads do not overlap each other. The application sets a high-depth-width-ratio groove type MIM capacitor structure, combines conformal deposition of a high-dielectric-constant oxide layer and an electrode, fully utilizes the surface area of the groove sidewall, creates a three-dimensional structure MIM capacitor, increases the effective surface area of the capacitor under the condition of limited area, and obtains higher capacitor density as the depth-width ratio of the groove is improved. In addition, the corners of the groove profile are rounded to avoid breakdown of the corners of the groove sidewall caused by a strong electric field.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a MIM capacitor structure and its formation method. Background Technology

[0002] In logic chip manufacturing, metal-insulator-metal capacitors (MIMCAPs) are large-capacity capacitors, mainly manufactured after the upper copper back-end metal (Cu BEOL) process and before the aluminum back-end metal (Al BEOL) process, or even later in the process.

[0003] Currently, the mainstream processes are divided into two types: one is to pattern the metal, insulating layer and metal plate structure to make a single-layer capacitor; the other is to make a stacked capacitor by multi-layer stacking process in order to increase the capacitance value per unit area.

[0004] The fabrication process for this type of stacked capacitor is as follows: sequentially deposit each layer of high dielectric constant oxide (HKOx) and electrode, and then pattern each layer. By repeating the above process, electrical isolation between each layer of capacitor is achieved.

[0005] Existing MIM capacitor structures can achieve capacitance values ​​equivalent to planar two-layer structures. To further increase capacitance, there are two main approaches: 1) Lateral expansion: increasing the planar area of ​​the MIM capacitor; 2) Increasing the number of stacked layers: creating more layers to form a multi-layer MIM capacitor structure. However, this is limited by chip layout area, and increasing the number of stacked layers will correspondingly increase the patterning process. Summary of the Invention

[0006] The purpose of this invention is to provide a MIM capacitor structure and a method for forming the same, so as to improve the capacitance of the MIM capacitor structure.

[0007] To solve the above technical problems, the present invention provides a MIM capacitor structure, comprising:

[0008] A substrate having a dielectric layer formed thereon and a plurality of trenches extending through the dielectric layer and into the substrate, each trench extending along a first horizontal direction, the plurality of trenches being arranged along a second horizontal direction, the first direction being perpendicular to the second direction, and the top and bottom corners of each trench being rounded.

[0009] A multilayer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench and extending onto the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and even-numbered layers are located on different sides of the electrode layers in a second direction, and the projections of each pad do not overlap.

[0010] Optionally, the multiple electrode layers and the multiple pads are made of the same material and are selected from one of TiNx, NbOx, Al, Mo, AlCu, and Cu, where x is an integer greater than 1.

[0011] Optionally, the insulating layers are made of the same material and are selected from one or more single-layer structures or stacked structures of hafnium oxide, zirconium oxide, aluminum oxide, and silicon oxide.

[0012] Optionally, a contact structure corresponding to an electrical connection is formed on each of the pads.

[0013] Optionally, each of the contact structures is made of the same material and is selected from at least one of tungsten, aluminum, copper, molybdenum, polycrystalline silicon, and doped polycrystalline silicon.

[0014] Based on the same inventive concept, the present invention also provides a method for forming a MIM capacitor structure, comprising:

[0015] A substrate is provided, on which a dielectric layer is formed and a plurality of trenches extending through the dielectric layer and into the substrate, each trench extending along a first horizontal direction and the plurality of trenches arranged along a second horizontal direction, the first direction being perpendicular to the second direction;

[0016] The top and bottom corners of each of the grooves are rounded.

[0017] A multilayer stacked MIM capacitor structure is formed, comprising multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench and extending onto the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and the pads of even-numbered layers are located on different sides of the electrode layers in the second direction, and the projections of each pad do not overlap.

[0018] Optionally, the steps for forming a multilayer stacked MIM capacitor structure include:

[0019] A conductive material layer is formed, which is located on the bottom and sidewalls of the trench and extends to the dielectric layer;

[0020] The conductive material layer is patterned and etched to remove the conductive material layer with a preset edge width, while retaining the pad pattern to form the electrode layer and the corresponding electrical connection pads.

[0021] Optionally, the step of forming a multilayer stacked MIM capacitor structure further includes:

[0022] An insulating layer is formed, which covers the electrode layer and serves to isolate the electrode layers above and below.

[0023] Optionally, the electrode layer and the insulating layer are formed by conformal deposition using atomic layer deposition (ALD).

[0024] Optionally, after the step of forming the top electrode layer, the method further includes:

[0025] An interlayer dielectric layer is formed, which covers the top electrode layer, each of the pads, and the dielectric layer;

[0026] Multiple contact holes are formed, each of the contact holes exposing one of the pads;

[0027] The contact holes are filled to form a plurality of contact structures, each of the contact structures being electrically connected to one of the pads.

[0028] In a MIM capacitor structure provided by the present invention, a dielectric layer and multiple trenches extending through the dielectric layer and into the substrate are formed on the substrate. Each trench extends along a first horizontal direction, and the multiple trenches are arranged along a second horizontal direction. The first direction is perpendicular to the second direction, and the top and bottom corners of each trench are rounded. The multilayer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located in the trenches, and extend to the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to a pad, and the pads of odd-numbered layers and even-numbered layers are located on different sides of the electrode layer in the second direction. The projections of each pad do not overlap. This invention utilizes a high aspect ratio trench structure, combined with conformal deposition of a high dielectric constant oxide layer and an electrode layer, to fully leverage the surface area of ​​the trench sidewalls and create a three-dimensional MIM capacitor, increasing the effective surface area of ​​the capacitor under area constraints. As the trench aspect ratio increases, higher capacitance density can be achieved. The trench contour is rounded at the corners to prevent breakdown at the trench sidewall corners caused by strong electric fields. Furthermore, leveraging the excellent conformal properties of the deposited thin film, a multi-layer stacked MIM capacitor structure is designed to further enhance the capacitance value of the MIM capacitor structure. Attached Figure Description

[0029] Figure 1 This is a three-dimensional schematic diagram of the MIM capacitor structure according to an embodiment of the present invention.

[0030] Figure 2 This is a flowchart of a method for forming a MIM capacitor structure according to an embodiment of the present invention.

[0031] Figure 3 This is a top view schematic diagram of the MIM capacitor structure after the formation of the first conductive material layer according to an embodiment of the present invention.

[0032] Figure 4 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the first conductive material layer according to an embodiment of the present invention.

[0033] Figure 5 This is a top view schematic diagram of the MIM capacitor structure after the formation of the first layer of electrodes according to an embodiment of the present invention.

[0034] Figure 6 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the first layer of electrodes according to an embodiment of the present invention.

[0035] Figure 7 This is a top view schematic diagram of the MIM capacitor structure after the formation of the second conductive material layer according to an embodiment of the present invention.

[0036] Figure 8This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the second conductive material layer according to an embodiment of the present invention.

[0037] Figure 9 This is a top view schematic diagram of the MIM capacitor structure after the formation of the second layer electrode according to an embodiment of the present invention.

[0038] Figure 10 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the second layer electrode according to an embodiment of the present invention.

[0039] Figure 11 This is a top view schematic diagram of the MIM capacitor structure after the formation of the third conductive material layer according to an embodiment of the present invention.

[0040] Figure 12 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the third conductive material layer according to an embodiment of the present invention.

[0041] Figure 13 This is a top view schematic diagram of the MIM capacitor structure after the formation of the third electrode layer according to an embodiment of the present invention.

[0042] Figure 14 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the third electrode layer according to an embodiment of the present invention.

[0043] Figure 15 This is a top view schematic diagram of the MIM capacitor structure after the contact structure is formed according to an embodiment of the present invention.

[0044] Figure 16 This is a cross-sectional schematic diagram of the MIM capacitor structure after the contact structure is formed according to an embodiment of the present invention.

[0045] In the figure: 10-substrate; 11-dielectric layer; 12-trench; 13-first electrode layer; 13a-first conductive material layer; 13b-first pad; 13c-first contact structure; 14-first insulating layer; 15-second electrode layer; 15a-second conductive material layer; 15b-second pad; 15c-second contact structure; 16-second insulating layer; 17-third electrode layer; 17a-third conductive material layer; 17b-third pad; 17c-third contact structure; 18-interlayer dielectric layer. Detailed Implementation

[0046] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0047] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0048] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.

[0049] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0050] Figure 1 This is a three-dimensional schematic diagram of the MIM capacitor structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a MIM capacitor structure, which is fabricated using the MIM capacitor structure formation method described above, including:

[0051] A substrate 10, on which a dielectric layer 11 is formed and one or more trenches 12 penetrating the dielectric layer 11 and extending into the substrate 10, preferably multiple trenches 12. Each trench 12 may extend along a first horizontal direction, and the multiple trenches 12 may be arranged along a second horizontal direction, the first direction preferably being perpendicular to the second direction. The top and bottom corners of each trench 12 are rounded.

[0052] A multilayer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench 12 and extending onto the dielectric layer 11. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and even-numbered layers are located on different sides of the electrode layers in the second direction, and the projections of each pad do not overlap.

[0053] Please continue to refer to this. Figure 1In this embodiment, the multilayer stacked MIM capacitor structure includes a first electrode 13, a first insulating layer 14, a second electrode 15, a second insulating layer 16, a third electrode 17, a third insulating layer, a fourth electrode, a fourth insulating layer, and a fifth electrode, corresponding to first pad 13b, second pad 15b, third pad 17b, fourth pad, and fifth pad, and corresponding to first contact structure 13c, second contact structure 15c, third contact structure 17c, fourth contact structure, and fifth contact structure. It is worth emphasizing that the multilayer stacked MIM capacitor structure can also include more electrode layers and corresponding insulating layers. Increasing the number of stacked high-dielectric-constant oxide (HKOx) layers further improves the capacitance value of the MIM capacitor structure.

[0054] It is worth noting that, from Figure 1 As can be seen, in the MIM capacitor structure prepared by the above method, the positions of each pad are basically at the same height, that is, they are all located near the surface of the dielectric layer 11, rather than at the same height as the connected electrode layer. Compared with leading out contact structures from pads at different heights, the design of this invention can greatly simplify the process complexity and control difficulty of contact hole etching, metal filling and other steps, and the prepared MIM capacitor structure can have better electrical connection reliability.

[0055] Figure 2 This is a flowchart illustrating a method for forming a MIM capacitor structure according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for forming a MIM capacitor structure, including:

[0056] Step S10: A substrate is provided, on which a dielectric layer is formed and a plurality of trenches are formed through the dielectric layer and extending into the substrate, each trench extending along a first horizontal direction, and the plurality of trenches being arranged along a second horizontal direction, wherein the first direction is perpendicular to the second direction;

[0057] Step S20: Round the top and bottom corners of each of the grooves;

[0058] Step S30: A multi-layer stacked MIM capacitor structure is formed. The multi-layer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench and extending onto the dielectric layer. The bottom and top layers of the multi-layer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and the pads of even-numbered layers are located on different sides of the electrode layer in the second direction. The projections of each pad do not overlap.

[0059] Figures 3 to 16 This is a schematic diagram corresponding to the steps of the method for forming the MIM capacitor structure according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 16 Specific embodiments of the present invention will be described in detail below.

[0060] Figure 3 This is a top view schematic diagram of the MIM capacitor structure after the formation of the first conductive material layer according to an embodiment of the present invention. Figure 4 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the first conductive material layer according to an embodiment of the present invention. Figure 3 and Figure 4 As shown, a substrate 10 is provided, which serves as an operating platform for subsequent processes. The substrate 10 can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components. Optionally, the substrate 10 is a silicon substrate. A dielectric layer 11 and one or more trenches 12 extending through the dielectric layer 11 and into the substrate 10 are formed on the substrate 10. The aspect ratio of the trenches 12 meets a preset value, and the top and bottom corners of each trench 12 are rounded. A back-etching process can be used to round the contours of the top and bottom corners of the trenches 12 to avoid breakdown at the trench sidewall corners caused by a strong electric field. Using high aspect ratio (HAR) trenches maximizes the effective surface area of ​​the subsequently fabricated MIM capacitors, increasing the capacitance density per unit area without adopting a stepped structure. In other words, by utilizing high aspect ratio trenches, the effective surface area of ​​the capacitor is increased under area constraints; as the trench aspect ratio increases, a higher capacitance density can be obtained.

[0061] Here, the aspect ratio of the trench 12 is mainly determined by the number of electrode layers, the number of insulating layers, the thickness of each electrode layer, the thickness of each insulating layer, and the deposition effect achievable by the deposition process. On the one hand, the greater the depth and / or width of the trench 12, the larger the effective surface area of ​​the fabricated MIM capacitor. Moreover, increasing the depth of the trench 12 has a more significant effect on expanding the effective surface area of ​​the MIM capacitor than increasing the width of the trench 12. Therefore, given a fixed width of the trench 12, a larger aspect ratio should be used as much as possible. On the other hand, given a fixed thickness of each electrode layer and insulating layer deposited subsequently, the more electrode layers and insulating layers there are, the wider the trench 12 should be to avoid affecting the deposition uniformity of each layer and to prevent the formation of voids or undesirable trench closures during the deposition process. In summary, it is recommended to use the largest possible trench aspect ratio within the limits of the process, and this aspect ratio is expected to continue to improve with the continuous advancement of deposition technology.

[0062] This embodiment uses only two parallel trenches 12 as an example for illustration and explanation, and the invention should not be limited thereto. In other embodiments, only one trench may be formed, or three or more parallel trenches may be formed, and a MIM capacitor with an increased effective surface area can still be fabricated using the following method steps. For ease of description, the region in a semiconductor device where a MIM capacitor is formed is called the capacitor region. Given a capacitor region area, the more trenches there are, the larger the effective surface area of ​​the MIM capacitor. In the following text, the capacitor region also refers to the region covering all trenches.

[0063] Please continue to refer to this. Figure 3 and Figure 4 A first conductive material layer 13a is formed, which covers the bottom and sidewalls of the trench 12 and extends onto the dielectric layer 11. The material of the first conductive material layer 13a is, for example, one of TiNx, NbOx, Al, Mo, AlCu, and Cu, where x is an integer greater than 1. The first conductive material layer 13a can be formed using atomic layer deposition (ALD) technology.

[0064] Figure 5 This is a top view schematic diagram of the MIM capacitor structure after the formation of the first layer of electrodes according to an embodiment of the present invention. Figure 6 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the first layer of electrodes according to an embodiment of the present invention. Figure 5 and Figure 6 As shown, the first conductive material layer 13a is patterned and etched with pads. That is, except for the pad patterns to be retained, a predetermined width of the first conductive material layer 13a at both edges of the capacitor region is removed, thereby forming the first layer electrode 13 and the first pad 13b. The first pad 13b is located on the dielectric layer 11 and is electrically connected to the first layer electrode 13. The predetermined width here can be greater than or equal to the width of the first pad 13b.

[0065] Figure 7 This is a top view schematic diagram of the MIM capacitor structure after the formation of the second conductive material layer according to an embodiment of the present invention. Figure 8 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the second conductive material layer according to an embodiment of the present invention. Figure 8 As shown, prior to the step of forming the second conductive material layer, a first insulating layer 14 is formed, which covers the first layer electrode 13, the first pad 13b, and the dielectric layer 11. The material of the first insulating layer 14 is a high dielectric constant oxide (HKO) layer. x For example, it can be a single-layer structure or multiple stacked structures of hafnium oxide, zirconium oxide, aluminum oxide, and silicon oxide. In other words, hafnium oxide (HfO) can be selected. x Zirconia (ZrO) x ), aluminum oxide (AlO)x ), silicon dioxide (SiO) x ), or a composite system of the above materials (such as hafnium zirconium oxide HfZrO). x Alternatively, a multilayer stacked structure (such as HfO / ZrO / HfO, ZrO / AlO / ZrO, etc.) can be used for deposition. In this embodiment, there is no limitation on the number of stacked layers. Atomic layer deposition (ALD) can be used to form the first insulating layer 14 and the first electrode layer 13, with conformal deposition. Here, conformal deposition means that the surface morphology of the subsequently deposited first insulating layer 14 is consistent with the surface morphology of the previously deposited first electrode layer 13. In other words, protrusions and depressions on the surface of the first electrode layer 13 also appear as protrusions and depressions at corresponding positions on the first insulating layer 14. It should be noted that the first insulating layer 14 also covers the edge sidewalls of the first electrode layer 13. Figure 1 To clearly show the cross-sectional structure of each layer, the insulating layers on the sidewalls are not depicted in the 3D diagram. In reality, the pads of any layer are isolated from other electrode layers by insulating layers.

[0066] Please continue to refer to this. Figure 7 and Figure 8 A second conductive material layer 15a is formed, which covers the first insulating layer 14. The material of the second conductive material layer 15a is, for example, one of TiNx, NbOx, Al, Mo, AlCu, and Cu, where x is an integer greater than 1. It can be formed using atomic layer deposition (ALD) technology, with the second conductive material layer 15a and the first insulating layer 14 being conformally deposited.

[0067] Figure 9 This is a top view schematic diagram of the MIM capacitor structure after the formation of the second layer electrode according to an embodiment of the present invention. Figure 10 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the second layer of electrodes according to an embodiment of the present invention. Figure 9 and Figure 10 As shown, the second conductive material layer 15a is patterned and etched. Except for the pad patterns to be retained, a predetermined width of the second conductive material layer 15a is removed from both sides of the capacitor region to form the second layer electrode 15 and the second pad 15b. The second pad 15b is located on the first insulating layer 14 and is electrically connected to the second layer electrode 15. The second pad 15b and the first pad 15a are located on different sides of the first layer electrode 13 and the second layer electrode 15, i.e., on opposite sides of the capacitor region. It is worth emphasizing that during the patterning etching of the second conductive material layer 15a, the etching stops at the first insulating layer 14, retaining the first insulating layer 14 to prevent short circuits in the upper electrode.

[0068] Figure 11This is a top view schematic diagram of the MIM capacitor structure after the formation of the third conductive material layer according to an embodiment of the present invention. Figure 12 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the third conductive material layer according to an embodiment of the present invention. Figure 12 As shown, prior to the formation of the third conductive material layer 17a, a second insulating layer 16 is formed, which covers the second layer electrode 15, the second pad 15b, and the first insulating layer 14. The material of the second insulating layer 16 is a high dielectric constant oxide (HKO) layer. x For example, it can be a single-layer structure or multiple stacked structures of hafnium oxide, zirconium oxide, aluminum oxide, and silicon oxide. In other words, hafnium oxide (HfO) can be selected. x Zirconia (ZrO) x ), aluminum oxide (AlO) x ), silicon dioxide (SiO) x ), or a composite system of the above materials (such as hafnium zirconium oxide HfZrO). x Alternatively, a multilayer stacked structure (such as HfO / ZrO / HfO, ZrO / AlO / ZrO, etc.) can be used for deposition. In this embodiment, there is no limitation on the number of stacked layers. It can be formed using atomic layer deposition (ALD) process, with the second insulating layer 16 and the second electrode layer 15 conformally deposited.

[0069] Please continue to refer to this. Figure 11 and Figure 12 A third conductive material layer 17a is formed, which covers the second insulating layer 16. The material of the third conductive material layer 17a is, for example, one of TiNx, NbOx, Al, Mo, AlCu, and Cu, where x is an integer greater than 1. It can be formed using atomic layer deposition (ALD) technology, with the third conductive material layer 17a and the second insulating layer 16 conformally deposited.

[0070] Figure 13 This is a top view schematic diagram of the MIM capacitor structure after the formation of the third electrode layer according to an embodiment of the present invention. Figure 14 This is a cross-sectional schematic diagram of the MIM capacitor structure after the formation of the third electrode layer according to an embodiment of the present invention. Figure 13 and Figure 14As shown, the third conductive material layer 17a is patterned and etched. Except for the pad patterns to be retained, a predetermined width of the third conductive material layer 17a is removed from both sides of the capacitor region to form the third electrode 17 and the third pad 17b. The third pad 17b is located on the second insulating layer 16 and is electrically connected to the third electrode 17. The third pad 17b and the first pad 17b are located on the same side of the first electrode 13 and the second electrode 15, and their projected patterns do not overlap, preferably not overlapping, and more preferably spaced apart, to reduce the difficulty of subsequent contact structure fabrication. It is worth emphasizing that during the patterning etching of the third conductive material layer 17a, the etching stops on the second insulating layer 16, retaining the second insulating layer 16 to avoid short circuits in the upper electrode.

[0071] Figure 15 This is a top view schematic diagram of the MIM capacitor structure after the contact structure is formed according to an embodiment of the present invention. Figure 16 This is a cross-sectional schematic diagram of the MIM capacitor structure after the contact structure is formed according to an embodiment of the present invention. Figure 15 and Figure 16 As shown, after forming the third electrode 17, the method further includes: forming an interlayer dielectric layer 18, which covers the third electrode 17, the third pad 17b, and the second insulating layer 16; the material of the interlayer dielectric layer is, for example, silicon oxide, which can be formed by chemical vapor deposition for gap filling. A first contact hole, a second contact hole, and a third contact hole are formed using a through-hole process. The first contact hole is connected to the first pad, the second contact hole is connected to the second pad, and the third contact hole is connected to the third pad. A first contact structure 13c, a second contact structure 15c, and a third contact structure 17c are formed. The first contact structure 13c is electrically connected to the first pad 13b, the second contact structure 15c is electrically connected to the second pad 15b, and the third contact structure 17c is electrically connected to the third pad 17b. The first contact structure 13c, the second contact structure 15c, and the third contact structure 17c are made of the same material and are at least one of tungsten, aluminum, copper, molybdenum, polycrystalline silicon, and doped polycrystalline silicon.

[0072] In summary, in the MIM capacitor structure provided by the embodiments of the present invention, a dielectric layer and multiple trenches extending through the dielectric layer and into the substrate are formed on the substrate. Each trench extends along a first horizontal direction, and the multiple trenches are arranged along a second horizontal direction. The first direction is perpendicular to the second direction, and the top and bottom corners of each trench are rounded. The multilayer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located in the trenches, and extend to the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to a pad, and the pads of odd-numbered layers and even-numbered layers are located on different sides of the electrode layer in the second direction, and the projections of each pad do not overlap. This invention utilizes a high aspect ratio trench structure, combined with conformal deposition of a high dielectric constant oxide layer and an electrode layer, to fully leverage the surface area of ​​the trench sidewalls and create a three-dimensional MIM capacitor, increasing the effective surface area of ​​the capacitor under area constraints. As the trench aspect ratio increases, higher capacitance density can be achieved. The trench contour is rounded at the corners to prevent breakdown at the trench sidewall corners caused by strong electric fields. Furthermore, leveraging the excellent conformal properties of the deposited thin film, a multi-layer stacked MIM capacitor structure is designed to further enhance the capacitance value of the MIM capacitor structure.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0074] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A MIM capacitor structure, characterized in that, include: A substrate having a dielectric layer formed thereon and a plurality of trenches extending through the dielectric layer and into the substrate, each trench extending along a first horizontal direction, the plurality of trenches being arranged along a second horizontal direction, the first direction being perpendicular to the second direction, and the top and bottom corners of each trench being rounded. A multilayer stacked MIM capacitor structure includes multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench and extending onto the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and even-numbered layers are located on different sides of the electrode layers in a second direction, and the projections of each pad do not overlap.

2. The MIM capacitor structure as described in claim 1, characterized in that, The electrode layers and the multiple pads are made of the same material and are selected from one of TiNx, NbOx, Al, Mo, AlCu, and Cu, where x is an integer greater than 1.

3. The MIM capacitor structure as described in claim 1, characterized in that, The insulating layers are made of the same material and are selected from one or more single-layer structures of hafnium oxide, zirconium oxide, aluminum oxide, and silicon oxide.

4. The MIM capacitor structure as described in claim 1, characterized in that, A contact structure corresponding to an electrical connection is formed on each of the pads.

5. The MIM capacitor structure as described in claim 4, characterized in that, Each of the contact structures is made of the same material and is selected from at least one of tungsten, aluminum, copper, molybdenum, polycrystalline silicon, and doped polycrystalline silicon.

6. A method for forming a MIM capacitor structure, characterized in that, include: A substrate is provided, on which a dielectric layer is formed and a plurality of trenches extending through the dielectric layer and into the substrate, each trench extending along a first horizontal direction and the plurality of trenches arranged along a second horizontal direction, the first direction being perpendicular to the second direction; The top and bottom corners of each of the grooves are rounded. A multilayer stacked MIM capacitor structure is formed, comprising multiple electrode layers, multiple insulating layers, and multiple pads. The multiple electrode layers and multiple insulating layers are sequentially overlapped and conformally deposited, located within the trench and extending onto the dielectric layer. The bottom and top layers of the multilayer stacked MIM capacitor structure are both electrode layers, and the projected patterns of each electrode layer overlap. Each electrode layer is electrically connected to one pad, and the pads of odd-numbered layers and the pads of even-numbered layers are located on different sides of the electrode layers in the second direction, and the projections of each pad do not overlap.

7. The method for forming a MIM capacitor structure as described in claim 6, characterized in that, The steps for forming a multilayer stacked MIM capacitor structure include: A conductive material layer is formed, which is located on the bottom and sidewalls of the trench and extends to the dielectric layer; The conductive material layer is patterned and etched to remove the conductive material layer with a preset edge width, while retaining the pad pattern to form the electrode layer and the corresponding electrical connection pads.

8. The method for forming a MIM capacitor structure as described in claim 7, characterized in that, The steps for forming a multilayer stacked MIM capacitor structure also include: An insulating layer is formed, which covers the electrode layer and serves to isolate the electrode layers above and below.

9. The method for forming a MIM capacitor structure as described in claim 6, characterized in that, The electrode layer and the insulating layer are formed by conformal deposition using atomic layer deposition (ALD).

10. The method for forming a MIM capacitor structure as described in claim 6, characterized in that, Following the step of forming the top electrode layer, the method further includes: An interlayer dielectric layer is formed, which covers the top electrode layer, each of the pads, and the dielectric layer; Multiple contact holes are formed, each of the contact holes exposing one of the pads; The contact holes are filled to form a plurality of contact structures, each of the contact structures being electrically connected to one of the pads.

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