Heterojunction bipolar transistor, radio frequency module, and communication device

Abstract

Embodiments of the present application provide a heterojunction bipolar transistor, a radio frequency module and a communication device, the heterojunction bipolar transistor comprising: a sub-collector layer, a base region step arranged on the sub-collector layer, a base metal arranged on the base region step, and a collector metal arranged on the sub-collector layer; the base region step has a step top surface and a step side surface; the step side surface comprises a first side surface; wherein, an outer edge of a one of the base metal and the step top surface which is closer to the collector metal in the first direction is defined as a step top edge; a spacing distance between the step top edge and the collector metal in the first direction is defined as a first lateral distance; a concave part is formed on the first side surface, so that the first lateral distance is less than or equal to 1 μm. The control of the lateral spacing between the collector metal and the base region step top is realized by the concave part, which can reduce the base-collector resistance Rc, thereby improving the PAE.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a heterojunction bipolar transistor, a radio frequency module, and a communication device. Background Technology

[0002] Heterojunction bipolar transistors (HBTs) are widely used in high-frequency electronic devices such as RF power amplifiers and satellite communications due to their excellent high-frequency characteristics, high current gain, and high power density. Power-added efficiency (PAE), a core indicator for measuring the energy efficiency of HBTs and their corresponding power amplifier circuits, directly determines the battery life, heat dissipation stress, and operational stability of electronic devices. Therefore, improving the PAE level of HBTs is one of the core directions in the current development of RF devices. Furthermore, with the rapid development of high-frequency electronic devices towards miniaturization, high power, and low power consumption, even higher requirements are placed on the PAE level of HBTs. Summary of the Invention

[0003] Therefore, embodiments of the present invention provide a heterojunction bipolar transistor, a radio frequency module, and a communication device. By controlling the lateral spacing between the collector metal and the top of the base region step through the recessed portion, the base-collector resistance Rc can be reduced, thereby improving the PAE.

[0004] This invention provides a heterojunction bipolar transistor, comprising: a secondary collector layer having a first surface; A base region step is disposed on the first surface; the base region step includes a collector layer, a base layer and an emitter layer stacked sequentially along the thickness direction; the surface of the emitter layer away from the base layer forms a top surface of the step; the base region step has a side surface of the step adjacent to the top surface of the step; the side surface of the step includes a first side surface; An emitter step is disposed on the top surface of the step and connected to the emitter layer; Emitter metal is disposed on the emitter step; A base metal is disposed on the base region step and connected to the base layer; The collector metal is partially disposed on the first surface and adjacent to the first side surface along the first direction; Wherein, the outer edge of the one that is closer to the collector metal than the base metal and the top surface of the step along the first direction is defined as the top edge of the step; the interval between the top edge of the step and the collector metal along the first direction is defined as the first lateral distance; and a concave portion is formed on the first side surface such that the first lateral distance is less than or equal to 1 μm.

[0005] This invention also provides a radio frequency module, including the aforementioned heterojunction bipolar transistor.

[0006] This invention also provides a communication device, including the aforementioned radio frequency module.

[0007] The above embodiments of the present invention have at least one or more of the following beneficial effects: by forming a recess on the first side of the base region step, and achieving a first lateral distance of less than or equal to 1 μm based on the recess, the current path between the base metal and the collector metal is shortened while the thickness of the base region step remains unchanged, thereby reducing the base-collector resistance Rc and improving the PAE of the device. Attached Figure Description

[0008] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0009] Figure 1 This is a top view of a heterojunction bipolar transistor provided in one embodiment of the present invention.

[0010] Figure 2 for Figure 1 The diagram shows a cross-sectional view (AA) of a heterojunction bipolar transistor.

[0011] Figure 3 To and Figure 2 A schematic diagram of a modified embodiment corresponding to a specific viewpoint.

[0012] Figure 4 To and Figure 2 A schematic diagram of another modified embodiment corresponding to the viewpoint.

[0013] Figure 5 for Figure 2 A structural schematic diagram of another modified embodiment corresponding to the viewpoint.

[0014] Figure 6 This is a schematic diagram of an intermediate structure during the fabrication process of a heterojunction bipolar transistor.

[0015] Figure 7 for Figure 6 The diagram shows the structure obtained by proceeding to the next preparation step from the intermediate structure shown.

[0016] Figure 8 This is a schematic diagram of a heterojunction bipolar transistor in a related technology.

[0017] Figure 9 In one specific embodiment Figure 2 A magnified view of the local dimensions.

[0018] Figure 10In one specific embodiment Figure 2 A magnified view of the local dimensions.

[0019] Figure 11 This is a schematic diagram of the black-white cross-section of a heterojunction bipolar transistor in one embodiment.

[0020] Figure 12 This is a schematic diagram of the black-white cross-section of a heterojunction bipolar transistor in one embodiment.

[0021] Figure 13 In one specific embodiment Figure 2 A magnified view of the local dimensions.

[0022] [Explanation of Labels in the Attached Image] 100. Heterojunction bipolar transistor; 10. Substrate; 20. Secondary collector layer; 21. First surface; 30. Base step; 31. Collector layer; 32. Base layer; 33. Emitter layer; 341. First side surface; 3411. First side surface segment; 3412. Second side surface segment; 3413. Third side surface segment; 3414. Recessed portion; 3415. Seventh side surface segment; 3416. Eighth side surface segment; 342. Second side surface; 3421. Fourth side surface segment; 3422. Fifth side surface segment; 3423. Sixth side surface segment; 35. Step top surface; 36. Etch stop layer; 40. Base metal; 41. Suspended portion; 42. Finger; 421. Edge finger; 422. Middle finger; 43. Connector; 51. Emitter step; 52. Emitter metal; 60. Collector metal. Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0027] Reference Figure 1 and Figure 2 This invention provides a heterojunction bipolar transistor 100, which includes a secondary collector layer 20, a base region step 30, a base metal 40, an emitter step 51, an emitter metal 52, and a collector metal 60.

[0028] The secondary collector layer 20 has a first surface 21. In some embodiments, the heterojunction bipolar transistor 100 further includes a substrate 10, on which the secondary collector layer 20 is disposed, and the first surface 21 is the surface of the secondary collector layer 20 facing away from the substrate 10. In some embodiments, the heterojunction bipolar transistor 100 further includes an etch stop layer 36 disposed on the secondary collector layer 20.

[0029] The substrate 10 may be made of a III-V semiconductor, such as any one or a combination of GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs.

[0030] The secondary collector layer 20 can be, for example, a III-V semiconductor, including III-V semiconductors such as GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs, or any combination of multiple of them. The secondary collector layer 20 can be a multilayer structure.

[0031] The etch stop layer 36 can be, for example, a III-V semiconductor, such as any one or a combination of GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs.

[0032] A base region step 30 is disposed on the first surface 21. The base region step 30 includes a collector layer 31, a base layer 32 and an emitter layer 33 stacked sequentially along the thickness direction.

[0033] The collector layer 31 can be, for example, a III-V group semiconductor, such as any one or a combination of GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs. The collector layer 31 can be a multilayer structure.

[0034] The base layer 32 can be, for example, a III-V group semiconductor, such as any one or a combination of GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs. The base layer 32 can be a multilayer structure.

[0035] The emitter layer 33 can be, for example, a III-V group semiconductor, such as any one or a combination of GaN, SiC, C (diamond), Ga2O3, AlGaN, AlN, GaAs, GaAsSb, AlGaAs, InP, InGaP, InGaAs, AlAs, and InAlAs. The emitter layer 33 can be a multilayer structure. A stepped top surface 35 is formed on the surface of the emitter layer 33 away from the base layer 32.

[0036] The base step 30 has a step side adjacent to the step top surface 35. The step side includes two first side surfaces 341 arranged opposite each other along a first direction (Y direction), and two second side surfaces 342 arranged opposite each other along a second direction (X direction). The first direction is perpendicular to the second direction. The second side surfaces 342 are adjacent to the first side surfaces 341 and the step top surface 35, respectively. A recess 3414 is formed on the first side surface 341.

[0037] The secondary collector layer 20, collector layer 31, and emitter layer 33 are doped with a first doping type, while the base layer 32 is doped with a second doping type. When the first doping type is n-type, the second doping type is p-type. When the first doping type is p-type, the second doping type is n-type.

[0038] An emitter step 51 is disposed on the top surface 35 of the step and connected to the emitter layer 33. An emitter metal 52 is disposed on the emitter step 51. The emitter step 51 can be multilayered, for example, including an InGaAs cap layer and a GaAs transition layer. The InGaAs layer is used to provide an ohmic contact for the emitter metal; the GaAs layer is used to solve the lattice matching problem between the InGaAs cap layer and the InGaP emitter layer. The emitter metal 52 can be a conductive metal such as Ti, Pt, Au, Al, Cu, W, Ni, or Ge. Figure 1 and Figure 2 The width of the emitter metal 52 shown may not be equal to the width of the emitter step 51; however, in some embodiments, the width of the emitter metal 52 may be equal to the width of the emitter step 51. Multiple emitter steps 51 and multiple emitter metals 52 may be provided.

[0039] The base metal 40 is disposed on the base step 30 and connected to the base layer 32. The base metal 40 can be a multilayer metal consisting of Pt / Ti / Pt / Au / Ti stacks. Specifically, for example... Figure 1 As shown, the base metal 40 includes a connecting portion 43 and a plurality of fingers 42. (As...) Figure 2 The finger portion 42 shown can be two, such as Figure 3 The number of fingers 42 shown can be three, consisting of two edge fingers 421 and a middle finger 422 located between the two edge fingers 421. Of course, the number of fingers 42 can also be other than that shown in this embodiment. A connecting portion 43 extends along a first direction, and each finger 42 extends along a second direction. Multiple fingers 42 are arranged at intervals along the first direction and connected by the connecting portion 43. An emitter step 51 and an emitter metal 52 are provided between two adjacent fingers 42. In some embodiments, the base metal 40 contacts and connects to the base layer 32 through an opening on the emitter layer 33. Alternatively, the base metal 40 is alloyed with the emitter layer 33 and then connected to the base layer 32.

[0040] The collector metal 60 is at least partially disposed on the first surface 21 and adjacent to the first side surface 341 along the first direction. For example Figure 1 and Figure 2 As shown, a collector metal 60 is disposed on each of two opposite sides of the base region step 30 along the first direction, and each collector metal 60 is adjacent to and spaced apart from a corresponding first side surface 341. The collector metal 60 is, for example, an AuGe / Ni / Au or Au / Ge / Ni / Au metal stack structure. In some embodiments, refer to Figure 4The collector metal 60 is partially embedded in the secondary collector layer 20. This increases the contact area between the collector metal 60 and the secondary collector layer 20, reducing the Rc resistance. In some embodiments, the secondary collector layer 20 includes a bulk material layer and at least one low-bandgap semiconductor material, the bandgap of which is lower than the bandgap of the bulk material layer. The low-bandgap semiconductor material layer can be made of materials such as InGaAs and / or GaAsSb. The collector metal 60 forms an ohmic contact with the at least one low-bandgap semiconductor material layer, further reducing the collector contact resistance based on the low bandgap of the low-bandgap semiconductor material.

[0041] [First Embodiment] The outer edge of the one that is closer to the collector metal 60 along the first direction, between the base metal 40 and the step top surface 35, is defined as the top edge of the step. (Refer to...) Figure 2 The first lateral distance L1 is defined as the distance between the top edge of the step and the collector metal 60 along the first direction. In the first embodiment, a recess 3414 is formed on the first side surface 341, such that the first lateral distance L1 is less than or equal to 1 μm. For example, the first lateral distance L1 can be 0.9 μm, 0.8 μm, 0.7 μm, 0.5 μm, 0.4 μm, 0.3 μm, etc. In some embodiments, the first lateral distance is greater than or equal to 0.3 μm.

[0042] For example, refer to Figure 2 The base metal 40 is located within the edge of the top surface 35 of the step, corresponding to the collector metal 60 on the same side. The distance between the edge of the top surface 35 of the step and the collector metal 60 along the first direction is smaller. Therefore, the outer edge of the top surface 35 of the step is the top edge of the step. For each collector metal 60, the distance between the outer edge of the top surface 35 of the step and the collector metal 60 along the first direction is the first lateral distance L1. For example, corresponding to... Figure 2 The horizontal distance between the left edge of the top surface 35 of the step and the left collector metal 60 on the left is the first lateral distance L1. Figure 2 The horizontal distance between the right edge of the right collector metal 60 and the right edge of the step top surface 35 and the right collector metal 60 is the first lateral distance L1.

[0043] For example, refer to Figure 5In some embodiments, the base metal 40 extends beyond the edge of the top surface 35 of the step to form a suspended portion 41. In a first direction, the suspended portion 41 is located between the collector metal 60 and the base region step 30. For the collector metal 60 on the same side, the edge of the suspended portion 41 (i.e., the edge of the base metal 40) is closer to the collector metal 60 along the first direction. Therefore, the outer edge of the suspended portion 41 is the top edge of the step. For each collector metal 60, the distance between the outer edge of the suspended portion 41 on the same side and the collector metal 60 along the first direction is a first lateral distance L1. For example, corresponding to… Figure 5 The horizontal distance from the left edge of the left-side suspended portion 41 to the left-side collector metal 60 is the first lateral distance L1. Figure 5 The horizontal distance from the right edge of the right-side collector metal 60 and the right-side suspended portion 41 to the right-side collector metal 60 is the first lateral distance L1.

[0044] The heterojunction bipolar transistor 100 provided in the first embodiment forms a recess 3414 on the first side 341 of the base region step 30. Based on the recess 3414, the first lateral distance L1 is less than or equal to 1 μm. This shortens the current path between the base metal 40 and the collector metal 60 while keeping the thickness of the base region step 30 unchanged, thereby reducing the base-collector resistance Rc. Since PAE is strongly correlated with base-collector resistance, the heterojunction bipolar transistor 100 can effectively improve the device's PAE.

[0045] The heterojunction bipolar transistor 100 provided in this application embodiment can be obtained through a combination of dry etching and wet etching. Specifically, for Figure 6 The intermediate structure shown is subjected to dry etching to obtain, as shown Figure 7 The structure shown, Figure 7 In the middle, a portion of the collector layer 31 remains unetched. Then... Figure 7 The structure shown is subjected to wet etching. During the wet etching process, a structure like this can be formed. Figure 2 The structure shown can increase the degree of concavity of the concave portion 3414 by increasing the wet process time, thereby allowing the collector metal 60 to be set closer to the base region step 30, and thus controlling the first lateral distance L1 to be less than or equal to 1 μm.

[0046] For example in Figure 2In the first side surface 341, there are three sequentially connected side surface segments 3411, 3412, and 3413. The first side surface segment 3411 is connected to the top surface 35 of the step. In a first direction, the first side surface segment 3411 is inclined towards the collector metal 60. The second side surface segment 3412 and the third side surface segment 3413 together form a recess 3414. The first lateral distance L1 is the distance between the outer edge of the top surface 35 of the step and the collector metal 60 in the first direction. The first side surface segment 3411 is formed by a dry etching step, while the second side surface segment 3412, the third side surface segment 3413, and the recess 3414 are formed by a wet etching step.

[0047] By adjusting the height of the dry etching and the duration of the wet etching, the degree of concavity of the recess 3414 can be further increased, for example, to the extent that... Figure 5 The structure shown. Figure 5 In the first side surface 341, a seventh side surface segment 3415 and an eighth side surface segment 3416 are connected sequentially. The seventh side surface segment 3415 is connected to the top surface 35 of the step, and the eighth side surface segment 3416 is connected to the first surface 21. The seventh side surface segment 3415 and the eighth side surface segment 3416 together form a recess 3414. The seventh side surface segment 3415, the eighth side surface segment 3416, and the recess 3414 are all formed by wet etching. At this time, the base metal 40 forms a suspended portion 41, and the width of the suspended portion 41 along the first direction is referenced. Figure 5 The width of the base metal 40 (the width of the finger 42 where the suspended portion 41 is located) is shown in the figure. Figure 5 The ratio of W1 to W2 is less than or equal to 0.5. For example, if W2 is 1.0 μm, then W1 is less than or equal to 0.5 μm. Figure 5 In this process, due to the reduced bottom width of the base region step 30, the distance between the collector metal 60 and the base region step 30 can be further reduced. Figure 5 In the illustrated embodiment, the first lateral distance L1 can be as small as 0.1 μm. This also allows for further reduction of the BC junction capacitance Cbc, further improving device performance.

[0048] In related technologies, base region steps can be fabricated using a two-step wet etching process. However, due to poor process stability, the dimensions of the base region steps fluctuate greatly and are difficult to control precisely, significantly impacting the electrical performance stability and reliability of the device. To avoid the large variations in the bottom dimensions of the base region steps caused by the large process fluctuations in the two-step wet etching process, the lateral spacing between the collector metal and the base region steps needs to be appropriately widened, resulting in a larger base-collector resistance Rc.

[0049] In another related technology, the base region step can be obtained by dry etching directly to the etch stop layer 36. Dry etching typically involves a specific etching angle; therefore, the side of the step formed after dry etching exhibits a shape similar to... Figure 8 The slope shown is such that, due to the fixed etching angle, the width of the base region step increases as it descends closer to the secondary collector layer. Changing the etching angle to make the step sides steeper would be detrimental to metal interconnection. Therefore, as... Figure 8 The lateral distance L1' shown cannot be reduced further. If the collector layer is thicker, the lateral distance L1' will be larger, and the base-collector resistance Rc will also be larger.

[0050] In this embodiment, the base region step 30 is formed by the above-mentioned dry etching + wet etching process, and the recess 3414 is formed so that the distance between the collector metal 60 and the base region step 30 is reduced to less than 1.0 μm, which can reduce the base-collector resistance Rc and improve the device PAE.

[0051] In some embodiments, refer to Figure 2 Along the first direction, the recessed portion 3414 is located between the base metal 40 and the collector metal 60. (Refer to...) Figure 2 In the first direction, the left-side recess 3414 is recessed to the right, and its apex angle does not exceed the left edge of the base metal 40; the right-side recess 3414 is recessed to the left, and its apex angle does not exceed the right edge of the base metal 40. This further ensures that the current path within the base region step 30 is as small as possible, thereby ensuring a lower base-collector resistance Rc, and thus ensuring a higher PAE. Of course, in other embodiments, for example… Figure 3 In the embodiment shown, a deeper recess 3414 is beneficial for shortening the current path between the middle finger 422 of the base metal 40 and the collector metal 60, so the degree of recess of the recess 3414 is not limited by this.

[0052] Reference Figure 9 The second lateral distance L2 is defined as the distance between the boundary between the second side segment 3412 and the third side segment 3413 (i.e., the apex corner of the recessed portion 3414) and the collector metal 60 along the first direction. The third lateral distance L3 is defined as the distance between the boundary between the third side segment 3413 and the first surface 21 and the collector metal 60 along the first direction. The third lateral distance L3 is less than the second lateral distance L2. The third lateral distance L3 can be made less than the second lateral distance L2 by controlling the depth of the side etching during wet etching. Similarly, controlling the third lateral distance L3 to be less than L2 can control the depth of wet etching. Therefore, the etching degree of the base step 30 along the second direction can be controlled, avoiding excessive etching that may affect the interconnect metal traces.

[0053] In some embodiments, the third lateral distance L3 is greater than or equal to 0.1 μm. This ensures that the collector metal 60 and the base step 30 are spaced apart, preventing the collector metal 60 from contacting the base step 30 during fabrication, which could affect the reverse breakdown voltage (BVCBO) of the collector-base junction and cause device reliability failures.

[0054] [Second Embodiment] Reference Figure 10 The first side surface 341 of the heterojunction bipolar transistor 100 provided in the second embodiment of the present invention includes a first side surface segment 3411, a second side surface segment 3412, and a third side surface segment 3413 connected in sequence. The first side surface segment 3411 is connected to the top surface 35 of the step. Furthermore, in a first direction, the first side surface segment 3411 is inclined along a direction gradually approaching the collector metal 60. The second side surface segment 3412 and the third side surface segment 3413 together form a recess 3414. (Refer to...) Figure 11 The second side surface 342 includes a fourth side surface segment 3421, a fifth side surface segment 3422, and a sixth side surface segment 3423 connected in sequence. The fourth side surface segment 3421 is connected to the top surface 35 of the step. The sixth side surface segment 3423 is connected to the first surface 21. In the second direction, the fourth side surface segment 3421 and the sixth side surface segment 3423 are inclined away from the top surface 35 of the step. The inclination angle between the first side surface segment 3421 and the first surface 21 is defined as the first included angle (refer to...). Figure 10 (middle angle a). Define the included angle between the second lateral segment 3412 and the third lateral segment 3413 as the second included angle (refer to...). Figure 10 (middle angle b). Define the included angle between the third side surface segment 3413 and the first surface 21 as the third included angle (refer to...). Figure 10 (C) The included angle between the fourth side segment 3421 and the first surface 21 is defined as the fourth included angle (refer to...). Figure 11 (middle angle d), define the angle between the sixth side segment 3423 and the first surface 21 as the fifth included angle (refer to) Figure 11 (e) of the middle angle.

[0055] In some embodiments, the first included angle ranges from 60° to 75° (for example, it can be 60°, 63°, 65°, 66°, 70°, 75°, etc.), the second included angle ranges from 90° to 150° (for example, it can be 90°, 100°, 110°, 115°, 120°, etc.), and the third included angle ranges from 20° to 50° (for example, it can be 20°, 25°, 30°, 40°, 50°, etc.).

[0056] The heterojunction bipolar transistor 100 provided in the second embodiment of this application can be obtained by a combination of dry etching and wet etching. Specifically, for Figure 6 The intermediate structure shown is subjected to dry etching to obtain, as shown Figure 7 The structure shown, Figure 7 In the middle, a portion of the collector layer 31 remains unetched, and then... Figure 7 The structure shown is subjected to wet etching. The range of the first included angle can be controlled by controlling the composition, ratio, and radio frequency power of the etching gas during dry etching; the range of the second and third included angles can be controlled by adjusting the thickness ratio of dry etching and wet etching, the wet etching time, and the concentration of the etching solution.

[0057] In the second embodiment, by setting the range of the first included angle, the second included angle and the third included angle, it is possible to ensure that the recessed portion 3414 has a suitable degree of concavity so that the lateral distance between the collector metal 60 and the base metal 40 is smaller, the current path between the base metal 40 and the collector metal 60 is shortened, the base-collector resistance Rc is reduced, and the PAE of the device is effectively improved.

[0058] In some embodiments, the ratio of the first included angle to the second included angle ranges from 0.4 to 0.85 (for example, it can be 0.4, 0.43, 0.5, 0.67, 0.7, 0.8, 0.83, etc.), and the ratio of the second included angle to the third included angle ranges from 1.5 to 8 (for example, it can be 1.5, 2, 2.2, 3, 4.5, 6.1, 7.5, etc.). In some embodiments, the fourth included angle ranges from 60° to 75° (for example, it can be 60°, 67°, 70°, 75°, etc.). The fifth included angle is smaller than the fourth included angle, and the range of the fifth included angle is 30° to 60° (for example, it can be 30°, 42°, 50°, 60°, etc.). The fifth side segment 3422 is parallel to the first surface 21.

[0059] Since both the fourth side segment 3421 and the first side segment 3411 are obtained through a dry etching process, the fourth included angle is the same as the first included angle. By setting the range of the first and fourth included angles, the fourth side segment 3421 can be prevented from being too steep, which could lead to problems such as cracks, voids, or even breaks when the interconnect metal traces cross the base region step 30, affecting current flow and causing device failure, thus ensuring the reliability of subsequent processes. Furthermore, the fourth side segment 3421 can be prevented from being too gentle, which could result in an excessively large width of the base region step 30 along the second direction, leading to problems such as a large BC junction capacitance Cbc and collector-emitter offset voltage Vceoff.

[0060] Based on the angle range of the first included angle, the aforementioned range of the second included angle or the range of the ratio of the first included angle to the second included angle is set as described above. This ensures that the degree of concavity of the recessed portion 3414 is appropriate, minimizing the lateral distance between the collector metal 60 and the base metal 40, while avoiding excessive concavity that could adversely affect device stability. Reducing the distance between the apex of the recessed portion 3414 (i.e., the junction of the second side segment 3412 and the third side segment 3413) and the top surface 35 of the step facilitates a smaller rate of change in the BC junction capacitance Cbc under different bias voltages, thereby improving the device performance of the heterojunction bipolar transistor.

[0061] By further setting the range of the third included angle or the ratio range of the second included angle to the third included angle as described above, it is possible to ensure that the width of the bottom of the base area step 30 (where the base area step 30 is connected to the first surface 21) is smaller, which is beneficial to setting the collector metal 60 closer to the base area step 30, thereby ensuring a smaller lateral distance between the collector metal 60 and the base metal 40.

[0062] Further adjustments to the fifth included angle make the area between the fourth side section 3421 and the sixth side section 3423 gradually flatten out. The two-slope design avoids the problem that if the fourth side section 3421 is steep, the interconnect metal traces are prone to breakage, while if it is flat, the width of the base area step 30 along the second direction will increase. This balances the stability of the metal traces and the size of the device.

[0063] [Third Embodiment] In the third embodiment, refer to Figure 12 The second side surface 342 includes a fourth side surface segment 3421, a fifth side surface segment 3422, and a sixth side surface segment 3423 connected in sequence. The fourth side surface segment 3421 is connected to the top surface 35 of the step. The sixth side surface segment 3423 is connected to the first surface 21. In the second direction, the fourth side surface segment 3421 and the sixth side surface segment 3423 are inclined in a direction that gradually moves away from the top surface 35 of the step.

[0064] In the third embodiment, the height of the fourth side segment 3421 (refer to...) Figure 12 (middle h1) and the total thickness of the base step 30 (refer to h1) Figure 12 The ratio of H to H is greater than 0.67 and less than 0.85. For example, it can be 0.69, 0.75, 0.81, etc.

[0065] The heterojunction bipolar transistor 100 provided in this embodiment can be obtained through a combination of dry etching and wet etching. In this embodiment, the height of the fourth side segment 3421 is the total thickness of the stack of collector layer 31, base layer 32, and emitter layer 33 etched during dry etching. By designing the height of the fourth side segment 3421, the thickness of the wet etching can be reduced, ensuring uniformity and process stability throughout the surface during subsequent wet etching. The side etching generated during wet etching in the second direction can be controlled to ensure that the interconnect metal traces cross the base step 30. If the h1 / H ratio is less than 0.67, excessive wet etching leads to poor process stability and is detrimental to uniform etching throughout the surface. If the h1 / H ratio is greater than 0.85, excessive dry etching results in a greater downward extension of the base step side, leading to a larger lateral distance between the collector metal and the top of the base step, and a smaller reduction in Rc resistance.

[0066] [Fourth Embodiment] Reference Figure 13 The first side surface 341 of the heterojunction bipolar transistor 100 provided in the fourth embodiment of the present invention includes a first side surface segment 3411, a second side surface segment 3412, and a third side surface segment 3413 connected in sequence. The first side surface segment 3411 is connected to the top surface 35 of the step. In a first direction, the first side surface segment 3411 is inclined along the direction gradually approaching the collector metal 60. The second side surface segment 3412 and the third side surface segment 3413 together form a recess 3414.

[0067] The inclination angle between the first side segment 3411 and the first surface 21 is defined as the first included angle (refer to...). Figure 13 (middle angle α). The ratio of the height of the base step 30 to the tangent of the first included angle is defined as the fourth lateral distance L4, i.e., L4 = H / tan ∠α. In the fourth embodiment, the concave portion 3414 makes the first lateral distance L1 less than or equal to the fourth lateral distance L4.

[0068] In some embodiments, the second side surface 342 includes a fourth side surface segment 3421, a fifth side surface segment 3422, and a sixth side surface segment 3423 connected sequentially. The fourth side surface segment 3421 is connected to the top surface 35 of the step. The sixth side surface segment 3423 is connected to the first surface 21. In the second direction, the fourth side surface segment 3421 and the sixth side surface segment 3423 are inclined in a direction gradually moving away from the top surface 35 of the step. The inclination angle between the fourth side surface segment 3421 and the first surface 21 is the fourth included angle (refer to...). Figure 11 The angle d in the figure. Based on the equality of the first included angle and the fourth included angle, the ratio of the tangent of the first and fourth included angles of the height of the base step 30 can also be defined as the fourth lateral distance, i.e., L4 = H / tan ∠d. In some embodiments, the first lateral distance L1 is less than or equal to the fourth lateral distance L4. See reference Figure 13That is, the first side segment 3411 extends to the first surface 21 and intersects with the first surface 21 at the boundary O, and the collector metal 60 is at least partially located between the boundary O and the base region step 30. Figure 8 As can be seen, in this embodiment, the bottom of the base step 30 is recessed by forming the concave portion 3414 (e.g., by...). Figure 13 The boundary line O is shifted to the left to the vertex of the third included angle, thereby reducing the lateral distance between the collector metal 60 and the top of the base step 30 from necessarily greater than L4 to less than or equal to L4. This can shorten the current path and reduce the base-collector resistance.

[0069] Some embodiments of the present invention also provide a radio frequency (RF) module, including a heterojunction bipolar transistor (HBT) provided in any of the foregoing embodiments or a HBT fabricated by the fabrication method of the HBT provided in any of the foregoing embodiments. The RF module may be, for example, an integrated RF switch or filter. The RF module provided in this embodiment has at least the same effects as a HBT, which will not be elaborated further here.

[0070] Some embodiments of the present invention also provide a communication device, including the aforementioned radio frequency module. The communication device may be, for example, a mobile phone, a WiFi wireless router, etc. It has at least the same effects as the aforementioned heterojunction bipolar transistor, and will not be described in detail here. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that, include: Secondary collector layer, the secondary collector layer having a first surface; A base region step is disposed on the first surface; the base region step includes a collector layer, a base layer and an emitter layer stacked sequentially along the thickness direction; the surface of the emitter layer away from the base layer forms a top surface of the step; the base region step has a side surface of the step adjacent to the top surface of the step; the side surface of the step includes a first side surface; An emitter step is disposed on the top surface of the step and connected to the emitter layer; An emitter metal is disposed on the emitter step; A base metal is disposed on the base region step and connected to the base layer; The collector metal is partially disposed on the first surface and adjacent to the first side surface along the first direction; Wherein, the outer edge of the one that is closer to the collector metal than the base metal and the top surface of the step along the first direction is defined as the top edge of the step; the interval between the top edge of the step and the collector metal along the first direction is defined as the first lateral distance; and a concave portion is formed on the first side surface such that the first lateral distance is less than or equal to 1 μm.

2. The heterojunction bipolar transistor as described in claim 1, characterized in that, The first lateral distance is greater than or equal to 0.3 μm.

3. The heterojunction bipolar transistor as described in claim 1, characterized in that, The first side surface includes a first side segment, a second side segment, and a third side segment connected in sequence; the first side segment is connected to the top surface of the step; and in the first direction, the first side segment is inclined along the direction of gradually approaching the current collector metal; the second side segment and the third side segment together form the concave portion; the first lateral distance is the distance between the outer edge of the top surface of the step approaching the current collector metal along the first direction and the current collector.

4. The heterojunction bipolar transistor as described in claim 3, characterized in that, The angle of inclination between the first side segment and the first surface is defined as the first included angle; the angle between the second side segment and the third side segment is defined as the second included angle; the angle between the third side segment and the first surface is defined as the third included angle; the range of the first included angle is 60°~75°, the range of the second included angle is 90°~150°, and the range of the third included angle is 20°~50°.

5. The heterojunction bipolar transistor as described in claim 3, characterized in that, The angle of inclination between the first side segment and the first surface is defined as the first included angle; the angle between the second side segment and the third side segment is defined as the second included angle; the angle between the third side segment and the first surface is defined as the third included angle; the ratio of the first included angle to the second included angle is in the range of 0.4 to 0.85, and the ratio of the second included angle to the third included angle is in the range of 1.5 to 8.

6. The heterojunction bipolar transistor as described in claim 3, characterized in that, The side of the step also includes a second side adjacent to the top surface of the step and the first side; the second side includes a fourth side segment, a fifth side segment and a sixth side segment connected in sequence; the fourth side segment is connected to the top surface of the step; the sixth side segment is connected to the first surface; the fourth side segment and the sixth side segment are inclined in a direction that gradually moves away from the top surface of the step in a second direction; the second direction is perpendicular to the first direction.

7. The heterojunction bipolar transistor as described in claim 6, characterized in that, The angle between the fourth side segment and the first surface is defined as the fourth included angle, and the range of the fourth included angle is 60°~75°.

8. The heterojunction bipolar transistor as described in claim 7, characterized in that, The angle between the sixth side segment and the first surface is defined as the fifth angle, which is smaller than the fourth angle and ranges from 30° to 60°.

9. The heterojunction bipolar transistor as described in claim 6, characterized in that, Along the thickness direction, the ratio of the height of the fourth side segment to the total thickness of the base step is greater than 0.67 and less than 0.

85.

10. The heterojunction bipolar transistor as claimed in claim 1, characterized in that, The first side surface includes a seventh side surface segment and an eighth side surface segment connected in sequence; the seventh side surface segment connects to the top surface of the step, and the eighth side surface segment connects to the first surface, the seventh side surface segment and the eighth side surface segment together form the concave portion; the base metal includes a suspended portion, which is located between the base region step and the current collector metal along the first direction; along the first direction, the ratio of the width of the suspended portion to the width of the base metal is less than or equal to 0.5; the first lateral distance is the interval distance between the suspended portion and the current collector metal along the first direction.

11. The heterojunction bipolar transistor as described in claim 3, characterized in that, The distance between the boundary between the second side segment and the third side segment and the collector electrode along the first direction is defined as the second lateral distance; the distance between the boundary between the third side segment and the first surface and the collector electrode along the first direction is defined as the third lateral distance, and the third lateral distance is less than the second lateral distance.

12. The heterojunction bipolar transistor as claimed in claim 11, characterized in that, The third lateral distance is greater than or equal to 0.1 μm.

13. The heterojunction bipolar transistor as described in claim 3, characterized in that, The inclination angle between the first side segment and the first surface is defined as the first included angle; the ratio of the height of the base step to the tangent of the first included angle is defined as the fourth lateral distance, and the first lateral distance is less than or equal to the fourth lateral distance.

14. A heterojunction bipolar transistor, characterized in that, include: Secondary collector layer, the secondary collector layer having a first surface; A base region step is disposed on the first surface; the base region step includes a collector layer, a base layer and an emitter layer stacked sequentially along the thickness direction; the surface of the emitter layer away from the base layer forms a step top surface; the base region step has a step side surface adjacent to the step top surface; the step side surface includes an adjacent first side surface and a second side surface; An emitter step is disposed on the top surface of the step and connected to the emitter layer; An emitter metal is disposed on the emitter step; A base metal is disposed on the base region step and connected to the base layer; A collector metal is disposed on the first surface and adjacent to the first side surface along a first direction; The second side includes a fourth side segment connected to the top surface of the step, which is inclined in the first direction away from the top surface of the step. The outer edge of the one that is closer to the collector metal than the base metal in the first direction is defined as the top edge of the step. The distance between the top edge of the step and the collector metal in the first direction is defined as the first lateral distance. The angle between the fourth side segment and the first surface is defined as the fourth angle. The ratio of the height of the base step to the tangent of the first angle is defined as the fourth lateral distance, and the first lateral distance is less than or equal to the fourth lateral distance.

15. A radio frequency module, characterized in that, Including the heterojunction bipolar transistor as described in any one of claims 1 to 14.

16. A communication device, characterized in that, Includes the radio frequency module as described in claim 15.

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