An adaptive floating P-zone short-circuit tolerant LIGBT

Abstract

This invention discloses an adaptive floating P-region short-circuit resistant LIGBT, comprising a device substrate (1), an SOI oxide layer (2), a floating P2 region (3), a self-biased NMOS P-type substrate (4), a self-biased NMOS source (5), a self-biased NMOS gate oxide layer (6), a self-biased NMOS drain (7), a LIGBT P-barrier (8); an emitter P+ region (9), an N-type carrier storage layer (10), an emitter N+ region (11), a trench gate (12), a floating P+ region (13), a floating P1 region (14), a collector P+ region (15), an N-type buffer layer (16), and a drift region (17). By introducing dual floating P-regions and a self-biased NMOS, this device enables the floating P-region to adapt to the device's operating state and change its potential. Under forward withstand voltage or high current, it automatically enters a low potential extended depletion layer; during normal conduction, it accumulates charge carriers in a floating state, thereby improving the device's withstand voltage and short-circuit withstand time while maintaining a low on-state voltage drop, effectively enhancing the device's operational reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a short-circuit resistant LIGBT device with an adaptive floating P-region. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) combines the advantages of MOSFET and Bipolar Junction Transistor (BJT), offering low drive power, fast switching speed, and strong current capability. It is mainly targeted at the medium-to-high power and medium-to-high frequency market and is widely used in industrial, automotive electronics, and consumer electronics fields.

[0003] One of the most common failures of LIGBTs is short-circuit failure. In this case, the device may unexpectedly turn on or operate with negligible bus parasitic inductance, causing a sharp rise in junction temperature. If not turned off in time, this can have serious consequences. Therefore, it is essential to control the short-circuit time of LIGBTs and maximize their short-circuit tolerance. Furthermore, short circuits in LIGBTs can lead to additional transient failure modes, potentially causing direct device failure. Because LIGBTs are used in critical applications, their failure and reliability are receiving increasing attention. Researching device failure mechanisms not only enables the design of higher-performance and safer chips but also helps in fault diagnosis, improving product utilization and reducing costs.

[0004] To address the aforementioned problems, the present invention LIGBT is proposed. Summary of the Invention

[0005] This invention provides a device with an adaptive floating P-region that, while minimizing the impact on the forward conduction voltage, improves the device's withstand voltage and short-circuit withstand capability, thereby enhancing the device's operational reliability.

[0006] To achieve the above objectives, the present invention proposes the following technical solution:

[0007] An adaptive floating P-region short-circuit resistant LIGBT includes a device substrate 1, an SOI oxide layer 2, a floating P2 region 3, a self-biased NMOS P-type substrate 4, a self-biased NMOS source 5, a self-biased NMOS gate oxide layer 6, a self-biased NMOS drain 7, a LIGBT P-barrier 8, an emitter P+ region 9, an N-type carrier storage layer 10, an emitter N+ region 11, a trench gate 12, a floating P+ region 13, a floating P1 region 14, a collector P+ region 15, an N-type buffer layer 16, and a drift region 17.

[0008] The LIGBT device consists of a substrate layer 1, an SOI oxide layer 2, a LIGBT P-barrier 8, an emitter P+ region 9, an N-type carrier storage layer 10, an emitter N+ region 11, a trench gate 12, a collector P+ region 15, an N-type buffer layer 16, and a drift region 17.

[0009] The floating P2 region 3 is located on the lower surface of the drift N-drift17 and the upper surface of the substrate layer 1, and is isolated from the self-biased NMOS and conventional LIGBT emitter structure through an oxide layer;

[0010] The P-type substrate 4 of the NMOS is located on the upper surface of the drift N-drift 17 and below the self-biased NMOS source 5, the self-biased NMOS gate oxide layer 6, and the self-biased NMOS drain 7, forming an NMOS, and is isolated from the floating P2 region 3 by the oxide layer.

[0011] The floating P1 region 14 is located on the upper surface of the drift N-drift 17, below the floating P+ region 13 and wrapping it, and is isolated from the conventional LIGBT emitter structure through the trench. The floating P+ region 13 is connected to the floating P2 region 3, the self-biased NMOS oxide gate, and the self-biased NMOS drain 7 through the floating electrode.

[0012] Furthermore, when the normal conduction anode voltage is low, the hole accumulation in the floating P region is insufficient to turn on the self-biased NMOS. The floating P region enhances its carrier aggregation effect and reduces conduction losses.

[0013] Furthermore, when the normal conduction anode voltage is large, the accumulation of holes in the floating P region causes its voltage to rise, resulting in the self-biased NMOS to turn on, extracting holes in the floating P region, clamping the voltage of the floating P region, expanding the depletion layer between the floating P region and the N drift region, reducing the saturation current of the device, and thus improving the short-circuit withstand time of the device.

[0014] Furthermore, in the forward blocking state, due to the lack of a low-impedance discharge path in the floating P region, the potential rises synchronously with the N-drift region potential, causing the self-biased NMOS to turn on, pulling down the voltage in the floating P region. This results in a more uniform electric field distribution and improves the device's breakdown voltage.

[0015] Furthermore, the clamping capability of the self-biased NMOS can be changed by altering the concentration of the P-type substrate 4 of the self-biased NMOS, thereby controlling the clamping voltage of the floating P-region.

[0016] The beneficial effects of this invention are as follows: Based on the traditional IGBT device, this invention introduces a double floating P-region and a self-biased NMOS to control the depletion layer and carriers by controlling the voltage of the two P-regions. During forward conduction, if the current is small, the potential of the floating P-region is floating, primarily accumulating holes to ensure a low on-state voltage drop. During forward conduction with a large current, holes accumulate in the floating P-region, causing its voltage to rise. This allows the self-biased NMOS to clamp the floating P-region, expanding the depletion layer and reducing the saturation current. In the forward blocking state, the potential of the P-region also gradually increases, enabling a more uniform electric field distribution and improving voltage withstand capability.

[0017] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a schematic diagram and cross-sectional view of the novel LIGBT device according to Embodiment 1 of the present invention;

[0020] Figure 2 The forward conduction voltage curves of the present invention and conventional trench gate LIGBTs are shown.

[0021] Figure 3 The saturation current curves of the present invention and conventional trench gate LIGBTs are shown.

[0022] Figure 4 This invention and conventional trench gate LIGBTs demonstrate the forward blocking voltage capability of devices with different drift region lengths under different drift region lengths.

[0023] Figure 5 The forward short-circuit withstand time curves of the present invention and conventional trench gate LIGBTs are shown.

[0024] The attached diagram shows the device substrate (1), SOI oxide layer (2), floating P2 region (3), P-type substrate of self-biased NMOS (4), source of self-biased NMOS (5), gate oxide layer of self-biased NMOS (6), drain of self-biased NMOS (7), P-barrier of LIGBT (8), emitter P+ region (9), N-type carrier storage layer (10), emitter N+ region (11), trench gate (12), floating P+ region (13), floating P1 region (14), collector P+ region (15), N-type buffer layer (16), and drift region (17). Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0028] Example 1:

[0029] like Figure 1 As shown, this embodiment improves upon traditional trench gate LIGBT devices by providing an adaptive floating P-region short-circuit resistant LIGBT, comprising a device substrate 1, an SOI oxide layer 2, a floating P2 region 3, a self-biased NMOS P-type substrate 4, a self-biased NMOS source 5, a self-biased NMOS gate oxide layer 6, a self-biased NMOS drain 7, a LIGBT P-barrier 8, an emitter P+ region 9, an N-type carrier storage layer 10, an emitter N+ region 11, a trench gate 12, a floating P+ region 13, a floating P1 region 14, a collector P+ region 15, an N-type buffer layer 16, and a drift region 17.

[0030] When the normal conduction anode voltage is low, the hole accumulation in the floating P-region is insufficient to turn on the self-biased NMOS. The floating P-region enhances its carrier aggregation effect, reducing conduction losses. When the normal conduction anode voltage is high, the hole accumulation in the floating P-region causes its voltage to rise, leading to the turn on of the self-biased NMOS. This extracts holes from the floating P-region, clamping the voltage of the floating P-region and expanding the depletion layer between the floating P-region and the N-drift region. This reduces the device's saturation current and improves the device's short-circuit withstand time. In the forward blocking state, because the floating P-region lacks a low-impedance discharge path, its potential rises synchronously with the N-drift region's potential, causing the self-biased NMOS to turn on and lowering the floating P-region voltage. This makes the electric field distribution of the device more uniform and improves the device's withstand voltage capability.

[0031] Figure 2 The diagram shows the forward conduction curves of Example 1 and a conventional trench gate LIGBT. The forward conduction capability of Example 1 is slightly weaker than that of the conventional LIGBT, by about 1.017V (the conventional trench LIGBT is about 0.907V).

[0032] Figure 3 The figure shows the forward saturation current of Example 1 and a conventional trench gate LIGBT. It can be seen that the saturation current of Example 1 is approximately 3100 A / cm. -2 Compared to traditional trench gate LIGBTs, the current is reduced, and the saturation current is relatively stable during operation.

[0033] Figure 4 The figure shows the forward blocking voltage capability of Example 1 and conventional trench gate LIGBT under different drift region lengths. As shown in the figure, the highest voltage capability of Example 1 can reach 344V (both with a drift region length of 20μm).

[0034] Figure 5 The figures show the forward short-circuit withstand time curves of the present invention and the conventional trench gate LIGBT; the short-circuit withstand time of Example 1 is about 5.5 μs, while the short-circuit withstand time of the conventional trench gate LIGBT is less than 0.5 μs.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. This invention discloses an adaptive floating P-region short-circuit resistant LIGBT, comprising a device substrate (1), an SOI oxide layer (2), a floating P2 region (3), a self-biased NMOS P-type substrate (4), a self-biased NMOS source (5), a self-biased NMOS gate oxide layer (6), a self-biased NMOS drain (7), a LIGBT P-barrier (8); an emitter P+ region (9), an N-type carrier storage layer (10), an emitter N+ region (11), a trench gate (12), a floating P+ region (13), a floating P1 region (14), a collector P+ region (15), an N-type buffer layer (16), and a drift region (17). Traditional LIGBT devices consist of a substrate layer (1), an SOI oxide layer (2), a LIGBT P-barrier (8), an emitter P+ region (9), an N-type carrier storage layer (10), an emitter N+ region (11), a trench gate (12), a collector P+ region (15), an N-type buffer layer (16), and a drift region (17). The floating P2 region (3) is located on the lower surface of the drift N-drift (17) and the upper surface of the substrate layer (1), and is isolated from the self-biased NMOS and conventional LIGBT emitter structure by an oxide layer; The P-type substrate (4) of the NMOS is located on the upper surface of the drift N-drift (17) and below the self-biased NMOS source (5), the self-biased NMOS gate oxide layer (6), and the self-biased NMOS drain (7), forming an NMOS, and is isolated from the floating P2 region (3) by the oxide layer. The floating P1 region (14) is located on the upper surface of the drift N-drift (17), below the floating P+ region (13) and envelops it, and is isolated from the conventional LIGBT emitter structure through the trench. The floating P+ region (13) is connected to the floating P2 region (3), the self-biased NMOS oxide gate, and the self-biased NMOS drain (7) through the floating electrode.

2. The adaptive floating P-region short-circuit resistant LIGBT according to claim 1, characterized in that, Including self-biased NMOS: P-type substrate (4), source (5), gate oxide layer (6), drain (7), floating P region: floating P2 region (3), floating P+ region (13), floating P1 region (14).

3. The adaptive floating P-region short-circuit resistant LIGBT according to claim 1, characterized in that, The floating P-region can be turned on by the potential rise caused by the accumulated charge carriers (mainly holes). After it is turned on, the holes in the floating P-region can be extracted through the floating electrode, so that the potential of the floating P-region is kept at a low level. This allows it to distribute the electric field evenly and expand the depletion layer to reduce the current under high voltage and large current conduction conditions.

4. The adaptive floating P-region short-circuit resistant LIGBT according to claim 1, characterized in that, During a short circuit, the self-biased NMOS can lower the potential of the floating P-region, causing the depletion layer to expand and increasing the short circuit withstand time.

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