Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductor chips, aiming to solve the problem of great difficulty in preparation of the back collector structure of reverse-conducting devices. The semiconductor structure preparation method comprises the following steps: providing a substrate, the substrate comprising a first surface and a second surface arranged oppositely in the thickness direction; etching the substrate on the first surface to form a protruding part and a supporting base; forming an epitaxial part on one side of the supporting base close to the protruding part, the doping type of the protruding part being different from that of the epitaxial part; forming a first epitaxial layer on one side of the protruding part and the epitaxial part away from the supporting base, the doping concentration of the first epitaxial layer being less than that of the protruding part; and forming a second epitaxial layer on one side of the first epitaxial layer away from the supporting base, the doping concentration of the second epitaxial layer being less than that of the first epitaxial layer. The semiconductor structure prepared by the semiconductor structure preparation method can be used to prepare a reverse-conducting semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) are primarily used as power switching devices in power electronic equipment. For example, in an inverter circuit driving a motor, the DC bus voltage needs to be pulse-width modulated and inverted into AC power with adjustable frequency and amplitude before it can drive a permanent magnet synchronous motor. To achieve efficient, low-loss power conversion and precise motor torque control, RC-IGBTs are used for high-frequency switching conversion of electrical energy. RC-IGBTs have wide applications in equipment for new energy vehicles, rail transit traction, industrial variable frequency speed control, smart grid power transmission and distribution, photovoltaic and wind power conversion, and electrochemical energy storage systems, and are core components of modern energy conversion and power electronic systems.

[0003] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses physical properties such as a large bandgap, high breakdown electric field strength, high thermal conductivity, and fast electron saturation drift velocity. Therefore, SiC devices are well-suited for the aforementioned RC-IGBT applications.

[0004] However, the fabrication process of RC-IGBTs requires the preparation of cell structures on the front side of the wafer and collector structures on the back side. When using wide-bandgap materials (e.g., SiC) to fabricate RC-IGBTs, the fabrication of the collector structure on the back side of the wafer is extremely difficult, and the process can affect the cell structure on the front side. Therefore, reducing the fabrication difficulty of the back-side collector structure for reverse-conductive devices has become a pressing technical problem. Summary of the Invention

[0005] The embodiments of this disclosure provide a method for fabricating a semiconductor structure and a semiconductor structure, which aim to reduce the difficulty of fabricating the back collector structure of a reverse-conducting device.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a method for fabricating a semiconductor structure is provided. The method includes the following steps: Step 1: Providing a substrate; the substrate includes a first surface and a second surface, the first surface and the second surface being opposite each other in the thickness direction of the substrate. Step 2: Etching the substrate on the first surface to form protrusions and a supporting substrate; the plurality of protrusions are spaced apart on one side of the supporting substrate. Step 3: Forming epitaxial portions on the side of the supporting substrate near the protrusions; the epitaxial portions are located between the protrusions, and the protrusions and the epitaxial portions have different doping types. Step 4: Forming a first epitaxial layer on the side of the protrusions and the epitaxial portions away from the supporting substrate, the doping concentration of the first epitaxial layer being less than the doping concentration of the protrusions. Step 5: Forming a second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate, the doping concentration of the second epitaxial layer being less than the doping concentration of the first epitaxial layer.

[0007] The semiconductor structure fabrication method provided in the above embodiments of this disclosure involves etching a doped substrate to obtain a support substrate and protrusions spaced apart on one side of the support substrate. Epitaxial portions with different doping types than the protrusions are then grown on this substrate, with the epitaxial portions located between the protrusions. The protrusions and epitaxial portions with different doping types constitute short-circuited N+ and P+ doped regions. Thus, the fabrication of the back-side collector structure of a reverse-conducting device can be completed without complex fabrication processes. Furthermore, a first epitaxial layer with a doping concentration lower than that of the protrusions and a second epitaxial layer with a doping concentration lower than that of the first epitaxial layer are sequentially grown. The first epitaxial layer can be an N-buffer layer, and the second epitaxial layer can be an N-drift layer. During the fabrication of the back-side collector structure, since the front-side cell structure of the reverse-conducting device has not yet been fabricated, damage to the front-side cell structure during the fabrication of the back-side collector structure can be completely avoided, thereby improving production yield.

[0008] In some embodiments, etching the substrate on the first surface to form a protrusion and a support substrate includes the following steps: forming a mask pattern on the first surface, the mask pattern including an opening that exposes a portion of the substrate; and simultaneously etching the mask pattern and the exposed portion of the substrate using an etchant to form the protrusion and the support substrate.

[0009] In some embodiments, the ratio of the etching rate of the etchant on the mask pattern to the etching rate of the etchant on the substrate is greater than or equal to 4.

[0010] In some embodiments, forming an epitaxial portion on the side of the support substrate near the protrusion includes: reacting a first growth gas with a first doping source gas in a first carrier gas environment to form an initial epitaxial portion; grinding the surface of the initial epitaxial portion away from the support substrate to expose the protrusion and form the epitaxial portion.

[0011] In some embodiments, the first growth gas includes a silicon source gas and a carbon source gas, and the first doping source gas includes a P-type doping source gas.

[0012] In some embodiments, before forming the first epitaxial layer on the side of the protrusion and the epitaxial portion away from the support substrate, the method further includes: performing in-situ vapor phase etching pretreatment on the surface of the protrusion and the epitaxial portion on the side away from the support substrate, thereby reducing the surface roughness of the protrusion and the epitaxial portion.

[0013] In some embodiments, forming a first epitaxial layer on the side of the protrusion and the epitaxial portion away from the supporting substrate includes: reacting a second growth gas with a second doping source gas in a second carrier gas environment to form the first epitaxial layer, wherein the second growth gas includes a silicon source gas and a carbon source gas, and the second doping source gas includes an N-type doping source gas.

[0014] In some embodiments, forming a second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate includes: reacting a third growth gas with a third doping source gas in an environment of a third carrier gas to form the second epitaxial layer, wherein the third growth gas includes a silicon source gas and a carbon source gas, the ratio of the number of carbon atoms to the number of silicon atoms in the second growth gas is less than the ratio of the number of carbon atoms to the number of silicon atoms in the third growth gas, and the third doping source gas includes an N-type doping source gas.

[0015] In some embodiments, before forming the first epitaxial layer on the side of the protrusion and the epitaxial portion away from the support substrate, the method further includes forming a third epitaxial layer on the side of the protrusion and the epitaxial portion away from the support substrate, wherein the doping concentration of the third epitaxial layer is less than the doping concentration of the first epitaxial layer.

[0016] In some embodiments, after forming a second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate, the method further includes forming a fourth epitaxial layer on the side of the second epitaxial layer away from the supporting substrate, wherein the doping concentration of the fourth epitaxial layer is greater than the doping concentration of the second epitaxial layer.

[0017] In some embodiments, after forming a second epitaxial layer on the side of the first epitaxial layer away from the support substrate, the method further includes: grinding the support substrate on the second surface until the protrusion and the epitaxial portion are exposed.

[0018] On the other hand, a semiconductor structure is provided, fabricated using the method described in any of the above embodiments. The semiconductor structure includes a composite layer, a first epitaxial layer, and a second epitaxial layer. The composite layer includes a plurality of protrusions spaced apart. The composite layer also includes epitaxial portions located between adjacent protrusions. The two surfaces of the protrusions in the thickness direction and the two surfaces of the epitaxial portions in the thickness direction are flush. The protrusions and the epitaxial portions have different doping types. The first epitaxial layer is located on one side of the composite layer, and its doping concentration is lower than that of the protrusions. The second epitaxial layer is located on the side of the first epitaxial layer away from the composite layer, and its doping concentration is lower than that of the first epitaxial layer.

[0019] In some embodiments, the semiconductor structure further includes a support substrate located on the side of the composite layer away from the first epitaxial layer, and the support substrate is made of the same material as the protrusion.

[0020] In some embodiments, the semiconductor structure further includes a third epitaxial layer located between the composite layer and the first epitaxial layer, wherein the doping concentration of the third epitaxial layer is less than that of the first epitaxial layer.

[0021] In some embodiments, the semiconductor structure further includes a fourth epitaxial layer located on the side of the second epitaxial layer away from the composite layer, and the doping concentration of the fourth epitaxial layer is greater than that of the second epitaxial layer.

[0022] It is understood that the beneficial effects of the semiconductor structure provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below.

[0024] Figure 1 This is a schematic diagram of the structure of an RC-IGBT according to some embodiments.

[0025] Figure 2 The process of fabricating a semiconductor structure according to some embodiments Figure 1 .

[0026] Figure 3 This is a structural diagram of the semiconductor structure fabrication process according to some embodiments.

[0027] Figure 4 A flowchart illustrating the etching of a substrate on a first surface to form a protrusion and a support substrate according to some embodiments.

[0028] Figure 5 This is a structural diagram of the process of etching a substrate on a first surface to form a protrusion and a support substrate according to some embodiments.

[0029] Figure 6 This is a flowchart illustrating the formation of a mask pattern on a first surface according to some embodiments.

[0030] Figure 7 This is a structural diagram of the process of forming a mask pattern on the first surface according to some embodiments.

[0031] Figure 8 This is a flowchart illustrating the formation of an extension portion on the side of a support substrate near a protrusion, according to some embodiments.

[0032] Figure 9 This is a structural diagram of the process of forming an epitaxial portion on the side of a support substrate near the protrusion, according to some embodiments.

[0033] Figure 10 The process of fabricating a semiconductor structure according to some embodiments Figure 2 .

[0034] Figure 11 This is a structural diagram of the process of forming a third epitaxial layer on the side of the protrusion and epitaxial portion away from the supporting substrate, according to some embodiments.

[0035] Figure 12 The process of fabricating a semiconductor structure according to some embodiments Figure 3 .

[0036] Figure 13 This is a structural diagram of the process of forming a fourth epitaxial layer on the side of the second epitaxial layer away from the supporting substrate, according to some embodiments.

[0037] Figure 14 The process of fabricating a semiconductor structure according to some embodiments Figure 4 .

[0038] Figure 15 This is a structural diagram of the process of grinding a support substrate on the second surface according to some embodiments until the protrusions and epitaxial portions are exposed.

[0039] Figure 16The structure of a semiconductor structure according to some embodiments Figure 1 .

[0040] Figure 17 The structure of a semiconductor structure according to some embodiments Figure 2 .

[0041] Figure 18 The structure of a semiconductor structure according to some embodiments Figure 3 .

[0042] Figure 19 The structure of a semiconductor structure according to some embodiments Figure 4 . Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0048] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0049] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0052] The technical terms used in the embodiments of this application are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called a doped semiconductor or an intrinsic semiconductor. When the impurities in a doped semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, this type of doped semiconductor is also called a conductive semiconductor, for example, conductive silicon carbide material, with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities introduced into a doped semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this application, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0053] Ohmic contact: Ohmic contact refers to the low-resistance contact formed between a metal electrode and a semiconductor structure. Under ohmic contact, current can flow freely in both directions.

[0054] PN junction: A PN junction is an interface structure formed when semiconductor regions of different doping types come into contact, exhibiting unidirectional conductivity. Unidirectional conductivity means that current can flow through the PN junction when a forward voltage is applied (the potential on the P-type doped region is higher than that on the N-type doped region); however, almost no current flows through the PN junction when a reverse voltage is applied (the potential on the N-type doped region is higher than that on the P-type doped region).

[0055] Threshold voltage: The threshold voltage is the minimum voltage between the gate and emitter required to form a continuous conductive channel on the semiconductor surface. For the N-type conductive channel in this embodiment, the threshold voltage is positive; for the P-type conductive channel, the threshold voltage is negative.

[0056] Unless otherwise defined, all technical terms used herein have the same meaning as those known to one of ordinary skill in the art. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0057] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0058] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] The technical solution of this application can be applied to electronic devices, such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices, as well as network devices such as base stations. The electronic device can also be a power amplifier or similar device used in the aforementioned electronic devices. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0060] The reverse-conducting insulated-gate bipolar transistor (RC-IGBT) integrates the IGBT switching unit and the anti-parallel freewheeling diode on the same chip, which significantly improves the power density of power devices and eliminates the parasitic inductance and contact resistance caused by the external freewheeling diode. Therefore, it is widely used in power electronics fields such as new energy power generation, motor drive, and rail transportation.

[0061] like Figure 1 As shown, the core structure of a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) is shown from the front to the back. Figure 1 From top to bottom, the structure comprises: gate G, emitter E, contact region 1, emitter region 2, drift layer 3, buffer layer 4, cathode region 5, collector region 6, and collector C. The gate G, emitter E, contact region 1, emitter region 2, and a portion of the drift layer 3 constitute a cell structure; the buffer layer 4, cathode region 5, collector region 6, and collector C constitute the collector structure. The doping types and interconnections of the above structure are explained below.

[0062] Either contact region 1 or emitter region 2 is a first-type doped region and the other is a second-type doped region. Both are in ohmic contact with the emitter E and are connected to the gate G through the gate dielectric layer (not shown in the figure).

[0063] As an example, either the first type or the second type is N-type, and the other is P-type. As an example, contact region 1 can be a P-type doped region and emitter region 2 can be an N-type doped region, or contact region 1 can be an N-type doped region and emitter region 2 can be a P-type doped region. This disclosure does not specifically limit the embodiments in this way.

[0064] The drift layer 3 and the buffer layer 4 have the same doping type, and the same doping type as the emitter region 2. The doping concentration of both the drift layer 3 and the buffer layer 4 is lower than that of the emitter region 2, and the doping concentration of the drift layer 3 is lower than that of the buffer layer 4. The drift layer 3 is connected to the gate G through the gate dielectric layer (not shown in the figure).

[0065] Cathode region 5 and collector region 6 are located between collector electrode C and buffer layer 4. Multiple collector regions 6 are distributed at intervals, and cathode regions 5 are located between adjacent collector regions 6. Cathode regions 5 and collector regions 6 are electrically connected through collector electrode C. Cathode regions 5 and contact region 1 have the same doping type, and collector regions 6 and buffer layer 4 have the same doping type. The doping concentration of collector regions 6 is greater than that of buffer layer 4.

[0066] The following example illustrates the working principle of RC-IGBT, using contact region 1 and cathode region 5 as P-type doped regions and emitter region 2, drift layer 3, buffer layer 4 and collector region 6 as N-type doped regions.

[0067] RC-IGBT includes three basic operating states: forward blocking state, forward conducting state, and reverse conducting state.

[0068] When the potential of the collector C is higher than the potential of the emitter E, and the voltage applied between the gate G and the emitter E does not reach the threshold voltage, the RC-IGBT is in a forward blocking state. At this time, the voltage applied between the gate G and the emitter E is less than the threshold voltage, and a conductive channel connecting the emitter region 2 and the drift layer 3 cannot be formed; at the same time, the PN junction formed between the contact region 1 and the drift layer 3 is in a reverse bias state, blocking the flow of current from the collector C side to the emitter E side. The applied forward voltage is mainly borne by the drift layer 3 and the buffer layer 4, and the RC-IGBT is in a turn-off state.

[0069] When the potential of the collector C is higher than that of the emitter E, and the potential of the gate G is higher than that of the emitter E and greater than the threshold voltage, the RC-IGBT is in the forward conduction state. At this time, the voltage applied to the gate G will form a conductive channel connecting the emitter region 2 and the drift layer 3 on the surface of the contact region 1 near the gate G; electrons are injected from the emitter region 2 into the drift layer 3 through this conductive channel, while holes are injected from the cathode region 5 into the drift layer 3 through the buffer layer 4; the carrier concentration in the drift layer 3 increases significantly, and the conductivity is greatly enhanced.

[0070] When the potential of the emitter E is higher than that of the collector C, and the voltage applied between the gate G and the emitter E does not reach the threshold voltage, the RC-IGBT is in reverse conduction. At this time, the voltage applied between the gate G and the emitter E is less than the threshold voltage, making it impossible to form a conductive channel connecting the emitter region 2 and the drift layer 3. Simultaneously, the PN junction formed between the contact region 1 and the drift layer 3 is in a forward bias state, while the PN junction formed between the cathode region 5 and the buffer layer 4 is in a reverse bias state. Holes are injected into the drift layer 3 from the contact region 1, and electrons are injected into the drift layer 3 from the collector region 6, thus enabling the RC-IGBT to conduct in reverse.

[0071] Currently, the typical fabrication method for silicon-based RC-IGBTs involves creating a cellular structure on the front side of a wafer, followed by forming a buffer layer 4, a cathode region 5, and a collector region 6 on the back side of the wafer via ion implantation. After high-temperature activation, these layers are then connected to the collector electrode C. As power electronic systems evolve towards higher voltages, higher frequencies, and higher operating temperatures, next-generation semiconductor materials such as silicon carbide (SiC) have become the preferred materials for next-generation power devices due to their excellent properties, including wide bandgap, high breakdown voltage, and high thermal conductivity. However, the fabrication methods for silicon-based RC-IGBTs are difficult to directly apply to SiC fabrication of RC-IGBTs. On the one hand, the activation temperature of SiC devices after ion implantation is as high as 1600℃ or more, which is much higher than the activation temperature of silicon-based devices. The high-temperature activation process after back-side ion implantation will severely damage the structure already fabricated on the front side of the device, leading to problems such as threshold voltage drift, increased gate leakage, and decreased reliability. On the other hand, in order to reduce conduction and switching losses, SiC power devices need to thin the wafer to below 100 μm. Back-side ion implantation, high-temperature annealing, and other processing steps can easily cause wafer warping and fragmentation after thinning, resulting in extremely low device fabrication yield.

[0072] In view of this, the present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which reduces the difficulty of fabricating reverse-conductive devices.

[0073] One aspect of this disclosure provides a method for fabricating a semiconductor structure 1000, such as... Figure 2 As shown, the method for fabricating the semiconductor structure 1000 includes steps S1 to S5.

[0074] S1, such as Figure 3 As shown, a substrate 10 is provided. The substrate 10 includes a first surface 11 and a second surface 12, which are opposite to each other in the thickness direction X of the substrate 10.

[0075] In some possible implementations, S1 includes selecting an N-type doped SiC substrate 10 with a 4H crystal form. Here, 4H crystal form refers to a crystal structure of SiC, which has the characteristics of high electron mobility and strong breakdown electric field.

[0076] In some examples, the selected substrate 10 is cut such that the normal direction of the first surface 11 is offset by 0° to 8° towards the <1-100> crystal direction relative to the <11-20> crystal direction of the substrate 10. As an example, the offset angle of the normal direction of the first surface 11 towards the <1-100> crystal direction relative to the <11-20> crystal direction of the substrate 10 can be 0°, 1°, 2°, 3°, 4°, 5°, 6°, 7°, and 8°. For example, the offset angle of the normal direction of the first surface 11 towards the <1-100> crystal direction relative to the <11-20> crystal direction of the substrate 10 is 4°.

[0077] The setting of this offset angle can provide sufficient step density for the epitaxial growth of other structures on substrate 10 in subsequent processes, suppress the three-dimensional island growth and stacking fault defects of the epitaxial layer, thereby obtaining a high-quality epitaxial structure.

[0078] In some examples, S1 also includes standard RCA cleaning of the substrate 10. Standard RCA cleaning is a semiconductor cleaning process developed by RCA, which removes different types of contaminants through three consecutive cleaning steps.

[0079] The specific process of RCA is as follows: First, the substrate 10 is immersed in SC1 cleaning solution (also known as alkaline hydrogen peroxide cleaning solution) prepared by ammonia, hydrogen peroxide and deionized water in a volume ratio of 1:1:5~1:2:7, and soaked at 65~80℃ for 10~15 minutes. The oxidizing effect of hydrogen peroxide decomposes organic contaminants, and at the same time, the alkalinity of ammonia makes the particle surface negatively charged, which generates electrostatic repulsion with the negatively charged surface of the substrate 10 to remove particulate impurities. Then, a solution with resistivity ≥18.2 MΩ is used. Rinse the substrate 10 with high-purity deionized water for 3-5 minutes to remove residual solution; then transfer the substrate 10 to a diluted hydrofluoric acid solution with a volume ratio of 1:50 to 1:100 and immerse it at room temperature for 30-60 seconds. The natural oxide layer and metal ions adsorbed on the oxide layer are removed from the substrate 10 through the chemical reaction between hydrofluoric acid and silicon oxide (SiO2) (SiO2 + 4HF = SiF4↑ + 2H2O). Immediately after removal, rinse with high-purity deionized water for 2-3 minutes to prevent corrosion from residual hydrofluoric acid. Finally, transfer the substrate... 10 is placed in SC2 cleaning solution (also known as acidic hydrogen peroxide cleaning solution) prepared by hydrochloric acid, hydrogen peroxide and deionized water in a volume ratio of 1:1:6~1:2:8, and soaked at 65~80℃ for 10~15 minutes. Hydrogen peroxide is used to oxidize the metal to high-valence ions, and then hydrochloric acid forms a soluble complex with the metal ions. After completion, it is rinsed with high-purity deionized water for 5~10 minutes to thoroughly remove all chemical residues. Finally, the surface of substrate 10 is dried with high-purity nitrogen gas to obtain a clean and atomically flat surface of substrate 10.

[0080] As an example, the doping type of substrate 10 can be either a first type or a second type, wherein either the first type or the second type is N-type and the other is P-type. For example, the doping type of substrate 10 can be N-type with a doping concentration of 1e18 cm⁻¹. -3 ~1e20 cm -3 The following description assumes that substrate 10 is N-type doped with a doping concentration of 1e18 cm⁻¹. -3 ~1e20 cm -3 Let's take an example to illustrate this.

[0081] S2, such as Figure 3 As shown, the substrate 10 is etched on the first surface 11 to form protrusions 20 and a support base 30. A plurality of protrusions 20 are spaced apart on one side of the support base 30.

[0082] In some possible implementations, such as Figure 4 As shown, S2 includes S21 and S22.

[0083] S21, such as Figure 5 As shown, a mask pattern 13 is formed on the first surface 11. The mask pattern 13 includes an opening 131 that exposes a portion of the substrate 10.

[0084] In some examples, the mask pattern 13 can be an oxide, such as SiO2.

[0085] As an example, such as Figure 6 As shown, S21 includes S211 to S215.

[0086] S211, such as Figure 7 As shown, a mask layer 130 is formed on the first surface 11.

[0087] As an example, S211 can be to deposit a layer of SiO2 on the first surface 11. For example, S211 can be to place the substrate 10 in the reaction chamber of a low-pressure chemical vapor deposition (LPCVD) apparatus, and introduce tetraethoxysilane (TEOS) and oxygen (O2) into the LPCVD reaction chamber at a temperature of 650°C to 750°C and a pressure of 100 mTorr to 300 mTorr, wherein the flow rate of TEOS is 30 sccm to 150 sccm and the flow rate of O2 is 10 sccm to 100 sccm, and a layer of SiO2 is deposited on the surface of the substrate 10 at a deposition rate of 3 nm / min to 20 nm / min.

[0088] S212, see further. Figure 7 A photoresist layer 140 is formed on the side of the mask layer 130 away from the substrate 10.

[0089] As an example, S212 can be formed by using a spin coater to form a photoresist layer 140 on the surface of the mask layer 130 away from the substrate 10.

[0090] S213, see further. Figure 7A portion of the photoresist layer 140 is removed to form a photoresist pattern 14. The photoresist pattern 14 includes an etching opening 141 that exposes a portion of the mask layer 130.

[0091] As an example, S213 can be performed by exposing and developing the photoresist layer 140 using a photolithography machine to remove part of the photoresist layer 140 and form a photoresist pattern 14, wherein the photoresist pattern 14 includes an etching opening 141, and the etching opening 141 exposes part of the mask layer 130.

[0092] S214, see further. Figure 7 The mask layer 130 is etched until the substrate 10 is exposed, forming a mask pattern 13.

[0093] As an example, S214 can be performed by using an inductively coupled plasma-reactive ion etching (ICP-RIE) device to selectively etch the mask layer 130 until the substrate 10 is exposed, forming a mask pattern 13. Here, selective etching means that the portion of the mask layer 130 covered by the photoresist pattern 14 is not etched, while the portion of the mask layer 130 exposed by the etching opening 141 is etched.

[0094] S215, see further. Figure 7 Remove the photoresist pattern 14.

[0095] As an example, S215 can be to remove the photoresist pattern 14 by wet cleaning to obtain a substrate 10 covered with the mask pattern 13.

[0096] S22, see further. Figure 5 Using an etchant, the mask pattern 13 and the exposed portion of the substrate 10 are simultaneously etched to form the protrusion 20 and the support substrate 30.

[0097] As an example, an ICP-RIE device can be used to simultaneously etch the mask pattern 13 and the substrate 10 to form the protrusion 20 and the support substrate 30.

[0098] In some possible implementations, the ratio of the etching rate of the etchant used in S22 on the mask pattern 13 to the etching rate of the etchant on the substrate 10 is greater than or equal to 4.

[0099] Because the etching rate and etching amount of substrate 10 are low, it is difficult to directly observe and determine the etching endpoint, resulting in large etching errors and poor etching accuracy. Using processes S21 and S22, the thickness H1 etched away from the mask pattern 13 during the etching process is more than four times the thickness H2 etched away from the substrate 10 (i.e., the height H2 of the formed protrusion 20). This allows the etching of the mask pattern 13, with its larger thickness variation, to characterize the etching of the substrate 10, with its smaller thickness variation. During the etching process, the etching status of the mask pattern 13 can be monitored in real time using optical emission spectroscopy, laser interferometry, and other methods to confirm the etching endpoint. Compared to directly monitoring the etching status of substrate 10, the monitoring signal strength and signal-to-noise ratio using processes S21 and S22 are higher, significantly improving the etching accuracy of substrate 10.

[0100] In some embodiments, the actual thickness of the mask pattern 13 can be greater than the etched thickness H1, so as to avoid the mask pattern 13 being completely etched before the substrate 10 is etched to a preset value, thereby ensuring that the substrate 10 is etched to a preset value, i.e., the thickness H2 of the formed protrusion 20, can reach the preset value.

[0101] As an example, when the material of the mask pattern 13 is SiO2 and the material of the substrate 10 is SiC, the etchant can be any one of the following: trifluoromethane / argon etching system (CHF3 / Ar), carbon tetrafluoride / oxygen etching system (CF4 / O2), or octafluorocyclobutane / oxygen etching system (C4F8 / O2).

[0102] As an example, in step S22, the entire mask pattern 13 can be etched away, and the moment when the mask pattern 13 is completely etched away can be taken as the etching endpoint. In this way, the significant abrupt change in the optical emission spectrum signal during the etching process can be used to achieve accurate endpoint monitoring. Alternatively, a portion of the mask pattern 13 can be retained and removed in subsequent processes using other methods. This avoids surface lattice damage to the surface of the protrusion 20 formed at the etching endpoint due to plasma bombardment, thus ensuring the surface quality and electrical performance of the protrusion 20. For example, the remaining portion of the mask pattern 13 can be selectively removed by wet cleaning.

[0103] S3, such as Figure 3 As shown, an epitaxial portion 40 is formed on the side of the support substrate 30 near the protrusion 20. The epitaxial portion 40 is located between the protrusions 20, and the doping types of the epitaxial portion 40 and the protrusions 20 are different.

[0104] The protrusion 20 formed in S2 is obtained by etching the substrate 10, and its doping type and doping concentration are the same as those of the substrate 10, which will not be described again here. The doping type of the epitaxial portion 40 formed in S3 is different from that of the protrusion 20. For example, the doping type of the epitaxial portion 40 can be P-type, and the doping concentration is 1e16 cm⁻¹. - ³~1e20 cm - ³.

[0105] In some possible implementations, such as Figure 8 As shown, S3 includes S31 and S32.

[0106] S31, such as Figure 9 As shown, in a first carrier gas environment, the first growth gas reacts with the first doping source gas to form the initial epitaxial portion 400.

[0107] In some possible implementations, the first growth gas includes a silicon source gas and a carbon source gas, and the first doping source gas includes a p-type doping source gas. For example, the silicon source gas includes silane (SiH4), the carbon source gas includes propane (C3H8), the p-type doping source gas includes any one of trimethylaluminium (TMA) or aluminum chloride (AlCl3), and the first support gas includes hydrogen (H2).

[0108] As an example, the process for forming the initial epitaxial portion 400 in S3 can be as follows: the support substrate 30 with the protrusions 20 is placed in the reaction chamber of a silicon carbide chemical vapor deposition (SiC CVD) epitaxial furnace. At a temperature of 1500℃~1650℃ and a pressure of approximately 100 mbar, H2 is introduced into the reaction chamber as the first carrier gas at a flow rate of approximately 20 L / min. SiH4, C3H8, and TMA are also introduced, wherein the flow rate of SiH4 is 5 sccm~50 sccm, the flow rate of C3H8 is 5 sccm~25 sccm, and the flow rate of TMA is 0.01 sccm~50 sccm, or the partial pressure of TMA is controlled to be 5 × 10⁻⁶. -5 mbar ~ 2.5 × 10 - ¹ mbar, after a certain reaction time, yields P-type doping with a doping concentration of 1e16 cm⁻¹. - ³~1e20 cm - The initial extension of ³ is 400.

[0109] S32, see further. Figure 9 The surface of the initial epitaxial portion 400 away from the support substrate 30 is ground to expose the protrusion 20, thus forming the epitaxial portion 40.

[0110] The initial epitaxial portion 400 formed in S31 grows on the surfaces of the protrusion 20 and the supporting substrate 30, covering the protrusion 20. At this time, the surface of the initial epitaxial portion 400 away from the supporting substrate 30 needs to be ground to remove the excess portion of the initial epitaxial portion 400, thus forming the epitaxial portion 40, thereby creating a layout where the protrusion 20 and the epitaxial portion 40 are arranged alternately. Grinding the surface of the initial epitaxial portion 400 away from the supporting substrate 30 can be done by using a chemical-mechanical polishing (CMP) polishing machine to polish the surface of the initial epitaxial portion 400 away from the supporting substrate 30 until the protrusion 20 is exposed. After polishing, the surface of the epitaxial portion 40 away from the supporting substrate 30 is flush with the surface of the protrusion 20 away from the supporting substrate 30.

[0111] In some possible implementations, before step S3, an in-situ vapor phase etching pretreatment is performed on the support substrate 30 with the protrusion 20. This reduces the surface roughness of the support substrate 30 on the side near the protrusion 20. This effectively removes defects such as mechanical grinding damage from the surface of the support substrate 30 on the side near the protrusion 20, providing an atomically smooth surface for subsequent epitaxial growth of the epitaxial portion 40 and improving the quality of the formed epitaxial portion 40.

[0112] As an example, the process of pre-treating the support substrate 30 with protrusions 20 by in-situ vapor phase etching can be as follows: the temperature in the reaction chamber of the above-mentioned SiC CVD is adjusted to 1200℃~1700℃, the pressure is adjusted to about 1 standard atmosphere for thermal annealing, and H2 with a flow rate of 50 sccm~100 slm is introduced into the reaction chamber for etching, and the etching time is 5 min~60 min.

[0113] S4, such as Figure 3 As shown, a first epitaxial layer 50 is formed on the side of the protrusion 20 and epitaxial portion 40 away from the supporting substrate 30. The doping concentration of the first epitaxial layer 50 is less than the doping concentration of the protrusion 20.

[0114] In some possible implementations, S4 includes: reacting a second growth gas with a second doping source gas in the presence of a second carrier gas to form a first epitaxial layer. The second growth gas includes a silicon source gas and a carbon source gas, and the second doping source gas includes an N-type doping source gas.

[0115] As an example, in S4, the silicon source gas includes SiH4, the carbon source gas includes either C3H8 or ethylene (C2H4), the second dopant source gas includes either nitrogen (N2) or ammonia (NH3), and the second carrier gas includes H2.

[0116] As an example, the process for forming the first epitaxial layer 50 in S4 can be as follows: The support substrate 30 with protrusions 20 and epitaxial portion 40 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104Pa~700 mbar, H2 is introduced into the reaction chamber as a second carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C3H8, and N2 are also introduced, with the flow rate of SiH4 being 15 sccm~24 sccm, the flow rate of C3H8 being 5 sccm~10 sccm, and the flow rate of N2 being 1 sccm~2000 sccm. After a certain reaction time, N-type doping is obtained, and the doping concentration is 1e16 cm⁻¹. - ³~1e19 cm - The first epitaxial layer 50 of ³.

[0117] Alternatively, as an example, the process for forming the first epitaxial layer 50 in S4 can be as follows: The support substrate 30 with the protrusions 20 and the epitaxial portion 40 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as a second carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C2H4, and NH3 are also introduced, with the flow rate of SiH4 being 15 sccm~24 sccm, the flow rate of C2H4 being 5 sccm~10 sccm, and the flow rate of NH3 being approximately 3 sccm. After a certain reaction time, N-type doping is obtained, with a doping concentration of 1e16 cm⁻¹. - ³~1e19 cm - The first epitaxial layer 50 of ³.

[0118] In some embodiments, in S4, the ratio of carbon atoms to silicon atoms in the second growth gas can be controlled to be 0.4 to 0.8.

[0119] As an example, the ratio of carbon atoms to silicon atoms in the second growth gas can be calculated using the following formula:

[0120] in, This refers to the types and quantities of carbon source gases. For the first Standard volumetric flow rate of a carbon source gas (unit: sccm, slm). For the first The number of carbon atoms in each molecule of a carbon source gas; This refers to the types and quantities of silicon source gases. For the first Standard volumetric flow rate of silicon source gas (unit: sccm, slm); For the first The number of carbon atoms contained in each molecule of a carbon source gas.

[0121] Taking the second growth gas as an example, where the carbon source gas is a single C3H8 gas with a flow rate of 5 sccm and the silicon source gas is a single SiH4 gas with a flow rate of 20 sccm, then... , , , , Based on the above formula, the ratio of carbon atoms to silicon atoms in the second growth gas is calculated to be 0.75.

[0122] In some possible implementations, prior to step S4, the process further includes: performing in-situ vapor phase etching pretreatment on the surface of the protrusion 20 and the epitaxial portion 40 away from the supporting substrate 30. This reduces the surface roughness of the protrusion 20 and the epitaxial portion 40. This effectively removes defects such as mechanical grinding damage from the surface of the protrusion 20 and the epitaxial portion 40 away from the supporting substrate 30, providing an atomically smooth surface for subsequent epitaxial growth of the first epitaxial layer 50 and improving the quality of the formed first epitaxial layer 50.

[0123] As an example, the process of in-situ vapor phase etching pretreatment of the support substrate 30 with protrusion 20 and epitaxial portion 40 can be as follows: the temperature in the reaction chamber of the above-mentioned SiC CVD is adjusted to 1200℃~1700℃, the pressure is adjusted to about 1 standard atmosphere for thermal annealing, and H2 with a flow rate of 50 sccm~100 slm is introduced into the reaction chamber for etching, and the etching time is 5 min~60 min.

[0124] S5, such as Figure 3 As shown, a second epitaxial layer 60 is formed on the side of the first epitaxial layer 50 away from the supporting substrate 30. The doping concentration of the second epitaxial layer 60 is less than that of the first epitaxial layer 50.

[0125] In some possible implementations, S5 includes: reacting a third growth gas with a third doping source gas in the presence of a third carrier gas to form a second epitaxial layer 60, wherein the third growth gas includes a silicon source gas and a carbon source gas, the ratio of the number of carbon atoms to the number of silicon atoms in the second growth gas is less than the ratio of the number of carbon atoms to the number of silicon atoms in the third growth gas, and the third doping source gas includes an N-type doping source gas.

[0126] As an example, the process for forming the second epitaxial layer 60 in S5 can be as follows: The support substrate 30 with the protrusions 20, epitaxial portion 40, and first epitaxial layer 50 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as the second carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C3H8, and N2 are also introduced, with the flow rate of SiH4 being 15 sccm~24 sccm, the flow rate of C3H8 being 5 sccm~10 sccm, and the flow rate of N2 being 1 sccm~2000 sccm. After a certain reaction time, N-type doping is obtained, and the doping concentration is 1e13 cm⁻¹. - ³~1e16 cm - The second epitaxial layer 60 of ³.

[0127] Alternatively, as an example, the process for forming the second epitaxial layer 60 in S5 can be as follows: The support substrate 30 with the protrusions 20, epitaxial portion 40, and first epitaxial layer 50 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as the second carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C2H4, and NH3 are also introduced, with the flow rate of SiH4 being 15 sccm~24 sccm, the flow rate of C2H4 being 5 sccm~10 sccm, and the flow rate of NH3 being approximately 3 sccm. After a certain reaction time, N-type doping is obtained with a doping concentration of 1e13 cm⁻¹. - ³~1e16 cm - The second epitaxial layer 60 of ³.

[0128] In some embodiments, in S5, the ratio of carbon atoms to silicon atoms in the third growth gas can be controlled to be 1.0 to 1.5.

[0129] Thus, the first epitaxial layer 50 formed has a low carbon-to-silicon ratio of 0.4 to 0.8 and a thickness of 1e16 cm⁻¹. - ³~1e19 cm - With a high doping concentration of ³, the second epitaxial layer 60 has a high carbon-to-silicon ratio of 1.0 to 1.5 and a 1e13 cm⁻¹. - ³~1e16 cm -The first epitaxial layer 50 corresponds to the buffer layer 4 in the RC-IGBT, and the second epitaxial layer 60 is used to prepare the drift layer 3 in the RC-IGBT. The second epitaxial layer 60 has a high carbon-to-silicon ratio, which can suppress the formation of intrinsic defects such as silicon vacancies in a carbon-rich growth environment, reduce the number of carrier recombination centers, and improve the carrier lifetime after the formation of the drift layer 3, thereby reducing the forward conduction voltage drop of the RC-IGBT. At the same time, it reduces structural defects such as stacking faults and basal dislocations, and improves the breakdown electric field strength of the drift layer 3 to ensure the withstand voltage capability of the RC-IGBT. The first epitaxial layer 50 has a relatively low carbon-silicon content, which can improve the doping efficiency of nitrogen atoms and obtain a higher doping concentration in a silicon-rich growth environment. As a buffer layer 4 of the RC-IGBT, it can effectively suppress the excessive injection of holes from the collector region 6, reduce its own series resistance, and introduce an appropriate amount of carbon vacancy recombination centers to shorten the carrier lifetime in the buffer layer 4. This accelerates the recombination of excess carriers during the RC-IGBT's switch from the reverse conduction state to the forward blocking state, thereby reducing the loss of the RC-IGBT during the switch from the reverse conduction state to the forward blocking state.

[0130] The method for fabricating the aforementioned semiconductor structure 1000 involves first fabricating the collector region 6 and cathode region 5 on the back side of the RC-IGBT, and then sequentially epitaxially growing the buffer layer 4 and drift layer 3 on top of these. This allows for the fabrication of the RC-IGBT based on the semiconductor structure 1000. This avoids the impact on the front cell structure of the RC-IGBT when fabricating the back collector structure after completing the front cell structure. Furthermore, the fabrication process does not employ complex processing techniques such as ion implantation, which result in lower product yields, thus reducing the fabrication difficulty of the RC-IGBT.

[0131] In some feasible implementations, such as Figure 10 As shown, the method for preparing the semiconductor structure 1000 may further include step S6 before step S4.

[0132] S6, such as Figure 11 As shown, a third epitaxial layer 70 is formed on the side of the protrusion 20 and epitaxial portion 40 away from the supporting substrate 30. The doping concentration of the third epitaxial layer 70 is less than the doping concentration of the first epitaxial layer 50.

[0133] Based on the RC-IGBT fabricated using the aforementioned semiconductor structure 1000, the third epitaxial layer 70 with a lower doping concentration can form a high-resistance isolation region between the cathode region 5 near the buffer layer 4 and the collector region 6. This effectively increases the lateral resistance between the cathode region 5 and the buffer layer 4, delaying the start-up speed of hole injection and the current rise rate in the collector region 6 when the RC-IGBT switches from the reverse conduction state back to the forward blocking state. This makes the current commutation process when the RC-IGBT switches from the reverse conduction state back to the forward blocking state smoother, reducing the risk of collector C voltage spikes and voltage bounces caused by sudden current changes, and improving the switching stability and system reliability of the RC-IGBT.

[0134] As an example, the process for forming the third epitaxial layer 70 in S6 can be as follows: The support substrate 30 with protrusions 20 and epitaxial portion 40 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104Pa~700 mbar, H2 is introduced into the reaction chamber as a carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C3H8, and N2 are also introduced, with the flow rate of SiH4 being 15 sccm~24 sccm, the flow rate of C3H8 being 5 sccm~10 sccm, and the flow rate of N2 being 1 sccm~2000 sccm. After a certain reaction time, N-type doping is obtained with a doping concentration of 1e13 cm⁻¹. - ³~1e18 cm - The third epitaxial layer 70 of ³.

[0135] Alternatively, as an example, the process for forming the third epitaxial layer 70 in S6 can be as follows: The support substrate 30 with the protrusions 20 and the epitaxial portion 40 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as a carrier gas at a flow rate of 10 L / min~80 L / min, along with SiH4, C2H4, and NH3. Specifically, the flow rate of SiH4 is 15 sccm~24 sccm, the flow rate of C2H4 is 5 sccm~10 sccm, and the flow rate of NH3 is approximately 3 sccm. After a certain reaction time, N-type doping is obtained with a doping concentration of 1e13 cm⁻¹. - ³~1e18 cm - The third epitaxial layer 70 of ³.

[0136] In some embodiments, the carbon-to-silicon ratio of the third epitaxial layer 70 is 1.0 to 1.5.

[0137] In some possible implementations, such as Figure 12As shown, the method for preparing the semiconductor structure 1000 may further include S7 after S5.

[0138] S7, such as Figure 13 As shown, a fourth epitaxial layer 80 is formed on the side of the second epitaxial layer 60 away from the supporting substrate 30. The doping concentration of the fourth epitaxial layer 80 is greater than that of the second epitaxial layer 60.

[0139] Based on the above semiconductor structure 1000, the RC-IGBT prepared by the higher doping concentration of the fourth epitaxial layer 80 can reduce the lateral series resistance between the cell structures, thereby improving the uniformity of the forward conduction current distribution between and within each cell structure, and thus improving the conduction performance of the RC-IGBT.

[0140] As an example, the process for forming the third epitaxial layer 70 in S7 can be as follows: The support substrate 30, which includes the protrusions 20, the epitaxial portion 40, the first epitaxial layer 50, and the second epitaxial layer 60, is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as a carrier gas at a flow rate of 10 L / min~80 L / min. SiH4, C3H8, and N2 are also introduced, with the SiH4 flow rate being 15 sccm~24 sccm, the C3H8 flow rate being 5 sccm~10 sccm, and the N2 flow rate being 1 sccm~2000 sccm. After a certain reaction time, N-type doping is obtained, with a doping concentration of 1e15 cm⁻¹. - ³~2e17 cm - The fourth epitaxial layer 80 of ³.

[0141] Alternatively, as an example, the process for forming the third epitaxial layer 70 in S6 can be as follows: The support substrate 30 with the protrusions 20 and the epitaxial portion 40 is placed in the reaction chamber of a SiC CVD epitaxial furnace. Under an environment of 1550℃~1650℃ and 104 Pa~700 mbar, H2 is introduced into the reaction chamber as a carrier gas at a flow rate of 10 L / min~80 L / min, along with SiH4, C2H4, and NH3. Specifically, the flow rate of SiH4 is 15 sccm~24 sccm, the flow rate of C2H4 is 5 sccm~10 sccm, and the flow rate of NH3 is approximately 3 sccm. After a certain reaction time, N-type doping is obtained with a doping concentration of 1e15 cm⁻¹. - ³~2e17 cm - The fourth epitaxial layer 80 of ³.

[0142] In some embodiments, the carbon-to-silicon ratio of the fourth epitaxial layer 80 is 0.7 to 1.0.

[0143] In some possible implementations, such as Figure 14 As shown, the method for preparing the semiconductor structure 1000 may further include S8 after S5.

[0144] S8, such as Figure 15 As shown, the support substrate 30 is ground on the second surface 12 until the protrusion 20 and the extension 40 are exposed.

[0145] As an example, an RC-IGBT front cell structure can be fabricated based on a semiconductor structure 1000 including a support substrate 30. After the fabrication of the RC-IGBT front cell structure is completed, step S8 is executed to remove the support substrate 30.

[0146] Specifically, the second surface 12 can be ground by using a CMP polishing device to grind the support substrate 30 until the protrusion 20 and the extension 40 are exposed.

[0147] In some possible implementations, the method for fabricating the semiconductor structure 1000 described above may further include, after S8: fabricating a contact region 1, an emitter region 2, a gate G, and an emitter E on the surface of the second epitaxial layer 60 away from the first epitaxial layer 50; and fabricating a collector C on the surface of the protrusion 20 and the epitaxial portion 40 away from the first epitaxial layer 50. Thus, an RC-IGBT can be obtained.

[0148] In another aspect of this disclosure, a semiconductor structure 1000 is provided, which is fabricated using the method described in any of the above embodiments. An RC-IGBT is obtained by fabricating a front cell structure and a back collector C based on this semiconductor structure 1000. Of course, any semiconductor device with a similar structure can also be fabricated based on this semiconductor structure 1000. For example, a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS) can also be fabricated based on this semiconductor structure 1000. This disclosure does not specifically limit the scope of the application.

[0149] like Figure 16As shown, the semiconductor structure 1000 includes a composite layer 240, a first epitaxial layer 50, and a second epitaxial layer 60. The composite layer 240 includes a plurality of protrusions 20 spaced apart. The composite layer 240 also includes epitaxial portions 40 located between adjacent protrusions 20. The two surfaces of the protrusions 20 in the thickness direction X and the two surfaces of the epitaxial portions 40 in the thickness direction X are flush. The protrusions 20 and the epitaxial portions 40 have different doping types.

[0150] In some possible implementations, such as Figure 17 As shown, the semiconductor structure 1000 also includes a support substrate 30, which is located on the side of the composite layer 240 away from the first epitaxial layer 50. The material of the support substrate 30 is the same as that of the protrusion 20.

[0151] In some possible implementations, such as Figure 18 As shown, the semiconductor structure 1000 also includes a third epitaxial layer 70, which is located between the composite layer 240 and the first epitaxial layer 50. The doping concentration of the third epitaxial layer 70 is less than that of the first epitaxial layer 50.

[0152] In some possible implementations, such as Figure 19 As shown, the semiconductor structure 1000 also includes a fourth epitaxial layer 80, which is located on the side of the second epitaxial layer 60 away from the composite layer 240, and the doping concentration of the fourth epitaxial layer 60 is greater than that of the second epitaxial layer 60.

[0153] In some possible implementations, such as Figure 1 As shown, the semiconductor structure 1000 may further include a gate G, an emitter E, a contact region 1, an emitter region 2, and a collector C. The positional relationships and operational mechanisms of these structures can be referred to the above description of RC-IGBTs, and will not be repeated here in the embodiments of this disclosure.

[0154] The beneficial effects that the semiconductor structure 1000 can achieve can be referred to the beneficial effects of the preparation method of the semiconductor structure 1000 described above, and will not be repeated here in the embodiments of this disclosure.

[0155] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; The substrate includes a first surface and a second surface, the first surface and the second surface being opposite each other in the thickness direction of the substrate; The substrate is etched on the first surface to form a protrusion and a supporting substrate; The plurality of protrusions are spaced apart on one side of the support base; An extension portion is formed on the side of the support base near the protrusion; The epitaxial portion is located between the protrusions, and the protrusions and the epitaxial portion have different doping types; A first epitaxial layer is formed on the side of the protrusion and the epitaxial portion away from the supporting substrate, and the doping concentration of the first epitaxial layer is less than the doping concentration of the protrusion. A second epitaxial layer is formed on the side of the first epitaxial layer away from the supporting substrate, and the doping concentration of the second epitaxial layer is less than that of the first epitaxial layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of etching the substrate on the first surface to form a protrusion and a supporting substrate includes: A mask pattern is formed on the first surface, the mask pattern including an opening that exposes a portion of the substrate; Using an etchant, the mask pattern and the exposed portion of the substrate are simultaneously etched to form the protrusion and the support substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The ratio of the etching rate of the etchant on the mask pattern to the etching rate of the etchant on the substrate is greater than or equal to 4.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method of forming an extension on the side of the support base near the protrusion includes: In the environment of the first carrier gas, the first growth gas reacts with the first doping source gas to form the initial epitaxial portion; The surface of the initial epitaxial portion away from the supporting substrate is ground to expose the protrusion, thus forming the epitaxial portion.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first growth gas includes silicon source gas and carbon source gas, and the first doping source gas includes P-type doping source gas.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the first epitaxial layer on the side of the protrusion and the epitaxial portion away from the supporting substrate, the method further includes: In-situ vapor phase etching pretreatment is performed on the surface of the protrusion and the epitaxial portion away from the supporting substrate to reduce the surface roughness of the protrusion and the epitaxial portion.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The formation of a first epitaxial layer on the side of the protrusion and the epitaxial portion away from the supporting substrate includes: In the environment of the second carrier gas, the second growth gas reacts with the second doping source gas to form the first epitaxial layer. The second growth gas includes silicon source gas and carbon source gas, and the second doping source gas includes N-type doping source gas.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming a second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate includes: In the environment of the third carrier gas, the third growth gas reacts with the third doping source gas to form the second epitaxial layer. The third growth gas includes silicon source gas and carbon source gas. The ratio of the number of carbon atoms to the number of silicon atoms in the second growth gas is less than the ratio of the number of carbon atoms to the number of silicon atoms in the third growth gas. The third doping source gas includes N-type doping source gas.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the first epitaxial layer on the side of the protrusion and the epitaxial portion away from the supporting substrate, the method further includes: A third epitaxial layer is formed on the side of the protrusion and the epitaxial portion away from the supporting substrate, and the doping concentration of the third epitaxial layer is less than that of the first epitaxial layer.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate, the method further includes: A fourth epitaxial layer is formed on the side of the second epitaxial layer away from the supporting substrate, and the doping concentration of the fourth epitaxial layer is greater than that of the second epitaxial layer.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 10, characterized in that, After forming the second epitaxial layer on the side of the first epitaxial layer away from the supporting substrate, the method further includes: The support substrate is ground on the second surface until the protrusion and the extension are exposed.

12. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 11; the semiconductor structure comprises: The composite layer includes a plurality of protrusions arranged at intervals; the composite layer also includes an epitaxial portion located between adjacent protrusions, wherein the two surfaces of the protrusions in the thickness direction and the two surfaces of the epitaxial portion in the thickness direction are respectively flush, and the protrusions and the epitaxial portion have different doping types. A first epitaxial layer is located on one side of the composite layer, and the doping concentration of the first epitaxial layer is less than the doping concentration of the protrusion. The second epitaxial layer is located on the side of the first epitaxial layer away from the composite layer, and the doping concentration of the second epitaxial layer is less than that of the first epitaxial layer.

13. The semiconductor structure according to claim 12, characterized in that, Also includes: A support substrate is located on the side of the composite layer away from the first epitaxial layer, and the material of the support substrate is the same as the material of the protrusion.

14. The semiconductor structure according to claim 11, characterized in that, Also includes: A third epitaxial layer is located between the composite layer and the first epitaxial layer, and the doping concentration of the third epitaxial layer is less than that of the first epitaxial layer.

15. The semiconductor structure according to claim 11, characterized in that, Also includes: The fourth epitaxial layer is located on the side of the second epitaxial layer away from the composite layer, and the doping concentration of the fourth epitaxial layer is greater than that of the second epitaxial layer.

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