Well region forming process for p-type field effect transistor
Patent Information
- Application Number
- CN202610542008.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-22
- Publication Date
- 2026-08-18
AI Technical Summary
然而，上述方法会影响器件栅氧的电学厚度Tinv，导致器件速度发生偏移，也可能会造成核心器件的漏电控制变差
1. 通过在N阱注入工艺之后增加一道锗离子注入工艺，从而在后续的高温热退火工艺之后，在顶层硅中形成一层位于N型阱区上方的锗-硅层。由于Ge-Si之间的存在势垒高度差，形成空穴陷阱，减少沟道处的空穴能量，从而减少空穴打断Si-H键、游离氢原子向栅极扩散的可能性，进而在不影响器件性能的情况下增强了器件的NBTI可靠性。
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Figure CN122602525A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically to a well region formation process for a P-type field-effect transistor. Background Technology
[0002] With the development of automotive electronics, the reliability requirements for automotive chips are getting higher and higher. Specifically, in terms of NBTI (Negative Bias Temperature Instability) reliability, not only has the test temperature increased (from 125 degrees Celsius to 150 degrees Celsius), but the failure rate requirements are also more stringent (from 0.1% to 1PPM).
[0003] NBTI is primarily related to the quality of the gate oxide layer. When a voltage is applied to the PMOS gate, a strong inversion occurs in the channel region, where holes act as the main charge carriers, carrying out current transport. These holes break the Si-H bonds at the gate oxide interface, causing free hydrogen atoms to form hydrogen gas or hydrated hydrogen ions that diffuse towards the gate. This leads to a decrease in the actual gate voltage, affecting the device's turn-on current and causing NBTI failure.
[0004] Currently, the reliability of NBTI is mainly improved by increasing gate oxide thickness, optimizing gate oxide quality, reducing electric field strength, and reducing dangling bonds. However, these methods affect the electrical thickness (Tinv) of the device gate oxide, causing device speed deviations and potentially worsening leakage current control of core devices. Summary of the Invention
[0005] This application provides a well formation process for P-type field-effect transistors, which can improve NBTI reliability without affecting device performance.
[0006] This application provides a well region formation process for a P-type field-effect transistor, including: S1: Provide a semiconductor substrate, wherein an active region is defined in the top silicon layer of the semiconductor substrate by shallow trench isolation; S2: A patterned photoresist layer is formed on the semiconductor substrate, and the openings in the photoresist layer define ion implantation windows; S3: Perform an N-well implantation process to form a plurality of N impurity implantation regions distributed from bottom to top in the active region; S4: Perform germanium ion implantation process using the photoresist layer as a mask to form a germanium ion implantation region in the active region that is located above all the N impurity implantation regions; S5: Remove the photoresist layer; S6: Perform a thermal annealing process to form an N-type well region and a germanium-silicon layer on the N-type well region in the active region of the top silicon layer.
[0007] In some embodiments, the N-well implantation process to form a plurality of N impurity implantation regions distributed from bottom to top in the active region includes: A first phosphorus ion implantation process is performed using the photoresist layer as a mask to form a first phosphorus ion implantation region in the active region. A second phosphorus ion implantation process is performed using the photoresist layer as a mask to form a second phosphorus ion implantation region in the active region, the second phosphorus ion implantation region being located above the first phosphorus ion implantation region. An arsenic ion implantation process is performed using the photoresist layer as a mask to form an arsenic ion implantation region in the active region, the arsenic ion implantation region being located above the second phosphorus ion implantation region.
[0008] In some embodiments, the ion implantation dose of the first phosphorus ion implantation process is 8 × 10⁻⁶. 12 cm -2 ~1.3×10 13 cm -2 The injected energy is 300~410keV; The ion implantation dose for the second phosphorus ion implantation process is 1.8 × 10⁻⁶. 13 cm -2 ~2.6×10 13 cm -2 The injected energy is 150~250keV; The ion implantation dose in the arsenic ion implantation process is 5.1 × 10⁻⁶. 12 cm -2 ~7.1×10 12 cm -2 The injected energy is 30~70keV.
[0009] In some embodiments, the ion implantation dose of the germanium ion implantation process is 1×10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The injected energy is 5~20keV.
[0010] In some embodiments, the germanium-silicon layer is formed at a depth of 200 to 400 angstroms in the top silicon layer.
[0011] In some embodiments, the annealing temperature of the hot annealing process is 900℃~1100℃.
[0012] In some embodiments, prior to step S2, the method further includes: A protective oxide layer is formed on the surface of the semiconductor substrate; The protective oxide layer is removed before the thermal annealing process.
[0013] The technical solution of this application has at least the following advantages: 1. By adding a germanium ion implantation process after the N-well implantation process, a germanium-silicon layer is formed in the top silicon layer above the N-type well region after the subsequent high-temperature thermal annealing process. Due to the potential barrier height difference between Ge and Si, hole traps are formed, reducing hole energy at the channel. This reduces the possibility of holes breaking Si-H bonds and free hydrogen atoms diffusing to the gate, thereby enhancing the NBTI reliability of the device without affecting device performance. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0015] Figure 1 This is a flowchart of a well region formation process for a P-type field-effect transistor provided in an exemplary embodiment of this application; Figures 2-5 This is a schematic diagram of the device structure during the implementation of a well region formation process for a P-type field-effect transistor, provided by an exemplary embodiment of this application.
[0016] Explanation of reference numerals in the attached figures: 1. Top silicon layer; 2. Shallow trench isolation layer; 3. Photoresist layer; 4. Protective oxide layer; 51. First phosphorus ion implantation region; 52. Second phosphorus ion implantation region; 53. Arsenic ion implantation region; 6. Germanium ion implantation region; 7. N-type well region; 8. Germanium-silicon layer. Detailed Implementation
[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0021] This application provides a well region formation process for a P-type field-effect transistor, referring to... Figure 1 It includes the following steps: S1: Provide a semiconductor substrate, wherein an active region is defined in the top silicon layer of the semiconductor substrate by shallow trench isolation.
[0022] For example, a semiconductor substrate is provided, which may be an SOI substrate, comprising, from bottom to top, a substrate silicon, a buried oxide layer, and a top silicon layer 1. (Refer to...) Figure 2 The active region for fabricating devices is defined in the top silicon layer 1 of the semiconductor substrate by shallow trench isolation 2.
[0023] S2: A patterned photoresist layer is formed on the semiconductor substrate, and the openings in the photoresist layer define ion implantation windows.
[0024] For example, firstly, a photoresist layer is formed on the surface of a semiconductor substrate, and then the photoresist layer 3 is patterned through exposure and development processes to obtain a patterned photoresist layer 3, such as... Figure 3 As shown, the area defined by the opening in the photoresist layer 3 is the ion implantation window.
[0025] Furthermore, prior to this step, a protective oxide layer 4, such as a silicon oxide layer, is first formed on the surface of the semiconductor substrate, so that the photoresist layer 3 is formed on the protective oxide layer 4. This protective oxide layer 4 is used to protect the surface of the top silicon layer 1 in subsequent implantation processes, to prevent lattice damage to the surface of the top silicon layer 1 caused by ion implantation, and at the same time, to suppress the channeling effect during the implantation process.
[0026] S3: Perform an N-well implantation process to form a plurality of N impurity implantation regions distributed from bottom to top in the active region.
[0027] For example, using a patterned photoresist layer 3 as a mask, an N-well implantation process is performed on the active region in the top silicon layer 1, thereby forming a number of N-impurity implantation regions distributed sequentially from bottom to top in the active region.
[0028] Furthermore, this step may include the following processing: S31: Perform a first phosphorus ion implantation process using the photoresist layer as a mask to form a first phosphorus ion implantation region in the active region.
[0029] For example, the first phosphorus ion implantation region has the deepest implantation depth, forming a high concentration of P-type doping distribution in the deeper region, which is used to construct the main doped layer of the subsequently formed well region.
[0030] Furthermore, in this step, the ion implantation dose of phosphorus ions is 8 × 10⁻⁶. 12 cm -2 ~1.3×10 13 cm -2 The injected energy is 300~410keV.
[0031] S32: Using the photoresist layer as a mask, a second phosphorus ion implantation process is performed to form a second phosphorus ion implantation region in the active region, wherein the second phosphorus ion implantation region is located above the first phosphorus ion implantation region.
[0032] For example, the second phosphorus ion implantation region further enhances the doping concentration below the channel region, forming an effective channel cutoff structure, thereby suppressing the short-channel effect and the leakage-induced barrier reduction effect, reducing subthreshold leakage current, and improving the device switching characteristics and operating stability.
[0033] Furthermore, in this step, the ion implantation dose of phosphorus ions is 1.8 × 10⁻⁶. 13 cm -2 ~2.6×10 13 cm -2 The injected energy is 150~250keV.
[0034] S33: Using the photoresist layer as a mask, perform an arsenic ion implantation process to form an arsenic ion implantation region in the active region, the arsenic ion implantation region being located above the second phosphorus ion implantation region.
[0035] Furthermore, the arsenic ion implantation region is concentrated in the near-surface area of the top silicon layer to finely control the effective doping concentration on the channel surface and precisely adjust the threshold voltage of the MOS device.
[0036] Optionally, in this step, the arsenic ion implantation dose is 5.1 × 10⁻⁶. 12 cm -2 ~7.1×10 12 cm -2 The injected energy is 30~70keV.
[0037] Reference Figure 4 Through the execution of steps S31 to S33, three N impurity implantation regions, namely the first phosphorus ion implantation region 51, the second phosphorus ion implantation region 52, and the arsenic ion implantation region 53, are formed in the active region in a sequentially spaced manner from bottom to top.
[0038] S4: Perform germanium ion implantation using the photoresist layer as a mask to form a germanium ion implantation region in the active region above all the N impurity implantation regions.
[0039] For example, refer to Figure 4 After completing the N-well implantation process, the top silicon 1 is subjected to germanium ion implantation using photoresist layer 3 as a mask to form a germanium ion implantation region 6 above all N-impurity implantation regions in the active region.
[0040] Optionally, in this step, the ion implantation dose of germanium ions is 1 × 10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The injected energy is 5~20keV.
[0041] S5: Remove the photoresist layer.
[0042] For example, the photoresist layer 3 can be completely removed by plasma ashing and wet cleaning processes.
[0043] Furthermore, following this step, the protective oxide layer 4 on the surface of the semiconductor substrate will be removed by a wet cleaning process.
[0044] S6: Perform a thermal annealing process to form an N-type well region and a germanium-silicon layer on the N-type well region in the active region of the top silicon layer.
[0045] For example, refer to Figure 5 A high-temperature thermal annealing process is performed on the semiconductor substrate after germanium ion implantation. This thermal annealing activates and diffuses N-type impurities, repairing lattice damage introduced by ion implantation, ultimately forming a uniform and electrically stable N-type well region 7 within the active region of the top silicon layer 1. Simultaneously, under the high temperature of this annealing process, the implanted germanium atoms mix and reconstruct with the surface silicon atoms, forming a germanium-silicon layer 8. Due to the potential barrier height difference between Ge and Si, hole traps are formed, reducing hole energy at the channel and thus reducing the possibility of holes breaking Si-H bonds and free hydrogen atoms diffusing to the gate, enhancing the NBTI reliability of the device.
[0046] Furthermore, the germanium-silicon layer 8 is formed at a depth of 200 angstroms to 400 angstroms in the top silicon layer 1.
[0047] Furthermore, the annealing temperature for the hot annealing process is 900℃~1100℃.
[0048] The well formation process for P-type field-effect transistors provided in this application involves adding a germanium ion implantation process after the N-well implantation process. This results in the formation of a germanium-silicon layer above the N-type well region in the top silicon layer after a subsequent high-temperature thermal annealing process. Due to the potential barrier height difference between Ge and Si, hole traps are formed, reducing hole energy at the channel. This reduces the likelihood of holes breaking Si-H bonds and free hydrogen atoms diffusing to the gate, thereby enhancing the NBTI reliability of the device without affecting device performance.
[0049] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A process for forming a well region in a P-type field-effect transistor, characterized in that, include: S1: Provide a semiconductor substrate, wherein an active region is defined in the top silicon layer of the semiconductor substrate by shallow trench isolation; S2: A patterned photoresist layer is formed on the semiconductor substrate, and the openings in the photoresist layer define ion implantation windows; S3: Perform an N-well implantation process to form a plurality of N impurity implantation regions distributed from bottom to top in the active region; S4: Perform germanium ion implantation process using the photoresist layer as a mask to form a germanium ion implantation region in the active region that is located above all the N impurity implantation regions; S5: Remove the photoresist layer; S6: Perform a thermal annealing process to form an N-type well region and a germanium-silicon layer on the N-type well region in the active region of the top silicon layer.
2. The well region formation process for a P-type field-effect transistor according to claim 1, characterized in that, The N-well implantation process, which forms a plurality of N impurity implantation regions distributed from bottom to top in the active region, includes: A first phosphorus ion implantation process is performed using the photoresist layer as a mask to form a first phosphorus ion implantation region in the active region. A second phosphorus ion implantation process is performed using the photoresist layer as a mask to form a second phosphorus ion implantation region in the active region, the second phosphorus ion implantation region being located above the first phosphorus ion implantation region. An arsenic ion implantation process is performed using the photoresist layer as a mask to form an arsenic ion implantation region in the active region, the arsenic ion implantation region being located above the second phosphorus ion implantation region.
3. The well region formation process for a P-type field-effect transistor according to claim 2, characterized in that, The ion implantation dose of the first phosphorus ion implantation process is 8 × 10⁻⁶. 12 cm -2 ~1.3×10 13 cm -2 The injected energy is 300~410keV; The ion implantation dose for the second phosphorus ion implantation process is 1.8 × 10⁻⁶. 13 cm -2 ~2.6×10 13 cm -2 The injected energy is 150~250keV; The ion implantation dose in the arsenic ion implantation process is 5.1 × 10⁻⁶. 12 cm -2 ~7.1×10 12 cm -2 The injected energy is 30~70keV.
4. The well region formation process for a P-type field-effect transistor according to claim 1, characterized in that, The ion implantation dose of the germanium ion implantation process is 1×10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The injected energy is 5~20keV.
5. The well region formation process for a P-type field-effect transistor according to claim 4, characterized in that, The germanium-silicon layer is formed at a depth of 200 to 400 angstroms in the top silicon layer.
6. The well region formation process for a P-type field-effect transistor according to claim 1, characterized in that, The annealing temperature of the hot annealing process is 900℃~1100℃.
7. The well region formation process for a P-type field-effect transistor according to claim 1, characterized in that, Prior to step S2, a protective oxide layer is formed on the surface of the semiconductor substrate, which is removed before the thermal annealing process.