Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate; forming a contact hole that penetrates the interlayer dielectric layer and extends into the semiconductor substrate; forming a barrier layer on the sidewalls and bottom of the contact hole; removing the barrier layer at the bottom of the contact hole, while retaining the barrier layer on the sidewalls of the contact hole; performing ion implantation and annealing using the barrier layer on the sidewalls of the contact hole as a mask; and removing the barrier layer on the sidewalls of the contact hole. This invention, by retaining the barrier layer on the sidewalls of the contact hole as a mask for ion implantation, effectively reduces the impact of contact hole ion implantation on adjacent channel regions, improves the divergence problem of the device threshold voltage, narrows the distribution range of the threshold voltage, and improves device yield and stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, power shielded gate trench transistors (Power SGTs) have been widely used in power management, automotive electronics and other fields due to their excellent device performance. In order to meet the requirements of device miniaturization and high integration, the pitch size of power shielded gate trench transistors is gradually decreasing.

[0003] However, as the pitch continues to shrink, the distance between the contact trench (CT) and the gate trench in the device becomes increasingly shorter. In current manufacturing processes, an interlayer dielectric layer is typically formed on the semiconductor substrate, followed by etching to create contact trenches that penetrate the interlayer dielectric layer and extend into the semiconductor substrate, and then contact trench ion implantation and annealing processes are performed. For ultra-high density shielded gate trench transistors (UDSGTs), the impact of the contact trench ion implantation process on the channel region is significantly increased due to the deep penetration of the contact trench bottom into the silicon substrate and its extremely close proximity to the gate trench. This impact can lead to uneven doping concentrations in localized areas of the channel, resulting in a divergence in the device's threshold voltage (VTH) and a wider distribution range of the threshold voltage. Significant fluctuations in subsequent production line processes can easily worsen the threshold voltage dispersion, even causing device parameters at some points to exceed specifications, ultimately leading to product failure and severely impacting device yield and reliability.

[0004] Therefore, how to reduce the impact of contact hole ion implantation on the channel region, improve the distribution range of threshold voltage, and improve device yield and stability has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The technical problem this invention aims to solve is that, as the pitch of power shielded gate trench transistors gradually decreases, the distance between the contact hole and the gate trench becomes increasingly closer. This significantly increases the impact of the contact hole ion implantation process on the channel region, easily causing localized areas with either excessively high or low doping concentrations. Consequently, the threshold voltage of the device diverges, and the threshold voltage distribution range widens, severely affecting the device's yield and reliability. To address this technical problem, this invention provides a method for manufacturing a semiconductor device.

[0006] A method for manufacturing a semiconductor device, comprising:

[0007] Step 1: Provide a semiconductor substrate, form an interlayer dielectric layer on the semiconductor substrate, and form contact holes that penetrate the interlayer dielectric layer and extend into the semiconductor substrate;

[0008] Step 2: Form a barrier layer on the sidewalls and bottom of the contact hole;

[0009] Step 3: Remove the blocking layer at the bottom of the contact hole, while retaining the blocking layer on the sidewall of the contact hole;

[0010] Step 4: Using the barrier layer on the sidewall of the contact hole as a mask, perform ion implantation and annealing.

[0011] Step 5: Remove the blocking layer from the sidewall of the contact hole.

[0012] Preferably, in step one, a gate and body regions located on both sides of the gate are formed in the semiconductor substrate, the contact hole is located in the regions on both sides of the gate, and the bottom of the contact hole extends into the body region.

[0013] Preferably, in step two, the material of the barrier layer includes oxides.

[0014] Preferably, in step two, the oxide comprises a chemical vapor deposition oxide.

[0015] Preferably, in step three, a dry etching process is used to remove the barrier layer at the bottom of the contact hole.

[0016] Preferably, in step four, after the ion implantation and before the annealing process, a wet cleaning process is further performed on the semiconductor substrate.

[0017] Preferably, in step five, a wet etching process is used to remove the barrier layer on the sidewall of the contact hole.

[0018] Preferably, the semiconductor device includes a shielded gate trench transistor.

[0019] Preferably, the shielded gate trench transistor includes a power shielded gate trench transistor.

[0020] As described above, the method for manufacturing the semiconductor device of the present invention has the following beneficial effects:

[0021] This invention deposits barrier layers on the sidewalls and bottom of the contact holes, and removes the bottom barrier layer using anisotropic etching while retaining the sidewall barrier layers. This creates a self-aligned sidewall mask without adding a complex photomask. During subsequent contact hole ion implantation, this sidewall barrier layer effectively absorbs and blocks impurity ions with lateral movement components, significantly reducing the interference of ion implantation on the doping concentration of adjacent channel regions. This method effectively prevents abnormal phenomena of excessively high or low doping concentrations in local channel regions, fundamentally improving the threshold voltage divergence problem in small-pitch shielded gate trench transistors, narrowing the threshold voltage distribution range, and thus significantly improving the electrical performance stability of the device, the process window, and the overall wafer yield. Attached Figure Description

[0022] Figure 1 The diagram shows a process flow diagram of the semiconductor device manufacturing method of the present invention;

[0023] Figure 2 The diagram shows a cross-sectional structure of the semiconductor device after step one of the present invention is completed.

[0024] Figure 3 The diagram shows a cross-sectional structure of the present invention after a barrier layer is formed inside the contact hole;

[0025] Figure 4 The diagram shows a cross-sectional structure of the present invention after removing the bottom blocking layer of the contact hole;

[0026] Figure 5 The diagram shown is a cross-sectional structural schematic of the ion implantation process of the present invention.

[0027] Figure 6 The diagram shows a cross-sectional structure of the present invention after removing the blocking layer on the sidewall of the contact hole. Detailed Implementation

[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] A method for manufacturing a semiconductor device includes the following steps:

[0030] In some embodiments, the semiconductor device includes a shielded gate trench transistor. In some embodiments, the shielded gate trench transistor includes a power shielded gate trench transistor. Figure 1 As shown, Figure 1This illustration shows a schematic diagram of the process flow for a semiconductor device manufacturing method provided in an embodiment of the present invention. Power shielded gate trench transistors (PSTs) can be used as core switching elements in power management chips, automotive electronic control modules, motor drivers, DC-DC converters, and other power device applications. With the continuous evolution of semiconductor process nodes, the pitch of PSTs inevitably decreases in order to achieve lower on-resistance and higher switching speeds per unit area. This reduction in pitch requires manufacturing processes with higher alignment accuracy and topography control capabilities to precisely control the electrical parameters of the device. Especially in ultra-high density shielded gate trench transistors, the physical distance between the contact holes and the adjacent first gate 103 and second gate 106 trenches is severely compressed, resulting in a narrower process window for subsequent process steps. Any minute process deviation can cause drastic fluctuations in critical electrical parameters such as the threshold voltage.

[0031] Step 1: Provide a semiconductor substrate 100, form an interlayer dielectric layer 109 on the semiconductor substrate 100, and form contact holes that penetrate the interlayer dielectric layer 109 and extend into the semiconductor substrate 100.

[0032] In some embodiments, in step one, a first gate 103, a second gate 106, and a body region 107 located on both sides of the second gate 106 are formed in the semiconductor substrate 100. The contact hole is located in the region on both sides of the second gate 106, and the bottom of the contact hole extends into the body region 107.

[0033] Combination Figure 2 As shown, Figure 2The cross-sectional structure of the semiconductor device after step one is shown. The semiconductor substrate 100 can be made of various material systems suitable for semiconductor device fabrication. For example, the semiconductor substrate 100 may include a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium substrate, or a silicon-germanium alloy substrate. For high-frequency, high-power applications, the semiconductor substrate 100 may also use wide-bandgap semiconductor materials, such as silicon carbide substrates, gallium nitride substrates, or gallium arsenide substrates. Furthermore, the semiconductor substrate 100 may also include other III-V compound semiconductors (e.g., indium phosphide, indium arsenide) or II-VI compound semiconductors. To improve the isolation characteristics of the device, the semiconductor substrate 100 may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, a strained silicon substrate, or a composite substrate containing multiple layers of semiconductor materials. The semiconductor substrate 100 typically also includes an epitaxial layer 101 formed on it. The epitaxial layer 101 can be grown on the base substrate using epitaxial growth processes such as chemical vapor deposition, molecular beam epitaxy, or atomic layer epitaxy to provide an active region with a specific doping concentration and thickness. The epitaxial layer 101 can be in-situ doped with P-type impurities (such as boron, indium) or N-type impurities (such as phosphorus, arsenic, antimony) according to the conductivity type of the device, and can have a uniform or gradient doping concentration distribution. A drain region 110 can also be formed at the bottom of the semiconductor substrate 100. The drain region 110 is usually a highly doped region, and a metal silicide layer (such as titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide) can be further formed on its surface to reduce the back contact resistance.

[0034] The first gate 103 and the second gate 106 are typically located within a trench in the semiconductor substrate 100. In the shielded gate trench transistor structure of this embodiment, a first dielectric layer 102, a first gate 103, an isolation dielectric 104, a second dielectric layer 105, and a second gate 106 are sequentially formed from bottom to top within the trench. The first gate 103 serves as a shielding gate, and the second gate 106 serves as a control gate. The formation process may include etching trenches in the semiconductor substrate 100 using a deep reactive ion etching process, followed by forming the first dielectric layer 102 on the inner wall of the trench using a thermal oxidation or deposition process. The materials of the first dielectric layer 102 and the second dielectric layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, or high dielectric constant materials, such as hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, or combinations thereof, or may be a multilayer composite structure comprising silicon oxide and silicon nitride. Subsequently, conductive material is filled using processes such as low-pressure chemical vapor deposition, physical vapor deposition, or electroplating, and then etched back to form the first gate 103. The materials of the first gate 103 and the second gate 106 may include doped polycrystalline silicon, amorphous silicon, or metallic materials, such as tungsten, aluminum, copper, titanium, tantalum, ruthenium, and cobalt. They may also include a work function metal layer (e.g., titanium nitride, tantalum nitride, titanium aluminum alloy, titanium aluminum nitride, tantalum carbide, tantalum carbonitride), conductive metal oxides (e.g., ruthenium dioxide), or metal silicides (e.g., nickel silicide, cobalt silicide, titanium silicide, tungsten silicide). In some embodiments, the first gate 103 and the second gate 106 may also be a multilayer composite gate structure comprising a barrier layer 111, a work function adjustment layer, and a main filling metal layer.

[0035] Next, an isolation dielectric 104 is deposited. The material of the isolation dielectric 104 may include high-density plasma oxide, flowable chemical vapor deposition oxide, tetraethyl orthosilicate oxide, or spin-coated glass, etc. Then, a second dielectric layer 105 and a second gate 106 are formed. Finally, excess conductive material outside the trench is removed by a chemical mechanical polishing process. The body region 107 can be formed by implanting P-type or N-type impurity ions into the semiconductor substrate 100 and performing impurity driving through a high-temperature thermal annealing process. An active region 108 is also formed above the body region 107. The doped impurities in the body region 107 and the source region 108 may include boron, boron difluoride, indium, phosphorus, arsenic, or antimony, and a stepped or gradient doping distribution with a specific depth can be formed through multiple ion implantations of different energies and doses. An interlayer dielectric layer 109 covers the semiconductor substrate 100, the source region 108, and the second gate 106 to achieve electrical isolation between different conductive layers and provide a flat surface.

[0036] The material of the interlayer dielectric layer 109 may include undoped silicate glass, doped silicate glass such as phosphosilicate glass, borosilicate glass, or fluorosilicone glass, or may include silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or low dielectric constant materials. Further, the interlayer dielectric layer 109 may also employ ultra-low dielectric constant materials, porous dielectric materials, carbon-doped silicon oxycarbide, organic polymers such as polyimide or benzocyclobutene, or a multilayer composite structure comprising an etch stop layer and a main dielectric layer. The interlayer dielectric layer 109 may be formed by plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or spin-coating processes.

[0037] The process for forming contact holes encompasses two main stages: photolithography and etching. Specifically, firstly, photoresist is coated onto the surface of the interlayer dielectric layer 109. Through pre-baking, exposure, development, and hardening steps, the contact hole pattern on the mask is transferred onto the photoresist. The photoresist used in the photolithography process can include deep ultraviolet (DUV) photoresist or extreme ultraviolet (EUV) photoresist. Before coating the photoresist, a bottom anti-reflective coating and a hard mask layer composed of titanium nitride, silicon oxynitride, or amorphous carbon can be sequentially formed on the surface of the interlayer dielectric layer 109 to improve lithographic resolution and etching selectivity. Subsequently, the semiconductor substrate 100 with the patterned photoresist is fed into a plasma etching machine. Using reactive ion etching (RIE) or inductively coupled plasma (ICP-CPE) processes, the interlayer dielectric layer 109 and a portion of the semiconductor substrate 100 are sequentially etched downwards. The etching gas can be switched depending on the material being etched. For example, a fluorocarbon-based gas (such as carbon tetrafluoride, trifluoromethane, octafluorocyclobutane, octafluorocyclopentene, or difluoromethane) can be used when etching the interlayer dielectric layer 109, while a bromine-based or chlorine-based gas (such as chlorine, hydrogen bromide, or boron trichloride) can be used when etching the semiconductor substrate 100. Oxygen, nitrogen, argon, or helium can be added in appropriate amounts to control the etching morphology and polymer deposition, thereby forming a contact hole that penetrates the interlayer dielectric layer 109, penetrates the source region 108, and extends into the body region 107. Because the bottom of the contact hole extends deep into the body region 107 and is spatially very close to the second gate 106, this compact structural layout makes it easy for lateral diffusion of impurity ions to occur during the subsequent ion implantation process at the bottom of the contact hole, which in turn has an undesirable effect on the doping distribution in the channel region near the second gate 106.

[0038] Step 2: Form a barrier layer 111 on the sidewalls and bottom of the contact hole.

[0039] In some embodiments, in step two, the material of the barrier layer 111 includes oxides.

[0040] In some embodiments, in step two, the oxide includes a chemical vapor deposition oxide.

[0041] Combination Figure 3 As shown, Figure 3 The cross-sectional structure after forming the barrier layer 111 within the contact hole is shown. The main function of the barrier layer 111 is to act as a sacrificial mask in the subsequent ion implantation process, adjusting the depth and lateral distribution of implanted ions into the semiconductor substrate 100 through physical blocking. Besides oxides, the material of the barrier layer 111 can be other dielectric materials selected based on process compatibility, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, or high dielectric constant materials such as hafnium oxide, aluminum oxide, and tantalum oxide. Using chemical vapor deposition (CVD) to form oxides can achieve excellent step coverage and film uniformity, ensuring that the sidewalls and bottom of the contact hole with a high aspect ratio are continuously and uniformly covered by the barrier layer 111. Specific forms of CVD processes can include low-pressure CVD, plasma-enhanced CVD, high-density plasma-enhanced CVD, or atomic layer deposition (ALD). For example, when using ALD, single-atom-level layer-by-layer growth can be achieved on the inner surface of the contact hole by alternately introducing precursor and reactive gases, thereby obtaining excellent thickness control precision. The above deposition processes can all be performed in the corresponding chemical vapor deposition chamber or atomic layer deposition chamber. The thickness of the barrier layer 111 can be flexibly adjusted according to the critical dimensions of the contact hole, the sidewall morphology, and the energy of subsequent ion implantation. Precise control of the thickness of the barrier layer 111 can prevent the bottom of the contact hole from being completely filled by the barrier layer 111 material or from becoming closed, thus reserving sufficient physical space for subsequent bottom-oriented etching and ion implantation.

[0042] Step 3: Remove the blocking layer 111 at the bottom of the contact hole, while retaining the blocking layer 111 on the sidewall of the contact hole.

[0043] In some embodiments, in step three, a dry etching process is used to remove the barrier layer 111 at the bottom of the contact hole.

[0044] Combination Figure 4 As shown, Figure 4The cross-sectional structure after removing the bottom barrier layer 111 of the contact hole is shown. Dry etching processes exhibit highly anisotropic etching characteristics. Their mechanism primarily relies on the vertical physical bombardment of ions accelerated by an electric field in the plasma, supplemented by a chemical reaction of free radicals. By finely adjusting process parameters in the dry etching apparatus, such as RF bias power, RF source power, gas flow rate ratio, chamber pressure, and electrostatic chuck temperature, high selectivity and high directionality etching of the bottom barrier layer 111 of the contact hole can be achieved, while maximizing the preservation of the barrier layer 111 on the sidewalls of the contact hole, forming a sidewall-like structure. The etching gas combination can include fluorine-based gases, such as carbon tetrafluoride, trifluoromethane, difluoromethane, octafluorocyclobutane, or sulfur hexafluoride, and can be mixed with inert gases such as argon, helium, and xenon as carrier gases to stabilize the plasma, or appropriate amounts of oxygen and nitrogen can be added to adjust the etching selectivity and polymer deposition rate. During the etching process, endpoint detection techniques such as optical emission spectroscopy can be used to monitor the etching progress in real time, ensuring that the bottom barrier layer 111 is completely removed without excessively damaging the bottom semiconductor substrate 100. Removing the bottom barrier layer 111 exposes the body region 107 of the semiconductor substrate 100 at the bottom of the contact hole, opening a channel for subsequent impurity ion implantation. The barrier layer 111 retained on the sidewall can effectively block ions with a certain divergence angle or that are scattered during subsequent ion implantation, reducing the range of ion lateral diffusion into the contact hole. This structural design of retaining the barrier layer 111 on the sidewall can reduce the interference of contact hole ion implantation on the doping concentration of adjacent channel regions, prevent abnormal phenomena of excessively high or low doping concentration in local channel regions, thereby improving the divergence problem of the device threshold voltage, narrowing the distribution range of the threshold voltage, and improving the electrical performance stability of the device and the overall yield of the wafer.

[0045] Step 4: Using the barrier layer 111 on the sidewall of the contact hole as a mask, perform ion implantation and annealing.

[0046] In some embodiments, step four, after ion implantation and before annealing, further includes a wet cleaning process for the semiconductor substrate 100.

[0047] Combination Figure 5 As shown, Figure 5The cross-sectional structure for performing an ion implantation process is shown. The ion implantation process is used to form specific doped regions in the semiconductor substrate 100 at the bottom of the contact hole, such as forming a highly concentrated heavily doped contact region 112 within the body region 107, to reduce the ohmic contact resistance between the subsequent metal plug and the semiconductor substrate 100. The type of implanted ions can be selected according to the conductivity type of the device; for example, boron ions, boron difluoride ions, or indium ions can be selected for P-type regions, and phosphorus ions, arsenic ions, or antimony ions can be selected for N-type regions. During implantation in the ion implanter, specific implantation energy, implantation dose, and tilt angle can be set. During ion implantation, the barrier layer 111 on the sidewall of the contact hole absorbs some ions with lateral motion components, limiting the lateral implantation range of the ions. A wet cleaning process is used to remove surface polymer residues, photoresist residues, microparticles, or metal ion contamination that may occur during ion implantation. The cleaning solution may include a mixture of sulfuric acid and hydrogen peroxide, a mixture of ammonia and hydrogen peroxide, a mixture of hydrochloric acid and hydrogen peroxide, dilute hydrofluoric acid, or buffered oxide etching solution, etc. Wet cleaning can be performed by immersion in a wet cleaning tank or by spraying combined with mega-sonic oscillation in a single-wafer cleaning device. Annealing is used to activate the implanted impurity ions, enabling them to enter the alternative sites in the semiconductor lattice and repair lattice damage or amorphization layers caused by high-energy ion bombardment during ion implantation. Annealing can be performed using processes such as rapid thermal annealing, rapid thermal treatment, laser spike annealing, flash lamp annealing, or traditional furnace tube annealing. Ion implantation can be performed in a high-energy or medium-current ion implanter, and annealing can be completed in a rapid thermal treatment device or a high-temperature annealing furnace. Due to the presence of the sidewall barrier layer 111, the lateral thermal diffusion of impurity ions during annealing is also controlled, further ensuring the uniformity of doping concentration in the channel region and the consistency of device electrical parameters.

[0048] Step 5: Remove the blocking layer 111 from the sidewall of the contact hole.

[0049] In some embodiments, in step five, a wet etching process is used to remove the barrier layer 111 on the sidewall of the contact hole.

[0050] Combination Figure 6 As shown, Figure 6The cross-sectional structure after removing the sidewall barrier layer 111 of the contact hole is shown. The wet etching process, with its isotropic etching characteristics and high material selectivity, can completely remove the sidewall barrier layer 111 while minimizing damage to the surrounding interlayer dielectric layer 109, source region 108, bottom exposed body region 107, and contact region 112. When the barrier layer 111 is an oxide, the wet etching process can use an etchant containing hydrofluoric acid, such as dilute hydrofluoric acid or buffered oxide etchant with different dilution ratios. If the barrier layer 111 is made of silicon nitride, it can be removed using a hot phosphoric acid solution. The amount of material removed can be precisely controlled by adjusting the concentration, temperature, and etching time of the etchant. After removing the sidewall barrier layer 111, the contact hole is restored to its predetermined physical dimensions, preparing it for subsequent metallization processes. Subsequent processes may include conformally depositing titanium, titanium nitride, tantalum, or tantalum nitride as a barrier layer metal on the inner wall of the contact hole, followed by filling with conductive materials such as tungsten, copper, aluminum, or cobalt metal plugs using chemical vapor deposition or electroplating, and finally planarizing the surface using chemical mechanical polishing. This manufacturing method, without adding complex photomasks or additional photolithography steps, utilizes thin-film deposition and anisotropic etching processes to form a self-aligned barrier layer 111 on the sidewall of the contact hole. This solves the process pain point of excessive influence of contact hole ion implantation on the channel in small-pitch devices, broadens the process window of semiconductor manufacturing, and improves product reliability and yield.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, At least including: Step 1: Provide a semiconductor substrate, form an interlayer dielectric layer on the semiconductor substrate, and form contact holes that penetrate the interlayer dielectric layer and extend into the semiconductor substrate; Step 2: Form a barrier layer on the sidewalls and bottom of the contact hole; Step 3: Remove the blocking layer at the bottom of the contact hole, while retaining the blocking layer on the sidewall of the contact hole; Step 4: Using the barrier layer on the sidewall of the contact hole as a mask, perform ion implantation and annealing. Step 5: Remove the blocking layer from the sidewall of the contact hole.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step one, a gate and body regions located on both sides of the gate are formed in the semiconductor substrate, the contact hole is located in the regions on both sides of the gate, and the bottom of the contact hole extends into the body region.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the material of the barrier layer includes oxides.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that: In step two, the oxide includes chemical vapor deposition oxide.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step three, a dry etching process is used to remove the barrier layer at the bottom of the contact hole.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step four, after the ion implantation and before the annealing process, a wet cleaning process is also performed on the semiconductor substrate.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step five, a wet etching process is used to remove the barrier layer on the sidewall of the contact hole.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The semiconductor device includes a shielded gate trench transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that: The shielded gate trench transistor includes a power shielded gate trench transistor.

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