Transistor and method of manufacturing the same

Abstract

The disclosure provides a transistor and a preparation method thereof. The preparation method comprises: manufacturing a channel layer; manufacturing a barrier layer on the channel layer; manufacturing a gate on the barrier layer; manufacturing a passivation insulating layer covering the gate on the barrier layer; manufacturing a source-drain layer on the passivation insulating layer, the source-drain layer being in contact with the barrier layer through the passivation insulating layer; manufacturing an interlayer insulating layer covering the source-drain layer on the source-drain layer, the stress of the interlayer insulating layer being-26.64 MPa, the interlayer insulating layer comprising a silicon nitride dielectric layer and a silicon oxide dielectric layer which are stacked in sequence, and the silicon-nitrogen ratio of the silicon nitride dielectric layer being less than a threshold value.

Description

Technical Field

[0001] This disclosure relates to the field of power devices, and in particular to a transistor and a method for fabricating the same. Background Technology

[0002] In the fabrication of GaN power devices, the reliability of the back-end interconnect process directly affects the device's electrical performance and long-term stability. A typical epitaxial structure of a GaN power device includes a Si substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer. Multiple dielectric layers (such as MOSiN, AlN, LPSiN, PESiN, etc.) are sequentially deposited on top as passivation insulating layers. Then, a metal layer Ti / AlSi / TiN is deposited as the source / drain layer (also called the contact layer). Next, a dielectric layer such as silicon oxide is deposited as an interlayer insulating layer. Finally, a source / drain lead layer (also called the top metal layer) is deposited.

[0003] Due to factors such as the deposition and etching of multiple passivation insulating layers and the filling of contact layers in the preceding processes, a microscopic height difference exists on the wafer surface (i.e., the surface of the PESiO dielectric layer) formed by the accumulation of multiple structures before the metal layer is deposited. This is especially true at the dielectric layer steps or contact hole edges, where sharp angles are formed. Depositing the dielectric layer on the contact layer surface using conventional deposition methods can lead to cracks at the step corners of the metal and dielectric layers due to high stress, resulting in a decrease in transistor yield. Summary of the Invention

[0004] This disclosure provides a transistor and its fabrication method, which can significantly reduce the stress in the dielectric layer and prevent cracks from forming in the dielectric layer. The technical solution is as follows: On one hand, a method for fabricating a transistor is provided, the method comprising: Create the channel layer; A barrier layer is fabricated on the channel layer; A gate is fabricated on the barrier layer; A passivation insulating layer covering the gate is formed on the barrier layer; A source-drain layer is fabricated on the passivation insulating layer, and the source-drain layer penetrates the passivation insulating layer and contacts the barrier layer; An interlayer insulating layer is fabricated on the source-drain layer to cover the source-drain layer. The stress of the interlayer insulating layer is -27 to -26 MPa. The interlayer insulating layer includes a silicon nitride dielectric layer and a silicon oxide dielectric layer stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer is less than a threshold value.

[0005] Optionally, in the silicon nitride dielectric layer fabricated by PECVD process, SiH4 and NH3 are used as silicon source and nitrogen source, respectively, and the ratio of the flow rate of SiH4 to the flow rate of NH3 is 1:0.8 to 1:0.6.

[0006] Optionally, the flow rate of SiH4 is 200~400 sccm, and the flow rate of NH3 is 120~320 sccm.

[0007] Optionally, when fabricating the silicon nitride dielectric layer, the chamber pressure is 3000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12~14mm.

[0008] Optionally, when fabricating the silicon oxide dielectric layer, SiH4 and N2O are used as the silicon source and oxygen source, respectively, and the ratio of the flow rate of SiH4 to the flow rate of N2O is 1:10 to 1:15.

[0009] Optionally, the flow rate of SiH4 is 80~500 sccm, and the flow rate of N2O is 1200~5000 sccm.

[0010] Optionally, when fabricating the silicon oxide dielectric layer, the chamber pressure is 2000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12.5~13.2mm.

[0011] Optionally, the thickness of the silicon nitride dielectric layer is 200~700nm, and the thickness of the silicon oxide dielectric layer is 500~4000nm.

[0012] On the other hand, a transistor is provided, the transistor comprising: a channel layer, a barrier layer, a gate, a passivation insulating layer, a source-drain layer, an interlayer insulating layer, and a source-drain lead layer; The channel layer, the barrier layer, and the gate are stacked sequentially. The passivation insulating layer is located on the barrier layer and covers the gate. The source-drain layer is located on the passivation insulating layer and contacts the barrier layer through the passivation insulating layer. The interlayer insulating layer covers the source-drain layer. The stress of the interlayer insulating layer is -27 to -26 MPa. The interlayer insulating layer includes a silicon nitride dielectric layer and a silicon oxide dielectric layer stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer is less than a threshold value. The source-drain lead layer is located on the interlayer insulating layer and contacts the source-drain layer through the interlayer insulating layer.

[0013] Optionally, the thickness of the silicon nitride dielectric layer is 200~700nm, and the thickness of the silicon oxide dielectric layer is 500~4000nm.

[0014] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a passivation insulating layer is fabricated on the barrier layer. The passivation insulating layer can isolate the gate from the barrier layer and suppress gate leakage. The interlayer insulating layer includes a silicon nitride dielectric layer and a silicon oxide dielectric layer stacked sequentially. The silicon nitride dielectric layer and the silicon oxide dielectric layer have different coefficients of thermal expansion. After the silicon nitride dielectric layer and the silicon oxide dielectric layer are stacked, stress can be mutually compensated and canceled. Finally, the stress of the interlayer insulating layer is -27 to -26 MPa, so that the interlayer insulating layer as a whole reaches a stress balance state, reducing the risk of warping, cracking and interface detachment of the interlayer insulating layer. The silicon-nitrogen ratio of the silicon nitride dielectric layer is less than the threshold, which increases the number of silicon dangling bonds inside the silicon nitride dielectric layer, thereby releasing the internal stress of the silicon nitride dielectric layer, solving the problem of thermal stress cracking caused by severe mismatch of thermal expansion coefficients, and improving the yield of transistors. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure embodiment; Figure 3 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure; Figure 4 These are topographic images of the interlayer insulation layer provided by related technologies; Figure 5 This is a topographic diagram of the interlayer insulation layer provided in an embodiment of this disclosure.

[0017] The attached figures are labeled as follows: 100: Substrate; 101: Channel layer; 102: Barrier layer; 103: Gate; 104: Passivation insulating layer; 105: Source / drain layer; 106: Interlayer insulating layer; 107: Source / drain lead layer; 108: Buffer layer; 1041: First dielectric sublayer; 1042: Second dielectric sublayer; 1043: Third dielectric sublayer; 1044: Fourth dielectric sublayer; 1045: Fifth dielectric sublayer; 1061: Silicon nitride dielectric layer; 1062: Silicon oxide dielectric layer; 2001: Ellipse. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0019] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure. See also... Figure 1 The method includes the following steps: S11, Create channel layer 101.

[0020] S12. A barrier layer 102 is fabricated on the channel layer 101.

[0021] The channel layer 101 and the barrier layer 102 constitute a heterojunction, providing a two-dimensional electron gas.

[0022] S13. A gate 103 is fabricated on the barrier layer 102.

[0023] S14. A passivation insulating layer 104 covering the gate 103 is formed on the barrier layer 102.

[0024] S15. A source-drain layer 105 is formed on the passivation insulating layer 104, and the source-drain layer 105 passes through the passivation insulating layer 104 and contacts the barrier layer 102.

[0025] S16. An interlayer insulating layer 106 is formed on the source-drain layer 105 to cover the source-drain layer 105. The stress of the interlayer insulating layer 106 is -27 to -26 MPa. The interlayer insulating layer 106 includes a silicon nitride dielectric layer 1061 and a silicon oxide dielectric layer 1062 stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer 1061 is less than a threshold value.

[0026] For example, the stress of the interlayer insulation layer 106 is -26.64 MPa.

[0027] The theoretical stoichiometry of silicon nitride (Si3N4) is Si / N = 0.75, corresponding to an ideal gas reaction ratio of NH3 / SiH4 = 4 / 3 ≈ 1.33. Therefore, in this embodiment, the threshold value can be 1.33.

[0028] In plasma-enhanced chemical vapor deposition (PECVD), the higher the SiH4 flow rate and the lower the NH3 flow rate, the higher the silicon-nitrogen ratio; conversely, the lower the NH3 flow rate and the lower the silicon-nitrogen ratio.

[0029] In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a passivation insulating layer is fabricated on the barrier layer. The passivation insulating layer can isolate the gate from the barrier layer and suppress gate leakage. The interlayer insulating layer includes a silicon nitride dielectric layer and a silicon oxide dielectric layer stacked sequentially. The silicon nitride dielectric layer and the silicon oxide dielectric layer have different coefficients of thermal expansion. After the silicon nitride dielectric layer and the silicon oxide dielectric layer are stacked, stress can be mutually compensated and canceled. Finally, the stress of the interlayer insulating layer is -27 to -26 MPa, so that the interlayer insulating layer as a whole reaches a stress balance state, reducing the risk of warping, cracking and interface detachment of the interlayer insulating layer. The silicon-nitrogen ratio of the silicon nitride dielectric layer is less than the threshold, which increases the number of silicon dangling bonds inside the silicon nitride dielectric layer, thereby releasing the internal stress of the silicon nitride dielectric layer, solving the problem of thermal stress cracking caused by severe mismatch of thermal expansion coefficients, and improving the yield of transistors.

[0030] Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure. See also... Figure 2 The method includes the following steps: S21. A buffer layer 108, a channel layer 101, and a barrier layer 102 are sequentially formed on the substrate.

[0031] In this embodiment of the disclosure, the substrate 100 can be any one of a sapphire substrate, a Si substrate, a SiC substrate, and a GaN substrate, and the material of the substrate is not limited in this embodiment of the disclosure.

[0032] For example, substrate 100 is a Si substrate.

[0033] In this embodiment of the disclosure, a buffer layer 108, a channel layer 101, and a barrier layer 102 are sequentially fabricated using a metal-organic chemical vapor deposition (MOCVD) process.

[0034] In one example, step S21 includes: The first step is to fabricate a buffer layer 108 on the substrate 100.

[0035] In this embodiment of the disclosure, the buffer layer 108 can be a GaN buffer layer.

[0036] In this embodiment of the disclosure, the thickness of the buffer layer 108 can be 1000~2000nm.

[0037] For example, the thickness of the buffer layer 108 is 1000, 1500 or 2000 nm.

[0038] The second step is to create a channel layer 101 on the buffer layer 108.

[0039] In this embodiment of the disclosure, the channel layer 101 may be a GaN channel layer.

[0040] In this embodiment of the disclosure, the thickness of the channel layer 101 can be 250~270nm.

[0041] For example, the thickness of the channel layer 101 is 250, 260 or 270 nm.

[0042] The third step is to fabricate a barrier layer 102 on the channel layer 101.

[0043] In this embodiment of the disclosure, the barrier layer 102 can be an AlGaN barrier layer.

[0044] In this embodiment of the disclosure, the thickness of the barrier layer 102 can be 20~50nm.

[0045] For example, the thickness of the barrier layer 102 is 20, 35, or 50 nm.

[0046] S22. A passivation insulating layer 104 is fabricated on the barrier layer 102.

[0047] In this embodiment of the disclosure, the passivation insulating layer 104 may include a first dielectric sublayer 1041, a second dielectric sublayer 1042, a third dielectric sublayer 1043, a fourth dielectric sublayer 1044, and a fifth dielectric sublayer 1045.

[0048] In one example, step S22 includes: The first step is to fabricate a SiN layer on the barrier layer 102 using the MOCVD process, which serves as the first dielectric sublayer 1041.

[0049] In this implementation, an MOCVD device is used to fabricate a SiN layer on the barrier layer as the first dielectric sublayer, which makes the fabricated film layer denser and has fewer impurities, thus passivating the barrier layer and preventing it from being eroded by water vapor in the external environment.

[0050] In this embodiment of the disclosure, the thickness of the first dielectric sublayer 1041 can be 50~60nm.

[0051] In this implementation, the thickness of the first dielectric sublayer is 50~60nm. The first dielectric sublayer is thick enough to provide good protection for the barrier layer. At the same time, the first dielectric sublayer of appropriate thickness can serve as a stress buffer layer to reduce the stress generated during subsequent deposition.

[0052] For example, the thickness of the first dielectric sublayer 1041 is 50, 55 or 60 nm.

[0053] The second step is to use an MOCVD device to fabricate an AlN layer on the first dielectric sublayer 1041, which serves as the second dielectric sublayer 1042.

[0054] In this implementation, an AlN layer is fabricated on the first dielectric sublayer using MOCVD technology as the second dielectric sublayer. AlN has high thermal conductivity, which can effectively conduct heat and help avoid heat concentration, thus preventing an increase in thermal stress. In addition, the AlN layer also acts as a barrier layer, preventing over-etching of the first dielectric sublayer during subsequent etching processes.

[0055] In this embodiment of the disclosure, the thickness of the second dielectric sublayer 1042 can be 1~5nm.

[0056] In this implementation, the thickness of the second dielectric sublayer is 1~5nm, which is sufficient to provide a good heat conduction channel, avoid thermal stress concentration, and the second dielectric sublayer is not too thick, thus meeting the requirements for lightweight design.

[0057] For example, the thickness of the second dielectric sublayer 1042 is 1, 3 or 5 nm.

[0058] The third step is to use MOCVD technology to fabricate a SiN layer on the second dielectric sublayer 1042, which serves as the third dielectric sublayer 1043.

[0059] In this implementation, a SiN layer is fabricated on the second dielectric sublayer using MOCVD technology, serving as the third dielectric sublayer. The SiN layer can balance the stress of the AlN layer and reduce stress concentration caused by differences in material properties.

[0060] In this embodiment of the disclosure, the thickness of the third dielectric sublayer 1043 can be 3~8nm.

[0061] In this implementation, the thickness of the third dielectric sublayer is 3~8nm, which can balance the stress of the second dielectric sublayer, reduce stress concentration caused by differences in material properties, and the third dielectric sublayer is not too thick, thus meeting the requirements for lightweighting.

[0062] For example, the thickness of the third dielectric sublayer 1043 is 3, 5, or 8 nm.

[0063] The fourth step involves fabricating a SiN layer on the third dielectric sublayer 1043 using a low-pressure chemical vapor deposition (LPCVD) process, which serves as the fourth dielectric sublayer 1044.

[0064] In this implementation, an LPCVD process is used to fabricate a SiN layer on the third dielectric sublayer as the fourth dielectric sublayer. The SiN layer prepared by LPCVD usually has low stress, which helps to reduce the stress level of the overall transistor structure. At the same time, the fourth dielectric sublayer also has a passivation effect, which can provide protection for the transistor.

[0065] In this embodiment of the disclosure, the thickness of the fourth dielectric sublayer 1044 can be 290~310nm.

[0066] In this implementation, the thickness of the fourth dielectric sublayer is 290~310nm, which is sufficient to enhance the insulation performance of the entire passivation insulating layer, and the fourth dielectric sublayer is not too thick, thus meeting the requirements for lightweight design.

[0067] For example, the thickness of the fourth dielectric sublayer 1044 is 290, 300, or 310 nm.

[0068] The fifth step is to use PECVD to fabricate a SiN layer on the fourth dielectric sublayer 1044, which will serve as the fifth dielectric sublayer 1045.

[0069] In this implementation, a SiN layer is fabricated on the fourth dielectric sublayer using the PECVD process, which serves as the fifth dielectric sublayer. PECVD has a high deposition rate and can quickly form a protective layer.

[0070] In this embodiment of the disclosure, the thickness of the fifth dielectric sublayer 1045 can be 590~610nm.

[0071] In this implementation, the thickness of the fifth dielectric sublayer can be 590~610nm. Using this thickness, it is possible to ensure the fabrication of a uniform and flat thin film on a large-area transistor, and the cost of the fifth dielectric sublayer is relatively low, making it suitable for mass production.

[0072] For example, the thickness of the fifth dielectric sublayer 1045 is 590, 600, or 610 nm.

[0073] In other embodiments, the passivation insulating layer 104 may include fewer film layers, such as only the first dielectric sublayer and the second dielectric sublayer therein.

[0074] In other embodiments, the sublayers in the passivation insulating layer 104 may also be fabricated in other ways, which will not be elaborated here.

[0075] S23. A source-drain layer 105 is fabricated on the passivation insulating layer 104.

[0076] In this embodiment of the disclosure, the source and drain layers 105 are fabricated using a PECVD process.

[0077] In this embodiment of the disclosure, the source and drain layers 105 can be a Ti, AlSi and TiN metal stack.

[0078] In other examples, the source-drain layer 105 can also be other structures, such as a TiN, Al and TiN metal stack.

[0079] S24. An interlayer insulating layer 106 is fabricated on the source-drain layer 105. The interlayer insulating layer 106 includes a silicon nitride dielectric layer 1061 and a silicon oxide dielectric layer 1062.

[0080] In one example, step S24 includes: The first step is to fabricate a silicon nitride dielectric layer 1061 on the source and drain layer 105 using the PECVD process.

[0081] In this embodiment, the silicon nitride dielectric layer 1061 can be a Si3N4 layer or a SiN layer. x Layer, x is greater than 0.

[0082] For example, the silicon nitride dielectric layer 1061 is a Si3N4 layer.

[0083] In the embodiments of this disclosure, when fabricating the silicon nitride dielectric layer 1061, SiH4 and NH3 are used as silicon source and nitrogen source, respectively, and the ratio of SiH4 flow rate to NH3 flow rate is 1:0.8 to 1:0.6.

[0084] In this implementation, the ratio of SiH4 flow rate to NH3 flow rate is 1:0.8 to 1:0.6. Compared with the silicon nitride dielectric layer fabrication process provided by related technologies, the amount of Si-H increases, which is beneficial for the passivation of semiconductor devices and reduces surface defects of semiconductor devices, thereby improving the electrical and insulating properties of semiconductor devices. Furthermore, the above ratio can achieve uniform coverage of holes and grooves.

[0085] For example, the flow rate of SiH4 to the flow rate of NH3 is 1:0.7.

[0086] In this embodiment of the disclosure, the flow rate of SiH4 is 200~400 sccm, and the flow rate of NH3 is 120~320 sccm.

[0087] In this implementation, the SiH4 flow rate is 200~400 sccm, ensuring a sufficient but not excessive supply of silicon source, resulting in stable film uniformity. This avoids the problem of insufficient silicon source leading to a loose film layer, increases the concentration of reaction precursors, significantly improves the deposition rate, and shortens the process time. Silicon atoms in the silicon-rich environment can fill the microscopic voids within the film, enhancing density and moisture barrier properties, and reducing pinhole defects. The NH3 flow rate is 120~320 sccm, which avoids excessive ammonia gas causing high tensile stress and reduces the risk of film cracking, warping, and delamination. At the same time, the above flow rate achieves a low silicon-nitrogen ratio, ensuring sufficient nitrogen elements participate in bonding to form stable Si-N bonds.

[0088] For example, the flow rate of SiH4 is 228~328 sccm, and the flow rate of NH3 is 160~230 sccm.

[0089] For example, the flow rate of SiH4 is 300 sccm, and the flow rate of NH3 is 210 sccm.

[0090] In this embodiment of the disclosure, when fabricating the silicon nitride dielectric layer 1061, the chamber pressure is 3000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12~14mm.

[0091] In this implementation, the chamber pressure is 3000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12~14mm. This can achieve low plasma energy and a mild and uniform plasma reaction, which avoids transistor surface damage caused by high-energy ion bombardment and ensures that the reactant gas can fully collide and decompose, improving the uniformity of the interlayer insulating layer. The resulting dielectric layer is crack-free and has low stress (-26.64MPa).

[0092] Low plasma energy refers to using lower radio frequency power and lower bias voltage during the deposition of silicon nitride dielectric layer, thereby reducing the degree of plasma ionization and ion bombardment kinetic energy, weakening the sputtering bombardment effect of high-energy ions on the substrate and the grown film, and keeping the film in a mild growth state.

[0093] Electrode spacing refers to the vertical distance between the high-frequency electrode in the cavity and the upper surface of the wafer.

[0094] For example, when fabricating the silicon nitride dielectric layer 1061, the chamber pressure is 4000 Torr, the high-frequency power is 400 W, and the electrode spacing is 13 mm.

[0095] In this embodiment, the growth time of the silicon nitride dielectric layer 1061 is 25~55s, and the required SiN layer thickness can be obtained under the condition that the ratio of SiH4 flow rate to NH3 flow rate is 1:0.8 to 1:0.6.

[0096] For example, the growth time of the silicon nitride dielectric layer 1061 is 30, 40 or 50 s.

[0097] In this embodiment of the disclosure, the thickness of the silicon nitride dielectric layer 1061 is 200~700nm.

[0098] In this implementation, the silicon nitride dielectric layer of the above thickness can ensure the deposition quality of the silicon nitride dielectric layer under low pressure and low silicon-nitrogen ratio conditions; at the same time, the dielectric sublayer is not too thin, which would make it easy to crack, nor is the dielectric sublayer too thick, which would make the transistor too thick.

[0099] For example, the thickness of the silicon nitride dielectric layer 1061 is 200~700nm.

[0100] The second step is to fabricate a silicon oxide dielectric layer 1062 on the silicon nitride dielectric layer 1061 using the PECVD process.

[0101] In this embodiment of the disclosure, the silicon oxide dielectric layer 1062 can be a SiO2 layer or a SiO layer.

[0102] For example, the silicon oxide dielectric layer 1062 is a SiO2 layer.

[0103] In this embodiment of the disclosure, when fabricating the silicon oxide dielectric layer 1062, SiH4 and N2O are used as silicon source and oxygen source, respectively, and the ratio of SiH4 flow rate to N2O flow rate is 1:10 to 1:15.

[0104] In this implementation, when the ratio of SiH4 flow rate to N2O flow rate is 1:10 to 1:15 to prepare the silicon oxide dielectric layer, the sufficient oxygen source can fully oxidize the silane, effectively reduce silicon dangling bonds and internal defects, reduce leakage current and improve insulation withstand voltage performance.

[0105] For example, the ratio of SiH4 flow rate to N2O flow rate is 1:13.

[0106] In this embodiment of the disclosure, the flow rate of SiH4 is 80~500 sccm, and the flow rate of N2O is 1200~5000 sccm.

[0107] In this implementation, the flow rate of SiH4 is 80~500 sccm and the flow rate of N2O is 1200~5000 sccm, which can match a reasonable ratio of reaction gases. Sufficient N2O can ensure the full oxidation reaction of silane, reduce internal defects in the film, improve the density and insulation performance of the silicon oxide dielectric layer, and reduce the risk of leakage.

[0108] For example, the flow rate of SiH4 is 200, 300 or 400 sccm, and the flow rate of N2O is 2000, 3000 or 4000 sccm.

[0109] In this embodiment of the disclosure, when fabricating the silicon oxide dielectric layer 1062, the chamber pressure is 2000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12.5~13.2mm.

[0110] In this implementation, the chamber pressure is 2000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12.5~13.2mm. This allows SiH4 and N2O to collide frequently, consuming a certain amount of kinetic energy during deposition, thereby reducing the stress generated during the deposition of the silicon oxide dielectric layer.

[0111] For example, when fabricating the silicon oxide dielectric layer 1062, the chamber pressure is 2000, 3000 or 4000 Torr, the high-frequency power is 200, 300 or 400 W, and the electrode spacing is 12.5, 13 or 13.2 mm.

[0112] In this embodiment of the disclosure, the deposition time of the silicon oxide dielectric layer 1062 is 29~210s.

[0113] For example, the deposition time of the silicon oxide dielectric layer 1062 is 100, 150 or 200 s.

[0114] In this embodiment of the disclosure, the thickness of the silicon oxide dielectric layer 1062 is 500~4000 nm.

[0115] In this implementation, using a silicon oxide dielectric layer of the aforementioned thickness ensures the deposition quality of the interlayer insulating layer; at the same time, the silicon oxide dielectric layer is neither too thin, which would make it prone to cracking, nor too thick, which would result in an overly thick transistor.

[0116] For example, the thickness of the silicon oxide dielectric layer 1062 is 500, 1500 or 2500 nm.

[0117] S25. Fabricate source and drain lead layers 107 on the interlayer insulating layer 106.

[0118] In this embodiment of the disclosure, the source and drain lead layer 107 is fabricated using a PECVD process.

[0119] In this embodiment of the disclosure, the source-drain lead layer 107 can be a Ti, AlSi and TiN metal stack.

[0120] Figure 3 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. See also... Figure 3 The transistor includes: a channel layer 101, a barrier layer 102, a gate 103, a passivation insulating layer 104, a source-drain layer 105, and an interlayer insulating layer 106.

[0121] A channel layer 101, a barrier layer 102, and a gate 103 are stacked sequentially. A passivation insulating layer 104 is located on the barrier layer 102 and covers the gate 103. A source-drain layer 105 is located on the passivation insulating layer 104 and contacts the barrier layer 102 through the passivation insulating layer 104. An interlayer insulating layer 106 covers the source-drain layer 105. The stress of the interlayer insulating layer 106 is -27 to -26 MPa. The interlayer insulating layer 106 includes a silicon nitride dielectric layer 1061 and a silicon oxide dielectric layer 1062 stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer 1061 is less than a threshold value.

[0122] In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a passivation insulating layer is fabricated on the barrier layer. The passivation insulating layer can isolate the gate from the barrier layer and suppress gate leakage. The interlayer insulating layer includes a silicon nitride dielectric layer and a silicon oxide dielectric layer stacked sequentially. The silicon nitride dielectric layer and the silicon oxide dielectric layer have different coefficients of thermal expansion. After the silicon nitride dielectric layer and the silicon oxide dielectric layer are stacked, stress can be mutually compensated and canceled. Finally, the stress of the interlayer insulating layer is -27 to -26 MPa, so that the interlayer insulating layer as a whole reaches a stress balance state, reducing the risk of warping, cracking and interface detachment of the interlayer insulating layer. The silicon-nitrogen ratio of the silicon nitride dielectric layer is less than the threshold, which increases the number of silicon dangling bonds inside the silicon nitride dielectric layer, thereby releasing the internal stress of the silicon nitride dielectric layer, solving the problem of thermal stress cracking caused by severe mismatch of thermal expansion coefficients, and improving the yield of transistors.

[0123] For example, the stress of the interlayer insulation layer 106 is -26.64 MPa.

[0124] In this embodiment of the present disclosure, the transistor may further include: a source-drain lead layer 107, which is located on the interlayer insulating layer 106 and passes through the interlayer insulating layer 106 to contact the source-drain layer 105.

[0125] In this embodiment of the disclosure, the source-drain layer 105 includes a source and a drain, and the source-drain lead layer 107 includes a source lead and a drain lead. The source lead passes through the interlayer insulating layer 106 and is connected to the source, and the drain lead passes through the interlayer insulating layer 106 and is connected to the drain.

[0126] In this implementation, the interlayer insulation layer can prevent the source lead from contacting the drain lead and the drain lead from contacting the source lead.

[0127] In this embodiment of the disclosure, the thickness of the silicon nitride dielectric layer 1061 is 200~700nm.

[0128] In this implementation, the silicon nitride dielectric layer of the above thickness can ensure the deposition quality of the silicon nitride dielectric layer under low pressure and low silicon-nitrogen ratio conditions; at the same time, the dielectric sublayer is not too thin, which would make it easy to crack, nor is the dielectric sublayer too thick, which would make the transistor too thick.

[0129] For example, the thickness of the silicon nitride dielectric layer 1061 is 200~700nm.

[0130] In this embodiment of the disclosure, the thickness of the silicon oxide dielectric layer 1062 is 500~4000 nm.

[0131] In this implementation, using a silicon oxide dielectric layer of the aforementioned thickness ensures the deposition quality of the interlayer insulating layer; at the same time, the silicon oxide dielectric layer is neither too thin, which would make it prone to cracking, nor too thick, which would result in an overly thick transistor.

[0132] For example, the thickness of the silicon oxide dielectric layer 1062 is 500, 1500 or 2500 nm.

[0133] In this embodiment of the disclosure, the channel layer 101 may be a GaN layer.

[0134] In this embodiment of the disclosure, the thickness of the channel layer 101 can be 250~270nm.

[0135] For example, the thickness of the channel layer 101 is 250, 260 or 270 nm.

[0136] In this embodiment of the disclosure, the barrier layer 102 can be an AlGaN layer.

[0137] In this embodiment of the disclosure, the thickness of the barrier layer 102 can be 20~50nm.

[0138] For example, the thickness of the barrier layer 102 is 20, 35, or 40 nm.

[0139] In this embodiment of the disclosure, the passivation insulating layer 104 may include a first dielectric sublayer 1041, a second dielectric sublayer 1042, a third dielectric sublayer 1043, a fourth dielectric sublayer 1044, and a fifth dielectric sublayer 1045 stacked sequentially.

[0140] In this embodiment of the disclosure, the first dielectric sublayer 1041 can be a SiN layer fabricated using MOCVD technology.

[0141] In this embodiment of the disclosure, the thickness of the first dielectric sublayer 1041 can be 50~60nm.

[0142] In this implementation, the thickness of the first dielectric sublayer is 50~60nm. The first dielectric sublayer is thick enough to provide good protection for the barrier layer. At the same time, the first dielectric sublayer of appropriate thickness can serve as a stress buffer layer to reduce the stress generated during subsequent deposition.

[0143] For example, the thickness of the first dielectric sublayer 1041 is 50, 55 or 60 nm.

[0144] In this embodiment of the disclosure, the second dielectric sublayer 1042 can be an AlN layer fabricated using MOCVD technology.

[0145] In this embodiment of the disclosure, the thickness of the second dielectric sublayer 1042 can be 1~5nm.

[0146] In this implementation, the thickness of the second dielectric sublayer is 1~5nm, which is sufficient to provide a good heat conduction channel and avoid thermal stress concentration. The second dielectric sublayer is not too thick, which meets the requirements of lightweight design.

[0147] For example, the thickness of the second dielectric sublayer 1042 is 1, 3 or 5 nm.

[0148] In this embodiment of the disclosure, the third dielectric sublayer 1043 can be a SiN layer fabricated using MOCVD technology.

[0149] In this embodiment of the disclosure, the thickness of the third dielectric sublayer 1043 can be 3~8nm.

[0150] In this implementation, the thickness of the third dielectric sublayer is 3~8nm, which can balance the stress of the second dielectric sublayer, reduce stress concentration caused by differences in material properties, and the third dielectric sublayer is not too thick, thus meeting the requirements for lightweighting.

[0151] For example, the thickness of the third dielectric sublayer 1043 is 3, 5, or 8 nm.

[0152] In this embodiment of the disclosure, the fourth dielectric sublayer 1044 can be a SiN layer fabricated using LPCVD technology.

[0153] In this embodiment of the disclosure, the thickness of the fourth dielectric sublayer 1044 can be 290~310nm.

[0154] In this implementation, the thickness of the fourth dielectric sublayer can be 290~310nm, which is sufficient to enhance the insulation performance of the entire passivation insulating layer, and the fourth dielectric sublayer is not too thick, thus meeting the requirements for lightweight design.

[0155] For example, the thickness of the fourth dielectric sublayer 1044 is 290, 300, or 310 nm.

[0156] In this embodiment of the disclosure, the fifth dielectric sublayer 1045 can be a SiN layer fabricated using a PECVD process.

[0157] In this embodiment of the disclosure, the thickness of the fifth dielectric sublayer 1045 can be 590~610nm.

[0158] In this implementation, the thickness of the fifth dielectric sublayer can be 590~610nm. Using this thickness, it is possible to ensure the fabrication of a uniform and flat thin film on a large-area transistor, and the cost of the fifth dielectric sublayer is relatively low, making it suitable for mass production.

[0159] For example, the thickness of the fifth dielectric sublayer 1045 is 590, 600, or 610 nm.

[0160] In this embodiment of the disclosure, the source / drain layer 105 and the source / drain lead layer 107 can be a Ti, AlSi, and TiN metal stack.

[0161] In this embodiment of the disclosure, the transistor may further include a substrate 100 and a buffer layer 108.

[0162] The buffer layer 108, the channel layer 101, the barrier layer 102 and the gate 103 are sequentially stacked on the substrate 100.

[0163] In this embodiment of the disclosure, the substrate 100 can be any one of sapphire substrate, Si substrate, SiC substrate and GaN substrate, and the material of the substrate 100 is not limited in this embodiment of the disclosure.

[0164] For example, substrate 100 is a Si substrate.

[0165] In this embodiment of the disclosure, the buffer layer 108 may be a GaN layer.

[0166] In this embodiment of the disclosure, the thickness of the buffer layer 108 can be 1000~2000nm.

[0167] For example, the thickness of the buffer layer 108 is 1000, 1500 or 2000 nm.

[0168] Figure 4 This is a topographic diagram of the interlayer insulation layer provided by related technologies. See also... Figure 4 The first image from left to right is a topographic view of the interlayer insulation layer; the second image is a magnified view of the X1 part of the topographic view of the interlayer insulation layer; the third image is a magnified view of the X2 part of the topographic view of the interlayer insulation layer. It can be seen that the interlayer insulation layer 106 has obvious cracks (at the position of ellipse 2001) and the stress is -81.69MPa.

[0169] Figure 5 This is a topographic diagram of the interlayer insulation layer provided in an embodiment of this disclosure. See also... Figure 5 The first image from left to right is a topographic view of the interlayer insulation layer, the second image is a magnified view of the Y1 part of the interlayer insulation layer topographic view, and the third image is a magnified view of the Y2 part of the interlayer insulation layer topographic view. The interlayer insulation layer 106 does not have cracks.

[0170] In this embodiment of the invention, the interlayer insulation layer fabricated using this embodiment is crack-free and has a stress of only -26.64 MPa.

[0171] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method of fabricating a transistor, comprising: The transistor fabrication method includes: Create the trench layer (101); A barrier layer (102) is fabricated on the channel layer (101); A gate (103) is fabricated on the barrier layer (102); A passivation insulating layer (104) covering the gate (103) is formed on the barrier layer (102). A source-drain layer (105) is formed on the passivation insulating layer (104), and the source-drain layer (105) passes through the passivation insulating layer (104) and contacts the barrier layer (102); An interlayer insulating layer (106) is formed on the source-drain layer (105) to cover the source-drain layer (105). The stress of the interlayer insulating layer (106) is -27 to -26 MPa. The interlayer insulating layer (106) includes a silicon nitride dielectric layer (1061) and a silicon oxide dielectric layer (1062) stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer (1061) is less than a threshold value.

2. The transistor fabrication method according to claim 1, characterized in that, The silicon nitride dielectric layer (1061) was fabricated using PECVD process. When fabricating the silicon nitride dielectric layer (1061), SiH4 and NH3 are used as silicon source and nitrogen source, respectively, and the ratio of the flow rate of SiH4 to the flow rate of NH3 is 1:0.8 to 1:0.

6.

3. The transistor fabrication method according to claim 2, characterized in that, The flow rate of SiH4 is 200~400 sccm, and the flow rate of NH3 is 120~320 sccm.

4. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, When fabricating the silicon nitride dielectric layer (1061), the chamber pressure is 3000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12~14mm.

5. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, When fabricating the silicon oxide dielectric layer (1062), SiH4 and N2O are used as silicon source and oxygen source, respectively, and the ratio of the flow rate of SiH4 to the flow rate of N2O is 1:10 to 1:

15.

6. The transistor fabrication method according to claim 5, characterized in that, The flow rate of SiH4 is 80~500 sccm, and the flow rate of N2O is 1200~5000 sccm.

7. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, When fabricating the silicon oxide dielectric layer (1062), the chamber pressure is 2000~5000 Torr, the high-frequency power is 200~500W, and the electrode spacing is 12.5~13.2mm.

8. The transistor fabrication method according to claim 7, characterized in that, The thickness of the silicon nitride dielectric layer (1061) is 200~700nm, and the thickness of the silicon oxide dielectric layer (1062) is 500~4000nm.

9. A transistor, characterized in that, The transistor includes: a channel layer (101), a barrier layer (102), a gate (103), a passivation insulating layer (104), a source-drain layer (105), and an interlayer insulating layer (106). The channel layer (101), the barrier layer (102), and the gate (103) are stacked sequentially. The passivation insulating layer (104) is located on the barrier layer (102) and covers the gate (103). The source-drain layer (105) is located on the passivation insulating layer (104). The source-drain layer (105) passes through the passivation insulating layer (104) and contacts the barrier layer (102). The interlayer insulating layer (106) covers the source-drain layer (105). The stress of the interlayer insulating layer (106) is -27 to -26 MPa. The interlayer insulating layer (106) includes a silicon nitride dielectric layer (1061) and a silicon oxide dielectric layer (1062) stacked sequentially. The silicon-to-nitrogen ratio of the silicon nitride dielectric layer (1061) is less than a threshold value.

10. The transistor according to claim 9, characterized in that, The thickness of the silicon nitride dielectric layer (1061) is 200~700nm, and the thickness of the silicon oxide dielectric layer (1062) is 500~4000nm.

Images