An enhanced gallium nitride high electron mobility transistor and its manufacturing method

Abstract

This application provides an enhanced gallium nitride (GaN) high electron mobility transistor (HEMT), comprising a substrate; a first epitaxial structure formed on the substrate, the first epitaxial structure including a channel layer and a first barrier layer formed on the channel layer; a groove penetrating the first barrier layer and extending into the channel layer; a second epitaxial structure including at least a second barrier layer; the second epitaxial structure covering the bottom, sidewalls, and upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure forming semiconductor-to-semiconductor direct contacts on the left and right sides of the top of the groove. The semiconductor-to-semiconductor direct contact between the first and second epitaxial structures can utilize the polarization synergy effect of the multilayer AlGaN barrier layer to increase the 2DEG concentration, thereby reducing the device's on-resistance, improving device performance, and lowering cost.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to an enhanced gallium nitride high electron mobility transistor and a method for manufacturing the same. Background Technology

[0002] The description in this section provides only background information relevant to the disclosure of this application and does not constitute prior art.

[0003] Reference Figure 1 As mentioned above, P-GaN gate technology is a common solution in the industry for enhancement-mode gallium nitride high electron mobility transistors. It achieves enhancement-mode functionality by inserting a P-GaN layer between the gate electrode (gate metal) and the barrier layer, depleting the 2DEG (two-dimensional electron gas) in the gate region through the P-GaN layer. However, research has shown that it has the following drawbacks: high sheet resistance (500-700 Ω / □, compared to 300 Ω / □ for normal AlGaN / GaN depletion-mode devices); high gate leakage current; and low maximum forward operating gate voltage (6V).

[0004] To overcome the above-mentioned shortcomings, another type of grooved gate MIS-HEMT device has received much attention from the academic community. It reduces the 2DEG concentration in the gate region by forming a groove in the gate region, that is, etching away part of the barrier layer in the gate region. After etching, the gate dielectric is deposited by LPCVD, and then the gate metal is deposited on the gate dielectric to form a MIS gate structure, thereby achieving enhancement mode.

[0005] However, research has revealed the following drawbacks of this structure: 1. Poor threshold voltage uniformity requires partial etching of the AlGaN barrier layer, resulting in poor uniformity and repeatability of the remaining AlGaN thickness. 2. Due to the high interface state density, the threshold voltage stability is poor.

[0006] In addition, Chinese patent application 202511840153.1 (hereinafter referred to as the "prior document") discloses an enhanced gallium nitride high electron mobility transistor and its fabrication method, the structure of which includes: a substrate; a first epitaxial structure (including a channel layer and a first barrier layer); a passivation layer formed on the first epitaxial structure; a groove penetrating the passivation layer and the first barrier layer and extending into the channel layer; a second epitaxial structure covering the bottom, sidewalls and top left and right sides of the passivation layer of the groove; and a gate metal formed on the second epitaxial structure.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] Through the inventor's creative discovery, the enhanced gallium nitride high electron mobility transistor with application number 2025118401531 has a lower 2DEG concentration and higher resistance, resulting in poorer device performance and cost because the second epitaxial structure and the first epitaxial structure are isolated by a passivation layer.

[0009] Based on the aforementioned deficiencies in the prior art, the transistor device and its manufacturing method disclosed in this application have superior performance.

[0010] To achieve the above objectives, this application provides the following technical solution: an enhanced gallium nitride high electron mobility transistor, comprising: Substrate; A first epitaxial structure is formed on the substrate, and the first epitaxial structure includes a channel layer and a first barrier layer formed on the channel layer. A groove, the groove penetrating the first barrier layer and extending into the interior of the channel layer; The second epitaxial structure includes at least a second barrier layer; the second epitaxial structure covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure form semiconductor-semiconductor direct contact on the surfaces of the left and right sides of the top of the groove. A gate dielectric layer, the gate dielectric layer being formed on the second barrier layer; Gate metal is formed on the gate dielectric layer.

[0011] Preferably, it further includes an ohmic electrode, which forms an ohmic contact with the second barrier layer through the gate dielectric layer.

[0012] Preferably, there is no passivation layer between the second epitaxial structure portion and the first epitaxial structure portion.

[0013] Preferably, the second epitaxial structure is composed only of the second barrier layer; The second barrier layer is in direct contact with the first barrier layer on the left and right sides of the top of the groove.

[0014] Preferably, the second epitaxial structure further includes a channel portion; The channel portion is located on the bottom, sidewalls, and upper surfaces of the first extensional structure portion on the left and right sides of the top of the groove, and is below the second barrier layer; The channel portion is in direct contact with the first barrier layer on the left and right sides of the top of the groove.

[0015] Preferably, the thickness of the channel portion is matched with the etching depth of the groove into the channel layer to compensate for the channel thickness loss due to etching, so that the two-dimensional electron gas height of the gate region and the non-gate region is consistent.

[0016] Preferably, the first epitaxial structure further includes a capping layer formed on the first barrier layer; The groove penetrates the cap layer, the first barrier layer and extends into the interior of the channel layer; The second barrier layer and the cap layer are in direct contact on the left and right sides of the top of the groove.

[0017] Preferably, the gate dielectric layer is an MOCVD in-situ SiN layer, or the gate dielectric layer includes an MOCVD in-situ SiN layer and an LPCVD SiN layer formed on the in-situ SiN layer.

[0018] This application also discloses a method for fabricating an enhanced gallium nitride high electron mobility transistor, comprising: Provide substrate; A first epitaxial structure is formed on the substrate by a first epitaxial growth, the first epitaxial structure including a channel layer and a first barrier layer; A groove is formed in the gate region, wherein the groove penetrates the first barrier layer and extends into the interior of the channel layer; A second epitaxial structure is formed by a second epitaxy, wherein the second epitaxial structure includes at least a second barrier layer; the second epitaxial structure covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure form semiconductor-semiconductor contacts on the surfaces of the left and right sides of the top of the groove. A gate dielectric layer is formed on the second epitaxial structure. A gate electrode is formed on the gate dielectric layer; In the ohmic electrode region, the gate dielectric layer is etched down to the second barrier layer, and ohmic metal is deposited to form the ohmic electrode that forms an ohmic contact with the second barrier layer.

[0019] Preferably, the second epitaxial structure is composed only of a second barrier layer, and the second barrier layer is in direct contact with the first barrier layer on the left and right sides of the top of the groove; or, The step "forming the second epitaxial structure through a second epitaxy" also includes: First, a channel portion is formed through secondary epitaxy, and then a second barrier layer is formed on the channel portion through secondary epitaxy; wherein, the channel portion and the first barrier layer are in direct contact on the left and right sides of the top of the groove; or, The step "forming a first epitaxial structure on the substrate by a first epitaxial growth, the first epitaxial structure including a channel layer and a first barrier layer, forming a groove in the gate region, wherein the groove penetrates the first barrier layer and extends into the channel layer; forming a second epitaxial structure by a second epitaxial growth, wherein the second epitaxial structure includes at least a second barrier layer; the second epitaxial structure covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure form semiconductor-semiconductor contacts on the surfaces of the top of the groove" further includes forming a capping layer on the first barrier layer; wherein the groove penetrates the capping layer and the first barrier layer and extends into the channel layer, and the second barrier layer covers the bottom and sidewalls of the groove and the upper surfaces of the capping layer on the left and right sides of the top of the groove; or,

[0020] The step "forming a gate dielectric layer on the second epitaxial structure" includes: an in-situ SiN layer generated by MOCVD; or, an in-situ SiN layer generated by MOCVD and a SiN layer formed on the in-situ SiN layer and generated by LPCVD.

[0021] The beneficial effects of this application, based on the above technical solutions, are as follows: The first and second epitaxial structures adopt semiconductor-to-semiconductor direct contact, which can utilize the polarization synergy effect of multilayer AlGaN to increase the 2DEG concentration. This can reduce the on-resistance of the device, improve device performance, and reduce cost.

[0022] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, illustrating how the principles of this application can be employed. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of this application include many changes, modifications, and equivalents.

[0023] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0024] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0025] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings: Figure 1 A schematic diagram of the structure of a transistor device in the prior art is shown.

[0026] Figure 2 A schematic diagram of another transistor device in the prior art is shown.

[0027] Figure 3 This shows a schematic diagram of the structure of yet another transistor device in the prior art.

[0028] Figure 4 A schematic diagram of the structure of a transistor device according to one embodiment of this application is shown.

[0029] Figures 5A-5F It shows Figure 4 The production process flowchart.

[0030] Figure 6 A schematic diagram of the structure of a transistor device according to another embodiment of this application is shown.

[0031] Figure 7 A schematic diagram of the structure of a transistor device in yet another embodiment of this application is shown.

[0032] Figure 8 A schematic diagram of the structure of a transistor device in another embodiment of this application is shown.

[0033] The reference numerals in the above figures are as follows: 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. First barrier layer; 5. Groove; 6. Second barrier layer; 7. Gate dielectric layer; 8. Gate metal; 9. Channel portion; 10. Ohmic electrode; 11. Passivation layer; 12. Capping layer. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0035] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0038] It should be noted that in the description of this application, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more.

[0039] Reference Figure 4 As shown in the figure, this application discloses an enhanced gallium nitride high electron mobility transistor, comprising: Substrate 1; A first epitaxial structure is formed on the substrate 1, and the first epitaxial structure includes a channel layer 3 and a first barrier layer 4 formed on the channel layer 3. The groove 5 penetrates the first barrier layer 4 and extends into the interior of the channel layer 3; The second epitaxial structure includes at least a second barrier layer 6; the second epitaxial structure covers the bottom and sidewalls of the groove 5 and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove 5; the second epitaxial structure and the first epitaxial structure form semiconductor-semiconductor direct contact on the surfaces of the left and right sides of the top of the groove 5. Gate dielectric layer 7, which is formed on the second barrier layer 6; Gate metal 8 is formed on the gate dielectric layer 7. The substrate 1 can be formed of silicon, silicon carbide, or sapphire, or it can be a composite of several materials such as silicon on insulator (SOI).

[0040] The first epitaxial structure can be formed on substrate 1 by in-situ growth via MOCVD. The first epitaxial structure may include a buffer layer 2 formed on substrate 1. The buffer layer 2 may be made of different materials depending on the substrate 1 and specific requirements. For example, when using a silicon substrate 1, it may be composed of an AlN nucleation layer, one or more AlGaN transition layers, and a superlattice buffer layer 2 formed by alternating and periodically growing AlN and AlGaN. Alternatively, it may be composed of an AlN nucleation layer and one or more AlGaN layers.

[0041] The first epitaxial structure also includes a channel layer 3 formed on the buffer 2. The channel layer 3 can be a GaN channel layer 3. Of course, in other alternative embodiments, the material of the channel layer 3 can also be set as needed.

[0042] The first epitaxial structure further includes a first barrier layer 4 formed on the channel layer 3. The first barrier layer 4 may be formed of a semiconductor material, such as a compound based on a gallium nitride ternary or quaternary alloy, such as Al. x Ga 1x N, AlInGaN, In x Ga 1x N, Al x In 1x Al, AlScN, etc. In this embodiment, the first barrier layer 4 can be an AlGaN layer with a thickness between 5nm and 35nm.

[0043] The groove 5 extends downward from the upper surface of the first barrier layer 4 into the interior of the channel layer 3. Generally, the opening angle of the groove 5 is between 15° and 90°. The etching depth of the groove 5 downward from the first barrier layer 4 can be between 0.1 nm and 100 nm. After forming the groove 5, a second epitaxial structure is formed in the gate region by a second in-situ growth using MOCVD. In this embodiment, the second epitaxial structure includes a second barrier layer 6 from bottom to top. The second barrier layer 6 covers the bottom of the groove 5 (i.e., the upper surface of the channel layer 3 not covered by the first barrier layer 4), the sidewalls (i.e., the portion of the first barrier layer 4 used to form the sidewalls of the groove 5), and the upper surfaces of the first barrier layers 4 on the left and right sides of the top of the groove 5. In this embodiment, the second barrier layer 6 extends from the top of the groove 5 to the left and right sides and completely covers the first barrier layer 4. In other words, except for the groove 5, the entire first barrier layer 4 is covered by the second barrier layer 6. That is, the second barrier layer 6 and the first barrier layer 4 are in direct contact on the left and right sides of the top of the groove 5. In other words, the portion of the first barrier layer 4 covered by the second barrier layer 6 is in direct contact with the second barrier layer 6 covered by the first barrier layer 4. Therefore, the polarization synergy effect of the multilayer AlGaN barrier layers can be used to increase the 2DEG concentration, thereby reducing the device's on-resistance, improving device performance, and lowering costs.

[0044] Furthermore, the second barrier layer 6 forms a barrier trench. The gate dielectric layer 7 covers the bottom, sidewalls, and upper surfaces of the second barrier layer 6 on the left and right sides of the top of the barrier layer 5 in the barrier trench. The gate dielectric layer forms a gate dielectric trench. Gate metal 8 fills the gate dielectric trench, and another portion of the gate metal 8 covers the upper surfaces of the gate dielectric layer 7 on the left and right sides of the top of the gate dielectric trench. A further portion of the gate metal 8 is located above the gate dielectric trench and forms a plate shape with the gate metal 8 formed on the upper surface of the gate dielectric layer 7. It is understood that the gate dielectric layer 7 covers the entire second barrier layer 6 except for the ohmic contact region. Optionally, the material of the second barrier layer 6 can be AlGaN, and its thickness can be 0.1nm-10nm. Of course, in other optional embodiments, the material of the second barrier layer 6 can be, for example, a ternary or quaternary alloy compound based on gallium nitride, such as Al x Ga 1x N, AlInGaN, In x Ga 1x N, Al x In 1xAl, AlScN, etc. The gate dielectric layer 7 is made of in-situ SiN, and its thickness can be 0.1nm-100nm. The gate metal 81 can be made of TiN, W, Ni / Au, Ti / Au, etc., and its thickness is between 10nm-1um.

[0045] Similar to existing technologies, this enhanced gallium nitride high electron mobility transistor also includes two ohmic electrodes 10 (e.g., source and drain), wherein the two ohmic electrodes 10 are located on opposite sides of the gate. Furthermore, the ohmic metals of both ohmic electrodes 10 form ohmic contacts with the second barrier layer 6.

[0046] The method for fabricating the enhanced gallium nitride high electron mobility transistor in this application includes the following steps: A substrate 1 is provided. The substrate 1 can be formed of silicon or silicon carbide material, or it can be composed of several materials such as single crystal silicon on insulator (SOI).

[0047] Reference Figure 5A As shown, a first epitaxial structure is formed on substrate 1 by MOCVD epitaxial growth. The first epitaxial structure may include a buffer layer 2 formed on substrate 1, a channel layer 3 formed on the buffer layer 2, and a first barrier layer 4 formed on the channel layer 3. The buffer layer 2, channel layer 3, and first barrier layer 4 are planar. The first barrier layer 4 is made of AlGaN material and has a thickness between 5 nm and 35 nm.

[0048] Reference Figure 5B As shown, in the gate region, etching is performed downwards from the upper surface of the first barrier layer 4 until it extends into the interior of the channel layer 3, thereby forming a groove 5. Specifically, etching is performed downwards from the upper surface of the first barrier layer 4 to completely remove the first barrier layer 4 in the gate region, and partially etching the channel layer 3. The etching depth downwards from the first barrier layer 4 can be between 0.1 nm and 100 nm, and the etching opening angle is between 15° and 90°.

[0049] Reference Figure 5C As shown, a second barrier layer 6 is grown epitaxially by MOCVD for the second time. The second barrier layer 6 covers the bottom and sidewalls of the groove 5, as well as the upper surface of the first barrier layer 4 on the left and right sides of the top of the groove 5. The second barrier layer 6 forms a barrier layer.

[0050] Reference Figure 5D As shown, the gate dielectric layer 7 is grown in situ by MOCVD. The material of the gate dielectric layer 7 can be silicon nitride (SiN), and the thickness is 0.1nm-100nm. At this time, the gate dielectric layer 7 is stacked and covers the second barrier layer 6.

[0051] Reference Figure 5E As shown, gate metal 81 is deposited on the second epitaxial structure. A portion of the gate metal 81 fills the gate dielectric trench, another portion of the gate metal 81 is formed on the upper surface of a portion of the gate dielectric layer 7, and a further portion of the gate metal 8 is located above the gate dielectric trench, forming a plate shape with the gate metal 8 formed on the upper surface of the gate dielectric layer 7. The gate metal 81 is made of materials such as TiN, W, Ni / Au, Ti / Au, etc., and its thickness is between 10 nm and 1 μm.

[0052] Referring to Figure 5F, with the second barrier layer 6 as the cutoff surface, an ohmic opening is made in the gate dielectric layer 7 within the ohmic electrode 10 region (source region and drain region). Ohmic deposition is performed at the ohmic opening to form the ohmic electrode 10, which forms an ohmic contact with the second barrier layer 6. (Refer to...) Figure 4 As shown, after the ohmic electrode 10 is formed, a passivation layer 11 is deposited over the ohmic electrode 10, the gate metal 8, and the gate dielectric layer 7 that is not covered by the ohmic electrode 10 and the gate metal 8.

[0053] Reference Figure 6 As shown, another embodiment of this application discloses an enhancement-mode gallium nitride high electron mobility transistor. Unlike the previous embodiment, the second epitaxial structure includes a channel portion 9 and a second barrier layer 6. The channel portion 9 covers the bottom, sidewalls, and upper surfaces of the first barrier layer 4 on the left and right sides of the top of the groove 5. In other words, the entire first barrier layer 4, except for the groove 5, is covered by the channel portion 9. That is, the channel portion 9 is in direct contact with the first barrier layer 4 on the left and right sides of the top of the groove 5. Specifically, there is direct contact between the portion of the first barrier layer 4 covered by the channel portion 9 and the channel portion 9 covered by the first barrier layer 4. The second barrier layer 6 completely covers the channel portion 9. In other words, the second barrier layer 6 is shaped to be offset from the channel portion 9.

[0054] The channel portion 9 can be made of GaN material. The thickness of the channel portion 9 is 1nm-50nm. The thickness of the channel portion 9 in this region is related to the amount of GaN layer lost during etching of the trench 5. After the second epitaxial structure is deposited, the total thickness of the channel portion 9 and the remaining channel layer 3 in this gate region should preferably not exceed the thickness of the channel layer 3 in other regions or the height of the 2DEG. Thus, the channel portion 9 can compensate for the thickness of the channel layer 3 removed by etching of the trench 5, ensuring that the two-dimensional electron gas in the channel region and the gate region is at the same height, thereby improving the electron transport characteristics of the device.

[0055] The difference between the preparation method in this embodiment and the previous embodiment is that, after forming the groove 5, the channel portion 9 and the second barrier layer 6 are formed by a second epitaxial growth.

[0056] Reference Figure 7 As shown, another embodiment of this application discloses an enhanced gallium nitride high electron mobility transistor. The difference from the previous embodiment is that the first epitaxial structure further includes a capping layer 12 formed on the first barrier layer 4; the groove 5 penetrates the capping layer 12 and the first barrier layer 4 and extends into the interior of the channel layer 3; the second barrier layer 6 and the capping layer 12 are in direct contact with the top left and right sides of the groove 5.

[0057] The capping layer 12 can be made of GaN. The capping layer 12 can have a thickness that reduces surface states, protects the barrier layer, and further modulates the polarization field. Specifically, the thickness of the capping layer 12 can be between 0.1 and 100 nm.

[0058] The difference between the preparation method in this embodiment and the previous embodiment is that, in the first epitaxial growth, a capping layer 12 is formed on the first barrier layer 4; the formed groove 5 penetrates the capping layer 12 and the first barrier layer 4 and extends into the interior of the channel layer 3, and a second epitaxial growth is performed on the capping layer 12. That is, the second barrier layer 6 covers the bottom, sidewalls, and upper surfaces of the capping layer 12 on the left and right sides of the top of the groove 5.

[0059] Reference Figure 8 As shown, another embodiment of this application discloses an enhancement-mode gallium nitride high electron mobility transistor, wherein the gate dielectric layer 7 may include an MOCVD in-situ SiN layer and an LPCVD-generated SiN layer formed on the in-situ SiN layer. Thus, low interface states are obtained through MOCVD in-situ SiN, and the SiN layer generated by LPCVD provides sufficient thickness, resulting in both excellent interface quality and good insulation properties.

[0060] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. An enhancement-grade gallium nitride high electron mobility transistor, characterized in that, include: Substrate; A first epitaxial structure is formed on the substrate, and the first epitaxial structure includes a channel layer and a first barrier layer formed on the channel layer. A groove, the groove penetrating the first barrier layer and extending into the interior of the channel layer; The second epitaxial structure portion includes at least a second barrier layer; the second epitaxial structure portion covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure portion on the left and right sides of the top of the groove; The second epitaxial structure portion and the first epitaxial structure portion form semiconductor-semiconductor direct contact on the left and right sides of the top of the groove; A gate dielectric layer, the gate dielectric layer being formed on the second barrier layer; Gate metal is formed on the gate dielectric layer.

2. The transistor according to claim 1, characterized in that: It also includes an ohmic electrode that forms an ohmic contact with the second barrier layer through the gate dielectric layer.

3. The transistor according to claim 1, characterized in that: There is no passivation layer between the second epitaxial structure and the first epitaxial structure.

4. The transistor according to claim 1, characterized in that: The second epitaxial structure is composed solely of the second barrier layer; The second barrier layer is in direct contact with the first barrier layer on the left and right sides of the top of the groove.

5. The transistor according to claim 1, characterized in that: The second epitaxial structure also includes a channel portion; The channel portion is located on the bottom, sidewalls, and upper surfaces of the first extensional structure portion on the left and right sides of the top of the groove, and is below the second barrier layer; The channel portion is in direct contact with the first barrier layer on the left and right sides of the top of the groove.

6. The transistor according to claim 5, characterized in that: The thickness of the channel portion is matched with the etching depth of the groove into the channel layer to compensate for the channel thickness loss due to etching, so that the two-dimensional electron gas height of the gate region and the non-gate region is highly consistent.

7. The transistor according to claim 1, characterized in that: The first epitaxial structure further includes a capping layer formed on the first barrier layer; The groove penetrates the cap layer, the first barrier layer and extends into the interior of the channel layer; The second barrier layer and the cap layer are in direct contact on the left and right sides of the top of the groove.

8. The transistor according to claim 1, characterized in that: The gate dielectric layer is an MOCVD in-situ SiN layer, or the gate dielectric layer includes an MOCVD in-situ SiN layer and an LPCVD SiN layer formed on the in-situ SiN layer.

9. A method for fabricating an enhanced gallium nitride high electron mobility transistor, characterized in that, include: Provide substrate; A first epitaxial structure is formed on the substrate by a first epitaxial growth, the first epitaxial structure including a channel layer and a first barrier layer; A groove is formed in the gate region, wherein the groove penetrates the first barrier layer and extends into the interior of the channel layer; A second epitaxial structure is formed by a second epitaxy, wherein the second epitaxial structure includes at least a second barrier layer; the second epitaxial structure covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure form semiconductor-semiconductor contacts on the surfaces of the left and right sides of the top of the groove. A gate dielectric layer is formed on the second epitaxial structure. A gate electrode is formed on the gate dielectric layer; In the ohmic electrode region, the gate dielectric layer is etched down to the second barrier layer, and ohmic metal is deposited to form the ohmic electrode that forms an ohmic contact with the second barrier layer.

10. The method according to claim 9, characterized in that: The second epitaxial structure consists only of a second barrier layer, which is in direct contact with the first barrier layer on the left and right sides of the top of the groove; or, The step "forming a second epitaxial structure through a second epitaxy" also includes: First, a channel portion is formed through secondary epitaxy, and then a second barrier layer is formed on the channel portion through secondary epitaxy; wherein, the channel portion and the first barrier layer are in direct contact on the left and right sides of the top of the groove; or, The step "forming a first epitaxial structure on the substrate by a first epitaxial growth, the first epitaxial structure including a channel layer and a first barrier layer, forming a groove in the gate region, wherein the groove penetrates the first barrier layer and extends into the channel layer; forming a second epitaxial structure by a second epitaxial growth, wherein the second epitaxial structure includes at least a second barrier layer; the second epitaxial structure covers the bottom and sidewalls of the groove and the upper surfaces of the first epitaxial structure on the left and right sides of the top of the groove; the second epitaxial structure and the first epitaxial structure form a semiconductor-semiconductor contact on the surfaces of the top of the groove" further includes forming a capping layer on the first barrier layer; wherein the groove penetrates the capping layer and the first barrier layer and extends into the channel layer, and the second barrier layer covers the bottom and sidewalls of the groove and the upper surfaces of the capping layer on the left and right sides of the top of the groove; or, The step "forming a gate dielectric layer on the second epitaxial structure" includes: an in-situ SiN layer generated by MOCVD; or, an in-situ SiN layer generated by MOCVD and a SiN layer formed on the in-situ SiN layer and generated by LPCVD.

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