Semiconductor layer structure, transistor, semiconductor device and method of manufacture

Abstract

The application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor layer structure, a transistor, a semiconductor device and a preparation method. The semiconductor layer structure comprises: a ferroelectric layer; a first interface layer arranged on one side of the ferroelectric layer, wherein the first interface layer comprises fixed positive charges; and a second interface layer arranged on the side, away from the first interface layer, of the ferroelectric layer, wherein the second interface layer comprises a charge trapping layer, and the charge trapping layer is used for trapping charges injected into the ferroelectric layer, and the fixed positive charges are used for exerting electric field force on the charges trapped by the charge trapping layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor device fabrication technology, and in particular to a semiconductor stacked structure, a transistor, a semiconductor device, and a fabrication method thereof. Background Technology

[0002] Ferroelectric field-effect transistors (FeFETs), as a type of non-volatile memory, have broad application prospects in embedded memory and 3D NAND flash memory. The core structure of a FeFET includes a gate, a ferroelectric layer, and a channel. Information is stored by the polarization direction of the ferroelectric layer, thereby achieving different threshold voltage states.

[0003] In FeFETs, the ferroelectric layer is typically disposed between an upper interface layer and a lower interface layer. The upper interface layer is located between the ferroelectric layer and the gate, while the lower interface layer is located between the ferroelectric layer and the channel. In the prior art, the upper interface layer is mainly used to adjust the interface characteristics between the gate and the ferroelectric layer, while the lower interface layer is mainly used to isolate the ferroelectric layer from the channel.

[0004] However, FeFETs in related technologies suffer from problems such as a small storage window and poor charge retention characteristics in practical applications. Specifically, during write or erase operations, the charge injected into the ferroelectric layer is easily trapped in the interface layer, but these trapped charges are unstable and prone to escape during subsequent operations or reads, leading to threshold voltage drift and preventing the storage window from being effectively enlarged. Furthermore, the presence of unstable charges also affects the device's durability and data retention characteristics, limiting the application of FeFETs in high-density memory. Summary of the Invention

[0005] This application discloses a semiconductor stacked structure, a transistor, a semiconductor device, and a fabrication method, which can increase the storage window of the semiconductor device and improve its durability and retention characteristics.

[0006] In a first aspect, embodiments of this application provide a semiconductor stacked structure, comprising: a ferroelectric layer; a first interface layer disposed on one side of the ferroelectric layer, the first interface layer including a fixed positive charge; and a second interface layer disposed on the side of the ferroelectric layer opposite to the first interface layer, the second interface layer including a charge trapping layer, the charge trapping layer being used to trap charges injected into the ferroelectric layer, and the fixed positive charge being used to apply an electric field force to the charges trapped by the charge trapping layer.

[0007] In one possible implementation, the second interface layer further includes a first dielectric layer and a second dielectric layer, with the charge trapping layer disposed between the first dielectric layer and the second dielectric layer.

[0008] In one possible implementation, the materials of the first dielectric layer and the second dielectric layer include a high-k dielectric material.

[0009] In one possible implementation, the material of the charge trapping layer includes at least one of the following: aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0010] In one possible implementation, the thickness of the first interface layer is 0 nm to 4 nm.

[0011] In one possible implementation, the thickness of the ferroelectric layer is 3 nm to 20 nm.

[0012] In one possible implementation, the thicknesses of the first dielectric layer, the charge trapping layer, and the second dielectric layer are 2 nm to 6 nm, respectively.

[0013] In one possible implementation, the thicknesses of the first dielectric layer and the second dielectric layer are not equal.

[0014] In one possible implementation, the first interface layer comprises silicon oxynitride, and the fixed positive charge is introduced into the first interface layer by a nitriding process.

[0015] Secondly, embodiments of this application also provide a transistor, comprising: a first substrate, the first substrate including a channel, a source and a drain, the source and the drain being disposed on opposite sides of the channel; a semiconductor stacked structure as described in any embodiment of the first aspect of this application, disposed on the first substrate; and a gate, disposed on the side of the semiconductor stacked structure opposite to the first substrate.

[0016] Thirdly, embodiments of this application also provide a semiconductor device, including: a second substrate; a stacked structure disposed on the second substrate, the stacked structure including: a plurality of insulating layers and a plurality of gate metal layers alternately stacked in a direction away from the second substrate, and a channel hole penetrating the plurality of insulating layers and the plurality of gate metal layers; a semiconductor stacked structure as described in any embodiment of the first aspect of this application, the semiconductor stacked structure being disposed within the channel hole, the semiconductor stacked structure including a first interface layer, the ferroelectric layer and the second interface layer in sequence from the inside to the outside along the radial direction of the channel hole.

[0017] Fourthly, embodiments of this application also provide a method for fabricating a semiconductor device, comprising: providing a second substrate; alternately depositing a plurality of insulating layers and a plurality of gate metal layers on the second substrate to form a stacked structure; etching the stacked structure to form at least one channel hole, the channel hole penetrating the plurality of insulating layers and the plurality of gate metal layers; sequentially forming a second interface layer, a ferroelectric layer and a first interface layer from the outside to the inside on the sidewall of the channel hole; performing a nitriding treatment on the first interface layer to introduce a fixed positive charge within the first interface layer; and forming a channel structure on the inner side of the first interface layer.

[0018] In one possible implementation, the step of sequentially forming a second interface layer, a ferroelectric layer, and a first interface layer on the sidewall of the channel hole includes: forming a first dielectric layer, a charge trapping layer, and a second dielectric layer on the sidewall of the channel hole to obtain the second interface layer; forming the ferroelectric layer on the second interface layer; and forming the first interface layer on the ferroelectric layer.

[0019] In one possible implementation, the step of nitriding the first interface layer to introduce a fixed positive charge within the first interface layer includes: nitriding the first interface layer using a decoupled plasma nitriding process to inject nitrogen ions into the first interface layer and generate a positive charge within the first interface layer; and annealing the nitrided first interface layer using a post-nitriding annealing process to fix the positive charge and form the fixed positive charge.

[0020] In the semiconductor stacked structure provided in this application embodiment, the second interface layer captures the charge injected into the ferroelectric layer through its internal charge trapping layer; the first interface layer applies an electric field force to the captured charge through its internal fixed positive charge. Through this method, the number of unstable charges remaining in the second interface layer after being trapped is reduced, the electrical state consistency of the semiconductor stacked structure under different operating conditions is improved, and the retention characteristics are enhanced. Simultaneously, the combination of the trapped charge and the polarization state of the ferroelectric layer increases the number of threshold voltage offset states of the semiconductor stacked structure, thus increasing the storage window. Furthermore, the voltage drop on the second interface layer decreases, the electric field stress on the ferroelectric layer during the write or erase process is reduced, and the durability characteristics of the ferroelectric layer are improved. The electric field generated by the fixed positive charge in the first interface layer during the read operation is opposite in direction to the externally applied positive voltage, reducing the interference of the positive voltage on the captured charge. In this application embodiment, the second interface layer also includes a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer are respectively disposed on both sides of the charge trapping layer, that is, the charge trapping layer is located between the first dielectric layer and the second dielectric layer.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is one of the schematic diagrams of a semiconductor stacked structure provided in an embodiment of this application; Figure 2 This is a second schematic diagram of a semiconductor stacked structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of the threshold voltage drift of the semiconductor stacked structure provided in the embodiments of this application under the action of a positive pulse; Figure 4 This is a schematic diagram of the threshold voltage drift of the semiconductor stacked structure provided in the embodiments of this application under the action of a negative pulse; Figure 5 A schematic diagram of a transistor structure provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 7 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application; Figure 8 This is one of the structural diagrams in the fabrication process of a semiconductor device provided in an embodiment of this application; Figure 9 This is a second structural diagram illustrating the fabrication process of a semiconductor device provided in an embodiment of this application. Figure 10 The third structural diagram is shown in the fabrication process of a semiconductor device fabrication method provided in this application embodiment. Figure 11 The fourth structural diagram is shown in the fabrication process of a semiconductor device fabrication method provided in this application embodiment. Figure 12 The fifth structural diagram is shown in the fabrication process of a semiconductor device fabrication method provided in this application embodiment. Figure 13 This is the sixth structural diagram of the fabrication process in a method for fabricating a semiconductor device provided in this application embodiment; Figure 14The seventh structural diagram is shown in the fabrication process of a semiconductor device fabrication method provided in this application embodiment. Figure 15 This is the eighth structural diagram of the fabrication process in a method for fabricating a semiconductor device provided in this application embodiment; Figure 16 This is diagram nine of the structural diagrams illustrating the fabrication process of a semiconductor device provided in this application embodiment. Figure 17 This is the tenth structural diagram of the fabrication process in a method for fabricating a semiconductor device according to an embodiment of this application; Figure 18 This is eleventh of the structural diagrams in the fabrication process of a semiconductor device provided in the embodiments of this application.

[0024] Explanation of reference numerals in the attached figures: 1-Semiconductor stacked structure; 10-Ferroelectric layer; 11-First interface layer; 12-Second interface layer; 121-First dielectric layer; 122-Charge trapping layer; 123-Second dielectric layer; 2-Transistor; 21-First substrate; 211-Channel; 212-Source; 213-Drain; 22-Gate; 3-Semiconductor device; 31-Second substrate; 32-Stacked structure; 321-Insulating layer; 322-Gate metal layer; 33-Channel via; 34-Channel substrate; 35-Channel structure. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0027] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0028] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0029] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0030] A first aspect of this application provides a semiconductor stacked structure 1, which can be used in a ferroelectric memory as part of a memory cell. When the ferroelectric memory is working, the polarization direction of the ferroelectric layer 10 is changed by an applied voltage, causing the semiconductor stacked structure 1 to exhibit different electrical states, thereby storing information.

[0031] like Figure 1 As shown, the semiconductor stacked structure 1 includes a ferroelectric layer 10, a first interface layer 11, and a second interface layer 12.

[0032] The ferroelectric layer 10 is made of hafnium-based ferroelectric material. When an external electric field is applied, the hafnium-based ferroelectric material can generate ferroelectric polarization, and the polarization direction can be partially maintained after the external electric field is removed. In the hafnium-based ferroelectric layer 10, due to the presence of oxygen vacancies or lattice defects, the ferroelectric polarization leads to charge injection at the interface. Specifically, the type of charge injected into the interface of the ferroelectric layer 10 differs depending on the direction of the external electric field, including electrons and holes. For example, under a forward external voltage, holes are injected into the upper interface of the ferroelectric layer 10; under a reverse external voltage, electrons are injected into the upper interface of the ferroelectric layer 10.

[0033] The first interface layer 11 is disposed on one side of the ferroelectric layer 10. The first interface layer 11 can be the lower interface layer of the ferroelectric layer 10. The first interface layer 11 includes fixed positive charges.

[0034] In one example, the first interface layer 11 can be a nitrided silicon oxynitride layer. This silicon oxynitride layer is implanted with nitrogen (N) at the silicon oxynitride interface through a decoupled plasma nitriding process, followed by annealing in a post-nitriding annealing process. After annealing, the N element distribution in the interface layer tends to be uniform, and a fixed positive charge is formed within the interface layer.

[0035] In another example, the first interface layer 11 can be made of other dielectric materials, introducing a fixed positive charge by doping with nitrogen or other dopants. Regardless of the material used, the first interface layer 11 must provide a fixed positive charge on one side of the ferroelectric layer 10.

[0036] The second interface layer 12 is disposed on the side of the ferroelectric layer 10 opposite to the first interface layer 11. The second interface layer 12 can be the upper interface layer of the ferroelectric layer 10. The second interface layer 12 includes a charge trapping layer 122. The second interface layer 12 is used to trap the charge injected into the ferroelectric layer 10 when ferroelectric polarization is generated in the ferroelectric layer 10. The trapped charge can be a hole or an electron, depending on the type of injected charge.

[0037] It should be noted that the charge injected into the ferroelectric layer 10 may not have entered the ferroelectric layer 10 before being captured by the charge trapping layer 122 in the second interface layer 12. These charges are captured before reaching the ferroelectric layer 10 and remain inside the second interface layer 12.

[0038] The second interface layer 12 can be a stacked structure of high-k materials. In one example, the second interface layer 12 includes an Al2O3 layer and an HfO2 layer, wherein the HfO2 layer serves as a charge trapping layer 122. The relative positional relationship between the Al2O3 layer and the HfO2 layer includes the following possibilities: the HfO2 layer is located between the two Al2O3 layers, or the HfO2 layer is located between the Al2O3 layer and the ferroelectric layer 10, or the HfO2 layer is located on the side of the Al2O3 layer away from the ferroelectric layer 10.

[0039] In another example, the Al2O3 layer in the second interface layer 12 can be replaced with other high-k oxides, such as ZrO2 or La2O3, with the HfO2 layer serving as a charge trapping layer 122. This structure also provides charge trapping functionality.

[0040] When the ferroelectric layer 10 is ferropolarized, the electric field strength at the interface between the ferroelectric layer 10 and the second interface layer 12 increases. With the increased electric field strength, the amount of charge injected into the ferroelectric layer 10 increases. Before reaching the ferroelectric layer 10, some of these charges are captured by the HfO2 charge-capturing layer 122 in the second interface layer 12. Specifically, when the ferroelectric layer 10 is in a positively polarized state, holes are injected at the interface between the second interface layer 12 and the ferroelectric layer 10; when the ferroelectric layer 10 is in a negatively polarized state, i.e., when the side of the ferroelectric layer 10 closest to the second interface layer 12 is positively charged, electrons are injected into the second interface layer 12. After the applied voltage is removed, the captured charges are confined within the second interface layer 12, forming an energy potential well. The presence of the energy potential well makes it difficult for the captured charges to escape. Therefore, this structure of the second interface layer 12 allows the captured charges to be retained for a longer period of time.

[0041] Due to the presence of trapped charges, the ferroelectric layer 10 remains affected by the electric field generated by the trapped charges even after the applied voltage is removed. Different polarizations of the ferroelectric layer 10 combined with different types of trapped charges cause the threshold voltage of the semiconductor device 3 using the semiconductor stacked structure 1, such as a ferroelectric memory, to exhibit multiple offset states. This increases the storage window of the ferroelectric memory and enables multi-value storage.

[0042] After the voltage drop on the second interface layer 12 decreases, the proportion of voltage that the ferroelectric layer 10 withstands increases, and the electric field stress of the ferroelectric layer 10 during the writing or erasing process decreases. After the electric field stress is reduced, the durability characteristics of the ferroelectric layer 10 are improved.

[0043] A fixed positive charge applies an electric field force to the charges captured by the charge trapping layer 122. For captured electrons, this electric field force manifests as an attractive force pointing towards the first interface layer 11; for captured holes, it manifests as a repulsive force moving away from the first interface layer 11. Both the attractive and repulsive forces regulate the captured charges, reducing the accumulation of unstable charges in the charge trapping layer 122, thereby improving the retention characteristics of the semiconductor stacked structure 1.

[0044] When the charge trapping layer 122 in the second interface layer 12 traps the charge injected into the ferroelectric layer 10, if these charges remain in the charge trapping layer 122 for a long time, they may affect the stability of the semiconductor device 3 using this semiconductor stack structure 1, such as a ferroelectric memory. The fixed positive charge in the first interface layer 11 exerts an electric field force on the trapped charge. Since the first interface layer 11 is located on one side of the ferroelectric layer 10, and the charge trapping layer 122 is located on the other side of the ferroelectric layer 10, the electric field generated by the fixed positive charge acts on the trapped charge in the charge trapping layer 122 of the second interface layer 12.

[0045] Taking the captured electron as an example, the electric field force manifests as an attractive force pointing towards the first interface layer 11, causing the electron to move towards the first interface layer 11. After the captured charge is subjected to the electric field force, the number of unstable charges in the charge trapping layer 122 of the second interface layer 12 decreases.

[0046] Thus, in the semiconductor stacked structure 1 provided in this application embodiment, the second interface layer 12 captures the charge injected into the ferroelectric layer 10 through its internal charge trapping layer 122, thereby increasing the storage window; the first interface layer 11 applies an electric field force to the captured charge through its internal fixed positive charge, thereby improving the retention stability of the captured charge in the second interface layer 12 and improving its durability and retention characteristics.

[0047] Furthermore, when the memory using this semiconductor stack-up structure 1 is in a read operation, an external circuit applies a positive voltage at a specific location. This positive voltage may affect the charges already trapped in the charge trapping layer 122. The electric field generated by the fixed positive charges in the first interface layer 11 is opposite in direction to the positive voltage applied during the read operation. During positive voltage read, the electric field of the fixed positive charges can partially cancel the interfering electric field generated by the positive voltage, thereby reducing the impact on the trapped charges. This cancellation effect is provided by the continuous presence of the fixed positive charges and is independent of the operating state of the semiconductor device 3.

[0048] Thus, in the semiconductor stacked structure 1 provided in this application embodiment, the second interface layer 12 captures the charge injected into the ferroelectric layer 10 through its internal charge trapping layer 122; the first interface layer 11 applies an electric field force to the captured charge through its internal fixed positive charge. In this way, the number of unstable charges remaining in the second interface layer 12 after being captured is reduced, the electrical state consistency of the semiconductor stacked structure 1 under different operating conditions is improved, and the retention characteristics are enhanced. Simultaneously, the captured charge combines with the polarization state of the ferroelectric layer 10, increasing the number of threshold voltage offset states of the semiconductor stacked structure 1 and enlarging the storage window. Furthermore, the voltage drop on the second interface layer 12 is reduced, the electric field stress on the ferroelectric layer 10 during the write or erase process is reduced, and the durability characteristics of the ferroelectric layer 10 are improved. The electric field generated by the fixed positive charge in the first interface layer 11 during the read operation is opposite in direction to the externally applied positive voltage, thus reducing the interference of the positive voltage on the captured charge.

[0049] like Figure 2 As shown, in some embodiments, the second interface layer 12 further includes a first dielectric layer 121 and a second dielectric layer 123. The first dielectric layer 121 and the second dielectric layer 123 are respectively disposed on both sides of the charge trapping layer 122, that is, the charge trapping layer 122 is located between the first dielectric layer 121 and the second dielectric layer 123.

[0050] In one example, the first dielectric layer 121 is located on the side of the charge trapping layer 122 closer to the ferroelectric layer 10, and the second dielectric layer 123 is located on the side of the charge trapping layer 122 away from the ferroelectric layer 10. The materials of the first dielectric layer 121 and the second dielectric layer 123 include Al2O3, and the material of the charge trapping layer 122 is HfO2. That is, the second interface layer 12 forms an Al2O3 / HfO2 / Al2O3 stacked structure.

[0051] In another example, the materials of the first dielectric layer 121 and the second dielectric layer 123 can be replaced with other high-k oxides, such as ZrO2 or La2O3, while the material of the charge trapping layer 122 remains HfO2. This structure can also provide charge trapping functionality.

[0052] When the charge injected into the ferroelectric layer 10 is captured by the charge trapping layer 122, if the charge trapping layer 122 is in direct contact with an adjacent layer, the captured charge may escape into the adjacent layer. A first dielectric layer 121 is disposed between the charge trapping layer 122 and the ferroelectric layer 10, forming a physical barrier; that is, the first dielectric layer 121 acts as a barrier layer. This first dielectric layer 121 increases the energy barrier height that the captured charge needs to overcome to move from the charge trapping layer 122 to the ferroelectric layer 10, thereby reducing the amount of captured charge escaping into the ferroelectric layer 10.

[0053] The second dielectric layer 123 is disposed on the side of the charge trapping layer 122 opposite to the ferroelectric layer 10, thus forming a physical barrier. This second dielectric layer 123 increases the energy barrier height that the trapped charge needs to overcome to move outward from the charge trapping layer 122, thereby reducing the amount of trapped charge escaping outward. The second dielectric layer 123 is the tunneling layer.

[0054] Thus, with the first dielectric layer 121 and the second dielectric layer 123 surrounding the charge trapping layer 122 on both sides, the trapped charge is confined within the charge trapping layer 122 after the applied voltage is removed, making it difficult for it to escape to the sides. Therefore, the presence of the first dielectric layer 121 and the second dielectric layer 123 extends the retention time of the trapped charge in the second interface layer 12. Due to the extended retention time, the amount of charge retained in the charge trapping layer 122 increases after the applied voltage is removed. The retained charge, combined with the different polarization states of the ferroelectric layer 10, increases the number of threshold voltage offset states of the semiconductor stacked structure 1, enlarges the storage window, and improves the retention characteristics of the semiconductor stacked structure 1. Simultaneously, the presence of the first dielectric layer 121 and the second dielectric layer 123 reduces the interface state density between the charge trapping layer 122 and adjacent layers. With the reduced interface state density, the electrical state consistency of the semiconductor stacked structure 1 under different operating conditions is improved.

[0055] In some embodiments, the materials of the first dielectric layer 121 and the second dielectric layer 123 include high-k dielectric materials. High-k dielectric materials refer to dielectric materials with a dielectric constant higher than that of silicon dioxide.

[0056] In one example, both the first dielectric layer 121 and the second dielectric layer 123 are made of Al2O3. The dielectric constant of Al2O3 is approximately 7-9, which is higher than that of silicon dioxide (approximately 3.9). In another example, both the first dielectric layer 121 and the second dielectric layer 123 are made of ZrO2. The dielectric constant of ZrO2 is approximately 20-25. In yet another example, the materials of the first dielectric layer 121 and the second dielectric layer 123 can be different; for example, the first dielectric layer 121 may be made of Al2O3, and the second dielectric layer 123 may be made of ZrO2.

[0057] When the first dielectric layer 121 and the second dielectric layer 123 are made of high-k dielectric materials, their equivalent oxide layer thickness is smaller for the same physical thickness. With a reduced equivalent oxide layer thickness, the voltage drop applied to the second interface layer 12 decreases. This reduced voltage drop means that more applied voltage is distributed to the ferroelectric layer 10, and the electric field strength experienced by the ferroelectric layer 10 during write or erase operations is relatively reduced. With a reduced electric field strength, the material fatigue of the ferroelectric layer 10 during repeated polarization processes is reduced, and the durability of the semiconductor stack-up structure 1 is improved.

[0058] Meanwhile, a smaller equivalent oxide layer thickness also means that the physical thickness of the first dielectric layer 121 and the second dielectric layer 123 can be appropriately increased without significantly increasing the voltage drop. With the increase in physical thickness, the isolation effect of the first dielectric layer 121 and the second dielectric layer 123 on the charge trapped in the charge trapping layer 122 is enhanced, the probability of the trapped charge escaping to both sides is reduced, and the retention time of the trapped charge is prolonged.

[0059] According to the semiconductor stacked structure 1 provided in the embodiments of this application, such as Figure 3 As shown, when a positive pulse is applied (black line), the ferroelectric layer 10 becomes polarized, causing a negative shift in the threshold voltage (green line). The charge injected into the second interface layer 12 further causes the threshold voltage to shift negatively (blue line), while the charge injected into the first interface layer 11 partially cancels out the negative shift (red line). The polarization of the ferroelectric layer 10 and the charge injected into the second interface layer 12 jointly dominate the negative shift of the threshold voltage, ultimately forming a wider storage window.

[0060] When applying a negative pulse (indicated by the black line), such as Figure 4 As shown, the ferroelectric layer 10 is reverse-polarized, causing a positive shift in the threshold voltage (shown by the green line). The charge injected into the second interface layer 12 further shifts the threshold voltage positively (shown by the blue line), while the charge injected into the first interface layer 11 partially cancels out the positive shift (shown by the red line). The polarization of the ferroelectric layer 10 and the charge injected into the second interface layer 12 jointly dominate the positive shift of the threshold voltage, ultimately forming a wider storage window.

[0061] Through the above methods, the semiconductor stacked structure 1 provided in this application embodiment can obtain a large threshold voltage offset under both positive and negative pulse operations, thereby increasing the storage window.

[0062] In some embodiments, the thickness of the first interface layer 11 ranges from 0 nm to 4 nm. The thickness of the first interface layer 11 affects the amount of fixed positive charge inside it and its own insulating properties.

[0063] In one example, the thickness of the first interface layer 11 is 2 nm. In another example, the thickness of the first interface layer 11 is 4 nm.

[0064] When the thickness of the first interface layer 11 is small, for example, 1 nm, the fixed positive charge is closer to the ferroelectric layer 10, and the electric field generated by the fixed positive charge is stronger at the ferroelectric layer 10 and the second interface layer 12, resulting in a stronger attraction for the trapped charge. When the thickness of the first interface layer 11 is large, such as 4 nm, the insulation performance of the first interface layer 11 is improved, the leakage current is reduced, and the retention characteristics of the semiconductor stacked structure 1 are improved. The thickness of the first interface layer 11 can be selected within the above range according to specific application requirements.

[0065] In this embodiment, the thickness of the ferroelectric layer 10 is from 3 nm to 20 nm. The thickness of the ferroelectric layer 10 affects the ferroelectric polarization intensity and the tolerance of the ferroelectric layer 10 during write / erase operations.

[0066] In one example, the thickness of the ferroelectric layer 10 is 5 nm. In another example, the thickness of the ferroelectric layer 10 is 10 nm. In yet another example, the thickness of the ferroelectric layer 10 is 15 nm.

[0067] When the thickness of the ferroelectric layer 10 is small, such as 5 nm, the polarization reversal of the ferroelectric layer 10 can occur under a lower applied voltage, resulting in a lower operating voltage. When the thickness of the ferroelectric layer 10 is large, such as 10 nm, the polarization intensity of the ferroelectric layer 10 is higher, and the remaining polarization intensity after the applied voltage is removed is also large, thus increasing the storage window of the semiconductor stack-up structure 1. The thickness of the ferroelectric layer 10 can be selected within the above range according to the specific requirements of the operating voltage and the storage window.

[0068] In some embodiments, the material of the charge trapping layer 122 includes at least one of the following: aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0069] In one example, the charge trapping layer 122 is made of HfO2. HfO2 contains oxygen vacancy defects, and these defect energy levels can trap electrons or holes. In another example, the charge trapping layer 122 is made of ZrO2. ZrO2 also has defect energy levels, enabling it to trap charges. In yet another example, the charge trapping layer 122 is made of titanium oxide. TiO2 has a high defect density and strong charge trapping ability.

[0070] When the charge trapping layer 122 uses the aforementioned material, the injected charge is trapped by the defect energy levels within the material as it passes through the second interface layer 12. The trapped charge remains in the charge trapping layer 122 after the applied voltage is removed. The trapped charge combines with the polarization state of the ferroelectric layer 10 to generate different threshold voltage offsets, thereby increasing the storage window. The choice of material for the charge trapping layer 122 can be adjusted according to specific application requirements: for longer charge retention time, materials with deeper defect energy levels, such as HfO2, can be selected; for a larger storage window, materials with higher defect density, such as TiO2, can be selected.

[0071] In some embodiments, the thicknesses of the first dielectric layer 121, the charge trapping layer 122, and the second dielectric layer 123 are 2 nm to 6 nm, respectively. The thickness of each layer affects the trapping efficiency of the charge trapping layer 122 and the isolation effect of the first dielectric layer 121 and the second dielectric layer 123 on the trapped charge.

[0072] In one example, the thickness of the first dielectric layer 121, the charge trapping layer 122, and the second dielectric layer 123 is 3 nm. In another example, the thickness of the first dielectric layer 121 is 2 nm, the thickness of the charge trapping layer 122 is 4 nm, and the thickness of the second dielectric layer 123 is 2 nm. In yet another example, the thickness of the first dielectric layer 121 is 4 nm, the thickness of the charge trapping layer 122 is 2 nm, and the thickness of the second dielectric layer 123 is 4 nm.

[0073] When the thickness of the charge trapping layer 122 increases within the above range, the number of defects inside the charge trapping layer 122 that can be used to trap charges increases, the number of charges that can be trapped increases, and the storage window increases.

[0074] When the thickness of the first dielectric layer 121 or the second dielectric layer 123 increases within the above range, the isolation effect of the first dielectric layer 121 or the second dielectric layer 123 on the captured charge in the charge trapping layer 122 is enhanced, the probability of the captured charge escaping to the adjacent layer is reduced, the retention time of the captured charge is extended, and the retention characteristics are improved.

[0075] When the thickness of the first dielectric layer 121 or the second dielectric layer 123 decreases within the above range, the overall physical thickness of the second interface layer 12 decreases, the voltage drop of the applied voltage on the second interface layer 12 decreases, the voltage ratio distributed on the ferroelectric layer 10 increases, and the operating efficiency of the ferroelectric layer 10 improves.

[0076] In some embodiments, the thicknesses of the first dielectric layer 121 and the second dielectric layer 123 are not equal.

[0077] In one example, the thickness of the first dielectric layer 121 is 4 nm, and the thickness of the second dielectric layer 123 is 2 nm. In another example, the thickness of the first dielectric layer 121 is 2 nm, and the thickness of the second dielectric layer 123 is 5 nm.

[0078] When the thicknesses of the first dielectric layer 121 and the second dielectric layer 123 are not equal, the performance of the second interface layer 12 can be optimized according to specific operating conditions. For example, in applications requiring stronger isolation to prevent trapped charges from escaping to the ferroelectric layer 10, the thickness of the first dielectric layer 121 on the side closer to the ferroelectric layer 10 can be set to be larger, for example, the first dielectric layer 121 can be 5 nm and the second dielectric layer 123 can be 2 nm. In applications requiring reduced voltage drop to improve durability, the thickness of the second dielectric layer 123 on the side farther from the ferroelectric layer 10 can be set to be larger, for example, the second dielectric layer 123 can be 5 nm and the first dielectric layer 121 can be 2 nm. By adjusting the thickness ratio of the first dielectric layer 121 and the second dielectric layer 123, a balance can be achieved between performance retention, durability, and operating voltage.

[0079] In some embodiments, the first interface layer 11 comprises silicon oxynitride (SiON). A fixed positive charge in the silicon oxynitride is introduced into the first interface layer 11 by a nitriding process.

[0080] In one example, the nitriding process employs a decoupled plasma nitriding technique. Specifically, after forming a silicon dioxide layer, nitrogen (N) is implanted into the silicon dioxide layer. After N implantation, the silicon dioxide layer transforms into a silicon oxynitride layer, introducing a fixed positive charge within the layer. A subsequent nitriding annealing process is then performed, which homogenizes the distribution of N in the silicon oxynitride layer.

[0081] In another example, the nitriding process can be performed using a thermal nitriding process. The silicon dioxide layer is placed in a nitrogen-containing atmosphere, such as NH3 or NO, and heat-treated at a high temperature, causing nitrogen to diffuse into the silicon dioxide layer, forming a silicon oxynitride layer and introducing a fixed positive charge.

[0082] When nitrogen (N) is introduced into a silicon dioxide layer through nitriding, the resulting silicon oxynitride layer contains fixed positive charges. These fixed positive charges are relatively stable and do not move with changes in the applied voltage.

[0083] The electric field generated by the fixed positive charge points from the first interface layer 11 to the ferroelectric layer 10. This electric field acts on the trapped charges in the charge trapping layer 122 of the second interface layer 12. For the trapped electrons, the electric field generated by the fixed positive charge exerts an attractive force on them in the direction of the first interface layer 11. Under the influence of this attractive force, the trapped electrons move towards the first interface layer 11, resulting in a reduction in the number of unstable electrons in the charge trapping layer 122 of the second interface layer 12. After the number of unstable electrons is reduced, the electrical state consistency of the semiconductor stack-up structure 1 under different operating conditions is improved, and the retention characteristics are enhanced.

[0084] For the trapped holes, the electric field generated by the fixed positive charge produces a repulsive force against them in a direction away from the first interface layer 11. This repulsive force causes the holes to move away from the first interface layer 11, which can also reduce the instability accumulation of holes in the charge trapping layer 122.

[0085] Furthermore, the nitriding process forms nitrogen bonds in the first interface layer 11. The bond energy of nitrogen bonds, such as Si-N bonds, is higher than that of Si-O bonds in the original silicon dioxide layer, resulting in higher structural strength. The introduction of nitrogen bonds makes the atomic bonding within the first interface layer 11 more compact, thus increasing its structural strength. This increased structural strength enhances the first interface layer 11's resistance to deformation or damage during subsequent processing or device use, improving the overall mechanical stability and process compatibility of the semiconductor stack-up structure 1.

[0086] Simultaneously, nitriding also improves the electrical quality of the first interface layer 11 itself. After nitriding followed by annealing, the interface state density in the first interface layer 11 decreases. With the interface state density reduced, the leakage current of the semiconductor stack-up structure 1 decreases, and its durability is improved.

[0087] like Figure 5 As shown, a second aspect of this application also provides a transistor 2. This transistor 2 can be a semiconductor transistor 2, and can be used as a ferroelectric field-effect transistor 2 in a ferroelectric memory. The transistor 2 includes a first substrate 21, a semiconductor stacked structure 1, and a gate 22.

[0088] The first substrate 21 includes a channel 211, a source 212, and a drain 213. The source 212 and the drain 213 are respectively disposed on both sides of the channel 211. The material of the first substrate 21 can be silicon or other semiconductor materials. The channel 211 is located between the source 212 and the drain 213 and is used to form a conductive path when the transistor 2 is operating.

[0089] A semiconductor stacked structure 1 is disposed on a first substrate 21. This semiconductor stacked structure 1 is the semiconductor stacked structure 1 provided in any embodiment of the first aspect of this application. Specifically, the semiconductor stacked structure 1 includes a ferroelectric layer 10, a first interface layer 11, and a second interface layer 12. The first interface layer 11 is disposed on the side of the ferroelectric layer 10 closest to the first substrate 21, and includes a fixed positive charge. The second interface layer 12 is disposed on the side of the ferroelectric layer 10 furthest from the first interface layer 11, and includes a charge trapping layer 122 for trapping charges injected into the ferroelectric layer 10. The fixed positive charge is used to apply an electric field force to the charges trapped by the charge trapping layer 122.

[0090] The semiconductor stacked structure 1 is disposed above the first substrate 21, covering the channel 211 region. When the transistor 2 is working, the gate voltage 22 is coupled to the channel 211 through the semiconductor stacked structure 1, controlling the channel 211 to be turned on or off.

[0091] In one example, the first interface layer 11 in the semiconductor stack 1 is directly disposed on the surface of the first substrate 21 and contacts the channel 211. In another example, an additional interface layer may exist between the first interface layer 11 and the first substrate 21, which does not change the control effect of the semiconductor stack 1 on the channel 211.

[0092] The gate 22 is disposed on the side of the semiconductor stack 1 opposite to the first substrate 21. The material of the gate 22 can be a metal, such as TiN, TaN, or W, or polysilicon. The gate 22 is used to receive an externally applied voltage and induce a charge in the channel 211 through the semiconductor stack 1, thereby controlling the current between the source 212 and the drain 213.

[0093] In one example, gate 22 is a TiN metal layer covering the upper surface of the second interface layer 12. In another example, gate 22 is a polysilicon layer formed by deposition and etching processes.

[0094] When an external voltage is applied to the gate 22, the voltage is transmitted to the channel 211 through the semiconductor stack-up structure 1. The ferroelectric layer 10 undergoes ferroelectric polarization under the applied voltage, and the polarization direction depends on the polarity of the applied voltage. The electric field generated by the ferroelectric polarization affects the charge distribution in the channel 211, thereby changing the threshold voltage of the transistor 2.

[0095] During voltage application, the charge injected into the ferroelectric layer 10 is captured by the charge trapping layer 122 in the second interface layer 12. These trapped charges, together with the polarization state of the ferroelectric layer 10, cause the threshold voltage of the transistor 2 to exhibit multiple offset states, thereby achieving multi-value storage. The trapped charges are subjected to the electric field force exerted by the fixed positive charges within the first interface layer 11, reducing the number of unstable charges, improving the retention stability of the trapped charges, and thus enhancing the retention and durability characteristics of the transistor 2.

[0096] Since the semiconductor stack-up structure 1 is disposed between the first substrate 21 and the gate 22 and covers the channel 211 region, the transistor 2 can realize multi-value storage function without increasing the device area, making it suitable for integration into large-scale memory chips.

[0097] like Figure 6 As shown, an embodiment of the third aspect of this application also provides a semiconductor device 3. This semiconductor device 3 can be used as a three-dimensional ferroelectric memory, for example, in a 3D NAND structure. The semiconductor device 3 includes a second substrate 31, a stacked structure 32, and a semiconductor stack-up structure 1.

[0098] The second substrate 31 is used to support the stacked structure 32. The material of the second substrate 31 can be polycrystalline silicon or other semiconductor materials (such as monocrystalline silicon or silicon-on-insulator). The surface of the second substrate 31 is planarized to provide a flat substrate for the subsequent formation of the stacked structure 32.

[0099] In one example, the second substrate 31 is a polycrystalline silicon substrate. In another example, the second substrate 31 is a monocrystalline silicon substrate. Regardless of the substrate material used, the second substrate 31 serves to support the stacked structure 32 above it.

[0100] A stacked structure 32 is disposed on a second substrate 31. The stacked structure 32 includes a plurality of insulating layers 321 and a plurality of gate metal layers 322 alternately stacked in a direction away from the second substrate 31. The top and bottom layers of the stacked structure 32 are both insulating layers 321. The stacked structure 32 also includes a channel hole 33 penetrating the plurality of insulating layers 321 and the plurality of gate metal layers 322. The channel hole 33 extends downward from the top surface of the stacked structure 32 until it exposes the second substrate 31 or stops at a predetermined depth.

[0101] The insulating layer 321 is used to electrically isolate the adjacent gate metal layer 322. The insulating layer 321 can be made of silicon dioxide or other insulating materials (such as silicon nitride or low-k dielectric materials). The gate metal layer 322 is used to provide the gate voltage 22 when the semiconductor device 3 is operating. The gate metal layer 322 can be made of TiN, W or other metallic materials.

[0102] In one example, the insulating layer 321 is a silicon dioxide layer, the gate metal layer 322 is a TiN layer, and the insulating layer 321 and the gate metal layer 322 are alternately stacked in 5 layers (3 layers of insulating layer 321 and 2 layers of gate metal layer 322 alternately), with the top and bottom layers both being insulating layers 321. In another example, the number of alternating stacked insulating layers 321 and gate metal layers 322 is 7, 9, or more. The more layers, the higher the storage density of the semiconductor device 3.

[0103] The channel hole 33 is formed by a deep hole etching process. The channel hole 33 can be cylindrical in shape, and its inner wall is used to set the semiconductor stack-up structure 1.

[0104] The semiconductor stacked structure 1 adopts the semiconductor stacked structure 1 provided in any embodiment of the first aspect of this application. The semiconductor stacked structure 1 is disposed in the channel hole 33. Specifically, the semiconductor stacked structure 1 includes, from the inside to the outside, a first interface layer 11, a ferroelectric layer 10 and a second interface layer 12 along the radial direction of the channel hole 33.

[0105] It should be noted that the channel hole 33 has a central axis and a radial direction. Along the radial direction, the layers are arranged sequentially from the center of the channel hole 33 to the outer wall. The first interface layer 11 is located on the innermost side, the second interface layer 12 is located on the outermost side (close to the side wall of the channel hole 33), and the ferroelectric layer 10 is located between the first interface layer 11 and the second interface layer 12.

[0106] In one example, a first interface layer 11, a ferroelectric layer 10, and a second interface layer 12 are sequentially disposed from the inside to the outside along the radial direction of the channel aperture 33. The first interface layer 11 contains fixed positive charges, and the second interface layer 12 contains a charge trapping layer 122. In another example, the deposition order of each layer can be adjusted according to process requirements, but the relative positional relationship of the first interface layer 11, the ferroelectric layer 10, and the second interface layer 12 remains as follows: the first interface layer 11 is located inside the ferroelectric layer 10, and the second interface layer 12 is located outside the ferroelectric layer 10.

[0107] When the semiconductor stacked structure 1 is disposed within the channel via 33, the second interface layer 12 is close to the sidewall of the channel via 33 and adjacent to the gate metal layer 322. The first interface layer 11 is located at the innermost side, close to the center of the channel via 33. A channel structure 35 can be further disposed in the central region of the channel via 33 to form a current path.

[0108] When semiconductor device 3 is operating, the gate voltage 22 is applied to the second interface layer 12 through the gate metal layer 322. The ferroelectric layer 10 is ferroelectrically polarized under the applied voltage. The charge injected into the ferroelectric layer 10 is captured by the charge trapping layer 122 in the second interface layer 12. The fixed positive charge in the first interface layer 11 exerts an electric field force on the captured charge, reducing the number of unstable charges and improving the retention stability of the captured charge.

[0109] Since the via 33 penetrates multiple insulating layers 321 and multiple gate metal layers 322, the same via 33 can be coupled to multiple gate metal layers 322 simultaneously. Thus, multiple memory cells can be formed within a single via 33 (each gate metal layer 322 corresponds to one memory cell). Through the combination of the polarization state and trapped charge of the ferroelectric layer 10 in the semiconductor stack-up structure 1, each memory cell can achieve multi-value storage, thereby increasing the storage density of the semiconductor device 3.

[0110] Furthermore, the alternating stacking of insulating layer 321 and gate metal layer 322 allows the semiconductor device 3 to stack multiple memory cells in the vertical direction. This significantly increases storage capacity without increasing chip area. The semiconductor device 3 is compatible with 3D NAND technology and is suitable for mass production.

[0111] Thus, in the semiconductor device 3 provided in this application embodiment, the stacked structure 32 includes a plurality of insulating layers 321 and a plurality of gate metal layers 322 alternately stacked in sequence along the direction away from the second substrate 31, and a channel hole 33 penetrating the plurality of insulating layers 321 and the plurality of gate metal layers 322. The semiconductor stacked structure 1 is disposed in the channel hole 33, and includes a first interface layer 11, a ferroelectric layer 10 and a second interface layer 12 in sequence from the inside to the outside along the radial direction of the channel hole 33. In the above manner, the semiconductor stacked structure 1 in the same channel hole 33 is coupled to the plurality of gate metal layers 322 respectively, forming a plurality of series memory cells in the vertical direction. Each memory cell is independently controlled, and it is not necessary to etch the channel hole 33 separately for each memory cell, thereby obtaining a higher storage density per unit chip area. Since the semiconductor stacked structure 1 is arranged in sequence from the inside to the outside along the radial direction of the channel hole 33, each layer naturally forms a surrounding structure in the channel hole 33. This surrounding structure ensures that the control effect of the gate metal layer 322 on the ferroelectric layer 10 is uniformly distributed around the channel aperture 33 in the circumferential direction, making the charge injection and capture behavior at different angles more consistent and reducing the differences in electrical performance between memory cells. Based on the multilayer stacking in the vertical direction, the second interface layer 12 in each memory cell captures the charge injected into the ferroelectric layer 10, and the fixed positive charge in the first interface layer 11 applies an electric field force to the captured charge.

[0112] Compared to current charge-trapping memory devices, the semiconductor device 3 provided in this application embodiment has a lower operating voltage, faster programming speed, and maintains good endurance and retention characteristics even under large memory window conditions. Furthermore, multiple insulating layers 321 separate adjacent gate metal layers 322, reducing crosstalk between different memory cells. The degree of mutual interference between memory cells of different heights within the same via 33 is reduced during operation, thus improving the operational reliability and data retention characteristics of the semiconductor device 3.

[0113] like Figure 7 As shown, the fourth aspect of this application also provides a method for fabricating a semiconductor device 3. This method is used to fabricate the semiconductor device 3 provided in the third aspect embodiment of this application. The method includes the following steps: Step 701: Provide a second substrate.

[0114] like Figure 8 As shown, a second substrate 31 is provided. The second substrate 31 is used to support the subsequently deposited stacked structure 32. The material of the second substrate 31 can be polycrystalline silicon, monocrystalline silicon, or silicon-on-insulator. The surface of the second substrate 31 is cleaned and planarized to remove surface contaminants and oxides.

[0115] In one example, the second substrate 31 is a polycrystalline silicon substrate, formed by a chemical vapor deposition process. In another example, the second substrate 31 is a monocrystalline silicon substrate, using a standard semiconductor substrate.

[0116] Step 702: Alternately deposit multiple insulating layers and multiple gate metal layers on the second substrate to form a stacked structure.

[0117] like Figure 9 As shown, multiple insulating layers 321 and multiple gate metal layers 322 are alternately deposited on the second substrate 31 to form a stacked structure 32. The insulating layers 321 are used to electrically isolate adjacent gate metal layers 322, and the gate metal layers 322 are used to provide gate voltage 22 when the device is in operation.

[0118] The insulating layer 321 can be made of silicon dioxide, silicon nitride, or a low-k dielectric material. The gate metal layer 322 can be made of TiN, W, or TaN. The deposition process can be chemical vapor deposition or atomic layer deposition.

[0119] In one example, a silicon dioxide layer is first deposited on a substrate as an insulating layer 321, and then a TiN layer is deposited on the silicon dioxide as a gate metal layer 322. This deposition process is repeated to form multiple alternating layers of insulating layers 321 and multiple alternating layers of gate metal layers 322. The top and bottom layers of the stacked structure 32 are both insulating layers 321. In another example, the insulating layer 321 is silicon nitride, the gate metal layer 322 is W, and the number of alternating layers is greater.

[0120] Step 703: Etch the stacked structure to form at least one channel hole, the channel hole penetrating multiple insulating layers and multiple gate metal layers.

[0121] exist Figure 9 On the semiconductor structure shown, the stacked structure 32 is etched to form at least one channel hole 33, resulting in the following: Figure 10The semiconductor structure shown. The channel hole 33 penetrates multiple insulating layers 321 and multiple gate metal layers 322, extending from the top surface of the stacked structure 32 to expose the substrate or stopping at a predetermined depth.

[0122] Etching processes can employ deep-hole etching, such as reactive ion etching or inductively coupled plasma etching. The etching gas is selected based on the material to be etched; for alternating stacks of silicon dioxide and TiN, fluorine-containing gases (such as CF4 or SF6) can be used for etching.

[0123] In one example, the location of the channel hole 33 is defined on the surface of the stacked structure 32 using photolithography, followed by anisotropic etching to form a cylindrical channel hole 33 with vertical sidewalls. In another example, the formed channel hole 33 is elliptical or square, and its depth is determined according to the number of layers in the stacked structure 32.

[0124] Step 704: Form the second interface layer, the ferroelectric layer and the first interface layer sequentially from the outside to the inside on the sidewall of the channel hole.

[0125] On the sidewall of the channel bore 33, a second interface layer 12, a ferroelectric layer 10, and a first interface layer 11 are formed sequentially from the outside to the inside. From the outside to the inside means that each layer is deposited sequentially from the side closest to the sidewall of the channel bore 33 toward the center of the channel bore 33 along the radial direction of the channel bore 33.

[0126] Specifically, in Figure 10 A second interface layer 12 is deposited on the surface of the semiconductor structure shown, resulting in the following: Figure 11 The semiconductor structure is shown. The second interface layer 12 includes a charge trapping layer 122. Then, the second interface layer 12 above the outermost insulating layer 321 is removed to obtain the semiconductor structure shown. Figure 12 The semiconductor structure.

[0127] In one example, the second interface layer 12 adopts a stacked structure, with a barrier layer, a charge trapping layer 122, and a tunneling layer deposited sequentially. The barrier layer and the tunneling layer are made of Al2O3, and the charge trapping layer 122 is made of HfO2. In another example, the material combination of the second interface layer 12 can be replaced with other high-k materials, such as ZrO2 or TiO2.

[0128] Then, in Figure 12 A ferroelectric layer 10 is deposited on the surface of the semiconductor structure shown, resulting in the following: Figure 13 The semiconductor structure shown is then obtained by removing the ferroelectric layer 10 above the outermost insulating layer 321. Figure 14The semiconductor structure is described. The ferroelectric layer 10 can be made of hafnium-based ferroelectric materials, such as Hf0.5Zr0.5O2, or Si or Al-doped HfO2 ferroelectric materials. The deposition process can be atomic layer deposition to precisely control the thickness and composition of the ferroelectric layer 10.

[0129] Finally, Figure 14 The semiconductor structure shown has a first interface layer 11 deposited on its surface to obtain the following: Figure 15 The semiconductor structure shown is then removed. The first interface layer 11 above the outermost insulating layer 321 is then removed to obtain the structure shown. Figure 16 The semiconductor structure. The material of the first interface layer 11 includes silicon dioxide or silicon oxynitride. The deposition process can be chemical vapor deposition or atomic layer deposition.

[0130] Step 705: Nitride the first interface layer to introduce a fixed positive charge into the first interface layer.

[0131] right Figure 16 The first interface layer 11 is nitrided to introduce a fixed positive charge. The nitriding process can be performed using a decoupled plasma nitriding process or a thermal nitriding process.

[0132] After nitriding, nitrogen bonds (e.g., Si-N bonds) are formed in the first interface layer 11. The structural strength of the nitrogen bonds is higher than that of the original Si-O bonds, thus improving the structural strength of the first interface layer 11. Simultaneously, a fixed positive charge is introduced into the interior of the first interface layer 11, resulting in... Figure 17 The semiconductor structure shown.

[0133] Step 706: Form a channel structure on the inner side of the first interface layer.

[0134] A channel structure 35 is formed inside the first interface layer 11. The channel structure 35 is used to provide a current path when the semiconductor device 3 is operating. The channel structure 35 can be made of polycrystalline silicon or other semiconductor materials (e.g., amorphous silicon or oxide semiconductor).

[0135] In one example, such as Figure 18 As shown, a channel substrate 34 is deposited inside the first interface layer 11 using chemical vapor deposition, and a portion of the material is etched onto the channel substrate 34 to form a channel structure 35. Then, the channel substrate 34 above the outermost insulating layer 321 is removed to obtain the desired structure. Figure 6 The semiconductor device shown. In another example, the deposited polysilicon layer covers only the inner surface of the first interface layer 11, forming a hollow tubular channel structure 35.

[0136] Thus, the method for fabricating the semiconductor device 3 provided in this application involves sequentially forming a second interface layer 12, a ferroelectric layer 10, and a first interface layer 11 from the outside to the inside on the sidewall of the channel hole 33. This fabrication sequence allows each layer to naturally form a surrounding structure within the channel hole 33, eliminating the need for additional alignment or patterning steps. Since each layer is formed sequentially through a deposition process, the interface continuity between layers is good, and the interface state density is low. After nitriding the first interface layer 11, a fixed positive charge is introduced into the first interface layer 11, and the structural strength of the first interface layer 11 is improved. The fixed positive charge is used to apply an electric field force to the charges subsequently captured by the charge trapping layer 122, reducing the number of unstable charges. The improved structural strength enhances the ability of the first interface layer 11 to resist deformation or damage during subsequent processes or device use.

[0137] The semiconductor device 3 fabricated by this method has multiple gate metal layers 322 coupled to the same channel via 33, forming multiple memory cells in the vertical direction. Since each layer is formed through deposition and etching processes, there is no need for photolithographic alignment for each memory cell, reducing the complexity of the fabrication process and making it suitable for large-scale production.

[0138] In some embodiments, step 704 above, which involves sequentially forming a second interface layer 12, a ferroelectric layer 10, and a first interface layer 11 on the sidewall of the channel hole 33, specifically includes steps 7041 to 7043: Step 7041: Form a first dielectric layer, a charge trapping layer, and a second dielectric layer on the sidewall of the channel hole to obtain a second interface layer.

[0139] Atomic layer deposition (ALD) was used to sequentially deposit a first dielectric layer 121, a charge trapping layer 122, and a second dielectric layer 123 on the sidewalls of the channel via 33. The first dielectric layer 121 and the second dielectric layer 123 were made of Al₂O₃, and the charge trapping layer 122 was made of HfO₂. The thickness of each layer was 2-6 nm.

[0140] Alternatively, a chemical vapor deposition process can be used: the first dielectric layer 121 and the second dielectric layer 123 are made of ZrO2, and the charge trapping layer 122 is made of TiO2.

[0141] Step 7402: Form a ferroelectric layer on the second interface layer.

[0142] Atomic layer deposition (ALD) was used to deposit a ferroelectric layer 10 on the second interface layer 12. The ferroelectric layer 10 was made of Hf0.5Zr0.5O2 and had a thickness of 3-20 nm.

[0143] Alternatively, a chemical vapor deposition process can be used: the material of the ferroelectric layer 10 is Si or Al-doped HfO2.

[0144] Step 7403: Form a first interface layer on the ferroelectric layer.

[0145] Atomic layer deposition (ALD) is used to deposit a first interface layer 11 on the ferroelectric layer 10. The first interface layer 11 is made of SiO2 and has a thickness of 0 nm to 4 nm.

[0146] Alternatively, a SiO2 layer can be deposited first, and then the SiO2 layer can be nitrided to form a SiON layer as the first interface layer 11.

[0147] In some embodiments, step 705: performing nitriding treatment on the first interface layer 11 to introduce a fixed positive charge into the first interface layer 11, specifically including: Step 7051: The first interface layer is nitrided using a decoupled plasma nitriding process to inject nitrogen ions into the first interface layer and generate positive charges within the first interface layer.

[0148] The substrate after the formation of the first interface layer 11 is placed in a decoupled plasma nitriding apparatus. Nitrogen gas is introduced as the nitrogen source gas. The radio frequency power is set to 2000W and the processing time is 60 seconds. Under the action of plasma, nitrogen ions are accelerated and injected into the first interface layer 11. The injection of nitrogen ions generates a positive charge within the first interface layer 11.

[0149] Alternatively, the parameters of the decoupled plasma nitriding process can be adjusted: the RF power can be set to the range of 1500W to 2500W, and the processing time can be set to the range of 30 seconds to 120 seconds. The nitrogen ion implantation dose increases with increasing power and time, and the number of positive charges generated in the first interface layer 11 increases accordingly.

[0150] Step 7052: Anneal the first interface layer after nitriding using a nitriding-annealing process to fix the positive charge and form a fixed positive charge.

[0151] The nitrided substrate was placed in an annealing apparatus. The annealing temperature was set to 1000℃ and the annealing time to 60 seconds. During the high-temperature annealing process, the injected nitrogen ions redistributed in the first interface layer 11, tending to become uniform. At the same time, positive charges were fixed at the defect sites or in the nitrogen phase bonded structures of the first interface layer 11, forming stable fixed positive charges.

[0152] Alternatively, adjust the parameters of the annealing process after nitriding: set the annealing temperature to the range of 900℃ to 1100℃, and the annealing time to the range of 30 seconds to 120 seconds. The higher the annealing temperature and the longer the time, the more uniform the nitrogen ion distribution and the more stable the fixation effect of the positive charge.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor stacked structure, characterized in that, include: Ferroelectric layer; A first interface layer is disposed on one side of the ferroelectric layer, and the first interface layer includes a fixed positive charge. A second interface layer is disposed on the side of the ferroelectric layer opposite to the first interface layer. The second interface layer includes a charge trapping layer for trapping charges injected into the ferroelectric layer. The fixed positive charge is used to apply an electric field force to the charges trapped by the charge trapping layer.

2. The semiconductor stacked structure according to claim 1, characterized in that, The second interface layer further includes a first dielectric layer and a second dielectric layer, and the charge trapping layer is disposed between the first dielectric layer and the second dielectric layer.

3. The semiconductor stacked structure according to claim 2, characterized in that, The materials of the first dielectric layer and the second dielectric layer include high-k dielectric materials; and / or The material of the charge trapping layer includes at least one of the following: aluminum oxide, silicon oxide, hafnium oxide, zirconium oxide, and titanium oxide.

4. The semiconductor stacked structure according to claim 2, characterized in that, The thickness of the first interface layer is 0 nm to 4 nm; and / or The thickness of the ferroelectric layer is 3nm~20nm; and / or The thicknesses of the first dielectric layer, the charge trapping layer, and the second dielectric layer are 2 nm to 6 nm, respectively; and / or The thicknesses of the first dielectric layer and the second dielectric layer are not equal.

5. The semiconductor stacked structure according to any one of claims 1 to 4, characterized in that, The first interface layer comprises silicon oxynitride, and the fixed positive charge is introduced into the first interface layer by nitriding treatment.

6. A transistor, characterized by include: A first substrate, the first substrate including a channel, a source and a drain, the source and the drain being respectively disposed on both sides of the channel; The semiconductor stacked structure as described in any one of claims 1 to 5 is disposed on the first substrate; A gate is disposed on the side of the semiconductor stack structure opposite to the first substrate.

7. A semiconductor device, characterized by include: Second substrate; A stacked structure is disposed on the second substrate, the stacked structure comprising: a plurality of insulating layers and a plurality of gate metal layers alternately stacked in a direction away from the second substrate, and a channel hole penetrating the plurality of insulating layers and the plurality of gate metal layers; The semiconductor stacked structure according to any one of claims 1 to 5, wherein the semiconductor stacked structure is disposed within the channel hole, and the semiconductor stacked structure comprises, from the inside to the outside, a first interface layer, the ferroelectric layer, and a second interface layer in sequence along the radial direction of the channel hole.

8. A method of manufacturing a semiconductor device, characterized by include: Provide a second substrate; Multiple insulating layers and multiple gate metal layers are alternately deposited on the second substrate to form a stacked structure; The stacked structure is etched to form at least one channel hole, the channel hole penetrating the plurality of insulating layers and the plurality of gate metal layers; A second interface layer, a ferroelectric layer, and a first interface layer are formed sequentially from the outside to the inside on the sidewall of the channel hole. The first interface layer is subjected to nitriding treatment to introduce a fixed positive charge into the first interface layer; A channel structure is formed on the inner side of the first interface layer.

9. The method of producing a semiconductor device according to claim 8, wherein The formation of a second interface layer, a ferroelectric layer, and a first interface layer sequentially on the sidewall of the channel hole includes: A first dielectric layer, a charge trapping layer, and a second dielectric layer are formed on the sidewall of the channel hole to obtain the second interface layer; The ferroelectric layer is formed on the second interface layer; The first interface layer is formed on the ferroelectric layer.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of nitriding the first interface layer to introduce a fixed positive charge within the first interface layer includes: The first interface layer is nitrided using a decoupled plasma nitriding process to inject nitrogen ions into the first interface layer and generate a positive charge within the first interface layer. The first interface layer after nitriding is annealed using a nitriding-annealing process to fix the positive charge and form the fixed positive charge.

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