Semiconductor device using ferroelectric polarization to suppress leakage current and method of manufacturing the same

Abstract

The application discloses a kind of semiconductor devices and preparation method for inhibiting leakage current using ferroelectric polarization, belong to semiconductor device technical field.The device structure is sequentially included from bottom to top heavy-doped conductive silicon substrate, interface passivation layer, charge shielding layer, ferroelectric film layer and top electrode layer, ferroelectric film layer thickness is 5-10nm, selects hafnium oxide doping, aluminum nitride doping and other ferroelectric materials, and charge shielding layer cooperates and blocks carrier migration by ferroelectric polarization effect, inhibits leakage current.Preparation method is through atomic layer deposition, magnetron sputtering, thin film preparation equipment such as thermal evaporation, grows passivation layer, charge shielding layer, ferroelectric film layer and top electrode layer, after being patterned by ultraviolet exposure, ion beam etching, then is shaped by heat annealing.The structure design of the present application is reasonable, process controllability is strong, can significantly improve the stability of thin film and leakage current inhibition effect, the prepared thin film can be used for metal oxide semiconductor capacitor and transistor device, suitable for high performance demand in the field of semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor thin film technology, and more specifically, relates to a semiconductor device that uses ferroelectric polarization to suppress leakage current and its preparation method. Background Technology

[0002] As semiconductor device dimensions continue to shrink, the physical thickness of the gate dielectric layer and other functional thin films is also significantly reduced. This triggers a significant quantum tunneling effect, leading to a surge in leakage current density and severely impacting the power consumption, reliability, and lifespan of semiconductor devices. To suppress leakage current while maintaining the capacitance characteristics of the thin film, high-k dielectric materials are used to replace traditional dielectrics (such as...). It has gradually become the mainstream technological approach.

[0003] Among high dielectric constant materials, hafnium oxide ( Due to its excellent dielectric properties and good compatibility with CMOS technology, it is widely used in various electronic devices. Currently, Thin films are mainly prepared using techniques such as atomic layer deposition (ALD), and also through interaction with alumina (… By combining it with other materials, the interfacial properties and insulation performance of the thin film can be further optimized.

[0004] However, existing methods using hafnium oxide ( In thin films prepared from high dielectric constant materials such as [material name], the leakage current suppression effect is often less than ideal, which directly affects the performance and reliability of semiconductor devices. The applicant's research has revealed that the root cause of the aforementioned technical problem lies in [reason]. The insulating properties of thin films are highly sensitive to their internal microscopic defects (such as oxygen vacancies) and interface state density, and the control of these defects is closely related to the process parameters of atomic layer deposition. This makes the process window for effectively suppressing leakage current very narrow. During mass production, even small process fluctuations can lead to a sharp deterioration in leakage performance, resulting in low yield. In addition, the plasma-enhanced atomic layer deposition (PEALD) technique, which is commonly used to achieve low-temperature deposition, carries the risk of introducing plasma damage into the underlying layer, potentially creating new leakage paths.

[0005] In essence, existing technologies for preparing thin films using high-k dielectric (high-κ) materials are passive insulation solutions. Their ability to block charge carriers depends on the inherent band gap and defect control level of the material itself, which makes it difficult to meet the stringent requirements of advanced semiconductor devices for low leakage current and high reliability. Summary of the Invention

[0006] The main objective of this invention is to propose a semiconductor device and its fabrication method that utilizes ferroelectric polarization to suppress leakage current. This addresses the technical problem that existing technologies for preparing thin films using high-k dielectric materials are passive insulation solutions, whose ability to block charge carriers depends on the inherent band gap and defect control level of the material itself, making it difficult to meet the stringent requirements of advanced semiconductor devices for low leakage current and high reliability.

[0007] To achieve the above objectives, in a first aspect, the present invention proposes a semiconductor device that utilizes ferroelectric polarization to suppress leakage current, the semiconductor device comprising, from bottom to top: The substrate is a heavily doped conductive silicon wafer, wherein the heavily doped conductive silicon wafer is N-type or P-type doped; An interface passivation layer is formed on the surface of the substrate; A charge shielding layer, wherein the charge shielding layer is formed on the surface of the interface passivation layer; A ferroelectric thin film layer, wherein the ferroelectric thin film layer is formed on the surface of the charge shielding layer; A top electrode layer is formed on the surface of the ferroelectric thin film layer; wherein... The thickness of the ferroelectric thin film layer is 5 nm to 10 nm.

[0008] Furthermore, the interface passivation layer is The interface passivation layer has a thickness of 1 nm to 15 nm. The charge shielding layer is The charge shielding layer is any one of the following: TiO2 layer, Nb2O5 layer, and the thickness of the charge shielding layer is 1 nm to 5 nm. The ferroelectric thin film layer is any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, and heterojunction stacked thin film with work function difference. The thickness of the top electrode layer is 20 nm to 80 nm.

[0009] Furthermore, the hafnium oxide doped thin film is any one of silicon doped hafnium oxide thin film, aluminum doped hafnium oxide thin film, yttrium doped hafnium oxide thin film, zirconium co-doped hafnium oxide thin film, and lanthanum / gadolinium doped hafnium oxide thin film; The aluminum nitride doped thin film is any one of scandium-doped aluminum nitride thin film, niobium-doped aluminum nitride thin film, titanium-doped aluminum nitride thin film, and magnesium / aluminum co-doped aluminum nitride thin film; The zirconia doped thin film is any one of yttrium doped zirconia thin film, calcium / magnesium doped zirconia thin film, hafnium doped zirconia thin film, and scandium doped zirconia thin film; The heterojunction stacked thin film with work function difference is any one of the following: high work function oxide / low work function oxide stack, metal nitride / oxide heterojunction stack, wide bandgap / narrow bandgap insulating layer stack, and transition metal chalcogenide / oxide heterojunction.

[0010] Furthermore, the top electrode layer is any one of the following: tungsten layer, gold layer, aluminum layer, platinum layer, palladium layer, titanium layer, copper layer, titanium nitride layer, and tantalum nitride layer.

[0011] Secondly, the present invention proposes a method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current, comprising: Step S1: Select a clean, heavily doped conductive silicon wafer as a substrate, and grow an interface passivation layer on the surface of the substrate by atomic layer deposition to obtain the first thin film. Step S2: A charge shielding layer is formed on the surface of the interface passivation layer by magnetron sputtering or atomic layer deposition to obtain a second thin film; Step S3: Deposit a ferroelectric thin film layer on the surface of the charge shielding layer by atomic layer deposition to obtain a third thin film. The ferroelectric thin film layer is used for electric field modulation and has a thickness ranging from 5 nm to 10 nm. Step S4: A top electrode layer is grown on the surface of the ferroelectric thin film layer by magnetron sputtering to obtain the fourth thin film layer; Step S5: Pattern the fourth thin film with the top electrode layer by ultraviolet exposure and ion beam etching to obtain a metal oxide semiconductor capacitor with electrodes. Step S6: Perform thermal annealing on the metal oxide semiconductor capacitor with electrodes to obtain the semiconductor device that uses ferroelectric polarization to suppress leakage current.

[0012] Furthermore, in step S1, the heavily doped conductive silicon wafer is N-type or P-type doped, and the resistivity of the heavily doped conductive silicon wafer is not greater than 10 Ω·m; the interface passivation layer is... The interface passivation layer has a thickness of 1 nm to 15 nm.

[0013] Furthermore, in step S2, a charge shielding layer is formed on the surface of the interface passivation layer by atomic layer deposition; wherein, the charge shielding layer is... The charge shielding layer can be any one of the following: TiO2 layer, Nb2O5 layer, or TiO2 layer, with a thickness of 1 nm to 5 nm.

[0014] Furthermore, the charge shielding layer is The atomic layer deposition uses trimethylaluminum as the aluminum precursor and water vapor as the oxygen source.

[0015] Furthermore, in step S3, the ferroelectric thin film layer is any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, or heterojunction stacked thin film with work function difference.

[0016] Furthermore, in step S3, the ferroelectric thin film layer is a zirconium co-doped hafnium oxide thin film, and a ferroelectric thin film layer is deposited on the surface of the charge shielding layer by atomic layer deposition, including: Step S31: Place the second thin film with the charge shielding layer in the reaction chamber of the atomic layer deposition equipment, set the reaction temperature, use tetraethylmethylaminohafnium and tetraethylmethylaminozirconium as metal precursors, use water vapor as oxygen source, and use nitrogen as purge gas. Step S32: Tetraethylmethylaminohafnium is introduced into the reaction chamber, causing it to chemically adsorb onto the surface of the charge shielding layer of the second thin film; then nitrogen gas is introduced to purge and remove unreacted tetraethylmethylaminohafnium and reaction byproducts; finally, water vapor is introduced to react with the chemically adsorbed tetraethylmethylaminohafnium to generate... Nitrogen gas is introduced to purge and remove unreacted water vapor and reaction byproducts; Step S33: Tetraethylmethylaminozirconium is introduced into the reaction chamber, causing tetraethylmethylaminozirconium to be chemically adsorbed onto... The surface was then purged with nitrogen gas to remove unreacted tetraethylmethylaminozirconium and reaction byproducts; water vapor was then introduced to react with the chemically adsorbed tetraethylmethylaminozirconium to generate... Nitrogen gas is introduced to purge and remove unreacted water vapor and reaction byproducts; Step S34, repeat steps S32 and S33 to form and By alternating growth and stacking, and controlling the number of cycles, zirconium co-doped hafnium oxide thin films with a thickness of 5 nm to 10 nm are finally obtained.

[0017] Furthermore, in step S4, the top electrode layer is a tungsten layer, and a top electrode layer is grown on the surface of the ferroelectric thin film layer by magnetron sputtering, including: Step S41: Clean the surface of the third thin film after the ferroelectric thin film deposition is completed to remove residual impurities on the surface; Step S42: Place the cleaned third thin film into the vacuum chamber of the magnetron sputtering equipment, select a tungsten target as the sputtering target material, and introduce argon gas as the sputtering gas in a vacuum environment. Step S43: Start the magnetron sputtering power supply and use DC sputtering mode to perform deposition, and finally deposit a tungsten layer with a thickness of 40 nm on the surface of the ferroelectric thin film layer; Step S44: After sputtering is completed, turn off the power and argon gas inlet valve, cool the temperature inside the vacuum chamber to room temperature, slowly release the vacuum, open the chamber and take out the fourth thin film with tungsten layer.

[0018] Furthermore, in step S5, the graphical processing includes: Step S51: Spin coat photoresist onto the surface of the pre-formed stacked film, and use a spin coater to spin coat the photoresist. Heat the film after spin coat treatment. Step S52: Perform hard contact and ultraviolet exposure on the heated photoresist, and then develop it in a developing solution after exposure; Step S53: Etch the photoresist to obtain a metal oxide semiconductor capacitor with electrodes.

[0019] Furthermore, in step S6, the thermal annealing includes: Step S61: Place the metal oxide semiconductor capacitor in a vacuum annealing furnace; Step S62: After evacuating the vacuum annealing furnace, nitrogen gas is introduced, and then the furnace is evacuated again. Step S63: After raising the temperature inside the vacuum annealing furnace to the preset temperature, stop heating and allow the metal oxide semiconductor capacitor to cool naturally to room temperature to complete the thermal annealing process.

[0020] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention provides a semiconductor device and its fabrication method that utilize ferroelectric polarization to suppress leakage current, wherein the ferroelectric thin film layer is selected from hafnium oxide-doped thin films, aluminum nitride-doped thin films, zirconium oxide-doped thin films, and heterojunction stacked thin films with work function differences. When the ferroelectric thin film layer is a zirconium co-doped hafnium oxide thin film, it is composed of... and The alternating stacked structure, with its high remanent polarization characteristics, can build a built-in electric field on the surface of semiconductor devices that is much stronger than the fixed charge electric field of traditional high dielectric constant materials. This built-in electric field can more effectively repel minority carriers and significantly reduce surface leakage current. (2) This invention provides a semiconductor device and its fabrication method that uses ferroelectric polarization to suppress leakage current. By controlling the polarization state of the ferroelectric thin film layer through post-electric polarization operation, the final passivation effect is decoupled from the front-end sensitive thin film deposition process, which broadens the process window for effectively suppressing leakage current, reduces the impact of process fluctuations on leakage performance in mass production environment, and significantly improves the yield and consistency of products. (3) This invention provides a semiconductor device that uses ferroelectric polarization to suppress leakage current and its preparation method. The materials used and the processes such as atomic layer deposition, magnetron sputtering, and ultraviolet exposure are all compatible with the mature technologies of existing semiconductor production lines. The newly added electrical polarization step can be completed using standard testing equipment without the need to introduce expensive non-standard equipment or make major modifications to the production line, thus reducing the threshold for industrial application. (4) This invention provides a semiconductor device that utilizes ferroelectric polarization to suppress leakage current and its fabrication method. The synergistic effect of the interface passivation layer and the charge shielding layer reduces interface defects and charge accumulation. Combined with the ferroelectric thin film layer quality optimized by thermal annealing, it further improves the long-term operational stability of semiconductor devices and meets the stringent high reliability requirements of advanced semiconductor devices. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a semiconductor device with an interface passivation layer grown on the substrate surface, which utilizes ferroelectric polarization to suppress leakage current in one embodiment of the present invention. Figure 2 This is a schematic diagram of a semiconductor device with a charge shielding layer formed on the surface of the interface passivation layer that utilizes ferroelectric polarization to suppress leakage current in one embodiment of the present invention. Figure 3 This is a schematic diagram of a semiconductor device in one embodiment of the present invention, in which a ferroelectric thin film layer is deposited on the surface of the charge shielding layer. Figure 4 This is a schematic diagram of a semiconductor device with a top electrode layer grown on the surface of a ferroelectric thin film layer, which utilizes ferroelectric polarization to suppress leakage current in one embodiment of the present invention. Figure 5 This is a flowchart illustrating the steps of a method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current according to one embodiment of the present invention. Figure 6 This is a schematic diagram of a metal oxide semiconductor capacitor structure with electrodes obtained by a method for fabricating a semiconductor device that uses ferroelectric polarization to suppress leakage current according to one embodiment of the present invention. Figure 7 This is a test result of the leakage current performance of a semiconductor device that utilizes ferroelectric polarization to suppress leakage current in one embodiment of the present invention. Figure 8 This describes the leakage current performance test results of existing semiconductor devices that do not utilize ferroelectric polarization to suppress leakage current. Detailed Implementation

[0022] The various aspects of the present invention will be further described in detail below.

[0023] Unless otherwise defined or stated, all technical and scientific terms used herein have the same meaning as are familiar to a user skilled in the art. Furthermore, any methods and materials similar to or equivalent to those described herein may be applied to the methods of this invention.

[0024] Example 1

[0025] See appendix Figure 1 To be continued Figure 4 In a first aspect, the present invention proposes a semiconductor device that utilizes ferroelectric polarization to suppress leakage current, the semiconductor device comprising, from bottom to top: Substrate 1, wherein the substrate 1 is a heavily doped conductive silicon wafer, and the heavily doped conductive silicon wafer is N-type or P-type doped; Interface passivation layer 2, wherein the interface passivation layer 2 is formed on the surface of the substrate. layer; Charge shielding layer 3, wherein the charge shielding layer 3 is formed on the surface of the interface passivation layer. Any one of the following: layer, TiO2 layer, and Nb2O5 layer; Ferroelectric thin film layer 4, wherein the ferroelectric thin film layer 4 is any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, or heterojunction stacked thin film with work function difference formed on the surface of the charge shielding layer. The top electrode layer 5 is any one of the following layers formed on the surface of the ferroelectric thin film layer: a tungsten layer, a gold layer, an aluminum layer, a platinum layer, a palladium layer, a titanium layer, a copper layer, a titanium nitride layer, and a tantalum nitride layer; wherein, The thickness of the ferroelectric thin film layer 4 is 5 nm to 10 nm, and the ferroelectric thin film layer 4 is used for electric field modulation; preferably, the thickness of the ferroelectric thin film layer 4 is 6 nm to 9 nm; more preferably, it is 7 nm to 8 nm.

[0026] In a preferred embodiment, the heavily doped conductive silicon wafer is N-type or P-type doped. It should be noted that N-type heavily doped conductive silicon wafers achieve high conductivity by doping with phosphorus or arsenic. Phosphorus or arsenic atoms have five valence electrons, and doping with phosphorus or arsenic can provide excess electrons to the silicon lattice, thereby significantly reducing the resistivity of the silicon wafer. P-type heavily doped conductive silicon wafers achieve high conductivity by doping with boron. Boron atoms have only three valence electrons, and doping with boron creates holes in the silicon lattice, which act as charge carriers to improve conductivity.

[0027] In a preferred embodiment, the interface passivation layer 2 is grown on the surface of the substrate 1 by magnetron sputtering or atomic layer deposition. Preferably, the interface passivation layer 2 is obtained by atomic layer deposition.

[0028] In a preferred embodiment, the charge shielding layer 3 is obtained by magnetron sputtering or atomic layer deposition. Preferably, the charge shielding layer 3 is obtained by atomic layer deposition.

[0029] In a preferred embodiment, the ferroelectric thin film layer is a hafnium oxide-doped thin film.

[0030] In a preferred embodiment, the ferroelectric thin film layer 4 is obtained by atomic layer deposition.

[0031] In a preferred embodiment, the top electrode layer 5 is obtained by magnetron sputtering.

[0032] Example 2

[0033] See appendix Figure 1 To be continued Figure 6 Secondly, this invention proposes a method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current, comprising: Step S1: Select a clean, heavily doped conductive silicon wafer as substrate 1, and grow an interface passivation layer 2 on the surface of substrate 1 using atomic layer deposition to obtain the first thin film. The interface passivation layer 2 is... layer; Step S2: A charge shielding layer 3 is formed on the surface of the interface passivation layer 2 by magnetron sputtering or atomic layer deposition, resulting in a second thin film. The charge shielding layer 3 is... Any one of the following: layer, TiO2 layer, and Nb2O5 layer; Step S3: A ferroelectric thin film layer 4 is deposited on the surface of the charge shielding layer 3 by atomic layer deposition to obtain a third thin film. The ferroelectric thin film layer 4 is selected from any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, and heterojunction layer thin film with work function difference, with a thickness range of 5 nm to 10 nm. The ferroelectric thin film layer is used for electric field control. Step S4: A top electrode layer 5 is grown on the surface of the ferroelectric thin film layer 4 by magnetron sputtering to obtain a fourth thin film. The top electrode layer 5 is any one of tungsten layer, gold layer, aluminum layer, platinum layer, palladium layer, titanium layer, copper layer, titanium nitride layer, and tantalum nitride layer. Step S5: The fourth thin film with the top electrode layer 5 is patterned by ultraviolet exposure and ion beam etching to obtain a metal oxide semiconductor capacitor 6 with electrodes. Step S6: Perform thermal annealing on the metal oxide semiconductor capacitor 6 with electrodes to obtain the semiconductor device that uses ferroelectric polarization to suppress leakage current.

[0034] In a preferred embodiment, in step S1, the heavily doped conductive silicon wafer is N-type or P-type doped, the resistivity of the heavily doped conductive silicon wafer is not greater than 10 Ω·m, and the thickness of the interface passivation layer 2 is 1 nm to 15 nm. Preferably, the thickness of the interface passivation layer 2 is 2 nm to 14 nm; preferably, 3 nm to 13 nm; preferably, 4 nm to 12 nm; preferably, 5 nm to 11 nm; preferably, 6 nm to 10 nm; preferably, 7 nm to 9 nm; preferably, 8 nm.

[0035] In a preferred embodiment, in step S2, the charge shielding layer 3 is A charge shielding layer 3 is formed on the surface of the interface passivation layer 2 by atomic layer deposition (ALD), comprising: Step S21, Place the [something] with The first thin film of the layer is placed in the reaction chamber of the atomic layer deposition equipment; Step S22: Trimethylaluminum (TMA) is introduced into the reaction chamber for 150 ms. The TMA is absorbed through chemisorption. A monolayer is formed on the surface of the interface passivation layer; Step S23: Purge the reaction chamber with nitrogen gas for 1 second to thoroughly remove unadsorbed TMA and reaction byproducts. Step S24: Water vapor is introduced into the reaction chamber for 150 ms. The water vapor reacts chemically with the TMA adsorbed on the surface to generate... Thin film layer; Step S25: Purge the reaction chamber with nitrogen gas again for 1 second to remove unreacted water vapor and reaction byproducts. Step S26: Repeat steps S22-S25 to form a complete ALD deposition cycle. By controlling the number of cycles, The thickness of the charge shielding layer reaches a preset value of 1nm to 5nm.

[0036] In a preferred embodiment, in step S26, the number of cycles is controlled to make... The thickness of the charge shielding layer reaches a preset value of 1.4nm to 4.9nm; preferably, it is 1.5nm to 4.8nm; preferably, it is 1.6nm to 4.7nm; preferably, it is 1.7nm to 4.6nm; preferably, it is 1.8nm to 4.5nm; preferably, it is 1.9nm to 4.4nm; preferably, it is 2.0nm to 4.3nm; preferably, it is 2.1nm to 4.2nm; preferably, it is 2.2nm to 4.1nm; preferably, it is 2.3nm to 4.0nm; preferably, it is 2.4nm to 3.9nm; preferably, it is 2.5nm to 3.8nm; preferably, it is 2.6nm to 3.7nm; preferably, it is 2.7nm to 3.6nm; preferably, it is 2.8nm to 3.5nm; preferably, it is 2.9nm to 3.4nm; preferably, it is 3.0nm to 3.3nm; preferably, it is 3.2nm.

[0037] In a preferred embodiment, in step S26, by controlling the number of cycles to 10 cycles, The thickness of the layer reaches 1 nm.

[0038] It should be noted that the TMA is an aluminum-containing precursor and the water vapor is an oxygen source.

[0039] It should be noted that when the charge shielding layer 3 is a TiO2 layer or a Nb2O5 layer, atomic layer deposition technology can still be used. To deposit a TiO2 or Nb2O5 layer on the surface of the layer, only the corresponding precursor and oxygen source need to be set.

[0040] In a preferred embodiment, in step S3, the ferroelectric thin film layer 4 is selected from any one of silicon-doped hafnium oxide thin film, aluminum-doped hafnium oxide thin film, yttrium-doped hafnium oxide thin film, zirconium co-doped hafnium oxide thin film, and lanthanum / gadolinium-doped hafnium oxide thin film.

[0041] In a preferred embodiment, in step S3, the ferroelectric thin film layer 4 is an HfZrO layer, and a ferroelectric thin film layer 4 is deposited on the surface of the charge shielding layer 3 by atomic layer deposition, including: Step S31, with The second thin film of the layer was placed in the reaction chamber of the atomic layer deposition equipment, and the reaction temperature was set to 300°C. Tetraethylmethylaminohafnium (TEMAH) and tetraethylmethylaminozirconium (TEMAZ) were used as metal precursors, and water vapor ( (Oxygen is used as the oxygen source, and nitrogen is used as the purging gas;) Step S32: Introduce TEMAH into the reaction chamber for 150 ms, allowing TEMAH to chemically adsorb onto the sample surface; then purge with nitrogen gas for 1 s to remove unreacted TEMAH and reaction byproducts; finally, introduce water vapor for 150 ms to react with the adsorbed TEMAH to form... Finally, nitrogen gas is introduced to purge for 1 second to remove unreacted water vapor and reaction byproducts. Step S33: Introduce TEMAZ into the reaction chamber for 150 ms. TEMAZ is chemically adsorbed onto... The surface was then purged with nitrogen for 1 second to remove unreacted TEMAZ and reaction byproducts; water vapor was then introduced for 150 ms to react with the adsorbed TEMAZ to form... Finally, nitrogen gas is introduced to purge for 1 second to remove unreacted water vapor and reaction byproducts. Step S34, repeat steps S32 and S33 to form and By alternating growth and stacking, and controlling the number of cycles, HfZrO layers with a thickness of 5nm to 10nm are finally obtained.

[0042] In a preferred embodiment, in step S34, the thickness of the HfZrO layer is made to 10 nm by controlling the number of cycles to 70 cycles.

[0043] It should be noted that, for example, when the ferroelectric thin film layer 4 is any one of silicon-doped hafnium oxide thin film, aluminum-doped hafnium oxide thin film, yttrium-doped hafnium oxide thin film, or lanthanum / gadolinium-doped hafnium oxide thin film, only the metal precursor in step S3 needs to be adaptively replaced, and the remaining steps are similar to the steps described above.

[0044] In a preferred embodiment, in step S4, the top electrode layer 5 is a tungsten layer, and a top electrode layer 5 is grown on the surface of the ferroelectric thin film layer 4 by magnetron sputtering, including: Step S41: Clean the surface of the third-layer film after HfZrO layer deposition to remove residual impurities and adsorbed water vapor on the surface and ensure a clean deposition interface. Step S42: Place the cleaned third-layer film into the vacuum chamber of the magnetron sputtering equipment, fix it in the center of the sample stage, and select a tungsten (W) target with a purity ≥99.99% as the sputtering target; close the chamber and evacuate to a vacuum level. In the following high vacuum environment, argon (Ar) is introduced as the sputtering gas, and the argon flow rate is adjusted to 20 sccm to 30 sccm to maintain the working pressure in the chamber at 0.5 Pa to 1.0 Pa; Step S43: Start the magnetron sputtering power supply, set the sputtering power to 100W, and use DC sputtering mode to deposit the W top electrode. During the deposition process, keep the sample stage rotating at a constant speed (10r / min to 20r / min) to ensure uniform film thickness. Continue sputtering for 1800s to deposit a tungsten layer with a thickness of about 40nm on the surface of the HfZrO layer. Step S44: After sputtering is completed, turn off the power and argon gas inlet valve, keep the chamber under vacuum and cool for 30 minutes. After the sample temperature drops to room temperature, slowly release the vacuum, open the chamber and take out the fourth thin film with tungsten layer.

[0045] In a preferred embodiment, in step S5, the graphical processing includes: Step S51: Spin coat the photoresist AZ-5214 onto the surface of the fourth thin film, and use a spin coater to spin coat the photoresist. The spin coater speed is 8000 r / min and the spin coat treatment time is 80s. Then heat it on a 90℃ heating table for 60s. Step S52: Perform hard contact and ultraviolet exposure on the heated photoresist. Hard contact lasts for 5 seconds, exposure lasts for 8 seconds, and then develop in the developer for 60 seconds after exposure. Step S53: The photoresist is etched using an ion beam etching machine with an ion beam energy of 500 eV, a beam current of 100 nA, and an etching time of 600 s to obtain a metal oxide semiconductor capacitor 6 with electrodes.

[0046] In a preferred embodiment, in step S6, the thermal annealing includes: Step S61: Place the metal oxide semiconductor capacitor 6 in a vacuum annealing furnace; Step S62: Evacuate the vacuum annealing furnace to 100 Pa and then introduce nitrogen gas for 30 seconds, and then evacuate it to 100 Pa again. Step S63: Raise the temperature inside the vacuum annealing furnace to 400°C at a heating rate of 20K / second, then stop heating and allow the metal oxide semiconductor capacitor to cool naturally to room temperature to complete the thermal annealing process.

[0047] Test Example 1 A clean, heavily doped p-type conductive silicon wafer was selected as substrate 1. The resistivity of the heavily doped conductive silicon wafer was no greater than 10 Ω·m. A 2 nm thick layer was deposited on the surface of substrate 1 using atomic layer deposition. Interface passivation layer; deposited using atomic layer deposition on the A 5nm thick layer is deposited on the interface passivation layer. Charge shielding layer; deposited using atomic layer deposition on the A 5 nm thick HfZrO ferroelectric thin film layer was deposited on the charge shielding layer; a 40 nm thick tungsten top electrode layer was deposited on the HfZrO ferroelectric thin film layer by magnetron sputtering; photoresist AZ-5214 was spin-coated onto the tungsten top electrode layer and baked at 90 °C for 60 s, exposed to ultraviolet light and developed for 60 s, and then the tungsten top electrode layer was patterned by ion beam etching. After patterning, the photoresist was removed with acetone, and then annealed in a vacuum annealing furnace at 400 °C in a nitrogen atmosphere for 30 s to obtain a semiconductor device that uses ferroelectric polarization to suppress leakage current.

[0048] See appendix Figure 7 To be continued Figure 8 The leakage current performance of the semiconductor device that uses ferroelectric polarization to suppress leakage current was tested. It can be seen that the leakage current performance of the stacked film with a 5nm thick HfZrO ferroelectric thin film layer is improved by about one order of magnitude compared with the film without HfZrO ferroelectric thin film layer.

[0049] In summary, this invention discloses a semiconductor device and its fabrication method that utilizes ferroelectric polarization to suppress leakage current. The ferroelectric thin film layer is any one of hafnium oxide-doped thin films, aluminum nitride-doped thin films, zirconium oxide-doped thin films, or heterojunction stacked thin films with a work function difference. When the ferroelectric thin film layer is an HfZrO layer, it is composed of… and The alternating stacked structure, with its high remanent polarization characteristics, can construct a built-in electric field on the semiconductor device surface that is far stronger than the fixed charge electric field of traditional high dielectric constant materials. This built-in electric field can more effectively repel minority carriers and significantly reduce surface leakage current. By controlling the polarization state of the ferroelectric thin film layer through post-processing electrical polarization, the final passivation effect is decoupled from the sensitive front-end thin film deposition process. This broadens the process window for effectively suppressing leakage current, reduces the impact of process fluctuations in mass production environments on leakage performance, and significantly improves product yield and consistency.

[0050] Based on this invention, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Furthermore, this device and / or practice the method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0051] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for users of ordinary skills in this field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0052] All documents mentioned in this invention are incorporated herein by reference as if each document were individually incorporated by reference. Furthermore, it should be understood that after reading the foregoing description of this invention, users skilled in the art can make various alterations or modifications to this invention, and these equivalent forms also fall within the scope defined by the appended claims.

Claims

1. A semiconductor device that utilizes ferroelectric polarization to suppress leakage current, characterized in that, The semiconductor device comprises, from bottom to top: The substrate is a heavily doped conductive silicon wafer, wherein the heavily doped conductive silicon wafer is N-type or P-type doped; An interface passivation layer is formed on the surface of the substrate; A charge shielding layer, wherein the charge shielding layer is formed on the surface of the interface passivation layer; A ferroelectric thin film layer, wherein the ferroelectric thin film layer is formed on the surface of the charge shielding layer; A top electrode layer is formed on the surface of the ferroelectric thin film layer; wherein... The thickness of the ferroelectric thin film layer is 5 nm to 10 nm.

2. The semiconductor device for suppressing leakage current using ferroelectric polarization according to claim 1, characterized in that, The interface passivation layer is The interface passivation layer has a thickness of 1 nm to 15 nm. The charge shielding layer is The charge shielding layer is any one of the following: TiO2 layer, Nb2O5 layer, and the thickness of the charge shielding layer is 1 nm to 5 nm. The ferroelectric thin film layer is any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, and heterojunction stacked thin film with work function difference. The top electrode layer is any one of tungsten, gold, aluminum, platinum, palladium, titanium, copper, titanium nitride, and tantalum nitride, with a thickness of 20 nm to 80 nm.

3. A method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current, characterized in that, include: Step S1: Select a clean, heavily doped conductive silicon wafer as a substrate, and grow an interface passivation layer on the surface of the substrate by atomic layer deposition to obtain the first thin film. Step S2: A charge shielding layer is formed on the surface of the interface passivation layer by magnetron sputtering or atomic layer deposition to obtain a second thin film; Step S3: Deposit a ferroelectric thin film layer on the surface of the charge shielding layer by atomic layer deposition to obtain a third thin film. The ferroelectric thin film layer is used for electric field modulation and has a thickness ranging from 5 nm to 10 nm. Step S4: A top electrode layer is grown on the surface of the ferroelectric thin film layer by magnetron sputtering to obtain the fourth thin film layer; Step S5: The fourth thin film with the top electrode layer is patterned by ultraviolet exposure and ion beam etching to obtain a metal oxide semiconductor capacitor with electrodes. Step S6: Perform thermal annealing on the metal oxide semiconductor capacitor with electrodes to obtain the semiconductor device that uses ferroelectric polarization to suppress leakage current.

4. The method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current according to claim 3, characterized in that, In step S1, the heavily doped conductive silicon wafer is N-type or P-type doped, and the resistivity of the heavily doped conductive silicon wafer is not greater than 10 Ω·m; the interface passivation layer is... The interface passivation layer has a thickness of 1 nm to 15 nm.

5. The method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current according to claim 3, characterized in that, In step S2, a charge shielding layer is formed on the surface of the interface passivation layer by atomic layer deposition; wherein, the charge shielding layer is... The charge shielding layer is of any one of the following: a TiO2 layer or a Nb2O5 layer, with a thickness of 1 nm to 5 nm.

6. The method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current according to claim 5, characterized in that, The charge shielding layer is The atomic layer deposition uses trimethylaluminum as the aluminum precursor and water vapor as the oxygen source.

7. The method for fabricating a semiconductor device using ferroelectric polarization to suppress leakage current according to claim 3, characterized in that, In step S3, the ferroelectric thin film layer is any one of hafnium oxide doped thin film, aluminum nitride doped thin film, zirconium oxide doped thin film, or heterojunction stacked thin film with work function difference.

8. The method for fabricating a semiconductor device that suppresses leakage current using ferroelectric polarization according to claim 7, characterized in that, In step S3, the ferroelectric thin film layer is a zirconium co-doped hafnium oxide thin film, and a ferroelectric thin film layer is deposited on the surface of the charge shielding layer by atomic layer deposition, including: Step S31: Place the second semiconductor device with a charge shielding layer in the reaction chamber of the atomic layer deposition equipment, set the reaction temperature, use tetraethylmethylaminohafnium and tetraethylmethylaminozirconium as metal precursors, use water vapor as oxygen source, and use nitrogen as purge gas. Step S32: Tetraethylmethylaminohafnium is introduced into the reaction chamber, causing it to chemically adsorb onto the surface of the charge shielding layer of the second semiconductor device; then nitrogen gas is introduced to purge and remove unreacted tetraethylmethylaminohafnium and reaction byproducts; finally, water vapor is introduced to react with the chemically adsorbed tetraethylmethylaminohafnium to generate... Nitrogen gas is introduced to purge and remove unreacted water vapor and reaction byproducts; Step S33: Tetraethylmethylaminozirconium is introduced into the reaction chamber, causing tetraethylmethylaminozirconium to be chemically adsorbed onto... The surface was then purged with nitrogen gas to remove unreacted tetraethylmethylaminozirconium and reaction byproducts; water vapor was then introduced to react with the chemically adsorbed tetraethylmethylaminozirconium to generate... Nitrogen gas is introduced to purge and remove unreacted water vapor and reaction byproducts; Step S34, repeat steps S32 and S33 to form and By alternating growth and stacking, and controlling the number of cycles, HfZrO layers with a thickness of 5nm to 10nm are finally obtained.

9. The method for fabricating a semiconductor device that utilizes ferroelectric polarization to suppress leakage current according to claim 3, characterized in that, In step S4, the top electrode layer is a tungsten layer, and a top electrode layer is grown on the surface of the ferroelectric thin film layer by magnetron sputtering, including: Step S41: Clean the surface of the third semiconductor device after the ferroelectric thin film layer deposition is completed to remove residual impurities on the surface; Step S42: Place the cleaned third semiconductor device into the vacuum chamber of the magnetron sputtering equipment, select a tungsten target as the sputtering target material, and introduce argon gas as the sputtering gas in a vacuum environment. Step S43: Start the magnetron sputtering power supply and use DC sputtering mode to perform deposition, and finally deposit a tungsten layer with a thickness of 40 nm on the surface of the ferroelectric thin film layer; Step S44: After sputtering is completed, turn off the power and argon gas inlet valve, cool the temperature inside the vacuum chamber to room temperature, slowly release the vacuum, open the chamber and take out the fourth semiconductor device with the tungsten layer.

10. The method for fabricating a semiconductor device using ferroelectric polarization to suppress leakage current according to claim 3, characterized in that, In step S5, the graphical processing includes: Step S51: Spin coat photoresist onto the surface of the pre-formed semiconductor device, and use a spin coater to spin coat the photoresist. Heat the photoresist after the spin coat process. Step S52: Perform hard contact and ultraviolet exposure on the heated photoresist, and then develop it in a developing solution after exposure; Step S53: Etch the photoresist to obtain a metal oxide semiconductor capacitor with electrodes.

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