A trench power device and a manufacturing method thereof

Abstract

The application discloses a trench power device and a manufacturing method thereof, which comprises a semiconductor layer, a cell trench structure and a terminal trench structure. The semiconductor layer comprises a substrate layer, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are stacked in sequence. The cell trench structure extends from the surface of the third epitaxial layer to the second epitaxial layer inside the semiconductor layer. The terminal trench structure extends from the surface of the third epitaxial layer to the second epitaxial layer inside the semiconductor layer. The trench power device provided by the application can greatly reduce the packaging size by changing the structure and current channel of the device and leading out the three electrodes of the SGT device on the same surface, and can be directly used for CSP packaging without external clamps or leads to adjust the position of the electrodes. Further, the semiconductor layer structure is compatible with an N-type furnace tube platform, and the trench type terminal structure can be used to form the structure of the semiconductor layer by epitaxial growth, thereby simplifying the process and improving the quality of the semiconductor layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a trench power device. Background Technology

[0002] Shielded Gate Trench (SGT) power devices are a common type of vertical metal-oxide-semiconductor field-effect transistor (MOSFET), widely used in power management, battery protection, and high-frequency switching. Figure 1 This is a schematic diagram of the existing SGT power device 100. (See attached diagram.) Figure 1 As shown, the SGT power device 100 includes: a semiconductor layer 101, including a substrate 102 and an epitaxial layer 103 located on one side of the substrate 102, a trench gate 104 formed in the epitaxial layer 103, and a body region 105 and a source region 106 on both sides of the trench gate 104. The trench gate 104 includes a gate electrode 108 located in the upper half of the trench, a field electrode 107 located in the lower half of the trench, and a dielectric layer 109 for isolating the electrode from the trench sidewalls. In the SGT power device 100, the source region 106 is located on the surface of the body region 105 and is connected to the external structure as the source S of the device; the gate electrode 108 is connected to the external structure as the gate G of the device; and the substrate 102 is connected to the external structure as the drain of the device.

[0003] In the SGT power device 100, the source region 106 and the gate electrode 108 are located on the front side of the device, while the drain region, i.e., the substrate 102, is located on the back side of the device. When the SGT power device 100 is packaged in a flip-chip package, the drain D typically needs to be connected to the same plane as the source S and the gate G through external structures, such as clamps or leads. This connection method often increases the package size and package parasitic inductance. Summary of the Invention

[0004] This application provides a trench power device. By changing the device structure and current channel, the three electrodes of the trench power device are led out on the same surface, thereby greatly reducing the package size and allowing direct use in CSP packaging without the need for external fixtures or leads to adjust the electrode positions. Furthermore, the trench power device and its fabrication method provided in this application are compatible with N-type furnace tubes, thereby reducing production costs.

[0005] According to an embodiment of the present invention, a trench power device is provided, comprising a semiconductor layer, a cell trench structure, and a termination trench structure. The semiconductor layer comprises a substrate layer, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked sequentially, wherein the substrate layer, the first epitaxial layer, and the third epitaxial layer have the same doping type, and the second epitaxial layer has an opposite doping type. The cell trench structure extends from the surface of the third epitaxial layer into the semiconductor layer to the second epitaxial layer. The cell trench structure includes a cell trench, a field electrode located in the upper half of the cell trench, a gate electrode located in the lower half of the cell trench, and a cell trench dielectric layer that isolates the cell trench, the field electrode, and the gate electrode. The termination trench structure extends from the surface of the third epitaxial layer into the semiconductor layer to the second epitaxial layer. The termination trench structure includes a termination trench, a termination electrode located in the termination trench, and a termination trench dielectric layer that isolates the termination electrode from the sidewalls of the termination trench.

[0006] According to one embodiment of this application, a method for fabricating a trench power device is provided, comprising: forming a semiconductor layer, including forming a substrate layer, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the substrate layer and the first and third epitaxial layers have the same doping type, and the second epitaxial layer has the opposite doping type; performing photolithography and etching processes on the second and third epitaxial layers to form cell trenches and terminal trenches in the second and third epitaxial layers; forming oxide layers on the sidewalls and bottoms of the cell trenches and terminal trenches, and depositing electrode material in the cell trenches and terminal trenches after the oxide layers are formed; and etching the terminal trenches to remove the electrode material and the terminal trenches. The bottom oxide layer forms a terminal dielectric layer on the sidewalls of the terminal trench; electrode material is deposited in the terminal trench to form a terminal electrode; the cell trench is etched to remove part of the electrode material in the cell trench, leaving part of the electrode material at the bottom of the cell trench to form a gate electrode; an oxide layer is deposited in the cell trench at the top of the gate electrode and then etched back, leaving an oxide layer of a certain thickness at the top of the gate electrode; an oxide layer is grown on the sidewalls and bottom of the cell trench at the top of the gate electrode to form a field oxide layer; electrode material is deposited in the cell trench formed after the oxide layer is grown to form a field electrode; and a first drain region and a second drain region are formed in the surface layer of the third epitaxial layer on both sides of the cell trench structure. Attached Figure Description

[0007] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0008] Figure 1 This is a schematic diagram of the existing SGT device 100;

[0009] Figure 2 This is a cross-sectional schematic diagram of a trench power device 200 according to an embodiment of this application;

[0010] Figure 3 This is a schematic diagram of the steps in a method 300 for manufacturing a trench power device 200 according to an embodiment of this application;

[0011] Figure 4A-4I This is a cross-sectional schematic diagram of a trench power device 200 after some steps of the manufacturing method 300 according to an embodiment of this application are completed;

[0012] Figure 5 This is a cross-sectional schematic diagram of a trench power device 500 according to an embodiment of this application;

[0013] Figure 6 This is a cross-sectional schematic diagram of a trench power device 600 according to an embodiment of this application. Detailed Implementation

[0014] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0015] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0016] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.

[0017] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0018] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0019] Figure 2 This is a schematic cross-sectional view of a trench power device 200 according to an embodiment of this application. Figure 2 As shown, the trench power device 200 includes a semiconductor layer 220, a cell trench structure 204 located in the semiconductor layer 220, and a terminal trench structure 214.

[0020] exist Figure 2 In this embodiment, the semiconductor layer 220 includes a substrate layer 201, a first epitaxial layer 202, a second epitaxial layer 203, and a third epitaxial layer 205 stacked sequentially. The substrate layer 201 and the first epitaxial layer 202 and third epitaxial layer 205 have the same doping type. The second epitaxial layer 203 has the opposite doping type to the substrate layer 201. The doping concentration of the substrate layer 201 is greater than the doping concentration of the first epitaxial layer 202 and the third epitaxial layer 205. In some embodiments, the substrate layer 201, the first epitaxial layer 202, and the third epitaxial layer 205 are N-type doped, while the second epitaxial layer 203 is P-type doped. In some embodiments, the substrate layer 201, the first epitaxial layer 202, and the third epitaxial layer 205 are P-type doped, while the second epitaxial layer 203 is N-type doped.

[0021] exist Figure 2In this embodiment, the cell trench structure 204 extends from the surface of the third epitaxial layer 205 into the interior of the semiconductor layer 220 into the second epitaxial layer 203. The cell trench structure 204 includes a cell trench T1, a field electrode 208 located in the upper half 204-1 of the cell trench T1, a gate electrode 207 located in the lower half 204-2 of the cell trench T1, and cell trench dielectric layers 209 and 210 that respectively isolate the cell trench T1, the field electrode 208, and the gate electrode 207. The cell trench dielectric layer 209 is a field oxide layer that encapsulates the field electrode 208. The cell trench dielectric layer 210 is a gate oxide layer that encapsulates the gate electrode 207. It should be understood that the gate oxide layer 210 and the field oxide layer 209 are interconnected to form a single dielectric layer, thereby isolating the gate electrode 207 and the field electrode 208 from the inner wall of the cell trench T1. Furthermore, a field oxide layer 209 fills the space between the gate electrode 207 and the field electrode 208, separating them. The field oxide layer 209 and the gate oxide layer 210 can be the same material or different materials, and may differ in thickness, such as... Figure 2 As shown.

[0022] exist Figure 2 In this embodiment, the width of the gate electrode 207 is greater than the width of the field electrode 208. In other embodiments, the widths of the gate electrode 207 and the field electrode 208 can be set according to the application requirements.

[0023] exist Figure 2 In this embodiment, the gate electrode 207 is located in the lower half 204-2 of the cell trench T1, extending from the third epitaxial layer 205 to the second epitaxial layer 203, and is isolated from the second epitaxial layer 203 and the third epitaxial layer 205 by the gate oxide layer 210. The gate electrode 207 comprises conductive materials such as polysilicon or metal. The field electrode 208 is located in the upper half 204-1 of the cell trench T1, within the third epitaxial layer 205, and is isolated from the third epitaxial layer 205 by the field oxide layer 209. The field electrode 208 comprises conductive materials such as polysilicon or metal. Depending on the application requirements, the gate electrode 207 and the field electrode 208 can be made of the same material or different materials.

[0024] exist Figure 2 In this embodiment, the termination trench structure 214 extends from the surface of the third epitaxial layer 205 into the semiconductor layer 220 into the second epitaxial layer 203. The termination trench structure 214 includes a termination trench T2, a termination electrode 216 located in the termination trench T2, and a termination trench dielectric layer 215 that isolates the termination electrode 216 and the sidewalls of the termination trench T2. The termination trench dielectric layer 215 may be made of the same material as the gate oxide layer or the field oxide layer, or it may be made of a different material than the gate oxide layer or the field oxide layer.

[0025] exist Figure 2In this embodiment, the semiconductor layer 220 further includes a first drain region 211 and a second drain region 212. For example... Figure 2 As shown, the first drain region 211 is located on the upper surface of the third epitaxial layer 205 and is adjacent to one side of the cell trench structure 204. The second drain region 212 is located on the upper surface of the third epitaxial layer 205 and is adjacent to the other side of the cell trench structure 204. The first drain region 211 and the second drain region 212 have the same doping type as the third epitaxial layer 205, for example, both are N-type doped. Furthermore, the doping concentration of the first drain region 211 and the second drain region 212 is higher than the doping concentration of the third epitaxial layer 205.

[0026] exist Figure 2 In this embodiment, the first drain region 211 is electrically connected to the first drain electrode D1, and the second drain region 212 is electrically connected to the second drain electrode D2. The field electrode 208 may be electrically connected to the first drain electrode D1 together with the first drain region 211, or it may be electrically connected to the second drain electrode D2 together with the second drain region 212. In some embodiments, the field electrode 208 is electrically connected to an independent potential, such as ground potential.

[0027] exist Figure 2 In this embodiment, the field electrode 208 is discontinuous on the front side of the device (the surface of the third epitaxial layer 205), with a break in the middle, so that the gate electrode 207 extends upward to expose the front side of the device so as to be electrically connected to the device gate G. The gate electrode 207 is wrapped by the gate oxide layer 210.

[0028] Depend on Figure 2 As shown, in the trench power device 200 of this embodiment, the gate electrode 207, the first drain region 211, and the second drain region 212 are all located on the front side of the device, so that the gate G, the first drain D1, and the second drain D2 can be directly led out through the metal layer on the front side of the device. When the trench power device 200 is turned on, by controlling the voltage of the gate G, the first drain D1, and the second drain D2, current can flow from the first drain D1 to the second drain D2, or current can flow from the second drain D2 to the first drain D1.

[0029] Figure 3 This is a schematic diagram of the steps of a method 300 for fabricating a trench power device 200 according to an embodiment of this application. The fabrication method 300 includes steps 301-310. Figure 4A-4I This is a cross-sectional schematic diagram of a trench power device 200 after some steps of the manufacturing method 300 according to an embodiment of this application are completed. The following is in conjunction with... Figure 3 and Figure 4A-4I Let me explain the production method in detail. (300)

[0030] In step 301, a semiconductor layer 220 is formed, including a substrate layer 201, a first epitaxial layer 202, a second epitaxial layer 203, and a third epitaxial layer 205. The substrate layer 201 and the first epitaxial layer 202 and third epitaxial layer 205 have the same doping type. The second epitaxial layer has the opposite doping type to the substrate layer 201. The doping concentration of the substrate layer 201 is greater than the doping concentration of the first epitaxial layer 202 and the third epitaxial layer 205. In one embodiment, the substrate layer 201, the first epitaxial layer 202, and the third epitaxial layer 205 are N-type doped, while the second epitaxial layer 203 is P-type doped.

[0031] In step 302, photolithography and etching processes are performed on the second epitaxial layer 203 and the third epitaxial layer 205 to form cell trenches T1 and terminal trenches T2 in the second epitaxial layer 203 and the third epitaxial layer 205, such as... Figure 4A As shown. Specifically, in step 302, photoresist 601 is first applied to the surface of the third epitaxial layer 205, and a specific pattern is formed on the photoresist using a photolithography process, exposing the portions that need to be etched into trenches. Subsequently, an etching process is used to etch away the portions of the third epitaxial layer 205 and the second epitaxial layer 203 that need to form trenches, until a certain depth is reached, forming cell trench T1 and terminal trench T2.

[0032] In step 303, an oxide layer 602 is formed on the sidewalls and bottom of trenches T1 and T2, and electrode material 604 is deposited in trenches T1 and T2 after the oxide layer 602 is formed, such as... Figure 4B As shown. The electrode material 604 can be a conductive material such as polycrystalline silicon or metal. It should be understood that... Figure 4B The cross-sectional view shown is only a schematic diagram of part of the device structure and does not represent the entire device. In some embodiments, chemical mechanical polishing (CMP) can be performed after depositing electrode material 604 to form a smooth surface.

[0033] In step 304, the terminal trench T2 is etched to remove the electrode material 604 and the oxide layer at the bottom of the terminal trench T2, forming a terminal dielectric layer 215, such as... Figure 4C As shown. While etching the terminal trench T2, the electrode material 604 in the cell trench T1 is retained.

[0034] In step 305, electrode material 604 is deposited in the terminal trench T2 to form a terminal electrode 216, as shown below. Figure 4D As shown.

[0035] In step 306, the cell trench T1 is etched to remove a portion of the electrode material 604 within the cell trench T1, retaining a portion of the bottom electrode material 604 to form the gate electrode 207. Figure 4E As shown. In Figure 4E In the embodiment shown, after the electrode material 604 is etched back, the top of the gate electrode 207 is higher than the top of the second epitaxial layer 203, while the bottom is located in the second epitaxial layer 203.

[0036] In step 307, an oxide layer is deposited in the trench at the top of the gate electrode 207 and then etched back, while retaining an oxide layer of a certain thickness at the top of the gate electrode 207, such as... Figure 4F As shown, the oxide layer on top of the gate electrode 207 forms part of the field oxide layer 209. In some embodiments, after depositing the oxide layer, a CMP process is performed to smooth the oxide layer before etching back.

[0037] In step 308, an oxide layer is grown on the sidewalls and bottom of the trench at the top of the gate electrode 207 to form a field oxide layer 209, such as... Figure 4G As shown.

[0038] In step 309, electrode material is deposited in the cell trench T1 formed after the growth of the oxide layer to form the field electrode 208, such as... Figure 4H As shown. Electrode materials can include conductive materials such as polycrystalline silicon or metals.

[0039] In step 310, a first drain region 211 and a second drain region 212 are formed in the surface layer of the third epitaxial layer 205 on both sides of the cell trench structure 204 and the terminal trench structure 214, respectively. Figure 4I As shown.

[0040] It should be understood that the order of some steps in fabrication method 300 is interchangeable; for example, the field electrode can be formed after the drain region is formed. Furthermore, after some steps are completed, CMP processing or other processes well-known to those skilled in the art will be performed. After completing the above steps, some subsequent processes are required on the front side of the device to form dielectric layers, metal layers, etc., to connect the various regions of the device to the corresponding electrodes. Since these subsequent processes are well-known to those skilled in the art, they will not be elaborated upon here.

[0041] The trench power device and its fabrication method provided in this application embodiment can use an N-type substrate, making it compatible with N-type furnace tubes, thereby reducing production costs. Compared to the prior art, which forms a terminal region in the third epitaxial layer through ion implantation, in this application embodiment, a terminal trench T2 is formed simultaneously with the formation of the cell trench T1, thereby setting a terminal trench structure 214 and connecting the potential of the second epitaxial layer 203. This reduces the ion implantation process, thus saving production costs. Furthermore, compared to the prior art, which forms the P-type and N-type regions of the device through ion implantation, the device structure in this application embodiment allows the P-type and N-type regions to be formed into stacked P-type and N-type epitaxial layers through epitaxial growth. This improves the consistency of the device threshold Vth while simplifying the process and reducing production costs.

[0042] Figure 5 This is a schematic cross-sectional view of a trench power device 500 according to an embodiment of this application. Figure 2 Compared to the trench power device 200 of this embodiment, the gate electrode 507 has a connected first portion 507-1 and a second portion 507-2. The width of the first portion 507-1 of the gate electrode 507 is greater than the width of the second portion 507-2 of the gate electrode 507. In other embodiments, the gate electrode may also have more portions of different widths. To reduce the current channel length, the width of the portion of the gate electrode located in the second epitaxial layer 203 can be relatively reduced, such that the maximum width of the portion of the gate electrode located in the third epitaxial layer 205 is greater than the minimum width of the portion of the gate electrode located in the second epitaxial layer 203.

[0043] In one embodiment, the method for fabricating the trench power device 500 is similar to... Figure 3 The fabrication method 300 in this embodiment is similar, except that when fabricating the trench power device 500, in step 302, etching is required to form a barrier layer followed by further etching to create cell trenches with different widths at the top and bottom. Furthermore, in step 306, when etching back the polysilicon material to form the gate electrode, the top of the gate electrode is kept within the third epitaxial layer 205.

[0044] Figure 6 This is a schematic cross-sectional view of a trench power device 600 according to an embodiment of this application. Figure 2 Compared to the trench power device 200 in the embodiment, in Figure 6 In this embodiment, the cell trench T1 further extends into the first epitaxial layer 202, meaning the bottom of the cell trench T1 is located in the first epitaxial layer 202. Furthermore... Figure 6In this embodiment, the gate electrode 607 also has a stepped shape, meaning that the gate electrode 607 includes at least two widths. The maximum width of the portion of the gate electrode 607 located in the third epitaxial layer 205 is greater than the minimum width of the portion of the gate electrode 607 located in the first epitaxial layer. The first epitaxial layer 202 covers the bottom of the cell trench T1, reducing the current channel length and thus reducing the channel resistance.

[0045] In other embodiments, the gate electrode may also have a uniform width when the cell trench T1 extends from the surface of the third epitaxial layer 205 into the first epitaxial layer 202. The top of the gate electrode is located in the third epitaxial layer 205, and the bottom is located in the first epitaxial layer 202.

[0046] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A trench power device, comprising: A semiconductor layer includes a substrate layer, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked sequentially, wherein the substrate layer and the first epitaxial layer and the third epitaxial layer have the same doping type, and the substrate layer and the second epitaxial layer have the opposite doping type. The cell trench structure extends from the surface of the third epitaxial layer into the interior of the semiconductor layer to the second epitaxial layer. The cell trench structure includes a cell trench, a field electrode located in the upper half of the cell trench, a gate electrode located in the lower half of the cell trench, and a cell trench dielectric layer that isolates the cell trench, the field electrode and the gate electrode respectively. as well as A termination trench structure extends from the surface of the third epitaxial layer into the interior of the semiconductor layer into the second epitaxial layer. The termination trench structure includes a termination trench, a termination electrode located in the termination trench, and a termination trench dielectric layer that isolates the termination electrode from the sidewalls of the termination trench.

2. The trench power device as described in claim 1, wherein: The substrate layer, the first epitaxial layer, and the third epitaxial layer are N-type doped; and The second epitaxial layer has P-type doping.

3. The trench power device as described in claim 1, wherein, The cell trench dielectric layer includes: The gate oxide layer encapsulates the gate electrode; and The field oxygen layer encapsulates the field electrode.

4. The trench power device as described in claim 1, wherein, The gate electrode includes at least two widths, with the maximum width of the portion of the gate electrode located in the third epitaxial layer being greater than the minimum width of the portion of the gate electrode located in the second epitaxial layer.

5. The trench power device as described in claim 1, wherein, The cell trench structure extends further into the first epitaxial layer, and the gate electrode extends from the third epitaxial layer into the first epitaxial layer.

6. The trench power device as described in claim 5, wherein, The gate electrode includes at least two widths, with the maximum width of the portion of the gate electrode located in the third epitaxial layer being greater than the minimum width of the portion of the gate electrode located in the first epitaxial layer.

7. The trench power device as claimed in claim 1, wherein, The semiconductor layer further includes: The first leak region is located on the upper surface of the third epitaxial layer and is adjacent to one side of the cell trench; and The second leak region is located on the upper surface of the third epitaxial layer and is adjacent to the other side of the cell trench. The first and second drain regions have the same doping type as the third epitaxial layer, and the doping concentration of the first and second drain regions is higher than that of the third epitaxial layer.

8. The trench power device as described in claim 7, wherein, The field electrode is electrically connected to the first drain region or the second drain region, or the field electrode is connected to other independent potentials.

9. A method for fabricating a trench power device, comprising: Forming a semiconductor layer includes forming a substrate layer, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the substrate layer and the first and third epitaxial layers have the same doping type, and the second epitaxial layer has the opposite doping type; Photolithography and etching processes are performed on the second and third epitaxial layers to form cell trenches and terminal trenches in the second and third epitaxial layers; An oxide layer is formed on the sidewalls and bottom of the cell trench and the terminal trench, and electrode material is deposited in the cell trench and the terminal trench after the oxide layer is formed. The terminal trench is etched to remove the electrode material and the oxide layer at the bottom of the terminal trench, so that the oxide layer on the sidewall of the terminal trench forms the terminal dielectric layer. Electrode material is deposited in the terminal trench to form the terminal electrode; The cell trenches are etched to remove some of the electrode material in the cell trenches, while retaining some of the electrode material at the bottom of the cell trenches to form the gate electrode. An oxide layer is deposited in the cell trench at the top of the gate electrode and then etched back, while retaining an oxide layer of a certain thickness at the top of the gate electrode. An oxide layer is grown on the sidewalls and bottom of the cell trench at the top of the gate electrode to form a field oxide layer; Electrode material is deposited in the cell trenches formed after the growth of the oxide layer to form a field electrode; as well as The first and second leak regions are formed in the surface layer of the third epitaxial layer on both sides of the cell trench structure.

10. The manufacturing method as described in claim 9, wherein: The process of performing photolithography and etching on the second and third epitaxial layers to form cell trenches and termination trenches in the second and third epitaxial layers includes: simultaneously performing photolithography and etching on the second and third epitaxial layers, and further performing photolithography and etching on the first epitaxial layer to form cell trenches in the first, second, and third epitaxial layers, and to form termination trenches in the second and third epitaxial layers.

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