Semiconductor device and method of manufacturing the same

Abstract

This application provides a semiconductor device and its fabrication method. The device includes a drain / collector metal layer, a substrate layer, a voltage withstand layer, a body region, a source / emitter contact region, a source / body contact region, a gate trench, a base contact region, a base-emitter region, a base metal layer, and a source / emitter metal layer. The voltage withstand layer contains alternating N-pillar and P-pillar regions to achieve charge balance. Source / emitter and source / body contact regions are spaced apart within the body region. The gate trench penetrates the body region and extends to the voltage withstand layer. The base contact region is located on the P-pillar region and contains the base-emitter region. The base metal layer is located within the gate trench and insulated from the gate, connecting to the base contact region. The source / emitter metal layer connects to the source / emitter contact region, the source / body contact region, and the base-emitter region. By independently biasing the gate and base, the device can switch between pure MOS mode and bipolar conduction mode, achieving both low switching losses and low conduction losses, and integrating a diode freewheeling function.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, specifically relating to a semiconductor device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, is gradually replacing traditional silicon power devices and is widely used in high-voltage, high-power power conversion systems in fields such as new energy vehicles, photovoltaic energy storage, and smart grids, thanks to its advantages such as wide bandgap, high critical breakdown electric field, and high thermal conductivity.

[0003] However, existing SiC power devices still have performance bottlenecks in high-voltage and high-frequency applications: the on-resistance of trench SiC MOSFETs increases sharply with the increase of withstand voltage; the P-pillar region of superjunction SiC MOSFETs does not participate in conduction when turned on, and the drift region is not fully utilized; SiC IGBTs have large turn-off tail current and high switching losses, and lack a body diode, requiring an external fast recovery diode. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its fabrication method, which can flexibly switch between unipolar conduction mode and bipolar conduction mode to balance high frequency low switching loss and high current low conduction loss.

[0005] This application provides a semiconductor device comprising: a drain / collector metal layer; a substrate layer of a first conductivity type disposed on the drain / collector metal layer; a withstand layer disposed on the substrate layer, the withstand layer including N-pillar regions and P-pillar regions alternately arranged in a direction parallel to the upper surface of the substrate layer, the N-pillar regions and the P-pillar regions having a first conductivity type and a second conductivity type respectively, the N-pillar regions and the P-pillar regions being configured to mutually deplete laterally when the semiconductor device is subjected to a reverse voltage to achieve charge balance; a body region disposed above the withstand layer and having a second conductivity type; a source / emitter contact region disposed within the body region and having a first conductivity type; a source / body contact region disposed within the body region and having a second conductivity type, and spaced apart from the source / emitter contact region; and at least one gate trench, from the device The upper surface extends downward, penetrating the body region and extending to the withstand voltage layer. The inner wall of the gate trench is covered with a gate dielectric layer, and the gate trench is filled with a gate, which is configured to receive a gate bias voltage. A base contact region has a second conductivity type and is disposed on and electrically connected to the P-pillar region. A base emitter region has a first conductivity type and is disposed within the base contact region. A base metal layer is disposed within the gate trench and is insulated from the gate within the same gate trench, and is electrically connected to the base contact region. A source / emitter metal layer is disposed on the body region and is electrically connected to the source / emitter contact region, the source / body contact region, and the base / emitter region, and the source / emitter metal layer covers at least a portion of the gate trench.

[0006] In one exemplary embodiment of this application, the semiconductor device includes two symmetrically arranged gate trenches, each of which contains a gate. The base metal layer is disposed in one of the gate trenches and is insulated from the gate in the same gate trench.

[0007] In one exemplary embodiment of this application, the semiconductor device includes two symmetrically arranged gate trenches, each of which contains a gate and a base metal layer, and the base metal layer is insulated from the gate in the same gate trench.

[0008] In one exemplary embodiment of this application, the widths of the N-pillar region and the P-pillar region are equal, and they satisfy charge balance.

[0009] In one exemplary embodiment of this application, the withstand layer includes: a first region comprising alternating N-pillar regions and P-pillar regions; and a second region comprising a drift region of a second conductivity type, the second region being located between the first region and the substrate layer.

[0010] In one exemplary embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0011] In one exemplary embodiment of this application, a resistive connection structure or a capacitive connection structure is provided between the gate and the base metal layer, so that the bias voltage on the base metal layer varies with the bias voltage of the gate.

[0012] In one exemplary embodiment of this application, the source / body contact region, the body region, the N-pillar region, and the substrate layer form a body diode, which is configured to provide a freewheeling path in the third quadrant operating state of the semiconductor device.

[0013] In one exemplary embodiment of this application, the semiconductor material of the semiconductor device is silicon carbide or silicon.

[0014] A second aspect of this application provides a method for fabricating a semiconductor device according to any one of the preceding claims, comprising the following steps: providing a substrate layer of a first conductivity type; forming a voltage-resistant layer on the substrate layer, the voltage-resistant layer comprising alternating N-pillar regions of the first conductivity type and P-pillar regions of the second conductivity type arranged along a direction parallel to the upper surface of the substrate layer, the N-pillar regions and P-pillar regions having equal widths and satisfying a charge balance condition; forming a body region of the second conductivity type on the voltage-resistant layer; forming a base contact region of the second conductivity type on the P-pillar regions; forming a source / body contact region of the second conductivity type within the body region; forming a source / emitter contact region of the first conductivity type within the body region, and simultaneously forming a base / emitter region of the first conductivity type within the base contact region; forming at least one gate trench. The gate trench extends downward from the upper surface of the device, through the body region, and to the withstand voltage layer; a gate dielectric layer is formed on the inner wall surface of the gate trench; a portion of the gate dielectric layer located in the base contact region is removed; a gate is filled in the gate trench, and a base metal layer is formed in at least one of the gate trenches, the base metal layer being electrically connected to the base contact region through the removed gate dielectric layer region; an interlayer dielectric layer is deposited to cover the gate and the base metal layer, such that the base metal layer is insulated from the gate in the same gate trench; a source / emitter metal layer is formed, the source / emitter metal layer being electrically connected to the source / emitter contact region, the source / body contact region, and the base / emitter region; a drain / collector metal layer is formed on the side of the substrate layer away from the withstand voltage layer.

[0015] The semiconductor device and its fabrication method described in this application have at least the following beneficial effects:

[0016] In this application, the breakdown voltage layer of the semiconductor device employs alternating N-pillar and P-pillar regions arranged parallel to the upper surface of the substrate. When the device is subjected to reverse voltage, these regions undergo lateral depletion to achieve charge balance, resulting in a rectangular electric field distribution and significantly improved breakdown voltage. Under the same breakdown voltage rating, the doping concentration of the N-pillar regions can be further increased, thereby effectively reducing on-resistance. The semiconductor device has independent gate and base metal layers. The gate is configured to receive the gate bias voltage, and the base metal layer is located within the gate trench and insulated from the gate. Independent bias control allows for zero or negative bias application to the base metal layer under high-frequency conditions. The base emitter region located within the base contact region does not inject electrons into the base contact region, enabling the device to operate in pure MOS mode with fast switching speed and low switching losses. Under high-current or low-frequency conditions, the base metal layer... When a forward bias is applied to the base layer, electrons are injected from the base-emitter region into the base contact region. The bipolar conductive path formed by the base contact region, the base-emitter region, and the voltage-shielding layer is activated, and the P-pillar region participates in conduction. The current path is expanded from a single N-pillar region to a collaborative conduction of the N-pillar and P-pillar regions, further reducing the on-state voltage drop. This achieves a balance between high-frequency low switching losses and high-current low conduction losses. The source / body contact region, body region, N-pillar region, and substrate layer constitute a parasitic body diode, providing a freewheeling path in the third quadrant operating state. No external fast recovery diode is required, simplifying system complexity. The base contact region is located on the P-pillar region and electrically connected to it. In the blocking state, the P-pillar region guides the electric field peak at the bottom corner of the gate trench to the PN junction between itself and the N-pillar region, effectively shielding the gate oxide electric field and improving the long-term reliability of the device.

[0017] In the fabrication method, after forming a gate dielectric layer on the inner wall of the gate trench, a portion of the gate dielectric layer above the base contact region is removed. Then, the gate is filled and a base metal layer is formed. This allows the base metal layer to be directly electrically connected to the base contact region through the removed gate dielectric layer region, ensuring low-resistance ohmic contact, improving the transmission efficiency and reliability of the base control signal. Furthermore, by depositing an interlayer dielectric layer to cover the gate and base metal layers, effective electrical isolation between them is achieved, ensuring the normal implementation of the independent bias function. The source / emitter contact region and the base-emitter region are formed simultaneously in the same implantation step, reducing the number of photolithography masks and lowering the process complexity and manufacturing cost.

[0018] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 A cross-sectional structural schematic diagram of a semiconductor device provided in Embodiment 1, Embodiment 4, or Embodiment 5 of this application is shown.

[0022] Figure 2 A schematic cross-sectional view of the semiconductor device of this application in the blocking state is shown.

[0023] Figure 3 A schematic cross-sectional view of the semiconductor device of this application in a single-stage conduction state is shown.

[0024] Figure 4 A cross-sectional structural schematic diagram of the semiconductor device of this application in the dual-stage conduction state is shown.

[0025] Figure 5 A cross-sectional structural schematic diagram of the semiconductor device of this application in the third quadrant freewheeling operating state is shown.

[0026] Figure 6 A schematic diagram of the fabrication process of the semiconductor device of this application is shown.

[0027] Figures 7a to 7l A schematic diagram of the fabrication process of the semiconductor device of this application is shown.

[0028] Figure 8 This illustration shows a cross-sectional structure of a base metal layer provided in a gate trench according to Embodiment 2 of this application.

[0029] Figure 9 The diagram shows a cross-sectional structure of the pressure-resistant layer provided in Embodiment 3 of this application, which uses a first region and a second region.

[0030] Explanation of reference numerals in the attached figures: 100. Drain / collector metal layer; 101. Substrate layer; 102. Withstand voltage layer; 102a. N-pillar region; 102b. P-pillar region; 102c. Second region; 103. Body region; 104. Source / emitter contact region; 105. Source / body contact region; 106. Gate trench; 107. Gate dielectric layer; 108. Gate; 109. Base contact region; 110. Base-emitter region; 111. Base metal layer; 112. Interlayer dielectric layer; 113. Source / emitter metal layer. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0035] The semiconductor material of the semiconductor device in this application can be silicon carbide (SiC) or silicon (Si). The following embodiments use silicon carbide (SiC) as an example for illustration.

[0036] Example 1 See Figure 1 As shown, the semiconductor device in this application is a power device composed of a trench superjunction MOS structure and an independently base-controlled bipolar conductive structure.

[0037] See Figure 1 As shown, the semiconductor device comprises, from bottom to top, a drain / collector metal layer 100, a substrate layer 101 of a first conductivity type, a voltage-resistant layer 102, a body region 103 of a second conductivity type, and a source / emitter metal layer 113.

[0038] The first conductivity type is N-type, and the second conductivity type is P-type. The following description will use N-type as the first conductivity type and P-type as the second conductivity type.

[0039] It is understood that by reversing the conductivity type of each layer, this application is also applicable to complementary devices where the first conductivity type is P-type and the second conductivity type is N-type.

[0040] In some embodiments, see Figure 1 As shown, the drain / collector metal layer 100 is located at the bottom of the device and is used to lead out the drain / collector. A substrate layer 101 is disposed on the drain / collector metal layer 100, and it can be an N-type heavily doped (N+) silicon carbide layer with a doping concentration of 1e⁻¹. 18 cm -3 ~1e 20 cm -3 The thickness can range from 100 μm to 300 μm. For example, its doping concentration is 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The thicknesses are 100μm, 200μm, and 300μm.

[0041] Understandably, the substrate 101 serves as both a mechanical support for the device and a means to form the back ohmic contact.

[0042] In some embodiments, see Figure 1 and Figure 2 As shown, the withstand voltage layer 102 is disposed on the substrate layer 101. The withstand voltage layer 102 may include N-pillar regions 102a and P-pillar regions 102b arranged alternately along a direction parallel to the upper surface of the substrate layer 101. The N-pillar regions 102a have N-type conductivity and the P-pillar regions 102b have P-type conductivity.

[0043] It should be noted that the N-pillar region 102a and the P-pillar region 102b have equal widths, and their doping concentrations and widths are configured to satisfy the charge balance condition; that is, the product of the doping concentration and width of the N-pillar region 102a is approximately equal to the product of the doping concentration and width of the P-pillar region 102b. When the device is subjected to a reverse voltage (i.e., a high voltage is applied to the drain / collector, and the source / emitter is grounded), the N-pillar region 102a and the P-pillar region 102b undergo lateral mutual depletion, resulting in the complete depletion of the entire breakdown layer 102. The electric field exhibits a uniform rectangular distribution along the longitudinal direction, significantly increasing the breakdown voltage. Figure 2 As shown. Meanwhile, due to the charge balance effect, the doping concentration of the N-pillar region 102a can be further increased under the same voltage rating, thereby effectively reducing the resistance when the device is turned on.

[0044] Furthermore, the epitaxial thickness of the withstand layer 102 can be 5 μm to 100 μm, and the doping concentration of the N-pillar region 102a and the P-pillar region 102b can be 1e. 16 cm -3 ~1e 18 cm -3 For example, the doping concentration of the withstand voltage layer 102 can be 1e. 16 cm -3 1e 17 cm -3 or 1e 18 cm -3 The epitaxial thicknesses are 5μm, 50μm, and 100μm.

[0045] In some embodiments, the body region 103 is disposed above the withstand voltage layer 102, and it can be a p-type silicon carbide layer (Pwell). The body region 103 can be formed by ion implantation, and its doping concentration can be 1e. 17 cm -3 ~1e 19 cm -3 The junction depth can range from 1 μm to 4 μm. For example, the doping concentration of the bulk region 103 can be 1e. 17 cm -3 1e 18 cm -3 or 1e 19 cm -3 The junction depth can be 1μm, 2μm, or 4μm.

[0046] In some embodiments, see Figure 1 or Figure 2 As shown, a source / emitter contact region 104 and a source / body contact region 105 are provided within the body region 103. The source / emitter contact region 104 can be an N-type heavily doped (N+) region, located within the body region 103, to provide an electron source for the MOS structure. The source / body contact region 105 is a P-type heavily doped (P+) region, also located within the body region 103, and spaced apart from the source / emitter contact region 104. The source / body contact region 105 provides a low-resistance ohmic contact for the body region 103, fixes the potential of the body region 103, and discharges holes during turn-off or freewheeling to prevent parasitic latch-up effects.

[0047] It should be noted that the doping concentration of both the source / emitter contact region 104 and the source / bulk contact region 105 can be 1e. 18 cm -3 ~1e 20 cm -3 The junction depth can range from 0.5 μm to 2 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm-3 or 1e 20 cm -3 The junction depth can be 0.5μm, 1μm, or 2μm.

[0048] In some embodiments, at least one gate trench 106 is formed on the upper surface of the semiconductor device.

[0049] For example, this embodiment uses two symmetrically arranged gate trenches 106 as an example. The gate trenches 106 extend downwards from the upper surface of the device, penetrate the body region 103, and extend into the voltage withstand layer 102. The depth of the gate trenches 106 can be 2μm to 5μm, and the width can be 1μm to 4μm. For example, the depth of the gate trenches 106 is 2μm, 3μm, or 5μm, and the width is 1μm, 2μm, or 4μm. The inner wall of the gate trenches 106 is covered with a gate dielectric layer 107, which can be a silicon dioxide (SiO2) layer with a thickness of 30nm to 70nm, for example, 30nm, 50nm, or 70nm. The gate trenches 106 are filled with a gate 108, which can be polysilicon, and the gate 108 is configured to receive a bias voltage.

[0050] In some embodiments, see Figure 1 or Figure 2 As shown, a base contact region 109 is provided on the P-pillar region 102b. The base contact region 109 is a heavily P-type doped (P+) region and is electrically connected to the P-pillar region 102b. The doping concentration of the base contact region 109 can be 1e 18 cm -3 ~1e 20 cm -3 The junction depth can range from 1 μm to 4 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The junction depth can be 1μm, 2μm, or 4μm. The top surface of the base contact region 109 is basically flush with the top surface of the body region 103, or slightly higher than the top surface of the body region 103, to facilitate subsequent metallization processes.

[0051] In some embodiments, see Figure 1 or Figure 2 As shown, a base-emitter region 110 is provided within the base contact region 109. The base-emitter region 110 is an N-type heavily doped (N+) region located within the base contact region 109. The base-emitter region 110 and the source / emitter contact region 104 can be formed simultaneously in the same ion implantation step to reduce the number of photolithography masks and lower process complexity. The doping concentration of the base-emitter region 110 can be 1e18 cm -3 ~1e 20 cm -3 The junction depth can range from 0.5 μm to 2 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The junction depth can be 0.5μm, 1μm, or 2μm.

[0052] In some embodiments, a base metal layer 111 is further provided within at least one gate trench 106.

[0053] For example, see Figure 1 or Figure 2 As shown, a base metal layer 111 is provided in each of the two gate trenches 106. The base metal layer 111 can be directly electrically connected to the base contact region 109 through the area where the gate dielectric layer 107 has been removed, forming a low-resistance ohmic contact. The base metal layer 111 and the gate 108 in the same gate trench 106 are electrically isolated by an interlayer dielectric layer 112. The interlayer dielectric layer 112 can be BPSG (borophosphosilicate glass) or USG (undoped silicate glass). The base metal layer 111 can be polysilicon or metal. The gate 108 is led out to the gate 108 metal electrode region through a three-dimensional layout, and the base metal layer 111 is led out to the base metal electrode region through a three-dimensional layout. The two are insulated from each other and can be biased independently.

[0054] In some embodiments, the source / emitter metal layer 113 is disposed on the body region 103, covering at least a portion of the gate trench 106. The source / emitter metal layer 113 forms ohmic contacts with the source / emitter contact region 104, the source / body contact region 105, and the base-emitter region 110, electrically connecting these three together. Thus, the source / emitter contact region 104 (N+) and the source / body contact region 105 (P+) are shorted through the source / emitter metal layer 113, and the base-emitter region 110 (N+) is also electrically connected to the source / emitter metal layer 113, so that the base-emitter region 110 and the source / emitter are at the same potential.

[0055] In some embodiments, each of the two gate trenches 106 contains a gate 108 and a base metal layer 111, forming a symmetrical dual-side base control structure. Thus, when conduction occurs, control signals can be injected simultaneously through both bases, ensuring uniform carrier injection in the P-pillar region 102b, avoiding localized overheating and current congestion, and improving the reliability of high-current operation.

[0056] As described above, the source / body contact region 105 (P+), body region 103 (Pwell), N-pillar region 102a, and substrate layer 101 sequentially constitute a PN-N-N+ structure, which can form a parasitic body diode. The anode of this body diode corresponds to the source / body contact region 105 and body region 103, and the cathode corresponds to the N-pillar region 102a and substrate layer 101. In the third quadrant operating state (i.e., the source potential is higher than the drain potential), the body diode is forward-biased, providing a freewheeling path for the reverse current, eliminating the need for an additional anti-parallel freewheeling diode.

[0057] The following combination Figures 1 to 5 This section explains the working principle of the semiconductor device in this embodiment.

[0058] I. Blocking State (Off State) See Figure 2 As shown, in the blocking state, a zero-bias or negative-bias voltage is applied to the gate 108, and the MOS channel is turned off; a zero-bias or negative-bias voltage (turn-off) is applied to the base metal layer 111, and the base-emitter region 110 does not inject electrons into the base contact region 109, the bipolar conductive path is in a cut-off state, and there is no hole injection. At this time, a high voltage is applied to the drain / collector, and the source / emitter is grounded. The N-pillar region 102a and the P-pillar region 102b in the withstand voltage layer 102 satisfy the charge balance condition, resulting in strong lateral mutual depletion and forming a rectangular electric field uniformly distributed along the longitudinal direction, which significantly increases the breakdown voltage of the device. Meanwhile, the base contact region 109 is located on the P-pillar region 102b, which extends to near the bottom of the gate trench 106. In the blocking state, the P-pillar region 102b guides the electric field peak, originally concentrated at the bottom corner of the gate trench 106, to the PN junction between itself and the N-pillar region 102a, effectively shielding the gate oxide electric field, reducing the risk of gate dielectric breakdown, and improving the long-term reliability of the device. At this time, the device exhibits the blocking characteristics of a pure superjunction MOS with extremely low leakage current.

[0059] II. Unipolar conduction state (high-frequency operating mode) See Figure 3As shown, under high-frequency operating conditions (e.g., above 50kHz) or light-load conditions, the device requires fast switching speed and low switching losses. In this case, a forward bias voltage is applied to the gate 108, causing inversion on the surface of the body region 103 on the sidewall of the gate trench 106, forming a vertical conductive channel. Electrons are injected from the source / emitter contact region 104 through the channel into the N-pillar region 102a, and flow along the N-pillar region 102a to the substrate layer 101, eventually reaching the drain / collector. The base metal layer 111 remains zero-biased or negative-biased (off), and the base-emitter region 110 does not inject electrons into the base contact region 109, thus the bipolar conductive path is not activated. Because the N-pillar region 102a and the P-pillar region 102b in the voltage-resistant layer 102 satisfy the charge balance condition, the doping concentration of the N-pillar region 102a can be higher than that of MOSFETs in related technologies at the same voltage rating, thus significantly reducing the on-resistance. At this point, the P-pillar region 102b is in a high-resistance depletion state, serving only as a withstand voltage support, while the current flows entirely along the N-pillar region 102a. Since there is no bipolar carrier injection and no stored charge, there is no tail current during turn-off, resulting in fast switching speed and low switching losses, making it suitable for high-frequency operation.

[0060] III. Bipolar conduction state (low-frequency high-current operating mode) See Figure 4 As shown, under high current conditions or low switching frequency conditions (e.g., less than 50kHz), the conduction loss of the device dominates, requiring the device to have the lowest possible on-state voltage drop. In this case, the gate 108 continues to be forward biased to keep the MOS channel on; simultaneously, the base metal layer 111 is forward biased. When the voltage between the base metal layer 111 and the source / emitter exceeds the turn-on voltage of the base-emitter region 110, the base-emitter region 110 (N+) begins to inject electrons into the base contact region 109 (P+). The bipolar conductive path formed by the base contact region 109, the base-emitter region 110, and the withstand layer 102 (N-pillar region 102a) is activated. Electrons are injected from the base-emitter region 110 into the base contact region 109 and then diffuse into the N-pillar region 102a. Simultaneously, the P-pillar region 102b also participates in conduction, injecting holes into the N-pillar region 102a, generating a conductivity modulation effect. The current path is expanded from the original single N-pillar region 102a to a combined conduction of N-pillar region 102a and P-pillar region 102b, further reducing the on-state voltage drop. In this embodiment, a base metal layer 111 is provided in both gate trenches 106, which can achieve bilateral symmetrical control, ensure uniform carrier injection in P-pillar region 102b, avoid local current congestion, and improve high-current reliability.

[0061] IV. Flexible Mode Switching Since the gate 108 and the base metal layer 111 are mutually insulated and can be independently biased, the device can flexibly select the operating mode according to the actual operating conditions: when the frequency is light and the load is high, the base bias is turned off and the device operates in unipolar mode to obtain high switching speed and low switching loss; when the frequency is heavy and the load is low, the base bias is turned on and the device operates in bipolar mode to obtain extremely low on-state voltage drop.

[0062] V. Third Quadrant Continued Flow Operating State See Figure 5 As shown, when the device is used in topologies requiring bidirectional conduction, such as bridge circuits, if the source potential is higher than the drain potential, the body diode, composed of the source / body contact region 105, body region 103, N-pillar region 102a, and substrate layer 101, will conduct in the forward direction, providing a freewheeling path for the reverse current. This body diode utilizes the wide bandgap characteristics of SiC material, resulting in an extremely short reverse recovery time and low freewheeling loss. Compared to the solution of requiring an external fast recovery diode in SiC IGBTs, the body diode integrated in this application simplifies system design and reduces system cost and parasitic parameters.

[0063] The following combination Figures 6 to 7 This embodiment describes a method for fabricating a semiconductor device, which includes the following steps: Step S100, see Figure 1 As shown, an N-type heavily doped silicon carbide substrate layer 101 is provided. The doping concentration is 1e. 18 cm -3 ~1e 20 cm -3 The thickness can range from 100 μm to 300 μm. For example, its doping concentration is 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The thicknesses are 100μm, 200μm, and 300μm.

[0064] In step S200, a voltage-resistant layer 102 is formed on the substrate layer 101 by an epitaxial growth and doping process, such as... Figure 7b As shown.

[0065] The withstand voltage layer 102 includes N-pillar regions 102a and P-pillar regions 102b arranged alternately along a direction parallel to the upper surface of the substrate layer 101. The N-pillar regions 102a and P-pillar regions 102b have equal widths and a doping concentration of 1e. 16 cm -3 ~1e 18 cm -3 The epitaxial thickness is 5μm to 100μm. For example, the doping concentration of the withstand voltage layer 102 can be 1e. 16 cm-3 1e 17 cm -3 or 1e 18 cm -3 The epitaxial thicknesses are 5 μm, 50 μm, and 100 μm. Furthermore, the doping concentration and width of the N-pillar region 102a and the P-pillar region 102b satisfy the charge balance condition.

[0066] Step S300: An N-type surface epitaxial layer is formed on the pressure-resistant layer 102 through epitaxial growth, such as... Figure 7c As shown. Its doping concentration is 1e. 16 cm -3 ~1e 18 cm -3 The thickness is 1μm to 5μm; for example, the doping concentration of the N-type surface epitaxial layer can be 1e. 16 cm -3 1e 17 cm -3 or 1e 18 cm -3 The epitaxial thicknesses are 1μm, 3μm, and 5μm.

[0067] Step S400: A P-type body region 103 (Pwell) is formed in the surface epitaxial layer by ion implantation, such as... Figure 7d As shown. Its doping concentration is 1e. 17 cm -3 ~1e 19 cm -3 The junction depth is 1 μm to 4 μm. For example, the doping concentration of the bulk region 103 can be 1e. 17 cm -3 1e 18 cm -3 or 1e 19 cm -3 The junction depth can be 1μm, 2μm, or 4μm.

[0068] In step S500, selective implantation is performed using a photolithography mask to form a heavily p-doped base contact region 109 above the p-pillar region 102b, as shown below. Figure 7e As shown. Its doping concentration is 1e. 18 cm -3 ~1e 20 cm -3 The junction depth can range from 1 μm to 4 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The junction depth can be 1μm, 2μm, or 4μm.

[0069] In step S600, selective implantation is performed using a photolithographic mask to form a heavily p-doped source / body contact region 105 (P+) within the body region 103, as shown below. Figure 7f As shown. Its doping concentration is 1e. 18 cm -3 ~1e 20 cm -3 The junction depth can range from 0.5 μm to 2 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The junction depth can be 0.5μm, 1μm, or 2μm.

[0070] In step S700, selective implantation is performed using a photolithographic mask to form an N-type heavily doped source / emitter contact region 104 within the body region 103, and simultaneously, an N-type heavily doped base / emitter region 110 is formed within the base contact region 109. Figure 7g As shown. This step involves the simultaneous formation of two N+ regions using the same implantation process, both with a doping concentration of 1e. 18 cm -3 ~1e 20 cm -3 The junction depth can range from 0.5 μm to 2 μm. For example, its doping concentration can be 1e. 18 cm -3 1e 19 cm -3 or 1e 20 cm -3 The junction depth can be 0.5μm, 1μm, or 2μm.

[0071] Understandably, high-temperature annealing is performed after implantation to activate impurities and repair lattice damage.

[0072] In step S800, two symmetrically arranged gate trenches 106 are formed by selective etching using a photomask, as shown below. Figure 7h As shown, the gate trench 106 extends downward from the upper surface of the device, penetrates the body region 103, and extends into the voltage withstand layer 102. The trench depth is 2μm to 5μm, and the width is 1μm to 4μm. For example, the depth of the gate trench 106 is 2μm, 3μm, and 5μm, and the width is 1μm, 2μm, and 4μm. After etching, the trench surface is roughened and rounded to reduce the microtrench effect and improve the reliability of the gate dielectric.

[0073] In step S900, a gate dielectric layer 107 is formed on the inner wall surface of the gate trench 106 by thermal oxidation growth, such as... Figure 7iAs shown, the gate dielectric layer 107 is SiO2 with a thickness of 30nm to 70nm, for example, 30nm, 50nm or 70nm.

[0074] In step S1000, selective etching is performed to remove a portion of the gate dielectric layer 107 located above the base contact region 109 to form a contact window.

[0075] Step S1100: Deposit polysilicon, fill the gate trench 106, and form the gate 108 and base metal layer 111 by photolithography and etching, as shown. Figure 7j As shown, gates 108 are formed in both gate trenches 106, and a base metal layer 111 is formed in each gate trench 106. The base metal layer 111 is in direct contact with the base contact region 109 through the area where the gate dielectric layer 107 has been removed, forming an ohmic connection.

[0076] In step S1200, an interlayer dielectric layer 112 (such as BPSG or USG, i.e., SiO2) is deposited to cover the gate 108 and the base metal layer 111, as shown below. Figure 7k As shown, this is to achieve electrical isolation between the base metal layer 111 and the same trench gate 108.

[0077] In step S1300, a front-side metal (such as Al) is deposited, and after photolithography and patterning, a source / emitter metal layer 113 is formed. The source / emitter metal layer 113 forms ohmic contacts with the source / emitter contact region 104, the source / bulk contact region 105, and the base-emitter region 110, and covers at least a portion of the gate trench 106. Simultaneously, the gate 108 and the base metal layer 111 are respectively led out to independent metal electrode regions through three-dimensional layout.

[0078] In step S1400, the wafer is flipped, and the back side of the substrate layer 101 is thinned to 100μm–200μm, for example, 100μm, 150μm, or 200μm. Then, a back-side metal (such as Ti / Ni / Ag) is deposited to form the drain / collector metal layer 100. Figure 7l As shown. The device fabrication is now complete.

[0079] This embodiment integrates the trench MOS structure, the superjunction withstand voltage layer 102, and the bipolar conductive structure with independent base control into one, achieving a balance between high withstand voltage, low on-resistance, high frequency and low switching loss, and high current and low on-resistance, while retaining the body diode freewheeling function. This solves the technical problem that SiC power devices in related technologies cannot simultaneously meet the above performance requirements.

[0080] Example 2 This embodiment is basically the same as Embodiment 1, except that only one of the two gate trenches 106 has a base metal layer 111, while the other gate trench 106 is only filled with a gate 108. That is, a single-sided base lead-out scheme is adopted. See [link to previous section]. Figure 8 As shown.

[0081] In this embodiment, the base contact region 109 is still located on the P-pillar region 102b, but a base metal layer 111 is formed only in one side of the gate trench 106 and electrically connected to it. The other side of the gate trench 106 only contains the gate 108, without the base metal layer 111. This design simplifies the base lead-out process and reduces the trench space occupied by the base metal layer 111.

[0082] In the fabrication method, after depositing polysilicon in step S1100, a base metal layer 111 is formed only in one of the gate trenches 106 by photolithography and etching, while only the gate 108 is retained in the other gate trench 106. The remaining steps are the same as in Example 1.

[0083] Example 3 This embodiment is basically the same as Embodiment 1, except that the pressure-resistant layer 102 adopts a semi-superjunction structure. For example, the pressure-resistant layer 102 includes a first region and a second region 102c, such as... Figure 9 As shown. The first region is located on top and consists of alternating N-pillar regions 102a and P-pillar regions 102b, which are used for charge balance and lateral depletion; the second region 102c is located between the first region and the substrate layer 101, and is a uniform N-type drift region, which is used to bear part of the withstand voltage and act as a buffer layer.

[0084] The semi-superjunction structure shortens the depth of the P-pillar region 102b and the N-pillar region 102a, reducing the difficulty and cost of epitaxial and etching processes. Simultaneously, the uniform drift region below reduces the direct connection between the P / N pillars and the substrate, improving the reverse recovery softness factor of the device's bulk diode and optimizing its reverse recovery characteristics.

[0085] In the preparation method, in step S200, a uniform N-type drift layer (second region 102c) is first epitaxially grown on the substrate layer 101, and then alternating N-pillar regions 102a and P-pillar regions 102b (first region) are formed on it through a side-epitaxial doping process. The remaining steps are the same as in Example 1.

[0086] Example 4 This embodiment is basically the same as Embodiment 1, except that a resistive connection structure or a capacitive connection structure is provided between the gate 108 and the base metal layer 111. The resistive connection structure is formed, for example, by a polysilicon resistor or a diffusion resistor, to electrically connect the gate 108 and the base metal layer 111; the capacitive connection structure is formed, for example, by a metal-insulator-metal (MIM) capacitor or a MOS capacitor, to couple the bias voltage change of the gate 108 to the base metal layer 111.

[0087] In this embodiment, the gate 108 and the base metal layer 111 are linked by a passive connection structure, and the bias voltage on the base metal layer 111 follows the bias voltage of the gate 108. When the gate 108 is forward biased to open the MOS channel, the base metal layer 111 is also forward biased simultaneously, automatically activating the bipolar conduction path; when the gate 108 is turned off, the base metal layer 111 is also turned off simultaneously. This solution eliminates the need for a separate drive pin for the base, simplifying the design of the external drive circuit. This solution is suitable for applications where drive circuit simplification and cost sensitivity are important.

[0088] In the fabrication method, after forming the gate 108 and the base metal layer 111 and before forming the source / emitter metal layer 113, an additional step is added to form a resistive or capacitive connection structure. The remaining steps are the same as in Example 1.

[0089] Example 5 This embodiment is basically the same as Embodiment 1, except that the semiconductor material is silicon (Si). By replacing the materials of each semiconductor layer with silicon and adjusting the doping concentration and process parameters accordingly, the device structure of this application is also applicable to silicon-based power devices.

[0090] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0091] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A semiconductor device, characterized in that, include: Drain / collector metal layer; A substrate of the first conductivity type is disposed on the drain / collector metal layer; A withstand voltage layer is disposed on the substrate layer, the withstand voltage layer including N-pillar regions and P-pillar regions arranged alternately along a direction parallel to the upper surface of the substrate layer, the N-pillar regions and the P-pillar regions having a first conductivity type and a second conductivity type, respectively, and the N-pillar regions and the P-pillar regions are configured to mutually deplete laterally when the semiconductor device is subjected to a reverse voltage to achieve charge balance; The body region is located above the pressure-resistant layer and has a second conductivity type; The source / emitter contact region is located within the body region and has a first conductivity type; A source / body contact region is disposed within the body region and has a second conductivity type, and is arranged at a distance from the source / emitter contact region; At least one gate trench extends downward from the upper surface of the device, through the body region and to the withstand voltage layer, the inner wall of the gate trench is covered with a gate dielectric layer, and the gate trench is filled with a gate, the gate being configured to receive a gate bias voltage. The base contact region has a second conductivity type, and the base contact region is disposed on the P-pillar region and electrically connected to the P-pillar region. The base-emitter region has a first conductivity type, and the base-emitter region is disposed within the base contact region; A base metal layer is disposed in the gate trench and is insulated from the gate in the same gate trench. The base metal layer is electrically connected to the base contact region. A source / emitter metal layer is disposed on the body region and electrically connected to the source / emitter contact region, the source / body contact region and the base-emitter region, and the source / emitter metal layer covers at least a portion of the gate trench.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes two symmetrically arranged gate trenches, each containing a gate. The base metal layer is disposed in one of the gate trenches and is insulated from the gate in the same gate trench.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes two symmetrically arranged gate trenches, each containing a gate and a base metal layer, wherein the base metal layer is insulated from the gate in the same gate trench.

4. The semiconductor device according to claim 1, characterized in that, The widths of the N-pillar region and the P-pillar region are equal, and they satisfy charge balance.

5. The semiconductor device according to claim 4, characterized in that, The pressure-resistant layer includes: The first region includes alternating N-column and P-column regions; The second region includes a drift region of a second conductivity type, and the second region is located between the first region and the substrate layer.

6. The semiconductor device according to claim 5, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

7. The semiconductor device according to claim 1, characterized in that, A resistive connection structure or a capacitive connection structure is provided between the gate and the base metal layer so that the bias voltage on the base metal layer varies with the bias voltage of the gate.

8. The semiconductor device according to claim 1, characterized in that, The source / body contact region, the body region, the N-pillar region, and the substrate layer form a body diode, which is configured to provide a freewheeling path in the third quadrant operating state of the semiconductor device.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor material of the semiconductor device is silicon carbide or silicon.

10. A method for preparing the semiconductor device according to any one of claims 1 to 9, characterized in that, Includes the following steps: Provide a substrate layer of the first conductivity type; A voltage-resistant layer is formed on the substrate layer. The voltage-resistant layer includes N-pillar regions of a first conductivity type and P-pillar regions of a second conductivity type, which are alternately arranged along a direction parallel to the upper surface of the substrate layer. The widths of the N-pillar regions and the P-pillar regions are equal and they satisfy the charge balance condition. A body region having a second conductivity type is formed on the pressure-resistant layer; A base contact region having a second conductivity type is formed on the P-pillar region; A source / body contact region having a second conductivity type is formed within the body region; A source / emitter contact region having a first conductivity type is formed in the body region, and a base / emitter region having a first conductivity type is formed in the base contact region; At least one gate trench is formed, the gate trench extending downward from the upper surface of the device, penetrating the body region and extending to the withstand layer; A gate dielectric layer is formed on the inner wall surface of the gate trench; Remove a portion of the gate dielectric layer located in the base contact region; A gate is filled within the gate trench, and a base metal layer is formed within at least one of the gate trenches, the base metal layer being electrically connected to the base contact region through a region of the removed gate dielectric layer; An interlayer dielectric layer is deposited to cover the gate and the base metal layer, such that the base metal layer is insulated from the gate in the same gate trench; A source / emitter metal layer is formed, which is electrically connected to the source / emitter contact region, the source / body contact region, and the base-emitter region; A drain / collector metal layer is formed on the side of the substrate away from the withstand voltage layer.

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