Shorted optimized split-gate 4h-sic tmos device

Abstract

The application provides a short-circuit optimized split-gate 4H-SiC TMOS device, and belongs to the technical field of power semiconductors.The device adopts a split-gate structure, N-type injection is performed at the bottom of a gate and a source trench, an N-type current path is arranged as a saturation current limiting area, and an N+ well region completely wraps around a trench corner, so that the short-circuit resistance of the device is improved; meanwhile, the split-gate structure can reduce the gate-drain capacitance of the device and reduce the switching loss of the device.The 4H-SiC TMOS structure has better switching characteristics and short-circuit resistance.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a short-circuit optimized split-gate 4H-SiC TMOS device. Background Technology

[0002] SiC material is a typical representative of third-generation wide bandgap semiconductor materials with great application prospects. Due to its advantages such as high critical breakdown electric field strength, high carrier saturation drift velocity, and high thermal conductivity, it has become an ideal material for manufacturing high-power, high-temperature, high-frequency, and radiation-resistant devices.

[0003] SiC power devices have become a crucial aspect of the semiconductor industry, and research on them is progressing rapidly. Current SiC power MOSFETs have reached 1200V, and the emergence of SiC will expand the application of MOSFETs and Schottky diodes to higher voltage levels. SiC has very low on-resistance per unit area, and compared to Si devices of comparable power, the chip size of SiC devices can be significantly reduced, resulting in lower parasitic capacitance, easier device driving, and faster switching speeds. However, it still has significant potential for development and optimization. For SiC MOSFETs, the gate-drain capacitance Cgd significantly affects the dynamic performance of the MOSFET; reducing Cgd can effectively optimize its switching performance and reduce dynamic losses. MOSFETs are often used in bridge circuits, which are subject to short-circuit risks. Short-circuit faults are one of the important causes of MOSFET failure; improving the short-circuit withstand capability of MOSFETs can effectively improve system reliability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a short-circuit optimized split-gate 4H-SiC TMOS device, which addresses the problems existing in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a short-circuit optimized split-gate 4H-SiC TMOS device, comprising: a drain, an N+ substrate, an N- epitaxial layer, a P-well, an N+ well region, an N+ contact region, a P+ contact region, an N+ saturation current control region, a gate oxide layer, a JFET region, a gate, a trench source, a surface source, and a SiO2 interlayer dielectric.

[0006] The drain, N+ substrate, and N- epitaxial layer are stacked sequentially from bottom to top;

[0007] The JFET region is located directly below the trench source and is connected to the N-epitaxial layer;

[0008] The P-well is located on top of the N- epitaxial layer and on both sides of the JFET region. The N+ saturated current control regions are located on both sides of the JFET region. The N+ saturated current control regions on both sides of the JFET region are located on top of the P-well, forming a current path. The N+ well regions on both sides of the JFET region are connected to the N+ saturated current control regions and are located on top of the P-well.

[0009] The gate oxide layer is located between the gate and the trench source, above the N+ saturated current control region and the JFET region, and the outermost corner of the gate oxide layer is completely wrapped by the N+ well region.

[0010] The gate is located between the N+ source region and the trench source. It is separated from the trench source by the gate oxide layer and from the surface source by the SiO2 interlayer dielectric.

[0011] The SiO2 interlayer dielectric is located on the gate oxide layer and the gate, isolating the gate from the surface source.

[0012] The trench source is located at the center of the trench and on the gate oxide layer, while the surface source is located at the top of the device. It is in contact with the N+ source region and the P+ contact region, and is separated from the gate by the SiO2 interlayer dielectric.

[0013] Based on the above technical solution, the present invention can be further improved as follows.

[0014] Furthermore, the N+ well region is located in the P well, and its current path is from the drain to the N+ substrate to the N- epitaxial layer to the JFET region to the N+ saturated current control region to the N+ well region to the channel region to the N+ contact region to the surface source.

[0015] Furthermore, the N+ saturated current control region is located in the P-well and at the bottom of the trench, and its top is connected to the trench source through the gate oxide layer to form a MOS structure, thus connecting the N+ well region and the JFET region.

[0016] Furthermore, the length of the N+ saturated current control region is 0.55 μm, and the width of the JFET region is 0.3 μm.

[0017] Furthermore, the gate is located on both sides of the trench source to form a split gate, and the trench source is directly above the N+ saturated current control region and the JFET region.

[0018] Furthermore, the N+ saturated current control region is implanted with n-ions, with a peak doping concentration of 5.3e17 cm⁻¹. -3 The distance from the peak to the bottom of the trench is 1.08 μm.

[0019] Furthermore, the drain electrode is formed into an ohmic contact using Ni sputtering.

[0020] Furthermore, the N+ trap region is formed into a box-shaped distribution using N-type ion implantation, meaning that impurities are uniformly distributed within a certain box-shaped spatial region, with a concentration of 2e19cm⁻¹. -3 It can completely cover the corners of the trench by extending laterally and longitudinally.

[0021] Furthermore, the P-well region is injected with P-type ions from the bottom of the trench, with a peak concentration of 5.14e18cm⁻¹. -3 The peak concentration depth is 1.57 μm, and the doping concentration of the Pbase region in the upper channel is approximately 8e16 cm⁻¹. -3 .

[0022] Furthermore, the length of the N+ saturated current control region is 0.55 μm, and the width of the JFET region is 0.3 μm. It is implanted with n-ions from the bottom of the trench, with a width on the order of 1e17 cm⁻¹. -3 .

[0023] The beneficial effects of this invention are as follows: When the device is in the blocking state, the P-well protects the gate oxide layer, effectively reducing the electric field strength of the gate oxide layer, thus ensuring that the blocking characteristics of the device remain consistent with those of the traditional 4H-SiC TMOS structure. When the device is in forward conduction, the introduction of the N+ saturation current control region and the expansion of the P-well control the current path size in saturation, resulting in higher short-circuit withstand capability. Furthermore, the split gate structure used in this invention reduces Cgd, improving the dynamic performance of the device. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a short-circuit optimized split-gate 4H-SiC TMOS device according to an embodiment of the present invention;

[0025] Figure 2 A comparison of the output characteristic curves of a conventional 4H-SiC TMOS device and a split-gate 4H-SiC TMOS device according to an embodiment of the present invention;

[0026] 1-Drain, 2-N+ substrate, 3-N-epitaxy layer, 4-P-well, 5-N+ well region, 6-N+ contact region, 7-P+ contact region, 8-N+ saturation current control region, 9-gate oxide layer, 10-JFET region, 11-gate, 12-trench source, 13-surface source, 14-SiO2 interlayer dielectric. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] like Figure 1 As shown, the present invention provides a short-circuit optimized split-gate 4H-SiC TMOS device, including: drain 1, N+ substrate 2, N- epitaxial layer 3, P-well 4, N+ well region 5, N+ contact region 6, P+ contact region 7, N+ saturation current control region 8, gate oxide layer 9, JFET region 10, gate 11, trench source 12, surface source 13, and SiO2 interlayer dielectric 14;

[0029] Drain 1, N+ substrate 2 and N- epitaxial layer 3 are stacked sequentially from bottom to top;

[0030] JFET region 10 is located directly below trench source 12 and is connected to N-epitaxial layer 3;

[0031] P-well 4 is located on top of N-epitaxy layer 3 and on both sides of JFET region 10. N+ saturated current control regions 8 are located on both sides of JFET region 10. The N+ saturated current control regions 8 on both sides of JFET region 10 are located on top of P-well 4 and serve as a current path. N+ well regions 5 on both sides of JFET region 10 are connected to N+ saturated current control regions 8 and are located on top of P-well 4.

[0032] The gate oxide layer 9 is located between the gate 11 and the trench source 12, above the N+ saturated current control region 8 and the JFET region 10, and the outermost corner of the gate oxide layer 9 is completely wrapped by the N+ well region 5.

[0033] Gate 11 is located between N+ source region 6 and trench source 12. It is separated from trench source 12 by gate oxide layer 9 and from surface source 13 by SiO2 interlayer dielectric 14.

[0034] SiO2 interlayer dielectric 14 is located on the gate oxide layer 9 and the gate 11, isolating the gate 11 from the surface source 13;

[0035] The trench source 12 is located at the center of the trench and on the gate oxide layer 9. The surface source 13 is located at the top of the device, which is in contact with the N+ source region 6 and the P+ contact region 7, and is separated from the gate 11 by the SiO2 interlayer dielectric 14.

[0036] Preferably, the N+ well region 5 is located in the P well 4, and its current path is from the drain 1 to the N+ substrate 2 to the N- epitaxial layer 3 to the JFET region 10 to the N+ saturation current control region 8 to the N+ well region 5 to the channel region to the N+ contact region 6 to the surface source 13.

[0037] Preferably, the N+ saturated current control region 8 is located in the P-well 4 and at the bottom of the trench, and its top is connected to the trench source 12 through the gate oxide layer 9 to form a MOS structure, connecting the N+ well region 5 to the JFET region 10.

[0038] Preferably, the length of the N+ saturated current control region is 0.55 μm, and the width of the JFET region is 0.3 μm.

[0039] Preferably, the gate 11 is located on both sides of the trench source 12 to form a split gate, and the trench source 12 is directly above the N+ saturated current control region 8 and the JFET region 10.

[0040] Preferably, the N+ saturated current control region 8 is implanted with n-ions, with a peak doping concentration of 5.3e17 cm⁻¹. -3 The distance from the peak to the bottom of the trench is 1.08 μm.

[0041] Preferably, the drain electrode 1 is formed into an ohmic contact by sputtering Ni metal.

[0042] Preferably, the N+ trap region 5 is formed by N-type ion implantation to create a box-shaped distribution, meaning that the impurities are uniformly distributed within a certain box-shaped space region, with a concentration of 2e19cm⁻¹. -3 It can completely cover the corners of the trench by extending laterally and longitudinally.

[0043] Preferably, the P-trap 4 is injected from the bottom of the trench with P-type ions at a peak concentration of 5.14e18cm⁻¹. -3 The peak concentration depth is 1.57 μm, and the doping concentration of the Pbase region in the upper channel is approximately 8e16 cm⁻¹. -3 .

[0044] Preferably, the length of the N+ saturated current control region 8 is 0.55 μm, and the width of the JFET region 10 is 0.3 μm, which is implanted with n-ions from the bottom of the trench, with a width on the order of 1e17 cm. -3 .

[0045] To illustrate the advantages of the device of this invention, a simulation analysis is performed below using a 1200V SiC TMOS as the main device. Specifically, the drain in the TMOS is made of metallic Ni; the N+ substrate has a concentration of 2E19 cm⁻¹. -3 The substrate is N-type doped with an N+ substrate thickness of 2 μm; the N- epitaxial layer has a concentration of 8E15 cm⁻¹.-3 The N-type doping layer is 10 μm thick; the P-well is formed by Al ion implantation to create a Gaussian distribution with a peak concentration of 5.14e18 cm⁻¹. -3 The peak concentration depth is 1.57 μm, and its right end is 0.3 μm away from the gate trench; the P-type doping concentration in the channel region is approximately 8e16 cm⁻¹. -3 The bottom of the N+ source region is 0.1 μm away from the bottom of the gate trench; the concentration of both the N+ source region and the P+ contact region is 1e20cm. -3 The gate oxide layer is made of silicon dioxide and has a thickness of 0.05 μm. The gate oxide layer is formed by thermal oxidation. The gate electrode is formed on the gate oxide layer by polysilicon deposition.

[0046] Build using TCAD software Silvaco, such as Figure 1 The device structure shown is illustrated below. To illustrate the advantages of the structure of this embodiment compared to the conventional structure, a comparison of the output characteristics of the structure of this embodiment and the conventional TMOS structure is presented below. Figure 2 As shown, compared with the traditional structure, the on-resistance of the present invention is slightly increased, but the saturation current is significantly reduced. The square and circular curves represent the drain current versus drain voltage curves of the traditional 4H-SiC TMOS device and the 4H-SiC TMOS device of the present invention at a gate voltage of 20V, respectively. The slope of the linear region of the curve represents the on-resistance of the device.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A short-circuit optimized split-gate 4H-SiC TMOS device, characterized in that, include: Drain (1), N+ substrate (2), N- epitaxial layer (3), P well (4), N+ well region (5), N+ contact region (6), P+ contact region (7), N+ saturated current control region (8), gate oxide layer (9), JFET region (10), gate (11), trench source (12), surface source (13), SiO2 interlayer dielectric (14); The drain (1), N+ substrate (2) and N- epitaxial layer (3) are stacked sequentially from bottom to top; The JFET region (10) is located directly below the trench source (12) and is connected to the N-epitaxial layer (3); The P-well (4) is located on the upper layer of the N-epitaxial layer (3) and on both sides of the JFET region (10). The N+ saturated current control regions (8) are located on both sides of the JFET region (10). The N+ saturated current control regions (8) on both sides of the JFET region (10) are located on the upper layer of the P-well (4) as a current path. The N+ well regions (5) on both sides of the JFET region (10) are connected to the N+ saturated current control regions (8) and are located on the upper layer of the P-well (4). The gate oxide layer (9) is located between the gate (11) and the trench source (12), above the N+ saturated current control region (8) and the JFET region (10), and the outermost corner of the gate oxide layer (9) is completely wrapped by the N+ well region (5). The gate (11) is located between the N+ source region (6) and the trench source (12), and is separated from the trench source (12) by the gate oxide layer (9), and from the surface source (13) by the SiO2 interlayer dielectric (14). The SiO2 interlayer dielectric (14) is located on the gate oxide layer (9) and the gate (11), isolating the gate (11) from the surface source (13); The trench source (12) is located in the center of the trench and on the gate oxide layer (9), and the surface source (13) is located at the top of the device. It is in contact with the N+ source region (6) and the P+ contact region (7), and is separated from the gate (11) by the SiO2 interlayer dielectric (14).

2. The short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The N+ well region (5) is located in the P well (4), and its current path is from the drain (1) to the N+ substrate (2) to the N- epitaxial layer (3) to the JFET region (10) to the N+ saturated current control region (8) to the N+ well region (5) to the channel region to the N+ contact region (6) to the surface source (13).

3. The short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The N+ saturated current control region (8) is located in the P well (4) and at the bottom of the trench. Its top is connected to the trench source (12) through the gate oxide layer (9) to form a MOS structure, connecting the N+ well region (5) and the JFET region (10).

4. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The length of the N+ saturated current control region is 0.55 μm, and the width of the JFET region is 0.3 μm.

5. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The gate (11) is located on both sides of the trench source (12) to form a split gate, and the trench source (12) is directly above the N+ saturated current control region (8) and the JFET region (10).

6. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The N+ saturated current control region (8) is implanted with n-ions, with a peak doping concentration of 5.3e17 cm⁻¹. -3 The distance from the peak to the bottom of the trench is 1.08 μm.

7. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The drain electrode (1) is formed into an ohmic contact by sputtering Ni metal.

8. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The N+ trap region (5) is formed into a box-shaped distribution by N-type ion implantation, that is, the impurities are uniformly distributed in a certain box-shaped space region, and the concentration is 2e19cm. -3 It can completely cover the corners of the trench by extending laterally and longitudinally.

9. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The P-trap (4) is injected from the bottom of the trench with P-type ions at a peak concentration of 5.14e18cm. -3 The peak concentration depth is 1.57 μm, and the doping concentration of the Pbase region in the upper channel is approximately 8e16 cm⁻¹. -3 .

10. A short-circuit optimized split-gate 4H-SiC TMOS device according to claim 1, characterized in that, The length of the N+ saturated current control region (8) is 0.55 μm, and the width of the JFET region (10) is 0.3 μm. It is implanted with n-ions from the bottom of the trench, and its order of magnitude is 1e17 cm. -3 .

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