An integrated heterojunction trench gate SiC power MOSFET device and a preparation method thereof

Abstract

This invention discloses an integrated heterojunction trench-gate SiC power MOSFET device and its fabrication method, belonging to the field of semiconductor device technology. The device includes a substrate layer, an epitaxial layer, a stepped trench, a buried layer, a structural fill layer, deep pillars, and a control gate structure. The stepped trench employs a stepped design with an upper first-stage trench and a lower second-stage trench, forming a unique stepped electric field modulation region. The buried layer is disposed at the top of the deep pillars, which enclose the structural fill layer and are electrically connected to the source. The control gate structure is disposed within the first-stage trench, consisting of a first conductive layer and a first gate dielectric layer, with a second gate dielectric layer disposed between them. The first and second gate dielectric layers are fabricated using materials with different dielectric constants. Through structural innovation, this invention achieves a dual improvement in device switching performance and short-circuit withstand capability without increasing on-resistance, making it suitable for fields with high device reliability requirements, such as new energy vehicles and low-altitude aircraft.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an integrated heterojunction trench gate SiC power MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) power MOSFETs, with their wide bandgap characteristics, exhibit significant advantages in high-temperature, high-voltage, and high-power applications, and have become core devices in fields such as solar inverters, electric vehicles, rail transportation, and spacecraft. However, these applications place stringent requirements on device reliability, with the stability of the gate oxide layer and short-circuit withstand capability being the core bottlenecks restricting their large-scale replacement of traditional Si-based IGBTs.

[0003] Compared to planar gate structures, trench-gate SiC power MOSFETs completely eliminate the JFET effect through multi-channel design, effectively reducing specific on-resistance. However, traditional trench gate structures have two inherent drawbacks: first, the peak electric field at the bottom of the trench is high, far exceeding the critical breakdown field strength of SiC gate oxide, making it highly susceptible to gate oxide breakdown; second, the large transfer capacitance increases switching losses and exacerbates current concentration under short-circuit conditions. These problems not only reduce the long-term reliability of the device but also result in a short-circuit withstand time that is generally only 2~5 μs, far lower than the 10 μs or more of Si-based IGBTs, severely limiting its application in high-safety-requirement fields such as power systems.

[0004] To improve the short-circuit withstand capability of trench-gate SiC power MOSFETs, existing technologies have focused on optimizing device structures. Introducing a P-type shield or floating field plate can effectively reduce the peak electric field, but this increases the specific on-resistance. Variable channel length designs automatically limit current growth during short circuits through channel pinch-off effects, but this affects conduction performance during normal operation. In summary, existing technologies often sacrifice other device performance, such as on-resistance and switching losses, or increase process complexity and cost while improving the short-circuit withstand capability of trench-gate SiC power MOSFETs. Therefore, there is an urgent need for a new trench-gate SiC power MOSFET structure and its fabrication method that can significantly improve short-circuit withstand capability without affecting breakdown voltage and on-resistance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an integrated heterojunction trench gate SiC power MOSFET device and its fabrication method. This device can effectively reduce the saturation current while ensuring that its breakdown voltage is not affected, thereby significantly improving the device's body short-circuit withstand capability.

[0006] This invention is implemented as follows: On one hand, this invention provides an integrated heterojunction trench gate SiC power MOSFET device, comprising a back metal layer, a substrate layer of highly doped SiC of a first conductivity type, an epitaxial layer of lightly doped SiC of the first conductivity type, a body region of a second conductivity type, a source region, a stepped trench, a buried layer, a deep pillar, a structural fill layer, a control gate structure, and a front metal layer; the back metal layer is disposed at the bottom of the device, and the substrate layer is disposed on the top surface of the back metal layer, forming an ohmic contact between the back metal layer and the substrate layer to constitute the drain of the device; the epitaxial layer is stacked on the upper surface of the substrate layer; the body region is disposed on the upper part of the epitaxial layer; the source region is disposed on the body region, including two P+ source regions of the second conductivity type on the left and right, and an N+ source region of the first conductivity type in the middle region; the front metal layer covers the upper surface of the source region, and the source electrode is led out from the source region, which is the front metal layer; the stepped trench consists of an upper primary trench and a lower secondary trench, the width of the primary trench is greater than that of the secondary trench, and the depth of the primary trench is less than that of the secondary trench, forming a stepped trench that is shallower at the top and deeper at the bottom; the deep pillar is disposed on the epitaxial layer. Within the primary trench, a secondary trench is located between the deep pillar and the buried layer. A primary trench is formed through the N+ source region, body region, and epitaxial layer. A structural filler layer is placed within the secondary trench. The deep pillar surrounds and covers the structural filler layer. The buried layer is laterally positioned at the upper opening of the secondary trench. The upper ends of the deep pillars are connected to the buried layer, and the deep pillars are electrically connected to the front metal layer. A control gate structure is located inside the primary trench and consists of a first conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The first gate dielectric layer is closely attached to the sidewall of the primary trench and is located in the body region, N+ source region, and epitaxial layer. Between the epitaxial layers, a first conductive layer is disposed within a first gate dielectric layer, and a second gate dielectric layer is sandwiched between the first gate dielectric layer and the first conductive layer; wherein, the control gate structure is a high dielectric constant / low dielectric constant structure, the first gate dielectric layer is a SiO2 dielectric material, which belongs to a low dielectric constant dielectric material, with a sidewall thickness of 30nm to 50nm and a bottom thickness of 48nm to 95nm; the second gate dielectric layer is a high dielectric constant dielectric material, including HfO2, ZrO2 or Al2O3, with a thickness of 2nm to 5nm.

[0007] More preferably, the first conductivity type is N-type, and the second conductivity type is P-type; the epitaxial layer doping concentration is 3×10⁻⁶. 15 cm -3 ~4×10 15 cm -3 The thickness is 30μm to 36μm; the width of the primary trench is 0.8μm to 1μm and the depth is 2μm to 2.5μm, and the width of the secondary trench is 0.4μm to 0.6μm and the depth is 10μm to 13μm; the buried layer is a heavily doped material of the second conductivity type with a doping concentration of 9×10⁻⁶. 16 cm -3 ~1×10 17 cm -3The thickness is 0.2μm to 0.4μm; the deep pillars are made of heavily doped SiC, a material of the second conductivity type, with a doping concentration of 9×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The structural filling layer is a SiO2 dielectric material with a thickness of 10 μm to 13 μm; the first conductive layer is a polycrystalline silicon conductive layer, which is doped with a heavily doped first conductivity type material with a doping concentration of 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The doping concentrations of the P+ and N+ source regions are 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The substrate depth is 0.2 μm to 0.5 μm; the substrate doping concentration is 1 × 10⁻⁶. 18 cm -3 ~5×10 18 cm -3 .

[0008] The beneficial effects of this invention are as follows: In the prior art, the epitaxial layer is only used as a conventional withstand voltage drift layer, responsible for withstand voltage and drift conductivity. The buried layer at the bottom of the trench is also mostly a single electric field shielding structure. The two are independent functional units, and there is no active heterojunction pair matching design. However, this solution breaks this conventional layout and innovatively constructs a heterojunction diode by using the buried layer and the epitaxial layer. The buried layer at the bottom of the trench and the epitaxial layer are directly coupled as two paired electrodes of the heterojunction diode. The two form a controllable heterojunction barrier at the interface, rather than a traditional homojunction PN junction. This fundamentally reconstructs the physical mechanism of the freewheeling path and realizes the rectangular reconstruction of the electric field distribution by means of the charge compensation effect, thereby reducing the on-resistance and switching loss of the device from the root. Meanwhile, existing integrated heterojunction diode solutions often place the heterojunction at the polysilicon-SiC interface on the trench sidewall. Furthermore, existing integrated freewheeling diode solutions require an additional independent active region within the cell, which reduces the conductive channel area of ​​the MOSFET and increases on-resistance. In contrast, this solution sets the two components of the heterojunction as a buried layer at the bottom of the trench and a SiC epitaxial layer, completely reusing the two existing functional layers within the device without introducing an additional heterojunction material layer. Moreover, this solution relies entirely on the inherent interface between the buried layer at the bottom of the trench and the epitaxial layer to construct the heterojunction, without adding any cell area. This structure precisely optimizes the carrier transport path, significantly reduces gate charge and output capacitance, and substantially improves switching speed.

[0009] Furthermore, this scheme employs a composite design of deep pillars encasing a dual-gate dielectric layer to construct an electric field modulation region, enabling precise control of the high electric field at the bottom corner of the trench. Specifically, the stepped trench in this scheme consists of an upper primary trench and a lower secondary trench: the width of the primary trench is greater than that of the secondary trench, while its depth is less, forming an overall stepped structure that is "wider at the top and narrower at the bottom, shallower at the top and deeper at the bottom." The beneficial effects of this structure are twofold: firstly, the upper primary trench can accommodate the complete dual-gate dielectric layer, ensuring the gate control capability of the trench region; secondly, the lower secondary trench provides space for the fabrication of deep pillars, allowing the deep pillars to completely encapsulate the bottom region of the trench, providing a structural basis for subsequent electric field shielding and leakage current suppression. Based on this, the dual-gate dielectric layer serves as the control gate. The structure consists of a gate dielectric composed of two layers with different functions and structures stacked together: the first gate dielectric layer, which is in close contact with the sidewalls and bottom of the trench, is a low dielectric constant material (such as SiO2), and its thickness is distributed in a stepped manner along the trench direction (thinner on the sidewalls and thicker at the bottom corners), forming a thickness step; on top of this low dielectric constant dielectric layer, an ultrathin high dielectric constant dielectric layer (i.e., the second gate dielectric layer, such as HfO2 / Al2O3) is stacked, forming a "low dielectric constant + high dielectric constant" dual-gate dielectric composite structure: the synergistic structure formed by the deep pillars and the dual-gate dielectric layers can effectively disperse the electric field concentration at the corners, significantly reduce the local electric field intensity, and prevent the dual-gate dielectric layer from failing due to electric field breakdown, thereby greatly improving the long-term reliability of the gate dielectric.

[0010] Furthermore, compared to the traditional floating column structure, the core breakthrough of this design lies in the use of a grounded deep column to solve the leakage current fluctuation problem caused by dynamic potential. This deep column is directly connected to the source through the device's connection hole and is fixed at the source potential (0V), which is grounded, rather than the "floating column" in the traditional scheme where the potential changes with the drain voltage. The potential of the traditional floating column changes dynamically with the drain voltage, which easily leads to a sharp increase in leakage current as the voltage rises. Moreover, the rise in the device's lattice temperature will further aggravate the leakage current deterioration and severely shorten the short-circuit withstand time. The deep column, through its fixed potential design, directly blocks the drain electron injection channel, suppressing the generation of leakage current from a physical level. Even under extreme conditions of high voltage and high temperature, it can still maintain a low leakage current level, thereby improving the device's short-circuit withstand time.

[0011] On the other hand, the present invention also provides a method for fabricating an integrated heterojunction trench gate SiC power MOSFET device, comprising the following steps: S1. Select highly doped SiC of the first conductivity type as the substrate layer, and grow a low-doped SiC epitaxial layer of the same type on the surface of the substrate layer using chemical vapor deposition. S2. First conductivity type doped ions are implanted on the surface of the epitaxial layer, and activated by high temperature annealing at 1600℃~1800℃ to form a buried layer. Then, the epitaxial layer continues to grow on the buried layer to complete the overall epitaxial layer preparation. S3. A second conductivity type body region is formed on the surface of the epitaxial layer by ion implantation; doping is performed on the body region by photolithography self-alignment process, with P+ source regions forming on the left and right regions and N+ source regions forming in the middle region. S4. Using the photoresist on the source region and body region as an etching mask, a primary trench is prepared by etching process; after removing the photoresist, the buried layer is used as a self-aligned mask to continue etching downwards to form a secondary trench. S5. After the secondary trench is formed, firstly, vertical ion implantation of dopants of the second conductivity type is performed to form deep pillars at the bottom of the trench, and then tilted ion implantation of dopants of the second conductivity type is performed to form deep pillars on the sidewalls of the trench. After implantation, the lattice is repaired and the doping is activated by high-temperature annealing. S6. Deposit a structural filler layer inside the secondary trench; grow a first gate dielectric layer on the inner wall of the primary trench; deposit a second gate dielectric layer on the surface of the first gate dielectric layer; and finally deposit a polysilicon conductive layer between the first gate dielectric layer and the second gate dielectric layer to obtain the first conductive layer of the control gate. S7. By using photolithography to create openings, the source region and the upper surface of the deep pillar are connected, thus achieving electrical connection between the deep pillar and the front metal layer. S8. A front metal layer is prepared on the upper surface of the source region by sputtering and electroplating processes to serve as the source metal electrode; a back metal layer is prepared on the side of the substrate layer away from the epitaxial layer by metallization processes to form the drain metal electrode.

[0012] The beneficial effects of this invention are as follows: By employing precise control of a highly doped first conductivity type substrate and a low-doped epitaxial layer, combined with buried layer transition growth technology, the breakdown voltage and lattice matching quality of the device are effectively improved; by fabricating the source region and two-level trenches through a self-aligned process, the device structure is precisely controlled, significantly reducing process complexity and manufacturing costs; by forming deep pillars at the bottom and sidewalls through vertical and tilted ion implantation processes, a highly efficient charge balance structure is constructed, greatly improving the breakdown voltage and current density of the device.

[0013] More preferably, in step S1, the epitaxial layer is grown using chemical vapor deposition at a growth temperature of 1500℃~1700℃ and a cavity working pressure of 100Torr~500Torr.

[0014] More preferably, in step S4, the etching process adopts inductively coupled plasma etching, and the etching gas is a mixture of SF6 and O2 with a gas flow ratio of (5~10):1.

[0015] More preferably, in step S5, the ion implantation energy is 200 keV~500 keV, and the implantation dose is 1×10⁻⁶. 13 cm -2 ~5×10 13 cm -2 The high-temperature annealing temperature is 1600 ℃~1800 ℃, and the time is 30 min~60 min.

[0016] More preferably, in step S7, the electrical connection between the deep pillar and the front metal layer is prepared by photolithography to create a contact window in the source region and the top region of the deep pillar, and then using hydrogen plasma to clean the surface of the contact window to remove oxides and contaminants. Subsequently, a Ti / Al / Ni / Ag multilayer metal structure is sequentially deposited by magnetron sputtering and rapidly thermally annealed in an argon protective atmosphere to form a low-resistance ohmic contact, thereby achieving the electrical connection between the deep pillar and the front metal layer.

[0017] More preferably, in step S6, for the dielectric filling of the secondary trench, a structural filling layer is achieved by low-pressure chemical vapor deposition, and global planarization is achieved by chemical mechanical polishing; in the primary trench, a first gate dielectric layer is first grown by high-temperature thermal oxidation at a temperature of 1100℃~1300℃ for 60 min~120 min; then, a second gate dielectric layer is deposited on the surface of the first gate dielectric layer by atomic layer deposition at a temperature of 300℃~500℃, and the thickness of the second gate dielectric layer is controlled to be 2nm~5nm, thus constructing a high dielectric constant / low dielectric constant composite gate dielectric structure, followed by rapid thermal annealing to optimize the interface quality; finally, a polycrystalline silicon conductive layer is deposited on the composite gate dielectric structure by low-pressure chemical vapor deposition, and patterned by reactive ion etching to form a control gate electrode.

[0018] The beneficial effects of adopting the above-mentioned further solutions are as follows: low-resistivity electrical interconnection is achieved by opening photolithographic contact windows in the source region and the top of the deep pillars, and ohmic contacts are formed by combining sputtering-electroplating of the front metal layer and back metallization process and alloying annealing, which significantly improves the current transmission efficiency; the epitaxial layer and the deep pillars construct a charge balance structure, which breaks through the JFET effect limitation while maintaining the breakdown voltage and greatly reduces the specific on-resistance; the first-level trench and the second-level trench achieve precise electric field modulation and suppress edge field concentration; the high-k / low-k (i.e., high dielectric constant / low dielectric constant) composite gate dielectric reduces the driving voltage and improves the gate control capability and switching speed while ensuring gate oxide reliability; the structural filling layer effectively buffers thermal stress and improves the long-term reliability of the device. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an integrated heterojunction trench gate SiC power MOSFET structure according to the present invention.

[0020] Figure 2 This is a schematic diagram of step S1 of the preparation method of the present invention.

[0021] Figure 3 This is a schematic diagram of steps S2 and S3 of the preparation method of the present invention.

[0022] Figure 4 This is a schematic diagram of step S4 of the preparation method of the present invention.

[0023] Figure 5 This is a schematic diagram of step S4 of the preparation method of the present invention.

[0024] Figure 6 This is a schematic diagram of step S5 of the preparation method of the present invention.

[0025] Figure 7 This is a schematic diagram of step S5 of the preparation method of the present invention.

[0026] Figure 8 This is a schematic diagram of step S6 in the preparation method of the present invention.

[0027] Figure 9 This is a schematic diagram of step S8 of the preparation method of the present invention.

[0028] Figure 10 A schematic diagram illustrating the steps of creating a connection hole between the source electrode and the deep post.

[0029] Explanation of reference numerals in the accompanying drawings: 101, back metal layer; 102, substrate layer; 103, epitaxial layer; 104, body region; 105, P+ source region; 106, deep pillar; 107, N+ source region; 108, front metal layer; 109, first conductive layer; 110, buried layer; 111, first gate dielectric layer; 112, structural fill layer; 113, second gate dielectric layer. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0031] Example 1: This example provides a method for fabricating an integrated heterojunction trench gate SiC power MOSFET device. The fabrication process is as follows: Figures 2-9 As shown, it includes the following steps: Step S1: Select a highly doped SiC material of the first conductivity type as the substrate layer 102, and grow a low-doped epitaxial layer 103 of the same type of first conductivity type on its surface by chemical vapor deposition process. The thickness and doping concentration of the epitaxial layer 103 are precisely controlled according to the device withstand voltage requirements. The above process steps, through customized epitaxial layer parameters, enable flexible development of devices with different voltage ratings. Step S2: Implant first conductivity type doped ions on the surface of epitaxial layer 103, and activate anneal at high temperature of 1600℃~1800℃ to form buried layer 110; use buried layer 110 as a transition layer to continue growing first conductivity type epitaxial layer 103 to ensure lattice matching and interface quality between buried layer 110 and epitaxial layer 103. The above-mentioned process steps involve using epitaxial growth to form a buried layer, reducing lattice damage caused by high-energy injection, improving interface quality and defects, and ensuring high process consistency when applied directly, making it suitable for large-scale mass production. Simultaneously, the heterojunction diode constructed from the buried layer 110 and the epitaxial layer 103 achieves rectangular reconstruction of the electric field distribution through charge compensation, resulting in a uniform electric field distribution in the epitaxial layer 103, fundamentally reducing the device's on-resistance and switching losses. Step S3: On the surface of the outermost epitaxial layer 103, a second conductivity type body region 104 is formed by ion implantation; on the surface of the body region 104, P+ source regions 105 of the second conductivity type are implanted on the left and right sides respectively, and N+ source regions 107 of the first conductivity type are implanted in the middle. The source regions are self-aligned and patterned by photolithography. The above process steps were derived from extensive experimentation. Directly applying these process steps can shorten the device manufacturing cycle and reduce costs. Step S4: Using the photoresist pattern of the source region and the body region 104 as a mask, the first-level trench is formed by inductively coupled plasma etching process; after removing the surface mask, the buried layer 110 is used as a self-aligned mask to continue etching to form the second-level trench. The depth and width of the two-level trenches are precisely controlled by etching time and power parameters. Preferably, step S4 further includes: the width of the first-level trench is in the range of 0.8 μm to 1 μm and the depth is in the range of 2 μm to 2.5 μm; the width of the second-level trench is in the range of 0.4 μm to 0.6 μm and the depth is in the range of 10 μm to 13 μm. Step S5: After the secondary trench structure is formed, firstly, second conductivity type doped ions are implanted into the bottom of the secondary trench using a vertical ion implantation process to form a bottom deep pillar 106; then, a tilted ion implantation process is performed, such as... Figure 7 As shown, second conductivity type dopant ions are injected obliquely into the sidewall of the secondary trench in the direction indicated by the arrow to form a sidewall deep pillar 106; after injection, high-temperature annealing is performed to activate the dopant ions and repair the crystal lattice. The above process steps are a tilted ion implantation process that effectively suppresses the channel effect, reduces lattice damage caused by ion implantation, improves doping activation rate, and reduces leakage current. In some embodiments, the doping concentration of the deep pillar 106 ranges from 9 × 10⁶. 16 cm -3 ~1×10 17 cm -3 The depth of the deep column 106 is 13.0~16.0 μm; Step S6: In the second-stage trench, a structural filler layer 112 is deposited using a low-pressure chemical vapor deposition process; a first gate dielectric layer 111 is grown on the sidewalls and bottom of the first-stage trench using a high-temperature thermal oxidation process; a second gate dielectric layer 113 is deposited on the surface of the first gate dielectric layer 111 using an atomic layer deposition process to form a high-k / low-k composite gate dielectric structure; a polycrystalline silicon conductive layer is deposited on the surface of the composite gate dielectric layer using a low-pressure chemical vapor deposition process to form a control gate electrode; The above process steps involve growing the first gate dielectric layer 111 using a high-temperature thermal oxidation process, which results in a high breakdown field strength; and depositing the second gate dielectric layer 113 using an atomic layer deposition process, which results in a high dielectric constant. The composite structure maintains gate oxide reliability while reducing the equivalent gate charge and improving switching speed. Preferably, step S6 further includes: the sidewall thickness of the first gate dielectric layer 111 is in the range of 30 nm to 50 nm, and the bottom thickness is in the range of 48 nm to 95 nm; the thickness of the second gate dielectric layer is in the range of 2 nm to 5 nm; the structural fill thickness is in the range of 10 μm to 13 μm; the first gate dielectric material is silicon dioxide or silicon nitride; the structural fill layer 112 is made of silicon dioxide; the second gate dielectric layer 113 is a high dielectric material, including but not limited to one of HfO2, ZrO2, and Al2O3; Compared to existing technologies, the fabrication method provided in this embodiment employs a high-k / low-k composite gate dielectric structure and a structural SiO2 filling layer. This contrasts with traditional trench-gate SiC power MOSFETs, which typically use pure thermally oxidized SiO2 as the gate dielectric. While SiO2 offers good interface quality, its low dielectric constant necessitates thinning to maintain sufficient gate control capability, leading to decreased breakdown field strength and increased leakage current. Conversely, while a single high-k material boasts a high dielectric constant, its interface with SiC contains numerous defect states, causing threshold voltage drift and reliability degradation. This embodiment utilizes thermally oxidized SiO2 as the bottom layer, leveraging its low interface state density with SiC to ensure reliability. A high-k material deposited at atomic levels forms the top layer, reducing the equivalent oxide layer thickness without sacrificing interface quality, significantly improving gate control efficiency, reducing gate charge, and increasing switching speed. In this structure, the first gate dielectric layer 111 has a sidewall thickness of 30–50 nm and a bottom thickness of 48–95 nm, forming a non-uniform thickness gradient design. This effectively alleviates the electric field concentration at the bottom of the trench, reduces the maximum electric field strength, and significantly suppresses the risk of gate oxide breakdown. Simultaneously, the ultra-thin deposition of the high-k layer (only 2–5 nm) avoids grain coarsening and leakage surges caused by thick films in high-k materials, achieving the dual goals of high breakdown field strength and low equivalent oxide layer thickness. This structure is fully compatible with existing processes, eliminating the need for expensive or immature deposition technologies. The high-k material uses mature systems such as HfO2, ZrO2, and Al2O3, avoiding process fluctuations associated with environmentally sensitive materials like La2O3. Furthermore, the thickness parameter range is clearly defined, facilitating mass production control and providing a replicable process solution for the industrialization of high-voltage SiC power MOSFETs. Step S7: After the control gate is fabricated, a connection hole is formed on the top of the source region and the deep pillar 106 by photolithography to form a contact window, thereby realizing the electrical connection between the source and the deep pillar 106.

[0032] In specific implementation, after the control gate electrode is fabricated, the contact area between the source region and the top of the deep pillar 106 is defined using photolithography, and two key openings are simultaneously completed using reactive ion etching. A contact window is etched on the top of the first conductive layer 109, and a contact hole penetrating the source region and the body region 104 is etched on the surface of the source region, ensuring physical contact between the bottom of the contact hole and the top of the deep pillar 106. Subsequently, the contact window is filled using metal deposition, allowing the first conductive layer 109 to form an electrical connection with the source electrode through the front metal layer 108. Simultaneously, the deep pillar 106 is directly connected to the source electrode through the source region contact hole, ultimately achieving a low-resistance electrical interconnection between the source electrode, the deep pillar 106, and the control gate. The process is as follows: Figure 10 As shown; The above process steps involve a low-resistance connection between the source and the deep post 106, which quickly clamps the potential of the deep post 106 under short-circuit conditions, reduces the saturation current, and improves the short-circuit withstand time of the device. Step S8: A front metal layer 108 is prepared on the surface of the source region by sputtering and electroplating to form a source metal electrode; a back metal layer 101 is prepared on the side of the substrate layer 102 away from the epitaxial layer 103 by metallization to form a drain metal electrode; the front metal layer 108 and the semiconductor region of the source region (source side), and the back metal layer 101 and the semiconductor region of the substrate layer 102 (drain side) are alloyed and annealed to form a low-resistance ohmic contact.

[0033] Example 2: Based on Example 1, this embodiment provides an integrated heterojunction trench gate SiC power MOSFET device, including a substrate layer 102, an epitaxial layer 103, a trench, a buried layer 110, source regions (P+ source region 105, N+ source region 107), a structural fill layer 112, a body region 104, a deep pillar 106, a control gate structure, a front metal layer 108, and a back metal layer 101. The substrate layer 102 is a highly doped SiC substrate of the first conductivity type; the epitaxial layer 103... The epitaxial layer 103 is stacked on the substrate 102; the body region 104 is disposed on the epitaxial layer 103, and the body region 104 is made of a second conductivity type material; the source region is disposed on the body region 104, including the left and right P+ source regions 105 of the second conductivity type on both sides and the middle N+ source region 107 of the first conductivity type; the trench adopts a two-stage trench structure design; the trench includes a primary trench and a secondary trench, the primary trench is located above the secondary trench, and the primary trench is opened through the N+ source region 107, the body region 104 and the epitaxial layer 103. The secondary trench is located between the deep pillar 106 and the buried layer 110; the deep pillar 106 is disposed within the epitaxial layer 103; the buried layer 110 is disposed above the deep pillar 106; the deep pillar 106 encloses the structural fill layer 112 and is electrically connected to the front metal layer 108; the control gate structure is disposed within the primary trench, including a first conductive layer 109 and a first gate dielectric layer 111; the first gate dielectric layer 111 is closely attached to the sidewall of the primary trench and is disposed between the body region 104, the N+ source region 107, and the epitaxial layer 103. A conductive layer 109 is disposed within the first gate dielectric layer 111, and a second gate dielectric layer 113 is disposed between the first conductive layer 109 and the first gate dielectric layer 111; the first gate dielectric layer 111 and the second gate dielectric layer 113 are made of materials with different dielectric constants; a front metal layer 108 is disposed above the source region and a source electrode is led out from the source region, and the source electrode is the front metal layer 108; a back metal layer 101 is disposed on the side surface of the substrate layer 102 away from the epitaxial layer 103, and the back metal layer 101 is the drain electrode.

[0034] In some embodiments, the doping concentration of the epitaxial layer 103 is 3 × 10⁻⁶. 15 cm -3 ~4×10 15 cm -3 The thickness is 30.0~36.0μm; In some embodiments, the first gate dielectric layer 111 is a SiO2 dielectric material with a sidewall thickness ranging from 30 nm to 50 nm and a bottom thickness ranging from 48 nm to 95 nm; the second gate dielectric layer 113 is a high dielectric constant dielectric material, including but not limited to one of HfO2, ZrO2, and Al2O3, with a thickness ranging from 2 nm to 5 nm; and the structural filling layer 112 is a SiO2 dielectric material with a thickness ranging from 10 μm to 13 μm. While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as defined in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. An integrated heterojunction trench gate SiC power MOSFET device, characterized in that, It includes a back metal layer (101), a substrate layer (102) of highly doped first conductivity type SiC, an epitaxial layer (103) of lightly doped first conductivity type SiC, a body region (104) of second conductivity type, a source region, a stepped trench, a buried layer (110), a deep pillar (106), a structural fill layer (112), a control gate structure, and a front metal layer (108). A back metal layer (101) is disposed at the bottom of the device, and a substrate layer (102) is disposed on the top surface of the back metal layer (101). The back metal layer (101) and the substrate layer (102) form an ohmic contact to constitute the drain of the device. An epitaxial layer (103) is stacked on the upper surface of the substrate layer (102). A body region (104) is disposed on the upper part of the epitaxial layer (103). A source region is disposed on the body region (104), including two P+ source regions (105) of the second conductivity type on the left and right, and an N+ source region (107) of the first conductivity type in the middle region. A front metal layer (108) covers the upper surface of the source region and leads out the source electrode from the source region, which is the front metal layer (108). The stepped trench consists of an upper first-level trench and a lower second-level trench. The width of the first-level trench is greater than that of the second-level trench, and the depth of the first-level trench is less than that of the second-level trench, forming a stepped trench that is shallower at the top and deeper at the bottom. The deep column (106) is set in the epitaxial layer (103), the secondary trench is located between the deep column (106) and the buried layer (110), the primary trench is opened through the N+ source region (107), the body region (104) and the epitaxial layer (103), the structural filler layer (112) is set in the secondary trench, the deep column (106) surrounds and covers the structural filler layer (112), the buried layer (110) is arranged laterally at the upper opening position of the secondary trench, the upper end of the deep column (106) is connected to the buried layer (110), and the deep column (106) is electrically connected to the front metal layer (108). The control gate structure is located inside the primary trench and consists of a first conductive layer (109), a first gate dielectric layer (111), and a second gate dielectric layer (113). The first gate dielectric layer (111) is closely attached to the sidewall of the primary trench and is located between the body region (104), the N+ source region (107), and the epitaxial layer (103). The first conductive layer (109) is located inside the first gate dielectric layer (111), and the second gate dielectric layer (113) is sandwiched between the first gate dielectric layer (111) and the first conductive layer (109). The control gate structure is a high dielectric constant / low dielectric constant structure. The first gate dielectric layer (111) is a SiO2 dielectric material, which is a low dielectric constant dielectric material with a sidewall thickness of 30nm to 50nm and a bottom thickness of 48nm to 95nm. The second gate dielectric layer (113) is a high dielectric constant dielectric material, including HfO2, ZrO2, or Al2O3, with a thickness of 2nm to 5nm.

2. The device according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; The epitaxial layer (103) has a doping concentration of 3×10⁻⁶. 15 cm -3 ~4×10 15 cm -3 Thickness 30μm~36μm; primary trench width 0.8μm~1μm, depth 2μm~2.5μm, secondary trench width 0.4μm~0.6μm, depth 10μm~13μm; The buried layer (110) is a heavily doped material of the second conductivity type, with a doping concentration of 9 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 Thickness 0.2μm~0.4μm; Deep pillar (106) is heavily doped SiC of the second conductivity type, with a doping concentration of 9×10⁶. 16 cm -3 ~1×10 17 cm -3 ; The structural filling layer (112) is a SiO2 dielectric material with a thickness of 10 μm to 13 μm; the first conductive layer (109) is a polycrystalline silicon conductive layer, which is doped with a heavily doped first conductivity type material with a doping concentration of 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The doping concentrations of the P+ source region (105) and the N+ source region (107) are 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The depth is 0.2μm to 0.5μm; the substrate (102) has a doping concentration of 1×10⁻⁶. 18 cm -3 ~5×10 18 cm -3 .

3. A method for fabricating an integrated heterojunction trench gate SiC power MOSFET device according to any one of claims 1 to 2, characterized in that, It includes the following steps: S1. Select highly doped first conductivity type SiC as the substrate layer (102), and grow a low doped first conductivity type SiC epitaxial layer (103) of the same type on the surface of the substrate layer (102) using chemical vapor deposition process. S2. First conductivity type doped ions are implanted on the surface of the epitaxial layer (103), and the buried layer (110) is activated by high temperature annealing at 1600℃~1800℃. Then, the epitaxial layer (103) is grown on the buried layer (110) to complete the preparation of the overall epitaxial layer (103). S3. A second conductivity type body region (104) is formed on the surface of the epitaxial layer (103) by ion implantation; doping is performed on the body region (104) by photolithography self-alignment process, and P+ source regions (105) are formed on the left and right regions and N+ source regions (107) are formed in the middle region. S4. Using the photoresist on the source region and body region (104) as an etching mask, a primary trench is prepared by etching process; After removing the photoresist, the buried layer (110) is used as a self-aligned mask to continue etching downwards to form a secondary trench; S5. After the secondary trench is formed, firstly, vertical ion implantation of dopants of the second conductivity type is performed to form deep pillars (106) at the bottom of the trench, and then tilted ion implantation of dopants of the second conductivity type is performed to form deep pillars (106) on the sidewall of the trench. After implantation, the lattice is repaired and the doping is activated by high-temperature annealing. S6. A structural filling layer (112) is deposited inside the secondary trench; a first gate dielectric layer (111) is grown on the inner wall of the primary trench; a second gate dielectric layer (113) is deposited on the surface of the first gate dielectric layer (111); and finally, a polysilicon conductive layer is deposited between the first gate dielectric layer (111) and the second gate dielectric layer (113) to obtain the first conductive layer (109) of the control gate. S7. By photolithographically opening holes, the source region and the upper surface of the deep pillar (106) are connected to achieve electrical connection between the deep pillar (106) and the front metal layer (108); S8. A front metal layer (108) is prepared on the upper surface of the source region by sputtering and electroplating processes to serve as the source metal electrode; a back metal layer (101) is prepared on the side of the substrate layer (102) away from the epitaxial layer (103) by metallization processes to form the drain metal electrode.

4. The preparation method according to claim 3, characterized in that: In step S1, the epitaxial layer (103) is grown by chemical vapor deposition at a growth temperature of 1500℃~1700℃ and a cavity working pressure of 100Torr~500Torr.

5. The preparation method according to claim 3, characterized in that, In step S4, the etching process adopts inductively coupled plasma etching method, and the etching gas is a mixture of SF6 and O2 with a gas flow ratio of (5~10):

1.

6. The preparation method according to claim 3, characterized in that, In step S5, the ion implantation energy is 200 keV~500 keV, and the implantation dose is 1×10⁻⁶. 13 cm -2 ~5×10 13 cm -2 The high-temperature annealing temperature is 1600 ℃~1800 ℃, and the time is 30 min~60 min.

7. The preparation method according to claim 3, characterized in that, In step S7, the electrical connection between the deep pillar (106) and the front metal layer (108) is prepared. A contact window is prepared in the source region and the top region of the deep pillar (106) by photolithography. The surface of the contact window is cleaned with hydrogen plasma to remove oxides and contaminants. Subsequently, a Ti / Al / Ni / Ag multilayer metal structure is deposited sequentially by magnetron sputtering and rapidly thermally annealed in an argon protective atmosphere to form a low-resistance ohmic contact, thereby realizing the electrical connection between the deep pillar (106) and the front metal layer (108).

8. The preparation method according to claim 3, characterized in that, In step S6, for the dielectric filling of the secondary trench, a structural filling layer (112) is achieved by low-pressure chemical vapor deposition, and global planarization is achieved by chemical mechanical polishing. In the primary trench, the first gate dielectric layer (111) is first grown by high-temperature thermal oxidation at an oxidation temperature of 1100℃~1300℃ and an oxidation time of 60 min~120 min. Then, the second gate dielectric layer (113) is deposited on the surface of the first gate dielectric layer (111) by atomic layer deposition at an oxidation temperature of 300℃~500℃. The thickness of the second gate dielectric layer (113) is controlled to be 2nm~5nm to construct a high dielectric constant / low dielectric constant composite gate dielectric structure. Subsequently, the interface quality is optimized by rapid thermal annealing. Finally, a polycrystalline silicon conductive layer is deposited on the composite gate dielectric structure by low-pressure chemical vapor deposition, and the pattern is formed by reactive ion etching to form the control gate electrode.

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